JP2013020684A - Semiconductor memory device and inspection method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a characteristic evaluation of a transfer transistor disposed on the side of a row decoder.SOLUTION: According to an embodiment, a semiconductor memory device includes a switching unit, a first transfer transistor, a first transistor, and a second transistor. When the switching unit is in a first state, the first and second transistors are turned off and the first transfer transistor is turned on, and when the switching unit is in a second state, the first and second transistors are turned on.

Description

  Embodiments described herein relate generally to a semiconductor memory device and a test method thereof.

  With the progress of miniaturization of semiconductor elements, higher integration and lower power consumption of semiconductor memory devices such as DRAMs, SRAMs, and flash memories are progressing. In a highly integrated semiconductor memory device, a transistor screening test is an important technology.

  For example, in a NAND flash memory as a semiconductor memory device, a memory cell transistor constituting a memory cell can be tested via a word line (WL) and a bit line (BL), and a selection transistor constituting the memory cell. Can be tested through the select gate line and the bit line (BL).

  The transfer transistor disposed on the row decoder side and provided between the driver and the memory cell transistor and between the driver and the selection transistor actually performs a function test to perform a write operation, a read operation, an erase operation, and the like on the memory cell. By performing it, it is possible to evaluate the characteristics indirectly. However, as a test of the transfer transistor itself, there is a problem that it is impossible to directly evaluate the presence or absence of characteristic abnormality by measuring, for example, a threshold voltage (Vth).

  When an abnormality occurs in the transfer transistor connected to the memory cell transistor, only a specific word line has an abnormal write characteristic, and the reliability of the semiconductor memory device is greatly reduced. In addition, when a failure mode such as a high resistance failure mode, an open failure mode, or a short-to-word line failure mode occurs in a word line (WL) or a selection gate line connected to a transfer transistor, a specific word line (WL) or a selection gate is selected. Only the line becomes abnormal in characteristics, and the reliability of the semiconductor memory device is greatly reduced.

JP 2006-12217 A

  An object of the present invention is to provide a semiconductor memory device and a test method therefor capable of evaluating characteristics of a transfer transistor arranged on a row decoder side.

  According to one embodiment, the semiconductor memory device includes a switching unit, a first transfer transistor, a first transistor, and a second transistor. The first transfer transistor has a first terminal connected to the first drive signal line, a second terminal connected to the word line, and a first control signal at the gate when the switching unit is in the first state. And an external voltage is applied to the gate when the switching unit is in the second state. In the first transistor, the first terminal is connected to the first drive signal line, the second terminal is connected to the low potential power source, and the second control signal is input to the gate. In the second transistor, the first terminal is connected to the word line, the second terminal is connected to the bit line, and the second control signal is input to the gate. When the switching unit is in the first state, the first and second transistors are turned off, the first transfer transistor is turned on, and when the switching unit is in the second state, the first and second transistors are turned on.

  According to another embodiment, a test method for a semiconductor memory device includes first to third steps. The semiconductor memory device is arranged in a matrix and is provided between memory cells, drive signal lines, and word lines. A row decoder having a transfer transistor, a first transistor provided between the drive signal line and the low-potential side power supply, and a second transistor provided between the word line and the bit line is provided. In the first step, a transfer transistor characteristic evaluation command is input. In the second step, an external voltage is applied to the gate of the transfer transistor via the external terminal. In the third step, the first and second transistors are turned on using a characteristic evaluation command, and a current is passed between the bit line and the low-potential side power supply to measure the threshold voltage of the transfer transistor.

1 is a block diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment. 2 is a circuit diagram showing a configuration of a row decoder and a memory cell block according to the first embodiment. FIG. It is a flowchart which shows the characteristic evaluation of the transfer transistor which concerns on 1st embodiment. It is a figure explaining the characteristic evaluation of the transfer transistor which concerns on 1st embodiment. It is a figure which shows the Vth evaluation result of the transfer transistor which concerns on 1st embodiment. It is a circuit diagram which shows the structure of the row decoder and memory cell block which concern on 2nd embodiment. It is a figure explaining the characteristic evaluation of the transfer transistor which concerns on 2nd embodiment. It is a circuit diagram which shows the structure of the row decoder and memory cell block which concern on 3rd embodiment. It is a figure explaining the characteristic evaluation of the transfer transistor which concerns on 3rd embodiment. It is a figure explaining WL high resistance failure mode concerning a third embodiment. It is a figure explaining WL open failure mode concerning a third embodiment. It is a figure explaining the short defect mode between WL which concerns on 3rd embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
First, a semiconductor memory device and a test method thereof according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device. FIG. 2 is a circuit showing a configuration of the row decoder and the memory cell block. In this embodiment, the first transistor is arranged on the driver side of the transfer transistor, and the second transistor is arranged on the memory cell side, so that an external voltage is applied to the gate of the transfer transistor as a device under test. The structure allows evaluation.

  As shown in FIG. 1, the semiconductor memory device 90 includes a memory cell array 1, a row decoder 2, a sense amplifier circuit 3, a column decoder 4, an address register 5, a data input / output buffer 6, a controller 7, an internal voltage generation circuit 8, And an external terminal Padex. The semiconductor memory device 90 is a NAND flash memory.

  The controller 7 receives an external control signal Sso (chip enable CEn, write enable WEn, read enable REn, address latch enable ALE, command latch enable CLE, etc.) and a command CMD output from the data input / output buffer 6. The controller 7 outputs signals for controlling the row decoder 2, the sense amplifier circuit 3, the address register 5, the data input / output buffer 6, and the internal voltage generation circuit 8, respectively.

  The data input / output buffer 6 exchanges input / output data I / O Data with the outside. The data input / output buffer 6 outputs the command CMD to the controller 7. The data input / output buffer 6 outputs the address Add to the address register 5.

  The internal voltage generation circuit 8 generates various voltages to be supplied to the row decoder 2 and the memory cell array 1 based on instructions from the controller 7.

  In the memory cell array 1, memory cells are arranged in a matrix and a plurality of memory cell blocks are provided. The memory cell array 1 receives a voltage generated by the internal voltage generation circuit 8 (erase voltage Vera). The memory cell array 1 receives a signal output from the row decoder 2 and selects a word line (WL) and a selection gate line. The memory cell array 1 outputs read data to the sense amplifier circuit 3.

  The row decoder 2 receives various voltages (write voltage Vpgm, pass voltage Vpass, pass voltage Vread, drive voltage Vsg, etc.) generated by the internal voltage generation circuit 8. The row decoder 2 receives the address information output from the address register 5. The row decoder 2 outputs a signal for selecting a word line (WL) and a selection gate line to the memory cell array 1 based on an instruction from the controller 7. The row decoder 2 receives an external voltage Vext via the external terminal Padex in the test mode.

  The column decoder 4 receives the address information output from the address register 5. The column decoder 4 selects read / write data.

  The sense amplifier circuit 3 amplifies the read data output from the memory cell array 1 and selected by the column decoder 4 based on an instruction from the controller 7, and outputs the amplified read data to the data input / output buffer 6.

  As shown in FIG. 2, the row decoder 2 includes a block decoder 21, a control unit 22, a switching unit 23, a driver 241, a driver 242, a driver 250, a driver 251, a driver 25n, a transfer transistor TG1, a transfer transistor TG2, and a transfer transistor. TG00, transfer transistor TG01, transfer transistor TG0n, transistor TR1, transistor TR2, transistor TR00, transistor TR01, transistor TR0n, transistor TTR1, transistor TTR2, transistor TTR00, transistor TTR01, and transistor TTR0n are provided.

  Transfer transistor TG1, transfer transistor TG2, transfer transistor TG00, transfer transistor TG01, transfer transistor TG0n, transistor TR1, transistor TR2, transistor TR00, transistor TR01, transistor TR0n, transistor TTR1, transistor TTR00, transistor TTR01, transistor TTR01, and transistor TTR0n Is an Nch MOS transistor.

  Here, the transfer transistor TG00, the transfer transistor TG01,..., The transfer transistor TG0n are (n + 1). The first transistors TR00, TR01,..., And transistor TR0n are (n + 1) transistors. The second transistors, ie, transistor TTR00, transistor TTR01,..., Transistor TTR0n are (n + 1) transistors. Here, the first and second transistors are provided for evaluating the characteristics of the transfer transistor.

  The block decoder 21 generates a control signal for controlling the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 when the semiconductor memory device 90 is in a normal operation.

  The switching unit 23 transmits control signals output from the block decoder 21 when the semiconductor memory device 90 is in a normal operation to the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2. Output to the gate. The switching unit 23 uses the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 to evaluate the external voltage Vext input via the external terminal Pad when evaluating the characteristics. Output to the gates of TG1, transfer transistor TG2, transfer transistor TG00, transfer transistor TG01, transfer transistor TG0n, and transfer transistor TG2.

  Note that one external terminal Padex is shown in FIGS. 1 and 2, but is not necessarily limited thereto. Two or more external terminals Padex may be arranged.

  The control unit 22 controls the transistor TR00, the transistor TR01,..., The transistor TR0n as the first transistors, and the transistors TTR00, the transistors TTR01,. Is generated.

  The driver 241, the driver 242, the driver 250, the driver 251, and the driver 25n output signals for activating the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, and the transfer transistor TG0n to the drive signal line side. To do. There are (n + 1) drivers 250, 251 and 25n.

  The transfer transistor TG1 has a first terminal (one of the source and the drain) connected to the drive signal line SGD, a second terminal (the other of the source and the drain) connected to the selection gate line SG1, and a gate connected to the signal line SS1. Is connected to the switching unit 23.

  The transistor TR1 has a first terminal (drain) connected to the drive signal line SGD, a second terminal (source) connected to the low potential power supply (ground potential) Vss, and a gate controlled via the signal line S1. Connected to the unit 22.

  The transistor TTR1 has a first terminal (one of the source and the drain) connected to the selection gate line SG1, a second terminal (the other of the source and the drain) connected to the bit line BL0, and a gate via the signal line S1. Connected to the control unit 22.

  The transfer transistor TG00 has a first terminal (one of the source and the drain) connected to the drive signal line CG0, a second terminal (the other of the source and the drain) connected to the word line WL0, and a gate connected to the signal line SS00. To the switching unit 23.

  The transistor TR00 has a first terminal (drain) connected to the drive signal line CG0, a second terminal (source) connected to the low potential side power supply (ground potential) Vss, and a gate controlled via the signal line S00. Connected to the unit 22.

  The transistor TTR00 has a first terminal (one of the source and the drain) connected to the word line WL0, a second terminal (the other of the source and the drain) connected to the bit line BL0, and a gate via the signal line S00. Connected to the controller 22.

  The transfer transistor TG01 has a first terminal (one of the source and the drain) connected to the drive signal line CG1, a second terminal (the other of the source and the drain) connected to the word line WL1, and a gate connected to the signal line SS01. To the switching unit 23.

  The transistor TR01 has a first terminal (drain) connected to the drive signal line CG1, a second terminal (source) connected to the low potential power source (ground potential) Vss, and a gate controlled via the signal line S01. Connected to the unit 22.

  The transistor TTR01 has a first terminal (one of the source and the drain) connected to the word line WL1, a second terminal (the other of the source and the drain) connected to the bit line BL0, and a gate via the signal line S01. Connected to the controller 22.

  The transfer transistor TG0n has a first terminal (one of the source and the drain) connected to the drive signal line CGn, a second terminal (the other of the source and the drain) connected to the word line WLn, and a gate connected to the signal line SS0n. To the switching unit 23.

  The transistor TR0n has a first terminal (drain) connected to the drive signal line CGn, a second terminal (source) connected to the low potential side power supply (ground potential) Vss, and a gate controlled via the signal line S0n. Connected to the unit 22.

  The transistor TTR0n has a first terminal (one of the source and the drain) connected to the word line WLn, a second terminal (the other of the source and the drain) connected to the bit line BL0, and a gate via the signal line S0n. Connected to the controller 22.

  The transfer transistor TG2 has a first terminal (one of the source and the drain) connected to the drive signal line SGS, a second terminal (the other of the source and the drain) connected to the selection gate line SG2, and a gate connected to the signal line SS2. Is connected to the switching unit 23.

  The transistor TR2 has a first terminal (drain) connected to the drive signal line SGS, a second terminal (source) connected to the low potential side power supply (ground potential) Vss, and a gate controlled via the signal line S2. Connected to the unit 22.

  The transistor TTR2 has a first terminal (one of the source and the drain) connected to the selection gate line SG2, a second terminal (the other of the source and the drain) connected to the bit line BL0, and a gate via the signal line S2. Connected to the control unit 22.

  The memory cell block 11 is provided with a memory cell MC0, a memory cell MC1, and a memory cell MCm. The memory cell MC0, the memory cell MC1,..., The memory cell MCm is composed of (m + 1) pieces.

  Memory cell MC0 has one end connected to bit line BL0 and the other end connected to source line SL. In the memory cell MC0, a selection transistor SGT10 connected to the bit line BL0, a memory cell transistor MCT00, a memory cell transistor MCT10,..., A memory cell transistor MCTn0, and a selection transistor SGT20 connected to the source line SL are connected in series. The

  Memory cell MC1 has one end connected to bit line BL1 and the other end connected to source line SL. In the memory cell MC1, a selection transistor SGT11 connected to the bit line BL1, a memory cell transistor MCT01, a memory cell transistor MCT11,..., A memory cell transistor MCTn1, and a selection transistor SGT21 connected to the source line SL are connected in series. The

  Memory cell MCm has one end connected to bit line BLm and the other end connected to source line SL. In the memory cell MCm, a selection transistor SGT1m connected to the bit line BLm, a memory cell transistor MCT0m, a memory cell transistor MCT1m,..., A memory cell transistor MCTnm, and a selection transistor SGT2m connected to the source line SL are connected in series. The

  The selection gate line SG1 is connected to the gates of the selection transistor SGT10, the selection transistor SGT11, and the selection transistor SGT1m. The selection gate line SG2 is connected to the gates of the selection transistor SGT20, the selection transistor SGT21, and the selection transistor SGT2m.

  The word line WL0 is connected to the gates of the memory cell transistor MCT00, the memory cell transistor MCT01, and the memory cell transistor MCT0m. The word line WL1 is connected to the gates of the memory cell transistor MCT10, the memory cell transistor MCT11, and the memory cell transistor MCT1m. Word line WLn is connected to the gates of memory cell transistor MCTn0, memory cell transistor MCTn1, and memory cell transistor MCTnm.

  Here, the selection transistor SGT10, the selection transistor SGT11, the selection transistor SGT1m, the selection transistor SGT20, the selection transistor SGT21, and the selection transistor SGT2m are configured by Nch MOS transistors. The memory cell transistor MCT00, the memory cell transistor MCT01, the memory cell transistor MCT0m, the memory cell transistor MCT10, the memory cell transistor MCT11, the memory cell transistor MCT1m, the memory cell transistor MCTn0, the memory cell transistor MCTn1, and the memory cell transistor MCTnm are stacked gate structures. Transistor.

  Next, characteristic evaluation of the transfer transistor will be described with reference to FIGS. FIG. 3 is a flowchart showing characteristic evaluation of the transfer transistor. FIG. 4 is a diagram for explaining the characteristic evaluation of the transfer transistor. FIG. 5 is a diagram showing a Vth evaluation result of the transfer transistor.

  As shown in FIG. 3, the semiconductor memory device 90 is powered on and power-on read is executed. For example, various parameter information is loaded into the register from the ROM fuse block, and the circuit enters an operating state and is initialized (STEP 1).

  Next, a dedicated command for reading the characteristics (for example, threshold voltage Vth) of the transfer transistor connected to the word line and the selection gate line is input (STEP 2).

  Subsequently, the external voltage Vext is input to the gate of the transfer transistor via the external terminal Padex and the switching unit 23 (STEP 3).

  Then, a control signal is output from the control unit 22 to the gates of the first and second transistors to turn on the first and second transistors. In this state, the threshold voltage (Vth) of the transfer transistor is measured by changing the external voltage Vext and causing a current to flow between the bit line and the low potential side power supply (ground potential) Vss.

  For example, as shown in FIG. 4, in the case of evaluating the characteristics of the transfer transistor TG01, the drive signal line CG1 is set to the “High” level, the signal line S01 is set to the “High” level, and the external voltage Vext is applied to the gate of the transfer transistor TG01. To do. With this setting, the transistor TR01 as the first transistor and the transistor TTR01 as the second transistor are turned on. The threshold value of the transfer transistor TG01 is changed by changing the external voltage Vext applied to the gate of the transfer transistor TG01 and causing a current to flow through the bit line BL0⇒transistor TTR01⇒transfer transistor TG01⇒transistor TR01⇒low-potential power supply (ground potential) Vss. The voltage (Vth) is measured. Although not shown, the threshold voltages (Vth) of the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG0n, and the like are sequentially measured by the same setting (STEP 4).

  Next, it is determined whether the acquired threshold voltage (Vth) of the transfer transistor satisfies a predetermined standard. Since the transfer transistor has the same structure as the selection transistor, it has the same threshold voltage (Vth) distribution. For this reason, it is necessary to determine the threshold voltage (Vth) of the transfer transistor in the same manner as the selection transistor, and to screen for a transistor that does not satisfy the standard.

  For example, a transfer transistor that does not satisfy the lower limit specification of the threshold voltage (Vth) shown in FIG. 5A and a transfer transistor that does not satisfy the upper limit specification of the threshold voltage (Vth) shown in FIG. ).

  Subsequently, when the transfer transistor does not satisfy the predetermined threshold voltage (Vth) standard, the memory cell block connected to the transfer transistor is subjected to bad block processing (use prohibition processing). For example, the memory cell block is registered in a bad block table provided in the memory space of the semiconductor memory device 90 and is prohibited from use (STEP 6).

  The memory cells connected to the word lines (WL) and select gate lines that may lead to poor reliability by executing the above STEP 1 to 6 for all the memory cell blocks provided in the semiconductor memory device 90 Block screening is possible.

  As described above, in the semiconductor memory device and the test method thereof according to the present embodiment, the memory cell array 1, row decoder 2, sense amplifier circuit 3, column decoder 4, address register 5, data input / output buffer 6, controller 7, internal voltage A generation circuit 8 and an external terminal Padex are provided. The memory cell block 11 is provided with a memory cell MC0, a memory cell MC1, and a memory cell MCm. When evaluating the characteristics of the transfer transistor, the first and second transistors are turned on and the external voltage Vext input to the gate of the transfer transistor is changed to change the bit line ⇒ second transistor ⇒ transfer transistor ⇒ first transistor ⇒Measure the threshold voltage (Vth) of the transfer transistor by passing a current through the low potential side power supply (ground potential) Vss.

  Therefore, it is possible to directly evaluate the presence / absence of characteristic abnormality of the transfer transistor. Therefore, screening of the memory cell block connected to the word line (WL) and the select gate line that may lead to a reliability failure of the semiconductor memory device 90 can be executed.

  In this embodiment, the first transistor (transistors TR1, TR2, TR00 to Tr0n) provided on the driver side of the transfer transistor and the second transistor (transistors TTR1, TTR2, TTR00 to Tr0n) provided on the memory cell side are used. Although Nch MOS transistors are used and Nch MOS transistors are used for the transfer transistors TG1, TG2, and TG00 to TG0n, the present invention is not necessarily limited to this. For example, a Pch MOS transistor or a transfer gate composed of a Pch MOS transistor and an Nch MOS transistor may be used.

(Second embodiment)
Next, a semiconductor memory device and a test method thereof according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing the configuration of the row decoder and the memory cell block. In this embodiment, the connection of the second transistor provided on the memory cell side is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 6, the semiconductor memory device is provided with a row decoder 2a and a memory cell block 11a. The semiconductor memory device of this embodiment has a configuration similar to that of the semiconductor memory device 90 of the first embodiment, and is a NAND flash memory.

  The row decoder 2 includes a block decoder 21a, a control unit 22, a switching unit 23a, a driver 241, a driver 242, a driver 250, a driver 251, a driver 25n, a transfer transistor TG1, a transfer transistor TG2, a transfer transistor TG00, a transfer transistor TG01, a transfer A transistor TG0n, a transistor TR1, a transistor TR2, a transistor TR00, a transistor TR01, a transistor TR0n, a transistor TTR1, a transistor TTR2, a transistor TTR00, a transistor TTR01, and a transistor TTR0n are provided.

  The block decoder 21a generates a control signal that collectively controls the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 when the semiconductor memory device is in a normal operation. .

  The switching unit 23a outputs control signals output from the block decoder 21a to the transfer transistor TG1, transfer transistor TG2, transfer transistor TG00, transfer transistor TG01, transfer transistor TG0n, and transfer transistor TG2 when the semiconductor memory device is in normal operation. Output to the gate. The switching unit 23a collects the external voltage Vext input through the external terminal Pad when evaluating the characteristics of the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2. Then, the data is output to the gates of the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2. The control signal or external voltage Vex output from the switching unit 23a is output to the gates of the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 via the signal line S21. .

  The transistor TTR00 has a first terminal (one of the source and the drain) connected to the word line WL0, a second terminal (the other of the source and the drain) connected to the bit line BL1, and a gate via the signal line S00. Connected to the controller 22.

  In the transistor TTR01, a first terminal (one of a source and a drain) is connected to the word line WL1, a second terminal (the other of the source and the drain) is connected to a bit line BL2 (not shown), and a gate is a signal line. It is connected to the control unit 22 via S01.

  The transistor TTR0n has a first terminal (one of a source and a drain) connected to the word line WLn, and a second terminal (the other of the source and the drain) connected to a bit line BL (m-1) (not shown). The gate is connected to the control unit 22 via the signal line S0n.

  The transistor TTR2 has a first terminal (one of the source and the drain) connected to the selection gate line SG2, a second terminal (the other of the source and the drain) connected to the bit line BLm, and a gate via the signal line S2. Connected to the control unit 22.

  The memory cell block 11a is provided with a memory cell MC0, a memory cell MC1, and a memory cell MCm. The memory cell block 11a is different from the memory cell block 11 of the first embodiment in connection with the second transistor.

  Next, characteristic evaluation of the transfer transistor will be described with reference to FIG. FIG. 7 is a diagram for explaining characteristic evaluation of the transfer transistor. In this embodiment, measurement of the threshold voltage (Vth) of the transfer transistor is performed collectively.

  As shown in FIG. 7, the external voltage Vext is applied to the gates of the transfer transistor TG1, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 via the external terminal Padex, the switching unit 23a, and the signal line S21. Is done.

  The drive signal line SGD, the drive signal line CG0, the drive signal line CG1, the drive signal line CGn, and the drive signal line SGS are set to the “High” level, and the signal line S1, the signal line S00, the signal line S01, the signal line S0n, And the signal line S2 are set to the “High” level, and the transistor TR1, the transistor TR00, the transistor TR01, the transistor TR0n, the transistor TR2, the transistor TTR1, the transistor TTR00, the transistor TTR01, the transistor TTR0n, and the transistor TTR2 are turned on. By changing the external voltage Vext, a current flows between the bit line and the low-potential side power supply (ground potential) Vss, and the threshold voltage (Vth) of the transfer transistor is collectively measured.

  Specifically, in the transfer transistor TG1, the threshold voltage (Vth) of the transfer transistor TG1 is measured by passing a current from the bit line BL0 → the transistor TTR1 → the transfer transistor TG1 → the transistor TR1 → the low potential side power supply (ground potential) Vss. Is done. In the transfer transistor TG00, the threshold voltage (Vth) of the transfer transistor TG00 is measured by passing a current from the bit line BL1 → the transistor TTR00 → the transfer transistor TG00 → the transistor TR00 → the low potential side power supply (ground potential) Vss. In the transfer transistor TG01, the threshold voltage (Vth) of the transfer transistor TG01 is measured by passing a current from the bit line BL2 → the transistor TTR01 → the transfer transistor TG01 → the transistor TR01 → the low potential side power supply (ground potential) Vss. In the transfer transistor TG0n, the threshold voltage (Vth) of the transfer transistor TG0n is measured by passing a current through the bit line BL (m−1) → the transistor TTR0n → the transfer transistor TG0n → the transistor TR0n → the low potential side power supply (ground potential) Vss. Is done. In the transfer transistor TG2, the threshold voltage (Vth) of the transfer transistor TG2 is measured by passing a current from the bit line BLm → the transistor TTR2 → the transfer transistor TG2 → the transistor TR2 → the low potential side power supply (ground potential) Vss. As in the first embodiment, the measured transfer transistor is subjected to threshold voltage (Vth) determination and bad block processing in the case of determination NG.

  By executing the measurement method described above for all the memory cell blocks provided with the semiconductor memory device of the present embodiment, it is connected to a word line (WL) and a select gate line that may cause a reliability failure. The memory cell block can be screened.

  As described above, in the semiconductor memory device and the test method thereof according to the present embodiment, all the first and second transistors arranged adjacent to the memory cell block 11a are turned on when the characteristics of the transfer transistor are evaluated. Bit line ⇒ second transistor ⇒ transfer transistor ⇒ first transistor ⇒ low potential side by changing external voltage Vext input to the gates of all transfer transistors arranged between the first transistor and the second transistor The threshold voltage (Vth) of the transfer transistor is measured by flowing a current to the power supply (ground potential) Vss.

  For this reason, it is possible to directly evaluate the presence or absence of characteristic abnormality of the transfer transistor more quickly than in the first embodiment. Therefore, screening of the memory cell block connected to the word line (WL) and the select gate line that may lead to a reliability failure of the semiconductor memory device can be executed.

(Third embodiment)
Next, a semiconductor memory device and a test method thereof according to the third embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing the configuration of the row decoder and the memory cell block. In this embodiment, the connection of the second transistor provided on the memory cell side is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, the semiconductor memory device is provided with a row decoder 2b and a memory cell block 11b. The semiconductor memory device of this embodiment has a configuration similar to that of the semiconductor memory device 90 of the first embodiment, and is a NAND flash memory.

  The row decoder 2b includes a block decoder 21a, a control unit 22, a switching unit 23a, a driver 241, a driver 242, a driver 250, a driver 251, a driver 25n, a transfer transistor TG1, a transfer transistor TG2, a transfer transistor TG00, a transfer transistor TG01, a transfer A transistor TG0n, a transistor TR1, a transistor TR2, a transistor TR00, a transistor TR01, a transistor TR0n, a transistor TTR1, a transistor TTR2, a transistor TTR00, a transistor TTR01, and a transistor TTR0n are provided.

  The block decoder 21a generates a control signal that collectively controls the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 when the semiconductor memory device is in a normal operation. .

  The switching unit 23a outputs control signals output from the block decoder 21a to the transfer transistor TG1, transfer transistor TG2, transfer transistor TG00, transfer transistor TG01, transfer transistor TG0n, and transfer transistor TG2 when the semiconductor memory device is in normal operation. Output to the gate. The switching unit 23a transfers the external voltage Vext input through the external terminal Pad when evaluating the characteristics of the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2. Output to the gates of the transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2. The control signal or external voltage Vext output from the switching unit 23a is output to the gates of the transfer transistor TG1, the transfer transistor TG2, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 via the signal line S21. .

  The transistor TTR1 has a first terminal (one of the source and the drain) connected to the bit line BL0, a second terminal (the other of the source and the drain) connected to the terminal portion of the selection gate line SG1, and a gate connected to the signal line. It is connected to the control unit 22 via S1. Note that the term “end portion” refers to an end portion of the select gate line SG1 that faces the transfer transistor TG1.

  The transistor TTR00 has a first terminal (one of the source and the drain) connected to the bit line BL1, a second terminal (the other of the source and the drain) connected to the terminal portion of the word line WL0, and a gate connected to the signal line S00. It is connected to the control unit 22 via Note that the term “end portion” refers to an end portion of the word line WL0 facing the transfer transistor TG00.

  The transistor TTR01 has a first terminal (one of a source and a drain) connected to the bit line BL2 (not shown), a second terminal (the other of the source and the drain) connected to a terminal portion of the word line WL1, and a gate Is connected to the control unit 22 via the signal line S01.

  In the transistor TTR0n, a first terminal (one of a source and a drain) is connected to a bit line BL (m-1) (not shown), and a second terminal (the other of the source and the drain) is a terminal portion of the word line WLn. The gate is connected to the control unit 22 via the signal line S0n.

  The transistor TTR2 has a first terminal (one of the source and the drain) connected to the bit line BLm, a second terminal (the other of the source and the drain) connected to the selection gate line SG2, and a gate via the signal line S2. Connected to the control unit 22.

  The memory cell block 11b is provided with a memory cell MC0, a memory cell MC1, and a memory cell MCm. The memory cell block 11b is different from the memory cell block 11 of the first embodiment in connection with the second transistor.

  Next, characteristic evaluation of the transfer transistor will be described with reference to FIG. FIG. 9 is a diagram for explaining characteristic evaluation of the transfer transistor. In this embodiment, the threshold voltage (Vth) measurement of the transfer transistor is collectively performed via the word line and the selection gate line. For this reason, the structure is such that the test as the wiring of the word line and the selection gate line can be performed.

  As shown in FIG. 9, the external voltage Vext is applied to the gates of the transfer transistor TG1, the transfer transistor TG00, the transfer transistor TG01, the transfer transistor TG0n, and the transfer transistor TG2 via the external terminal Padex, the switching unit 23a, and the signal line S21. Applied.

  The drive signal line SGD, the drive signal line CG0, the drive signal line CG1, the drive signal line CGn, and the drive signal line SGS are set to the “High” level, and the signal line S1, the signal line S00, the signal line S01, the signal line S0n, The signal line S2 is set to “High” level, and the transistor TR1, the transistor TR00, the transistor TR01, the transistor TR0n, the transistor TR2, the transistor TTR1, the transistor TTR00, the transistor TTR01, the transistor TTR0n, and TTR2 are turned on. By changing the external voltage Vext, a current flows between the bit line and the low-potential side power supply (ground potential) Vss, and the threshold voltage (Vth) of the transfer transistor is collectively measured.

  Specifically, in the transfer transistor TG1, the threshold voltage of the transfer transistor TG1 is caused by passing a current from the bit line BL0 → the transistor TTR1 → the selection gate line SG1 → the transfer transistor TG1 → the transistor TR1 → the low potential power supply (ground potential) Vss. (Vth) is measured. In the transfer transistor TG00, the threshold voltage (Vth) of the transfer transistor TG00 is measured by passing a current through the bit line BL1⇒transistor TTR00⇒word line WL0⇒transfer transistor TG00⇒transistor TR00⇒low potential side power supply (ground potential) Vss. The In the transfer transistor TG01, the threshold voltage (Vth) of the transfer transistor TG01 is measured by passing a current through the bit line BL2⇒transistor TTR01⇒word line WL1⇒transfer transistor TG01⇒transistor TR01⇒low potential side power supply (ground potential) Vss. The In the transfer transistor TG0n, the threshold voltage of the transfer transistor TG0n is set by passing a current through the bit line BL (m−1) → the transistor TTR0n → the word line WLn → the transfer transistor TG0n → the transistor TR0n → the low potential power supply (ground potential) Vss Vth) is measured. In the transfer transistor TG2, the threshold voltage (Vth) of the transfer transistor TG2 is measured by passing a current through the bit line BLm → the transistor TTR2 → the selection gate line SG2 → the transfer transistor TG2 → the transistor TR2 → the low potential side power supply (ground potential) Vss. Is done. As in the first embodiment, the measured transfer transistor is subjected to threshold voltage (Vth) determination and bad block processing in the case of determination NG.

  At the same time, the evaluation as the wiring of the word line and the selection gate line is also performed. One example will be described with reference to FIGS. FIG. 10 is a diagram for explaining the WL high resistance failure mode. FIG. 10 shows a case where the characteristics (threshold voltage Vth) of the transfer transistor TG00 are normal, for example, when the word line WL0 composed of the gate electrode is higher than a predetermined wiring resistance value (for example, the wiring width is reduced or the film thickness is reduced). Occurrence of thinning).

  As shown in FIG. 10, when a high resistance is added to the word line WL0, the current flowing through the bit line BL1⇒transistor TTR00⇒word line WL0⇒transfer transistor TG00⇒transistor TR00⇒low potential side power supply (ground potential) Vss As compared with the case where the word line WL0 is normal, it is greatly reduced.

  FIG. 11 is a diagram for explaining the WL open failure mode. FIG. 11 shows a case where an open portion is generated between the transfer transistor side and the terminal portion of the word line WL0 including the gate electrode.

  As shown in FIG. 11, when the word line WL0 is opened, the route of the current flowing through the bit line BL1⇒transistor TTR00⇒word line WL0⇒transfer transistor TG00⇒transistor TR00⇒low potential side power supply (ground potential) Vss is the word line Since it is interrupted by WL0, no current flows from the bit line BL1.

  FIG. 12 is a diagram for explaining a short circuit failure mode between WLs. FIG. 12 shows a case where a short circuit occurs between the word line WL0 and the adjacent word line WL1.

  As shown in FIG. 12, when the word line WL0 and the word line WL1 are short-circuited, the current flowing through the bit line BL1⇒transistor TTR00⇒word line WL0⇒transfer transistor TG00⇒transistor TR00⇒low potential side power supply (ground potential) Vss Route (current Ia) and bit line BL1⇒transistor TTR00⇒word line WL0⇒word line WL1⇒transfer transistor TG01⇒transistor TR01⇒low current side power supply (ground potential) Vss (current Ib) Occur. For this reason, the current flowing from the bit line BL1 increases.

  By executing the measurement method described above for all the memory cell blocks provided with the semiconductor memory device of the present embodiment, it is connected to a word line (WL) and a select gate line that may cause a reliability failure. It is possible to screen the memory cell block and determine the characteristics of the wiring of the word line and the selection gate line.

  As described above, in the semiconductor memory device and the test method thereof according to the present embodiment, when evaluating the characteristics of the transfer transistor, all the first and second transistors arranged adjacent to the memory cell block 11b are turned on. By changing the external voltage Vext input to the gates of all transfer transistors arranged between the first transistor and the second transistor, the bit line ⇒ second transistor ⇒ selection gate line or word line ⇒ transfer transistor ⇒ first One transistor ⇒ the threshold voltage (Vth) of the transfer transistor is measured by passing a current to the low potential side power supply (ground potential) Vss, and at the same time, the wiring characteristics of the selection gate line and the word line are measured.

  For this reason, it is possible to directly evaluate the presence or absence of characteristic abnormality of the transfer transistor more quickly than the first embodiment, and at the same time, it is possible to directly evaluate the wiring characteristics of the selection gate line and the word line. Therefore, screening of the memory cell block connected to the word line (WL) and the select gate line that may lead to a reliability failure of the semiconductor memory device can be executed.

  In the embodiment, the semiconductor memory device is a NAND flash memory in which the bit lines BL and the word lines WL are arranged in a matrix, but the present invention is not necessarily limited to this. For example, DRAM (dynamic random access memory), SRAM (static random access memory), PRAM (phase-change random access memory), MRAM (magnetic random access memory), RRAM (resistance random access memory), or FeRAM (ferroelectric random access memory) memory).

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Memory cell array 2, 2a, 2b Row decoder 3 Sense amplifier circuit 4 Column decoder 5 Address register 6 Data input / output buffer 7 Controller 8 Internal voltage generation circuit 11, 11a, 11b Memory cell block 21, 21a Block decoder 22 Control part 23, 23a switching unit 90 semiconductor memory device 241, 242, 250, 252, 25n driver add address BL0, BL1, BLm bit line CMD command CG0, CG1, CGn, SGD, SGS drive signal line Data data I / O Data input / output data MC0 , MC1, MCm Memory cells MCT00-0m, MCT10-1m, MCTn0-nm Memory cell transistor Padex External terminals S1, S2, S00-0n, S21, SS1, SS2, SS00-0n Line SG1, SG2 Selection gate line SL Source line Sso External control signal SGT10-1m, SGT20-2m Selection transistor TG1, TG2, TG00-0n Transfer transistor TR1, TR2, TR00-0n, TTR1, TTR2, TTR00-0n Transistor Vext External Voltage Vss Low potential side power supply (ground potential)
WL0-n word lines

Claims (6)

A switching unit;
The first terminal is connected to the first drive signal line, the second terminal is connected to the word line, and the first control signal is input to the gate when the switching unit is in the first state, and the switching A first transfer transistor in which an external voltage is applied to the gate when the portion is in the second state;
A first transistor having a first terminal connected to the first drive signal line, a second terminal connected to a low-potential side power supply, and a second control signal input to the gate;
A second transistor having a first terminal connected to the word line, a second terminal connected to the bit line, and a gate to which the second control signal is input;
The first and second transistors are turned off when the switching unit is in the first state, the first transfer transistor is turned on, and the first transistor is turned on when the switching unit is in the second state. And a second transistor is turned on. The first terminal is connected to the second drive signal line, the second terminal is connected to the selection gate line, and the first control signal is input to the gate when the switching unit is in the first state, A second transfer transistor in which the external voltage is applied to the gate when the switching unit is in the second state;
A third transistor in which a first terminal is connected to the second drive signal line, a second terminal is connected to the low-potential-side power supply, and a third control signal is input to the gate;
A fourth transistor in which a first terminal is connected to the selection gate line, a second terminal is connected to the bit line, and the third control signal is input to a gate;
The third and fourth transistors are turned off when the switching unit is in the first state, the second transfer transistor is turned on, and the second transistor is turned on when the switching unit is in the second state. 3. The semiconductor memory device according to claim 1, wherein the third and fourth transistors are turned on. A switching unit;
The first terminal is connected to the first drive signal line, the second terminal is connected to the word line, and the first control signal is input to the gate when the switching unit is in the first state, and the switching A first transfer transistor in which an external voltage is applied to the gate when the portion is in the second state;
A first transistor having a first terminal connected to the first drive signal line, a second terminal connected to a low-potential side power supply, and a second control signal input to the gate;
A second transistor having a first terminal connected to the first bit line, a second terminal connected to a termination portion of the word line, and a gate to which the second control signal is input;
The first and second transistors are turned off when the switching unit is in the first state, the first transfer transistor is turned on, and the first transistor is turned on when the switching unit is in the second state. And a second transistor is turned on. The first terminal is connected to the second drive signal line, the second terminal is connected to the selection gate line, and the first control signal is input to the gate when the switching unit is in the first state, A second transfer transistor in which an external voltage is applied to the gate when the switching unit is in the second state;
A third transistor in which a first terminal is connected to the second drive signal line, a second terminal is connected to the low-potential-side power supply, and a third control signal is input to the gate;
A fourth transistor in which a first terminal is connected to a second bit line, a second terminal is connected to a terminal portion of the selection gate line, and the third control signal is input to a gate;
The third and fourth transistors are turned off when the switching unit is in the first state, the second transfer transistor is turned on, and the second transistor is turned on when the switching unit is in the second state. 4. The semiconductor memory device according to claim 3, wherein the third and fourth transistors are turned on. Memory cells are arranged in a matrix, a transfer transistor provided between a drive signal line and a word line, a first transistor provided between the drive signal line and a low-potential side power source, and the word line and the bit line A method of testing a semiconductor memory device in which a second transistor provided therebetween is provided in a row decoder,
Inputting a command for evaluating the characteristics of the transfer transistor;
Applying an external voltage to the gate of the transfer transistor via an external terminal;
Turning on the first and second transistors using the characteristic evaluation command, and passing a current between the bit line and the low-potential side power source to measure a threshold voltage of the transfer transistor;
A method for testing a semiconductor memory device, comprising: Determining whether the measured threshold voltage satisfies a predetermined standard;
If the predetermined standard is not satisfied, a step of performing a bad block process on the memory cell block connected to the transfer transistor;
The method of testing a semiconductor memory device according to claim 5, further comprising:

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