JP2013016986A - Latch circuit, divider circuit, flip-flop circuit, pll circuit, multiplexer, and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a latch circuit capable of suppressing a circuit scale and power consumption by receiving CML level clock and outputting CMOS level data because level conversion is required for accommodating, at a CMOS level, an output of a divider circuit using the latch circuit for outputting CML level data.SOLUTION: The latch circuit is cross-connected to the drain terminal of an N-channel type MOS transistor receiving differential input data and the gate terminal of a P-channel type MOS transistor. CML level data is converted to CMOS level data in this way.

Description

  The present invention relates to a latch circuit, a frequency divider circuit, a flip-flop circuit, a PLL (Phase Locked Loop) circuit, a multiplexer, and a semiconductor integrated circuit. In particular, the present invention relates to a latch circuit, a frequency divider circuit, a flip-flop circuit, a PLL circuit, a multiplexer, and a semiconductor integrated circuit that receive data and a clock at a CML (Current Mode Logic) level.

  Latch circuits are used in circuits of various electronic devices. Further, a frequency divider circuit or a flip-flop circuit can be formed using a latch circuit. Many latch circuits operate by receiving CML level data and clocks.

  For example, Patent Document 1 discloses a latch circuit using a CML circuit composed of bipolar transistors.

  Further, Patent Document 2 discloses a flip-flop circuit and a frequency divider circuit that can operate at high speed by connecting a plurality of latch circuits in a master / slave configuration.

  Further, Patent Document 3 discloses a circuit called a dynamic latch (or direct latch). The dynamic latch disclosed in Patent Document 3 can realize a track mode in which precharging is performed when the clock is at the L level and a latch mode in which data is output when the clock is at the H level.

Japanese Patent Laid-Open No. 9-018312 JP 2009-246639 A JP 2001-189648 A

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  The frequency dividing circuit using the latch circuit disclosed in Patent Documents 1 and 2 accepts a CML level clock and outputs a CML level clock. In order to use the output clock of the frequency dividing circuit using the latch circuit disclosed in Patent Documents 1 and 2 in a circuit having a CMOS (Complementary Metal Oxide Semiconductor) level interface, level conversion is required. This causes an increase in the circuit scale and power consumption of the semiconductor integrated circuit including the frequency divider circuit and the subsequent circuit. Further, since the frequency dividing circuit itself operates at the CML level, there is a problem that a steady current is required and the power consumption of the frequency dividing circuit itself is large. Therefore, a latch circuit, a frequency dividing circuit, a flip-flop circuit, a PLL circuit, a multiplexer, and a semiconductor integrated circuit that realize a reduction in circuit scale and power consumption by receiving a CML level clock and outputting CMOS level data include: desired.

  According to a first aspect of the present invention, a first first conductivity type transistor that receives a first clock by a gate terminal, a source terminal connected to a drain terminal of the first first conductivity type transistor, and a gate A second first conductivity type transistor that receives first input data through a terminal, a source terminal connected to a drain terminal of the first first conductivity type transistor, and a gate terminal that is opposite to the first input data. A third first-conductivity-type transistor that accepts second input data in phase, a drain terminal connected to the drain terminal of the second first-conductivity-type transistor, and a gate terminal that is the third first-conductivity type A first second conductivity type transistor connected to a drain terminal of the transistor, and a drain terminal of the third first conductivity type transistor; A second second-conductivity type transistor having a gate terminal connected to a drain terminal of the second first-conductivity type transistor, and a second second-phase transistor having a phase opposite to the first clock by the gate terminal. A fourth first conductivity type transistor that receives a clock, a source terminal is connected to a drain terminal of the fourth first conductivity type transistor, and a gate terminal is connected to a drain terminal of the first second conductivity type transistor. A fifth first conductivity type transistor whose drain terminal is connected to the drain terminal of the second second conductivity type transistor, and a source terminal connected to the drain terminal of the fourth first conductivity type transistor; The gate terminal is connected to the drain terminal of the second second conductivity type transistor, and the drain terminal is the drain of the first second conductivity type transistor. A sixth transistor of the first conductivity type which is connected to the terminal, the latch circuit comprising a are provided.

  According to a second aspect of the present invention, there is provided a frequency divider circuit composed of the above-described latch circuit.

  According to a third aspect of the present invention, there is provided a flip-flop circuit composed of the above-described latch circuit.

  According to a fourth aspect of the present invention, there is provided a PLL circuit that divides the output of the voltage control oscillator by the above-described frequency dividing circuit.

  According to a fifth aspect of the present invention, there is provided a multiplexer including the above-described flip-flop circuit.

  According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit including a SERDES macro including at least one of the above PLL circuit or the above multiplexer.

  According to each aspect of the present invention, a latch circuit, a frequency dividing circuit, a flip-flop circuit, a PLL circuit, which realizes suppression of circuit scale and power consumption by receiving a CML level clock and outputting CMOS level data, Multiplexers and semiconductor integrated circuits are provided.

It is a figure which shows an example of the circuit structure of the latch circuit which concerns on the 1st Embodiment of this invention. 10 is a circuit diagram of a latch circuit that receives a CML level clock disclosed in Patent Document 1. FIG. It is a figure which shows the structure of the conventional dynamic latch circuit (FIG. 1 of patent document 3). It is a figure which shows an example of the circuit structure of the latch circuit which concerns on the 2nd Embodiment of this invention. FIG. 5 is a diagram for explaining the operation of the latch circuit shown in FIG. 4. It is a figure which shows an example of the internal structure of the frequency divider circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows an example of the output waveform of the frequency divider shown in FIG. It is a figure which shows another example of the output waveform of the frequency divider circuit shown in FIG. It is a figure which shows another example of the output waveform of the frequency divider circuit shown in FIG. 6 is a diagram illustrating an internal configuration of a frequency dividing circuit disclosed in Patent Document 2. FIG. It is a figure which shows an example of the internal structure of the flip-flop circuit which concerns on the 4th Embodiment of this invention. It is a figure which shows an example of the output waveform of the flip-flop circuit shown in FIG. It is a figure which shows another example of the output waveform of the flip-flop circuit shown in FIG. It is a figure which shows an example of a circuit structure of the flip-flop circuit shown in FIG. It is a figure which shows an example of the circuit structure of a flip-flop circuit. It is a figure which shows an example of the internal structure of NIC which uses the semiconductor integrated circuit carrying a SERDES macro. It is a figure for demonstrating the layout of the semiconductor integrated circuit carrying a SERDES macro. It is an example of a layout diagram of a semiconductor integrated circuit on which a SERDES macro is mounted. It is a figure which shows an example of the outline of a SERDES macro. FIG. 20 is a block diagram illustrating an example of an internal configuration of a PLL unit illustrated in FIG. 19. FIG. 20 is a block diagram illustrating an example of an internal configuration when the frequency dividing circuit illustrated in FIG. 6 is used in the PLL unit illustrated in FIG. 19. It is a figure which shows an example of the layout of the whole SERDES macro. It is the figure which expanded the dotted-line part of FIG. It is the figure which expanded the dotted-line part of FIG. 22 at the time of using the frequency divider shown in FIG. 6 for a SERDES macro. It is a figure which shows an example of the outline of a SERDES macro. FIG. 26 is a diagram showing an example of an internal configuration when the flip-flop circuit shown in FIG. 11 is used for the multiplexer shown in FIG. It is a figure which shows an example of the layout of the whole SERDES macro. It is a figure which shows an example of the layout of the highest layer of the whole SERDES macro.

  First, the outline of the embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, level conversion is required to handle the output of the frequency divider using the latch circuit that outputs CML level data at the CMOS level. In order to realize this level conversion, a level shifter is required, and there is a problem that the circuit scale and power consumption of a semiconductor integrated circuit including a frequency divider circuit are increased. Therefore, a latch circuit that receives a CML level clock and outputs CMOS level data to achieve a reduction in circuit scale and power consumption is desired.

  Therefore, as an example, the latch circuit shown in FIG. 1 is provided. In the latch circuit shown in FIG. 1, the drain terminals of N-channel MOS transistors (MN03 and MN04) that receive differential input data are cross-connected to the gate terminals of P-channel MOS transistors (MP01 and MP02). In this way, CML level data is converted to CMOS level data.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 1 is a diagram illustrating an example of a circuit configuration of a latch circuit 10 according to the present embodiment.

  The latch circuit 10 shown in FIG. 1 includes N-channel MOS transistors MN01 to MN06 and P-channel MOS transistors MP01 and MP02.

  The source terminal of the N-channel MOS transistor MN01 is connected to the ground voltage VSS, the gate terminal is connected to the clock input terminal CLKP, and the drain terminal is commonly connected to the source terminals of the N-channel MOS transistors MN03 and MN04. A connection point between the drain terminal of the N-channel MOS transistor MN01 and the source terminals of the N-channel MOS transistors MN03 and MN04 is defined as a node S1.

  The source terminal of the N-channel MOS transistor MN02 is connected to the ground voltage VSS, the gate terminal is connected to the clock input terminal CLKN, and the drain terminal is commonly connected to the source terminals of the N-channel MOS transistors MN05 and MN06. A connection point between the drain terminal of the N-channel MOS transistor MN02 and the source terminals of the N-channel MOS transistors MN05 and MN06 is defined as a node S2.

  The gate terminal of the N-channel MOS transistor MN03 is connected to the data input terminal INP, and the drain terminal is connected to the drain terminal of the P-channel MOS transistor MP01 and the gate terminal of the P-channel MOS transistor MP02. A connection point between the drain terminal of the N-channel MOS transistor MN03, the drain terminal of the P-channel MOS transistor MP01, and the gate terminal of the P-channel MOS transistor MP02 is defined as a node S3.

  The gate terminal of the N-channel MOS transistor MN04 is connected to the data input terminal INN, and the drain terminal is connected to the drain terminal of the P-channel MOS transistor MP02 and the gate terminal of the P-channel MOS transistor MP01. A connection point between the drain terminal of the N-channel MOS transistor MN04, the drain terminal of the P-channel MOS transistor MP02, and the gate terminal of the P-channel MOS transistor MP01 is defined as a node S4. The node S4 is a data output terminal OUTP, and the node S3 is a data output terminal OUTN.

  The gate terminal of the N-channel MOS transistor MN05 is connected to the data output terminal OUTN (node S3), and the drain terminal is connected to the data output terminal OUTP (node S4). Similarly, the gate terminal of the N-channel MOS transistor MN06 is connected to the data output terminal OUTP (node S4), and the drain terminal is connected to the data output terminal OUTN (node S3).

  The source terminals of the P-channel MOS transistors MP01 and MP02 are connected to the power supply voltage VDD. The latch circuit 10 receives the differential clock at the clock input terminals CLKP and CLKN. Further, the differential input data is received by the data input terminals INP and INN, and the differential output data is output from the data output terminals OUTP and OUTN.

  Next, the operation of the latch circuit 10 will be described. The clock received at the clock input terminals CLKP and CLKN is set to the CML level, and the data received at the data input terminals INP and INN is also set to the CML level.

  First, an operation when H level data (data input terminal INN is L level) is input to the data input terminal INP and an H level clock (clock input terminal CLKN is L level) is input to the clock input terminal CLKP. explain.

  When the H level is input to the clock input terminal CLKP, the N-channel MOS transistor MN01 is turned on, and the drain voltage (the voltage at the node S1) of the N-channel MOS transistor MN01 gradually decreases. When the voltage at the node S1 decreases and the gate-source voltage of the N-channel MOS transistor MN03 exceeds the threshold voltage of the N-channel MOS transistor (hereinafter referred to as Vthn), the N-channel MOS transistor MN03 is turned on. Become. As a result, the drain voltage of the N-channel MOS transistor MN03 (the voltage at the node S3) decreases. When the voltage at the node S3 decreases and the gate-source voltage of the P-channel MOS transistor MP02 exceeds the threshold voltage of the P-channel MOS transistor (hereinafter referred to as Vthp), the P-channel MOS transistor MP02 is turned on. . Then, the data output terminal OUTP (the voltage at the node S4) rises to substantially the power supply voltage VDD (H level).

  On the other hand, since the voltage of the node S4 rises to the power supply voltage VDD, the P-channel MOS transistor MP01 is turned off. Since the N-channel MOS transistors MN01 and MN03 are on, the voltage at the node S3 is substantially equal to the ground voltage VSS. Therefore, the data output terminal OUTN (the voltage at the node S3) is at the L level.

  As described above, by connecting the drain terminals of the N-channel MOS transistors MN03 and MN04 to the gate terminals of the P-channel MOS transistors MP01 and MN02, it is possible to output CMOS level data from the data output terminals OUTP and OUTN. become.

  Next, the operation when L level data (data input terminal INN is H level) is input to the data input terminal INP and L level clock (clock input terminal CLKN is L level) is input to the clock input terminal CLKP. explain. At this time, the latch circuit 10 needs to maintain the output when the clock input terminal CLKP is at the H level. When the L level is input to the clock input terminal CLKP, the N-channel MOS transistor MN01 is turned off. On the other hand, since the clock input terminal CLKN becomes H level, the N-channel MOS transistor MN02 is turned on. As a result, the drain voltage of the N-channel MOS transistor MN02 (the voltage at the node S2) decreases. At this time, since the voltage of the node S3 is L level and the voltage of the node S4 is H level, the N-channel MOS transistor MN05 is turned off and the N-channel MOS transistor MN06 is turned on. Therefore, the voltage at the node S3 maintains the L level, and the voltage at the node S4 maintains the H level.

  As described above, the N-channel MOS transistor MN02 is operated with a reverse-phase clock, and the gate terminals and drain terminals of the N-channel MOS transistors MN05 and MN06 are interchanged to enable a latch operation.

  FIG. 2 is a circuit diagram of a latch circuit that receives a CML level clock disclosed in Patent Document 1. In FIG. In the latch circuit shown in FIG. 2, the data output from the data output terminals OUTP and OUTN is also at the CML level. Therefore, when the latch circuit shown in FIG. 2 is used as a frequency dividing circuit and the subsequent circuit is operated at the CMOS level, it is necessary to convert the data output to the CMOS level. Therefore, a level shifter is required, and the circuit scale and power consumption of the frequency divider circuit increase. Furthermore, the fact that the resistance elements R1 and R2 are necessary for the latch circuit shown in FIG. 2 is one factor that increases the circuit scale.

  In addition, the latch circuit shown in FIG. 2 uses a steady current and consumes a large amount of power. Furthermore, the power consumption is constant regardless of the clock frequency. On the other hand, the latch circuit 10 according to the present embodiment can receive a CML level clock and output it as CMOS level data. Therefore, when the latch circuit 10 is used as a frequency dividing circuit, a level shifter is not required after the frequency dividing circuit, and the circuit scale and power consumption can be reduced. Further, when the clock frequency is low, the power consumption of the latch circuit 10 is reduced. This is because current flows only when the N-channel MOS transistors MN01 and MN02 are in the on state.

  FIG. 3 is a diagram showing a configuration of the dynamic latch circuit disclosed in Patent Document 3 (FIG. 1 of Patent Document 3). In the dynamic latch circuit shown in FIG. 3, it is necessary to input a CMOS level clock. However, in the latch circuit 10 according to the present embodiment, it is possible to input either a CMOS level clock or a CML level clock. Therefore, the latch circuit 10 can be used for circuits for various purposes.

  Further, output data cannot be latched only by the dynamic latch circuit shown in FIG. This is because when the clock is at L level, both differential output data are at L level. However, the latch circuit 10 does not have a state in which the differential output data is both at the L level or the H level, and the held data can be continuously output.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings. FIG. 4 is a diagram illustrating an example of a circuit configuration of the latch circuit 20 according to the present embodiment. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  The difference between the latch circuit 20 shown in FIG. 4 and the latch circuit 10 shown in FIG. 1 is that N-channel MOS transistors MN07 to MN10 are added and selection terminals SEL0 and SEL1 are provided. The source terminals of the N-channel MOS transistors MN07 and MN09 are connected to the drain terminal of the N-channel MOS transistor MN03, and the drain terminals of the N-channel MOS transistors MN07 and MN09 are connected to the drain terminal of the P-channel MOS transistor MP01. Further, the gate terminal of the N-channel MOS transistor MN07 is connected to the selection terminal SEL0, and the gate terminal of the N-channel MOS transistor MN09 is connected to the selection terminal SEL1. Similarly, the N channel type MOS transistors MN08 and MN10 are connected between the N channel type MOS transistor MN04 and the P channel type MOS transistor MP02.

  A connection point between the source terminals of the N-channel MOS transistors MN07 and MN09 and the drain terminal of the N-channel MOS transistor MN03 is a node S5. A connection point between the drain terminals of the N-channel MOS transistors MN07 and MN09 and the drain terminal of the P-channel MOS transistor MP01 is a node S7. A connection point between the source terminals of the N-channel MOS transistors MN08 and MN10 and the drain terminal of the N-channel MOS transistor MN04 is a node S6. A connection point between the drain terminals of the N-channel MOS transistors MN08 and MN10 and the drain terminal of the P-channel MOS transistor MP02 is a node S8.

  In the latch circuit 10 according to the first embodiment, a case where a high-frequency clock is input to the clock input terminals CLKP and CLKN, or a case where the input data and the clock have a small amplitude may not be operated correctly.

  The first reason is that fluctuations in the gate-source voltage of the P-channel MOS transistors MP01 and MP02 cannot follow the clock frequency. This is because the clock changes before the P-channel MOS transistors MP01 and MP02 change to the on state or the off state.

  Next, as a second reason, when the input data and the clock have a small amplitude, the increase in the drain voltage of the N-channel MOS transistors MN01 to MN04 cannot follow the clock frequency. When a circuit connected to the previous stage of the latch circuit 10 outputs CML level input data and a clock, the power supply voltage VDD is often used as a reference. That is, the H level of the input data and the clock is set to VDD, and the L level is set to VDD−single phase amplitude. In such a usage mode, if the amplitude width of the input data and the clock is small, the gate voltages of the N-channel MOS transistors MN01 to MN04 always fluctuate in the vicinity of the power supply voltage VDD. As a result, the drain voltages of the N-channel MOS transistors MN01 to MN04 are pulled in the direction of the ground voltage VSS not only when the input data and the clock are at the H level but also at the L level. Therefore, when the amplitude width of the input data and the clock is small, the time for the drain voltages of the N-channel MOS transistors MN01 to MN04 to rise increases. If the time during which the drain voltage rises becomes long, it may be assumed that the clock cannot be changed.

  In order to solve these problems, in the latch circuit 20 according to the present embodiment, N-channel MOS transistors MN07 to MN10 are added.

  Next, the operation of the latch circuit 20 will be described. First, an operation when an H level clock (data input terminal INN is L level) is input to the data input terminal INP and an H level clock (clock input terminal CLKN is L level) is input to the clock input terminal CLKP. explain. Note that the selection terminal SEL0 = 1 (H level) and the selection terminal SEL1 = 0 (L level).

  When the H level is input to the clock input terminal CLKP, the N-channel MOS transistor MN01 is turned on, and the drain voltage (the voltage at the node S1) of the N-channel MOS transistor MN01 gradually decreases. When the voltage at the node S1 decreases and the gate-source voltage of the N-channel MOS transistor MN03 exceeds the threshold voltage Vthn of the N-channel MOS transistor, the N-channel MOS transistor MN03 is turned on. As a result, the drain voltage of the N-channel MOS transistor MN03 (the voltage at the node S5) decreases.

  When the voltage at the node S5 decreases and the gate-source voltage of the P-channel MOS transistor MP02 exceeds the threshold voltage Vthp of the P-channel MOS transistor, the P-channel MOS transistor MP02 is turned on. Thereafter, the data output terminal OUTP (the voltage at the node S8) rises to substantially the power supply voltage VDD (H level). At this time, since the N-channel MOS transistor MN08 is in the on state, the voltage at the node S6 rises. When the voltage at the node S6 rises and the gate-source voltage of the N-channel MOS transistor MN08 falls below the threshold voltage Vthn, the N-channel MOS transistor MN08 is turned off. Then, the voltage fluctuation range of the node S6 is obtained from the ground voltage VSS to the power supply voltage VDD−Vthn. Since the voltage fluctuation range of the node S4 in the latch circuit 10 according to the first embodiment is the ground voltage VSS to the power supply voltage VDD, the fluctuation range of the gate voltage of the P-channel MOS transistor MP01 is reduced. Similarly, the fluctuation range of the gate voltage of the P-channel MOS transistor MP02 is also reduced.

  As described above, by setting the selection terminal SEL [1: 0] = 01, the fluctuation range of the gate voltage of the P-channel MOS transistors MP01 and MP02 can be reduced. Since the reduction in the fluctuation width of the gate voltage of the P-channel MOS transistors MP01 and MP02 is equivalent to the reduction in the fluctuation voltage of the drain voltage of the N-channel MOS transistors MN03 and MN04, the latch circuit 20 has a higher frequency clock. Even if input, it can operate.

  As described above, by setting the selection terminal SEL [1: 0] = 01 in the latch circuit 20, it becomes possible to cope with a high-frequency clock. However, depending on the rise time and fall time of the clock, the latch circuit 20 Is assumed to malfunction. In such a case, the selection terminal SEL [1: 0] = 11 is set.

  The reason why the latch circuit 20 malfunctions due to the rise and fall times of the clock will be described. In the description, it is assumed that the sine wave shown in FIG. 5 is input as a clock. At time t1 in FIG. 5, L level is input to the clock input terminal CLKP and H level is input to the clock input terminal CLKN. However, since the rising time and falling time of the input sine wave are long, the latch circuit 20 behaves as if an in-phase clock is input to the latch circuit 20 instead of a differential clock. More specifically, when a clock as shown at time t1 in FIG. 5 is input to the latch circuit 20, the N-channel MOS transistors MN01 and MN02 cannot completely transition to the on state and the off state. Since the L level is input to the clock input terminal CLKP and the H level is input to the clock input terminal CLKN, the latch circuit 20 is in a latched state, and the output of the latch circuit 20 is essentially not affected by the input data. However, since the N-channel MOS transistors MN01 and MN02 are not completely turned on and off, the output of the latch circuit 20 is affected by input data. When affected by the input data, the latch circuit 20 cannot perform the latch operation, and the latched data is inverted. If the amplitude of the clock input to the clock input terminals CLKP and CLKN increases after the output of the latch circuit 20 is inverted, the latch is determined with the output inverted. Once the latch is finalized, the correct output cannot be restored. Thus, if the clock rise time and fall time are long, the latch circuit 20 may malfunction.

  Therefore, the selection terminal SEL [1: 0] = 11 is set. When the selection terminal SEL1 = 1 is set, the N-channel MOS transistors MN09 and MN10 are turned on. This state is equivalent to an increase in the size of the N-channel MOS transistors MN07 and MN08, and can be regarded as a decrease in the on-resistance of the N-channel MOS transistors MN07 and MN08. When the on-resistances of the N-channel MOS transistors MN07 and MN08 decrease, the capacitances of the N-channel MOS transistors MN07 and MN08 as load capacitors increase. Then, it takes time to change the voltage of the data output terminals OUTP and OUTN, and before the data output terminals OUTP and OUTN are inverted due to the influence of the input data, the clock amplitude becomes large and the latch state can be determined. it can.

  As described above, by changing the setting of the selection terminal SEL [1: 0] according to the input data and the clock cycle and amplitude, the operation of the latch circuit 20 is stabilized, and at the same time, reduction of power consumption is realized. . In the latch circuit 20 according to the present embodiment, the case where the number of switching stages is 2 bits has been described. However, it is possible to perform finer settings using a larger number of bits.

[Third Embodiment]
Next, a third embodiment will be described in detail with reference to the drawings. In the present embodiment, a frequency dividing circuit 30 using the latch circuit 20 according to the second embodiment will be described.

  FIG. 6 is a diagram illustrating an example of an internal configuration of the frequency dividing circuit 30 according to the present embodiment. The frequency divider 30 shown in FIG. 6 connects the latch circuits 20 in series. The first-stage latch circuit 20 is referred to as a latch circuit 21, and the next-stage latch circuit 20 is referred to as a latch circuit 22. A clock having a phase opposite to that of the clock input to the latch circuit 21 is input to the clock input terminals (CLKP and CLKN) of the latch circuit 22. A common signal is input to the selection terminals SEL [1: 0].

  The data output terminals (OUTP and OUTN) of the latch circuit 21 are connected to the data input terminals (INP and INN) of the latch circuit 22. The data output terminal OUTP of the latch circuit 22 is connected to the data input terminal INN of the latch circuit 21, and the data output terminal OUTN of the latch circuit 22 is connected to the data input terminal INP of the latch circuit 21. That is, the data output of the latch circuit 22 is inverted and used as the data input of the latch circuit 21.

  A signal output from the data output terminal OUTP of the latch circuit 22 via the buffer B0 is referred to as OUT0. Similarly, a signal output from the data output terminal OUTN of the latch circuit 22 via the buffer B1 is output OUT180, a signal output from the data output terminal OUTN of the latch circuit 21 is output OUT90 via the buffer B2, and the buffer B3 is stored. A signal output from the data output terminal OUTP of the latch circuit 21 via this is referred to as OUT270. OUT0, OUT180, OUT90, and OUT270 are clocks (four-phase clocks) that respectively divide the input clock by two and have phase differences of 0 degrees, 180 degrees, 90 degrees, and 270 degrees with respect to the input clock. The clock received at the clock input terminals CLKP and CLKN is a CML level signal, and OUT0 to OUT270 are CMOS level signals.

  The frequency divider 30 can output a 4-phase frequency-divided clock by taking out the data outputs of the latch circuit 21 and the latch circuit 22, respectively. Further, the output waveform and the power consumption can be optimized by switching the selection terminals SEL [1: 0] according to the frequency of the clock received at the clock input terminals CLKP and CLKN.

  Next, the operation of the frequency dividing circuit 30 will be described. FIG. 7 is a diagram illustrating an example of an output waveform of the frequency dividing circuit 30 when a sine wave having a frequency of 10 GHz is input. The selection terminal SEL [1: 0] = 01 is set. FIG. 7 shows the clock input from the upper stage, the output of the latch circuit 22 (output of the data output terminals OUTP and OUTN), the output of the latch circuit 21 (output of the data output terminals OUTP and OUTN), OUT0 and OUT180, OUT90 and OUT270. ing. From FIG. 7, it can be seen that the CML level clock input can be output as a CMOS level clock.

  FIG. 8 is a diagram illustrating an example of an output waveform of the frequency dividing circuit 30 when the frequency of the sine wave input from the setting condition of FIG. 7 is 1 GHz. The signals shown in FIG. 8 are the same as the signals in FIG. In this case, since the selection terminals SEL [1: 0] = 01, the output data is erroneously inverted and cannot be normally divided (for example, time t2). At time t2 in FIG. 8, it is estimated that the event described with reference to FIG. 5 has occurred. That is, the latch circuit 22 needs to latch and output the input data at time t2, but the outputs (OUT0 and OUT180) of the latch circuit 22 are inverted immediately after time t2. At time t2, since the H level is input to the clock input terminal CLKP and the L level is input to the clock input terminal CLKN of the latch circuit 22, the latch circuit 22 is in a latch state in which the input data is output as it is. Therefore, the data output of the latch circuit 22 is inverted because the output of the latch circuit 21 is inverted. As described above, the latch circuit 20 may malfunction depending on the rise time and fall time of the clock, and it is considered that the latch circuit 21 malfunctions at time t2.

  FIG. 9 is a diagram illustrating an example of an output waveform of the frequency dividing circuit 30 when the selection terminal SEL [1: 0] = 11 is changed from the setting conditions of FIG. 9 is the same as the signal in FIG. By changing the setting, it can be seen that even a sine wave having a frequency of 1 GHz can be normally divided. If the clock rise time and fall time are short when the frequency divider circuit 30 is used, the frequency divider circuit can be used even if the setting shown in FIG. 8 (selection terminal SEL [1: 0] = 01). 30 will not malfunction. However, the clock used for the frequency dividing circuit 30 often has a high frequency of several GHz to several tens GHz. It is difficult to shorten the rise time and fall time of such a high frequency clock. Therefore, the frequency dividing circuit 30 can cope with a wide range of clocks by changing the setting of the selection terminals SEL [1: 0]. In addition, it can be set as -100mV-1.2V as an example of the voltage width of the vertical axis | shaft in FIGS.

  FIG. 10 shows a frequency dividing circuit disclosed in Patent Document 2. Since the frequency dividing circuit shown in FIG. 10 is configured using the latch circuit disclosed in Patent Document 1, a CML level clock is output. On the other hand, the frequency dividing circuit 30 according to the present embodiment receives a CML level clock, divides it into a CMOS level four-phase clock, and outputs it. Therefore, the circuit scale and the power consumption can be reduced as compared with the case where the frequency dividing circuit is configured using the CML circuit and the level conversion circuit is used thereafter.

[Fourth Embodiment]
Next, a fourth embodiment will be described in detail with reference to the drawings. In the present embodiment, it will be described that the flip-flop circuit 40 can be configured using the latch circuit 20.

  FIG. 11 shows an example of the internal configuration of the flip-flop circuit 40 according to the present embodiment. In FIG. 11, the same components as those in FIG. 6 are denoted by the same reference numerals, and the description thereof is omitted. The difference between the flip-flop circuit 40 shown in FIG. 11 and the frequency dividing circuit 30 shown in FIG. 7 is the connection of the input / output data of the latch circuits 21 and 22. In the flip-flop circuit 40, the input data signals DATAT and DATAN are received at the data input terminals INP and INN of the latch circuit 21. Further, data is output from the data output terminals OUTP and OUTN of the latch circuit 22 via the buffers B4 and B5.

  In the flip-flop circuit 40, the output data OUTP and OUTN can be at the CMOS level regardless of whether the clock input level is the CML level or the CMOS level. FIG. 12 is a diagram illustrating an example of an output waveform of the flip-flop circuit 40 when a clock having a CML level and a frequency of 10 GHz is input. FIG. 13 is a diagram illustrating an example of an output waveform of the flip-flop circuit 40 when a clock having a CMOS level and a frequency of 10 GHz is input. The transfer rate of input data is 10 Gbps. 12 and 13 show the clock input, the input data, the output of the latch circuit 22, and the output data after passing through the buffers B5 and B6. 12 and 13, it can be seen that the output data can be at the CMOS level regardless of whether the clock is at the CML level or the CMOS level. In addition, it can be set as -100mV-1.4V as an example of the voltage width of the vertical axis | shaft in FIG.12 and FIG.13.

  FIG. 14 is a diagram illustrating an example of the circuit configuration of the flip-flop circuit 40. The flip-flop circuit shown in FIG. 14 uses 18 transistors for differential input data. FIG. 15 is a diagram illustrating an example of a circuit configuration when a flip-flop circuit is configured without using the latch circuit 20. The flip-flop circuit shown in FIG. 15 requires 16 transistors for single-phase data input. Furthermore, 32 transistors are required for differential input data. As described above, the flip-flop circuit 40 according to the present embodiment requires fewer elements (transistors) and can reduce the circuit scale.

  In the flip-flop circuit 40, since the number of transistors driven by the clock is small, the load on the clock is reduced and the required power consumption is also reduced. At the same time, the transistors driven by the clock of the flip-flop circuit 40 are limited to N-channel MOS transistors. Since the P channel type MOS transistor has a larger W size in the CMOS P / N ratio, the load is reduced in this point as well, and the power consumption is reduced.

[Fifth Embodiment]
Next, a fifth embodiment will be described in detail with reference to the drawings. In the first to fourth embodiments, the latch circuit, the frequency dividing circuit, and the flip-flop circuit that receive the CML level clock and convert it to the CMOS level have been described. In the present embodiment, a semiconductor integrated circuit including the frequency dividing circuit 20 described in the third embodiment, particularly a semiconductor integrated circuit having a function called SERDES (Serializer / Deserializer) macro will be described.

  First, a SERDES macro and a product equipped with a SERDES macro will be described. The SERDES macro is a circuit module that converts serial data into parallel data or parallel data into serial data. In the SERDES macro, a high-speed clock such as several GHz is often used.

  The SERDES macro is used for products that implement bus standards such as SATA (Serial ATA), PCIe (PCI express), USB (Universal Serial Bus) 3.0, and HDMI (High-Definition Multimedia Interface). In recent years, data transmission / reception is performed between various devices, and products corresponding to the above bus standards are rapidly increasing. For this reason, there is an increasing demand for specifications of a semiconductor integrated circuit equipped with a SERDES macro, and further reduction in power consumption is required.

  FIG. 16 is a diagram illustrating an example of an internal configuration of a NIC (Network Interface Card) using a semiconductor integrated circuit on which a SERDES macro is mounted. The NIC is mounted on a personal computer or a server on the network. The NIC shown in FIG. 16 performs high-speed serial data transmission / reception between an optical module and a semiconductor integrated circuit equipped with a SERDES macro. In addition, a semiconductor integrated circuit on which a SERDES macro is mounted via an interface connector with a mother board transmits and receives parallel data with a CPU (Central Processing Unit) on the mother board.

  Next, the layout of the SERDES macro in the semiconductor integrated circuit will be described. FIG. 17 is a diagram for explaining a layout of a semiconductor integrated circuit on which a SERDES macro is mounted. Semiconductor integrated circuits can be broadly divided into general-purpose interface block arrangement areas and areas (core areas) in which logic elements and memory macros are arranged. The SERDES macro is often arranged in the general-purpose interface block arrangement area.

  The SERDES macro includes a transmission module, a reception module, and a common unit. The transmission module and the reception module are composed of logic circuits such as a multiplexer and a demultiplexer, and analog circuits such as a line driver and a receiver. The common unit is configured by an analog circuit such as a PLL circuit or a reference power generation circuit. The SERDES macro is often a larger circuit than the general-purpose interface block, and often has a configuration similar to a plurality of transmission / reception modules.

  FIG. 18 is an example of a layout diagram of a semiconductor integrated circuit on which a SERDES macro is mounted. Examples of circuits with high power consumption of the SERDES macro include a PLL circuit, a BGR (Band Gap Reference), a driver unit, a clock circuit, and the like. In the clock circuit, a CML level clock is used, and there is room for reducing power consumption by changing the clock from the CML level to the CMOS level. For this reason, the CML circuit immediately after the VCO (Voltage Controlled Oscillator) of the PLL circuit is changed to a CMOS circuit. As a result, the CML circuit used in the SERDES macro is minimized, and all clock distribution is performed at the CMOS level, thereby realizing reduction of power consumption.

  Next, the case where the frequency dividing circuit 30 according to the third embodiment is applied to the PLL section of the SERDES macro will be described. FIG. 19 is a diagram illustrating an example of an outline of the SERDES macro. The SERDES macro shown in FIG. 19 can be roughly divided into three blocks. A PLL unit that generates a clock, a transmission unit (TX) that converts parallel data into serial data, and a reception unit (RX) that converts serial data into parallel data. In the PLL unit, the fastest clock in the SERDES macro is generated and distributed to the transmission unit and the reception unit.

  20 is a block diagram showing an example of the internal configuration of the PLL unit (dotted line part in FIG. 19) shown in FIG. In FIG. 20, the frequency divider 30 according to the third embodiment is not used. FIG. 21 is an example of a block diagram when the frequency dividing circuit 30 according to the third embodiment is used in the PLL section of the SERDES macro. 20 and 21, common constituent elements are given the same reference numerals, and descriptions thereof are omitted. 20 and FIG. 21 indicate a CML level (or analog signal) signal, and a solid line indicates a CMOS level signal.

  The PLL unit shown in FIG. 20 includes a phase frequency comparator (PFD) 51, a charge pump 52, a loop filter 53, a VCO 54, frequency divider circuits 55 and 56, and a level shifter 57.

  The phase frequency comparator 51 detects whether the reference clock and the output of the frequency dividing circuit 55 are synchronized. The charge pump 52 increases the output voltage of the phase frequency comparator 51. The loop filter 53 is a filter circuit that removes noise from the output of the charge pump 52. The VCO 54 is a voltage control oscillator that can control the output frequency by the voltage of the output signal of the loop filter 53.

  The SERDES macro receiving unit may have a circuit configuration that requires a four-phase clock. In such a case, the PLL unit divides the output of the VCO 54 by two to generate a four-phase clock. In FIG. 20, the frequency dividing circuit 56 is constituted by a CML circuit, and the clock supplied to the receiving unit is also distributed at the CML level. Further, in the PLL section shown in FIG. 20, since the feedback path frequency divider 55 is composed of a CMOS circuit, the level shifter 57 converts the output of the frequency divider 56 from the CML level to the CMOS level.

  On the other hand, in the PLL section shown in FIG. 21, the output of the VCO 54 is divided using the frequency dividing circuit 30 immediately after the VCO 54. Since the clock output from the frequency dividing circuit 30 is at the CMOS level, the CMOS level clock can be distributed to the receiving unit. As a result, the circuit area and power consumption in the PLL part of the SERDES macro can be reduced. Further, since the level shifter 57 is not necessary in the feedback path, the circuit area and power consumption can be further reduced.

  Here, the RATESEL signal will be described. 19 to FIG. 21, the RATESEL signal is input. In the SERDES macro, when it is necessary to deal with a wide range of oscillation frequencies (or a plurality of oscillation frequencies), it is necessary to perform switching control of the oscillation frequency for the PLL unit. A signal for that purpose is a RATESEL signal. When the frequency dividing circuit 30 is used for the SERDES macro, the setting of the selection terminals SEL [1: 0] is determined based on the RATESEL signal.

  FIG. 22 is a diagram showing an example of the layout of the entire SERDES macro. In the PLL section of FIG. 22, there is an LCVCO (LC Voltage Controlled Oscillator) using an inductor. Since the SERDES macro shown in FIG. 22 needs to correspond to two types of frequency bands, there is an LCVCO having two inductors. Inductors are often made using wiring, and the circuit scale is large. FIGS. 23 and 24 are enlarged views of the dotted line portion of FIG. In FIG. 23, the frequency dividing circuit 30 is not used. In FIG. 24, the frequency dividing circuit 30 is used.

  In FIG. 23, the CML level frequency divider 56 is connected to the LCVCO through a CML buffer. Similarly, in FIG. 24, the frequency dividing circuit 30 is connected to the LCVCO via the CML buffer. The frequency dividing circuit 56 shown in FIG. 23 and the frequency dividing circuit 30 shown in FIG. 24 are both arranged in the vicinity of the LCVCO. However, since the frequency dividing circuit 30 shown in FIG. 24 is composed of CMOS, it can be seen that the frequency dividing circuit 30 can be realized with a smaller circuit configuration than the frequency dividing circuit 56 shown in FIG. As described above, when the frequency divider 30 according to the third embodiment is used in the PLL section of the SERDES macro, the circuit scale of the SERDES macro can be reduced.

  Further, when the power consumption of the circuit shown in FIG. 23 and the circuit shown in FIG. 24 is obtained by simulation, the power consumption is reduced by half in the circuit shown in FIG. Note that the calculated power consumption is power consumed in circuits after the frequency divider circuit, and includes a PLL unit, a transmission unit, and a reception unit. The clock at that time is calculated as 6 GHz.

[Sixth Embodiment]
Next, a sixth embodiment will be described in detail with reference to the drawings. In the present embodiment, a case where the flip-flop circuit 40 according to the fourth embodiment is applied to a transmission unit of a SERDES macro will be described.

  FIG. 25 is a diagram illustrating an example of an outline of the SERDES macro. A dotted line portion in FIG. 25 is a multiplexer 60 that converts the parallel data of the transmission unit into serial data. 25 and 19 are the same except that the position of the dotted line portion is different. The multiplexer 60 shown in FIG. 25 converts 2-input parallel data into serial data. In a high-speed serial interface circuit such as a SERDES macro, a differential configuration is adopted for the driver in consideration of noise resistance and the like. Therefore, the multiplexer 60 also has a differential configuration. Although the synchronization circuit or the shift circuit inside the multiplexer 60 also has a differential configuration, the flip-flop circuit 40 according to the fourth embodiment is used for the synchronization circuit and the shift circuit.

  FIG. 26 is a diagram showing an example of an internal configuration when the flip-flop circuit 40 is used for the multiplexer 60 shown in FIG. A multiplexer 60 shown in FIG. 26 includes flip-flop circuits 41 to 44 and a selector 45. The flip-flop circuits 41 to 44 are the same circuits as the flip-flop circuit 40 according to the fourth embodiment. The flip-flop circuits 41 to 44 form a synchronization circuit of the multiplexer 60. The output of the synchronization circuit is input to the selector 45, converted into serial data, and then output to the pre-driver. The output of the pre-driver is input to the main driver, and data is output from the main driver.

  FIG. 27 is a diagram illustrating an example of the layout of the entire SERDES macro. FIG. 28 is a diagram showing an example of the layout of the uppermost layer of the entire SERDES macro. From FIG. 27, it can be seen that the multiplexer 60 is arranged in the vicinity of the pre-driver and the main driver. Further, it can be seen that the main driver needs to be connected to the output PAD (see FIG. 28). As described above, the circuit scale of the flip-flop circuit 40 is reduced. Therefore, the circuit scale is also reduced in the multiplexer 60 using the plurality of flip-flop circuits 40.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. For example, even if the N channel type MOS transistor and the P channel type MOS transistor are exchanged, it can be dealt with by appropriately changing the connection of the power source or the like. That is, the N channel type MOS transistor can be regarded as a first conductivity type transistor, and the P channel type MOS transistor can be regarded as a second conductivity type transistor.

10, 20-22 Latch circuits 30, 55, 56 Frequency divider circuits 40-44 Flip-flop circuit 45 Selector 51 Phase frequency comparator 52 Charge pump 53 Loop filter 54 VCO
57 Level shifter 60 Multiplexers BO to B5 Buffers MN01 to MN18, N01 to N08 N-channel MOS transistors MP01 to MP04, P01 to P08 P-channel MOS transistors

Claims (8)

A first first conductivity type transistor that receives a first clock by a gate terminal;
A second first conductivity type transistor having a source terminal connected to a drain terminal of the first first conductivity type transistor and receiving first input data by a gate terminal;
A third first conductivity type transistor having a source terminal connected to a drain terminal of the first first conductivity type transistor and receiving second input data having a phase opposite to that of the first input data by a gate terminal; ,
A first second conductivity type transistor having a drain terminal connected to the drain terminal of the second first conductivity type transistor and a gate terminal connected to the drain terminal of the third first conductivity type transistor;
A second second conductivity type transistor having a drain terminal connected to the drain terminal of the third first conductivity type transistor and a gate terminal connected to the drain terminal of the second first conductivity type transistor;
A fourth first conductivity type transistor that receives a second clock having a phase opposite to that of the first clock by a gate terminal;
A source terminal is connected to a drain terminal of the fourth first conductivity type transistor, a gate terminal is connected to a drain terminal of the first second conductivity type transistor, and a drain terminal is connected to the second second conductivity type transistor. A fifth first conductivity type transistor connected to the drain terminal of
A source terminal is connected to a drain terminal of the fourth first conductivity type transistor, a gate terminal is connected to a drain terminal of the second second conductivity type transistor, and a drain terminal is connected to the first second conductivity type transistor. A sixth first conductivity type transistor connected to the drain terminal of
A latch circuit comprising: A first selection signal and a second selection signal that are switched according to the frequency of the first and second clocks;
The source terminal is connected to the drain terminal of the second first conductivity type transistor, the drain terminal is connected to the drain terminal of the first second conductivity type transistor, and the gate terminal receives the first selection signal. 7 first conductivity type transistors;
The source terminal is connected to the drain terminal of the second first conductivity type transistor, the drain terminal is connected to the drain terminal of the first second conductivity type transistor, and the gate terminal receives the second selection signal. 8 first conductivity type transistors;
The source terminal is connected to the drain terminal of the third first conductivity type transistor, the drain terminal is connected to the drain terminal of the second second conductivity type transistor, and the gate terminal receives the first selection signal. 9 first conductivity type transistors;
The source terminal is connected to the drain terminal of the third first conductivity type transistor, the drain terminal is connected to the drain terminal of the second second conductivity type transistor, and the gate terminal receives the second selection signal. 10 first conductivity type transistors;
The latch circuit according to claim 1.   A frequency dividing circuit comprising the latch circuit according to claim 1.   A flip-flop circuit comprising the latch circuit according to claim 1.   A PLL circuit, wherein the output of the voltage controlled oscillator is divided by the divider circuit according to claim 3.   6. The PLL circuit according to claim 5, wherein the operation of the frequency divider circuit is changed based on a signal for switching an output frequency of the voltage controlled oscillator.   5. A multiplexer comprising the flip-flop circuit of claim 4.   A semiconductor integrated circuit comprising a SERDES macro including at least one of the PLL circuit according to claim 5 or 6 or the multiplexer according to claim 7.

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