JP2013016581A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device microfabricated and including a plug in an active region and a plug arranged outside the active region, which can assuredly form a framed insulation film and optimize functions such as conductivity.SOLUTION: A semiconductor device comprises: a semiconductor substrate SUB having a principal surface; an active region formed on the principal surface of the semiconductor substrate SUB; a gate connection region formed on a periphery of the active region when viewed from above; a first connection layer CT formed in regions sandwiched by a plurality of first transistors TG formed on the active region, for electrically connecting the first transistors TG and layers on an upper side of the first transistors TG; and a second connection layer SNC for electrically connecting a second transistor TG formed on the gate connection region and layers on an upper side of the second transistor TG. The first connection layer CT includes a first conductive part PP1a and a second conductive part PP2a. The second connection layer SNC includes a third conductive part PP2b.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a connection layer made of polycrystalline silicon and a manufacturing method thereof.

  Due to high integration and miniaturization, there is an increasing tendency to make a plurality of microelements constituting a semiconductor device overlap in a plan view. With the increase in the number of semiconductor devices, there is often a technique in which a gate electrode of a transistor formed on the main surface of a semiconductor substrate and a layer above the transistor are electrically connected by a connection layer called a plug. Used. A configuration in which a gate electrode of a transistor and a layer disposed on the upper side are electrically connected by a plug is disclosed in, for example, Japanese Patent Laid-Open No. 2000-182991 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2004-79696 (Patent Document). 2).

  Among the above, the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2004-79696 is a volatile memory called SRAM (Static Random Access Memory). In the SRAM disclosed in Japanese Patent Application Laid-Open No. 2004-79696, a capacitor as a so-called DRAM (Dynamic Random Access Memory) is added to an SRAM circuit using a thin film transistor called a so-called TFT (Thin Film Transistor) as a load transistor. . Instead of the storage node portion, electric charge is held in the capacitor, and the potential of the capacitor is held by a so-called flip-flop circuit constituting the SRAM circuit. For this reason, it is possible to suppress the occurrence of a soft error due to alpha rays, compared to an SRAM in which charges are stored in the storage node portion. Further, since at least a part of the flip-flop circuit is provided above the bit line, the semiconductor device can be downsized (miniaturized).

JP 2000-182991 A JP 2004-79696 A

  An interlayer insulating layer is formed in the same layer as the plurality of transistors formed in the active region of the SRAM. In order to electrically connect the transistor and the upper layer, a conductive plug is formed in a region sandwiched between the plurality of transistors.

  An opening for forming a plug is formed in a region between the plurality of transistors. This opening is formed by etching away an interlayer insulating layer formed in the same layer as a plurality of transistors. This etching is stopped using an insulating layer formed on an outer surface such as a gate electrode constituting a plurality of transistors and having a high etching selectivity with respect to the interlayer insulating layer as a stopper film.

  Due to the recent high integration and miniaturization of semiconductor devices, the width of the connection layer is narrowed, so that it is difficult to secure a short margin between a pair of adjacent transistors. Here, the short margin means an error that is allowed in order to suppress a short circuit between the pair of transistors in the amount of etching performed when forming the opening for forming the connection layer. .

  That is, in the active region, the amount of etching for forming an opening is reduced by narrowing the width of a plug formed between a pair of adjacent transistors and electrically connecting the transistor and the upper layer. If this error exceeds an allowable range (short margin), a pair of transistors may be short-circuited via the plug.

  In order to suppress the short circuit, an additional insulating film (framed insulating film) may be formed on the side wall of the transistor formed in the active region, particularly outside the side wall insulating film. However, in the SRAM, for example, in a state where an opening for forming a plug for connecting a gate electrode of a transistor arranged outside the active region and a layer arranged at an upper portion is formed in a plan view, the frame is formed. If the attached insulating film is formed, the framed insulating film is also formed on the inner wall surface of the opening. Therefore, it becomes difficult to use the plug formed from the opening as a conductive connection layer.

  In the SRAM disclosed in Japanese Patent Application Laid-Open No. 2004-79696, a region between adjacent transistors is mostly formed of an insulating layer, and the outside of the plug is covered with a thick insulating layer. Because of such a configuration, a frame insulating film is not required in Japanese Patent Application Laid-Open No. 2004-79696. For this reason, JP-A-2004-79696 does not consider the above problem.

  Japanese Patent Laid-Open No. 2000-182991 does not disclose a configuration in which a transistor and a layer disposed on the upper side are electrically connected by a plug in both the active region and the periphery of the active region. Therefore, the problem in forming the framed insulating film is not considered.

  Furthermore, Japanese Patent Application Laid-Open No. 2004-79696 does not describe the impurity concentration distribution of the conductive layer constituting the plug of the semiconductor device. For this reason, it is difficult to optimize the function (for example, conductivity) of the semiconductor device due to the physical properties of the plug.

  The present invention has been made in view of the above problems. The purpose is to reliably form a framed insulating film and to optimize functions such as conductivity in a miniaturized semiconductor device having both the plug in the active region and the plug outside the active region. A semiconductor device that can be manufactured and a method for manufacturing the same.

A semiconductor device according to an embodiment of the present invention has the following configuration.
The semiconductor device is formed on a semiconductor substrate having a main surface, an active region formed on the main surface of the semiconductor substrate, a gate connection region formed around the active region in plan view, and an active region A first connection layer for electrically connecting the first transistor and a layer above the first transistor, which is formed in a region sandwiched between the plurality of first transistors, and the gate connection region; A second transistor to be formed and a second connection layer for electrically connecting a layer above the second transistor are provided. The first connection layer includes a first conductive portion and a second conductive portion, and the second connection layer includes a third conductive portion.

A semiconductor device according to another embodiment of the present invention has the following configuration.
The semiconductor device is formed on a semiconductor substrate having a main surface, an active region formed on the main surface of the semiconductor substrate, a gate connection region formed around the active region in plan view, and an active region A first connection layer for electrically connecting the first transistor and a layer above the first transistor, which is formed in a region sandwiched between the plurality of first transistors, and the gate connection region; A second transistor to be formed and a second connection layer for electrically connecting a layer above the second transistor are provided. The first connection layer includes a fourth conductive portion, and the second connection layer includes a fifth conductive portion and a sixth conductive portion.

A manufacturing method of a semiconductor device according to an embodiment of the present invention includes the following steps.
First, a semiconductor substrate having a main surface is prepared. An active region and a gate connection region disposed around the active region in plan view are formed on the main surface of the semiconductor substrate. By removing the interlayer insulating layer formed in the region sandwiched between the plurality of first transistors formed on the active region, the first opening is formed. A framed insulating film is formed so as to cover the side wall of the first transistor exposed by forming the first opening. A first conductive layer is formed so as to fill the first opening. After the first conductive layer is formed, a second opening is formed so as to remove a part of the gate electrode of the second transistor formed in the gate connection region. A part of the first conductive layer in the first opening is removed to form a first conductive part. A second conductive layer is formed on the first conductive portion in the first opening and so as to fill the second opening. The first transistor includes the first conductive portion and the second conductive portion as a part of the second conductive layer by removing the second conductive layer on the first and second openings. Including a first connection layer for electrically connecting the first transistor and a layer above the first transistor, and a third conductive portion as a part of the second conductive layer. A second connection layer for electrically connecting the upper layer of the two transistors is formed.

A method of manufacturing a semiconductor device according to another embodiment of the present invention includes the following steps.
First, a semiconductor substrate having a main surface is prepared. An active region and a gate connection region disposed around the active region in plan view are formed on the main surface of the semiconductor substrate. A second opening is formed so as to remove a part of the gate electrode of the second transistor formed in the gate connection region. A third conductive layer is formed so as to fill the second opening. After the third conductive layer is formed, an interlayer insulating layer formed in a region sandwiched between the plurality of first transistors formed on the active region is removed, thereby forming a first opening. Is done. A framed insulating film is formed so as to cover the side wall of the first transistor exposed by forming the first opening. A part of the third conductive layer in the second opening is removed to form a fifth conductive part. A fourth conductive layer is formed on the fifth conductive portion in the second opening and so as to fill the first opening. By removing the fourth conductive layer on the first and second openings, a fourth conductive portion as a part of the fourth conductive layer is included. From the first transistor and the first transistor, Also includes a first connection layer for electrically connecting the upper layer, a fifth conductive portion, and a sixth conductive portion as a part of the fourth conductive layer. A second connection layer for electrically connecting the upper layer of the two transistors is formed.

  According to the present embodiment, the conductive portion constituting the first connection layer formed in the active region and the conductive portion constituting the second connection layer formed in the gate connection region are different. Therefore, the functions such as the conductivity of the first and second connection layers of the semiconductor device can be optimized with a high degree of freedom according to the design conditions of the semiconductor device.

  According to the manufacturing method in one aspect of the present embodiment, the first opening is formed by the framed insulating film, and the second opening is formed in a state where the inside is filled with the first conductive layer. Is done. Therefore, in addition to the effect of the present embodiment, it is possible to suppress a problem that the framed insulating film is formed in the second opening. In other words, by properly forming the framed insulating film, a short circuit between the transistors in the active region can be reliably suppressed.

  According to the manufacturing method in another aspect of the present embodiment, the first insulating film is formed by the framed insulating film in a state where the entire inner wall surface of the second opening is covered. Therefore, in addition to the effect of the present embodiment, it is possible to suppress a problem that the framed insulating film is formed in the second opening. In other words, by properly forming the framed insulating film, a short circuit between the transistors in the active region can be reliably suppressed.

1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. 1 is an equivalent circuit diagram of a memory cell constituting a semiconductor device according to a first embodiment of the present invention. It is a schematic sectional drawing for demonstrating the equivalent circuit of FIG. 2 concretely. FIG. 4A is a schematic plan view showing an aspect in which transistors TG are arranged in an active region in FIG. 3 and a region around the active region. (B) It is a schematic plan view which shows the aspect which added arrangement | positioning of the plug to FIG. 4 (A). It is a schematic sectional drawing of the part which follows the VV line of FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 11th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. It is a schematic sectional drawing which shows the 12th process of the manufacturing method of the area | region shown in FIG. 5 in Embodiment 1 of this invention. FIG. 6 is a schematic cross-sectional view for comparison with FIG. 5 in a comparative example of the first embodiment. FIG. 19 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 18. FIG. 20 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 18. FIG. 21 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 18. FIG. 22 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 18. FIG. 23 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 18. FIG. 24 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 18. FIG. 6 is a schematic plan view showing a mode of a region corresponding to the region shown in FIG. 5 in the first embodiment of the semiconductor device according to the second embodiment of the present invention. FIG. 26 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25. FIG. 26 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25. FIG. 28 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25. FIG. 29 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25. FIG. 30 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25. FIG. 26 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25. FIG. 36 is a schematic cross-sectional view showing a step following the step in the method for manufacturing the region shown in FIG. 25.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
Referring to FIG. 1, semiconductor device DV of the present embodiment has a plurality of types of circuits formed on the main surface of semiconductor substrate SUB such as a semiconductor wafer made of silicon single crystal. As an example, a circuit constituting the semiconductor device DV includes a signal input / output circuit, a DA-AD converter, a power supply circuit, a CPU, a flash memory, and an SRAM (Static Random Access Memory).

  The role of each circuit constituting the semiconductor device DV is as follows. First, in the signal input / output circuit, an electrical signal is input / output to / from a circuit arranged outside the semiconductor device DV. In the DA-AD converter, an analog signal and a digital signal are converted. The power supply circuit supplies power necessary for driving the semiconductor device DV and controls the power. In the CPU, a logical operation is performed by a logic circuit. Data is stored in the flash memory or the SRAM.

  Next, the structure of the semiconductor device as the present embodiment will be described with reference to the memory cell of FIG.

  Referring to FIG. 2, in the semiconductor device in the present embodiment, an SRAM having a bit line pair BL and ZBL, a word line WL, a flip-flop circuit, and a pair of access transistors T5 and T6 is used as a memory cell. Have.

  The flip-flop circuit has driver transistors T1 and T2 and load transistors T3 and T4. The driver transistor T1 and the load transistor T3 form one CMOS (Complementary Metal Oxide Semiconductor) inverter, and the driver transistor T2 and the load transistor T4 form the other CMOS inverter. The flip-flop circuit is composed of these two CMOS inverters. An SRAM is a semiconductor memory device that has a flip-flop circuit and thus eliminates a process called so-called refresh that restores charges stored as information at a predetermined cycle. The SRAM in the present embodiment further includes capacitors C1 and C2 as DRAMs (Dynamic Random Access Memory).

  Driver transistors T1 and T2 constituting the flip-flop circuit are, for example, n-channel MOS transistors. The load transistors T3 and T4 are, for example, p-channel TFTs (Thin Film Transistors). Access transistors T5 and T6 are, for example, n-channel MOS transistors. As described above, the SRAM of the present embodiment is a so-called Advanced SRAM in which the load transistor is a TFT and a capacitor as a DRAM is added.

  In the flip-flop circuit, the gate electrodes of driver transistor T1 and load transistor T3 and capacitor C1 are electrically connected to each other, and these are electrically connected to source electrode S of access transistor T6. The source electrode S of the access transistor T6 is electrically connected to the drain electrode D of the driver transistor T2 and the load transistor T4, and the region where these are connected functions as a first storage node portion.

  The gate electrodes of driver transistor T2 and load transistor T4 and capacitor C2 are electrically connected to each other, and these are electrically connected to source electrode S of access transistor T5. The source electrode S of the access transistor T5 is electrically connected to the drain electrode D of the driver transistor T1 and the load transistor T3, and the region where these are connected functions as a second storage node portion.

  The source electrodes S of the driver transistors T1 and T2 are electrically connected to the GND potential, and the source electrodes S of the load transistors T3 and T4 are electrically connected to a Vcc wiring (power supply wiring) that applies the voltage Vcc. ing. Further, the capacitors C1 and C2 are electrically connected to a Vcc / 2 wiring that applies a voltage Vcc / 2 that is ½ of the voltage Vcc. Each of the pair of bit lines BL and ZBL is connected to the drain electrodes D of the pair of access transistors T5 and T6.

  Next, a more specific structure of the semiconductor device shown in FIG. 2 will be described with reference to the schematic cross-sectional view of FIG. However, the cross-sectional view of FIG. 3 is not a view showing a cross-sectional aspect in a specific region, but is gathered together to explain the shape of each element such as a transistor and a capacitor shown in FIG. 2 in the semiconductor device. .

  Referring to FIG. 3, the semiconductor device according to the present embodiment is formed on one main surface of a p-type semiconductor substrate SUB made of, for example, a silicon single crystal.

  The surface of the semiconductor substrate SUB is electrically isolated by STI (Shallow Trench Isolation). This STI is formed by embedding an insulating layer SI in a groove formed on the surface of the semiconductor substrate SUB. A plurality of transistors TG are formed on the surface of the semiconductor substrate SUB electrically separated by the STI.

  In the active region of the surface of the semiconductor substrate SUB, for example, a p-type well region PWL into which p-type conductive impurities are implanted is formed. The transistor TG (first transistor) formed on the active region has a pair of source / drain regions S / D, a gate insulating film GI, a gate electrode GE, and an insulating film IL. Each of the pair of source / drain regions S / D is formed on the surface of the semiconductor substrate SUB. The gate insulating film GI is formed on the surface of the semiconductor substrate SUB sandwiched between the pair of source / drain regions S / D. The gate electrode GE and the insulating film IL are formed on the gate insulating film GI and have a stacked structure of the gate electrode GE and the insulating film IL. The gate electrode GE has, for example, a so-called polycide structure (tungsten silicide: WSi) in which a polycrystalline silicon thin film and a tungsten thin film are stacked. The insulating film IL is made of, for example, a silicon oxide film and / or a silicon nitride film, and serves as an etching stopper film when performing so-called self-alignment processing using the insulating film IL as a mask. A sidewall insulating film SW is formed on the side walls of the gate electrode GE and the insulating film IL. Similar to the insulating film IL, the side wall insulating film SW also serves as an etching stopper film when performing so-called self-alignment processing using the side wall insulating film SW as a mask. Side wall insulating film SW is preferably a combination of a silicon oxide film and a silicon nitride film.

  Note that although the insulating film IL is formed over the gate electrode GE, the gate electrode GE is electrically connected to other wirings in a region extending in the depth direction of the paper not shown in the cross-sectional view of FIG.

  Of the surface of the semiconductor substrate SUB, the gate electrode GE constituting the transistor TG and the like are also disposed on the insulating layer SI that is the periphery (gate connection region) of the active region in plan view. The transistor TG formed in the periphery (outside) of the active region has a configuration in which the gate electrode GE and the like common to the transistor TG in the active region extend to the periphery (outside) of the active region. In the cross-sectional view of FIG. 3, the source / drain region S / D of the transistor TG in the gate connection region is not shown. This is because the source / drain region of the transistor TG extends, for example, in the depth direction of the drawing so that the gate electrode GE of the gate connection region reaches the active region, and the source / drain region S / D is formed in the active region. It is because it has been. Here, the structure in which the gate insulating film GI and the gate electrode GE and the like formed in the gate connection region are stacked is also referred to as a transistor TG (second transistor) (formed in the gate connection region).

  An interlayer insulating layer II1 made of, for example, a silicon oxide film is formed so as to fill a gap between the stacked structures of the gate electrode GE and the insulating film IL of the adjacent transistor TG. Contact holes (openings) are formed in the interlayer insulating layer II1, and plugs (first connection layers) CT and plugs (second connection layers) SNC are embedded in the contact holes and the like. . Plugs CT and SNC preferably have a conductive region formed of, for example, polycrystalline silicon.

  Interlayer insulating layers II2, II3, II4, II5, and II6 made of, for example, silicon oxide films are sequentially formed so as to be in contact with the upper surface of interlayer insulating layer II1, and silicon nitride, for example, is contacted with the upper surface of interlayer insulating layer II6. An interlayer insulating layer I1 made of a film is formed. Further, interlayer insulating layers II7, II8, II9, and II10 made of, for example, a silicon oxide film are sequentially formed so as to be in contact with the upper surface of the interlayer insulating layer I1.

  A plurality of bit lines BL are formed on the interlayer insulating layer II2 at intervals. The bit line BL extends in the depth direction of FIG. A sidewall insulating film is formed in contact with the sidewall surface of the bit line BL.

  Bit line BL is electrically connected to source / drain region S / D by, for example, one or more contact conductive layers CTC.

  On the interlayer insulating layer II3, a lower layer wiring 2G is formed. The lower layer wiring 2G is a wiring arranged to electrically connect a capacitor formed in an upper layer and the transistor TG by, for example, the contact conductive layers CTC and SC. The lower layer wiring 2G is preferably formed in a region that generally overlaps the capacitor in plan view. Lower layer wiring 2G is preferably composed of, for example, a polycrystalline silicon film having impurity ions. When the transistor TG or the like formed in the lower layer is, for example, an n-channel transistor, the lower-layer wiring 2G has a polycrystalline structure containing n-type impurity ions, for example, to facilitate electrical connection with the transistor TG. It may be composed of silicon.

  A polycrystalline silicon layer TP is formed on the interlayer insulating layer II4. The polycrystalline silicon layer TP is a semiconductor layer made of polycrystalline silicon into which impurity ions are introduced, and a channel region of a TFT as an SRAM load transistor T3, T4 (see FIG. 1) and a pair of sandwiching the channel region Source / drain regions. The polycrystalline silicon layer TP includes a part of power supply wiring for supplying power to the TFT. The polycrystalline silicon layer TP is preferably formed in a region that generally overlaps the capacitor in plan view.

  A TFT gate electrode layer TD is formed on the interlayer insulating layer II5. The gate electrode layer TD is preferably a semiconductor layer containing polycrystalline silicon having impurity ions.

  The electrical connection between the gate electrode layer TD and the lower layer wiring 2G is preferably made by a conductive layer called a data node contact DB. The data node contact DB is in contact with the end portion of the polycrystalline silicon layer TP and is electrically connected to the polycrystalline silicon layer TP while extending from the gate electrode layer TD toward the lower layer wiring 2G. The data node contact DB is a conductive layer for forming an SRAM flip-flop circuit (cross couple), and is formed of a semiconductor layer containing polycrystalline silicon having impurity ions, for example, like the gate electrode layer TD. The data node contact DB is preferably formed so as to extend from the gate electrode layer TD to the lower layer wiring 2G in a direction substantially perpendicular to the main surface of the semiconductor substrate SUB so as to penetrate the interlayer insulating layer.

  The data node contact DB may be formed to electrically connect a layer above the gate electrode layer TD, for example, the gate electrode layer TD and the capacitor, and a layer below the lower layer wiring 2G, for example, the lower layer wiring 2G. It may be formed so as to be electrically connected to contact conductive layer SC. In this case, the data node contact DB may be formed so as to penetrate the gate electrode layer TD, the polycrystalline silicon layer TP and the lower layer wiring 2G from the capacitor and reach the contact conductive layer SC, for example.

  A capacitor is formed on the interlayer insulating layer II6. The capacitor is electrically connected to the data node contact DB by contacting the upper surface of the data node contact DB.

  Metal interconnection MTL is formed above the capacitor, for example, on interlayer insulating layer II8 and interlayer insulating layer II9. Metal interconnection MTL is preferably made of, for example, aluminum, an aluminum-copper alloy, copper, tungsten, or the like, and its upper and lower surfaces are preferably covered with a barrier metal BRL made of, for example, tantalum, titanium, titanium nitride, or the like. Further, the connection between the metal wirings MTL and the connection between the metal wiring MTL and the bit line BL are preferably made by a metal contact conductive layer MCT made of, for example, copper or tungsten.

  Next, the aspect of the layer in which the transistor TG is formed in the semiconductor device shown in FIG. 3 will be described in more detail with reference to FIGS.

  Regions enclosed by rectangles in FIGS. 4A and 4B show unit cells, and particularly in a portion along the VV line in the unit cells and a particularly round dotted line “V” in FIG. The region where the enclosed transistor TG is formed is shown in more detail in FIG.

  Referring to FIG. 4A, within the range shown in the figure, the pattern of each component is symmetric with respect to a straight line extending in the left-right direction at the center in the vertical direction of the figure. Has been placed.

  The active region 1F is a region generally corresponding to the p-type well region PWL in FIG. Referring to FIGS. 4A and 5, gate electrode GE and insulating film IL are formed so as to cross active region 1F. In the active region 1F, a pair of source / drain regions are formed so as to sandwich the gate electrode GE and the insulating film IL in plan view. Thus, the driver transistor and the access transistor are configured. Therefore, the left transistor TG of the pair of transistors TG formed in the active region in the unit cell of FIG. 5 can be considered as the driver transistors T1 and T2, and the right transistor TG as the access transistors T5 and T6. The transistor TG formed in the periphery (gate connection region) of the active region can also be considered as the driver transistors T1 and T2 arranged on the upper right of the unit cell in FIG.

  Referring to FIGS. 4B and 5, plug CT (first electrode) formed in a region sandwiched by transistors TG formed so as to be aligned in the direction along the main surface of semiconductor substrate SUB in the active region in plan view. 1 connection layer) is formed so as to straddle a plurality of transistors TG above each transistor TG. Further, the plug SNC (second connection layer) connected to the transistor TG in the gate connection region in plan view is formed inside the gate electrode GE so as to fill a region where the gate electrode GE and a part of the insulating film IL are etched. It is formed to bite. The plug SNC is electrically connected to the gate electrode GE in the manner described above. Plug CT is in the active region, and plug SNC is in the gate connection region to electrically connect transistor TG to a conductive layer above transistor TG, such as bit line BL and lower wiring 2G (see FIG. 3). Is formed. In the electrical connection described above, contact conductive layers CTC, SC and data node contact DB (see FIG. 3) are used.

  Referring to FIG. 5, framed insulating film WSW is formed so as to cover the outer surface (side wall surface) of the stacked structure such as gate electrode GE including sidewall insulating film SW of each transistor TG in the active region. Yes. That is, the outside (side wall) of the region between the plurality of transistors TG is covered with a frame insulating film WSW that is additionally formed to cover the side wall insulating film SW in addition to the side wall insulating film SW. In other words, the framed insulating film WSW is formed so as to cover (on the inner side wall surface) the inner side wall surface of an opening such as an interlayer insulating layer formed in a region sandwiched between the plurality of transistors TG. Yes.

  That is, the conductive plug CT is formed between the adjacent transistors TG. However, since the frame insulating film WSW is sandwiched between the plug CT and the transistor TG (eg, the gate electrode GE), the adjacent transistor TG Short circuit between each other is suppressed. The frame insulating film WSW is preferably formed of, for example, a silicon nitride film. The frame insulating film WSW is preferably formed so as to cover at least a part of the side wall insulating film SW, and more preferably formed so as to cover the entire surface of the side wall insulating film SW. The framed insulating film WSW may be formed so as to cover the upper surface of the insulating film IL.

  On the other hand, in the transistor TG in the gate connection region, for example, a liner film LF is formed so as to cover the sidewall insulating film SW. The liner film LF is preferably made of, for example, a silicon nitride film. The liner film LF may cover a part of the region on the insulating film IL.

  The plug CT has two layers of conductive parts, a conductive part PP1a (first conductive part) and a conductive part PP2a (second conductive part), both of which are source / drain regions of the transistor TG in the active region. Extends to reach S / D. In this way, the plug CT is electrically connected to the source / drain region S / D.

  The plug SNC has one conductive portion of a conductive portion PP2b (third conductive portion) and is electrically connected to the gate electrode GE of the transistor TG. In the gate connection region, an interlayer insulating layer II1 is formed in the same layer as the transistor TG.

  In the present embodiment, it is preferable that conductive parts PP1a, PP2a, PP2b constituting plugs CT, SNC are all made of polycrystalline silicon. The concentration of conductive impurities (polycrystalline silicon) contained in conductive portion PP1a is preferably lower than the concentration of conductive impurities (polycrystalline silicon) contained in conductive portions PP2a and PP2b. Conversely, it is preferable that the concentration of the conductive impurities contained in the conductive portions PP2a and PP2b is higher than the concentration of the conductive impurities contained in the conductive portion PP1a. In the present embodiment, the conductive portion PP2a is formed above the conductive portion PP1a. For this reason, in the plug CT in which the two-layer conductive portions PP1a and PP2a are formed, the concentration of the conductive impurities in the lower conductive portion is preferably lower than the concentration of the conductive impurities in the upper conductive portion.

  It can be verified that the plug CT has two layers of the conductive portions PP1a and PP2a as follows. First, when the concentration of conductive impurities in each of the two layers is different, it can be confirmed by utilizing the difference in the etching rate between the two layers. In addition, even when the concentration of conductive impurities in each of the two layers is almost the same, the presence of an oxide film formed thinly at the interface between the two layers is confirmed, or the crystal of polycrystalline silicon is discontinuous at the interface between the two layers. It can be confirmed that two layers of polycrystalline silicon conductive layers are stacked.

  For example, the concentration of the conductive impurities contained in the conductive parts PP2a and PP2b is more preferably twice or more the concentration of the conductive impurities contained in the conductive part PP1a. However, the relationship of the concentration of conductive impurities contained in the conductive portions PP2a, PP2b and the conductive portion PP1a can be arbitrarily adjusted according to the design specifications and required functions of the semiconductor device. For example, the conductive portion PP2a , PP2b and conductive portion PP1a may have substantially the same concentration of conductive impurities.

  With the above configuration, in the present embodiment, it is preferable that the plug SNC as a whole has a higher concentration of conductive impurities and a lower electrical resistance than the plug CT.

  In the present embodiment, the crystal grains of the conductive material (polycrystalline silicon) included in the conductive portion PP1a are larger than the crystal grains of the conductive material (polycrystalline silicon) included in the conductive portions PP2a and PP2b. preferable. Here, the size of the crystal grains indicates the average size (grain size) of the crystal grains. Here, the grain size of a crystal grain is a cumulative volume obtained by integrating the volume of the powder from the small grain size side to the large grain size side when measured using a particle size distribution measurement method by a laser diffraction / scattering method. Means the value of the diameter of the powder cross-section at the point where is 50%. The shape and size of the crystal grains themselves can be observed by, for example, SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope). Thus, if the size of the crystal grains is different, it can be easily verified that the two-layer conductive portions PP1a and PP2a are formed in the plug CT.

  Since the conductive part PP1a is formed below the conductive part PP2a, the conductive part PP1a is formed before the conductive part PP2a. That is, the conductive part PP1a is heated by heat treatment or the like for a longer time than the conductive part PP2a. For this reason, crystal growth of the conductive part PP1a tends to be larger than that of the conductive part PP2a, and the crystal grains tend to be larger.

  Further, in each of the transistors TG in the active region and the gate connection region, the side surfaces of the gate insulating film GI and the gate electrode GE are preferably covered with the additional insulating film ETI. The additional insulating film ETI is formed for the purpose of relaxing the electric field in the vicinity of the region, and is preferably formed of, for example, a silicon oxide film.

  Next, a method for manufacturing the region shown in FIG. 5 of the semiconductor device (Advanced SRAM) of the present embodiment will be described with reference to FIGS.

  Referring to FIG. 6, first, a semiconductor substrate SUB made of, for example, a silicon single crystal containing p-type impurities is prepared. Next, an active region and an insulating layer SI (including a region that later becomes a gate connection region) that partitions the active region are formed on the main surface of the semiconductor substrate SUB.

  Although not specifically shown, first, a pad oxide film made of, for example, a silicon oxide film and a silicon nitride film are sequentially formed on one (upper) main surface of the semiconductor substrate SUB. Next, a part of the pad oxide film, silicon nitride film, and semiconductor substrate SUB in the region where the insulating layer SI is formed is removed by a normal photolithography technique and etching technique. By this process, a groove is formed in a part of the semiconductor substrate SUB in the region where the insulating layer SI is formed. An insulating layer SI is formed by depositing a silicon oxide film by, for example, a CVD (Chemical Vapor Deposition) method so as to fill the groove. After the insulating layer SI is formed, the silicon nitride film and the silicon oxide film are removed by, for example, a wet etching technique, leaving the pad oxide film on the main surface of the semiconductor substrate SUB.

  Next, a resist film pattern having an opening in a region where a well as an impurity region is to be formed is formed using a normal photolithography technique. Using the resist film as a mask, ions of a p-type impurity such as boron (B) are implanted into the semiconductor substrate SUB in a region where the p-type well region PWL is to be formed by a normal implantation technique. After ions of the p-type impurity are formed, normal heat treatment is performed to diffuse the impurity and form a p-type well region PWL. Thus, the active region and the insulating layer SI that partitions the active region are formed on the main surface of the semiconductor substrate SUB.

  Referring to FIG. 7, after the pad oxide film is removed, gate insulating film GI covers the upper surface of the main surface of semiconductor substrate SUB (excluding the upper surface of insulating layer SI) using, for example, a thermal oxidation method. Formed as follows. Gate insulating film GI is preferably made of, for example, a silicon oxide film. A polycrystalline silicon thin film is formed by, for example, a CVD method so as to cover the upper surface of the gate insulating film GI, and a tungsten (tungsten silicide: WSi) thin film is further formed by, for example, a sputtering method. The thin film of polycrystalline silicon and the thin film of tungsten are for forming the gate electrode GE as tungsten silicide (so-called polycide structure). Further, an insulating film IL is formed by, for example, a CVD method so as to cover the upper surface. The insulating film IL may be, for example, a single layer of a silicon nitride film, or may be composed of two layers of a silicon nitride film and a silicon oxide film (so-called tetraethoxysilane (TEOS) film).

  Next, after patterning so as to form a laminated structure constituting the transistor TG by a normal photoengraving technique and etching technique, the sidewall surfaces of the gate insulating film GI and the gate electrode GE of the laminated structure are made of, for example, a silicon oxide film. An additional insulating film ETI is formed. This additional insulating film ETI is formed by oxidizing the gate electrode GE. In FIG. 7, the additional insulating film ETI covers the side walls of the gate insulating film GI and the gate electrode GE.

  Next, an n-type impurity region is formed on the main surface of the semiconductor substrate SUB in the p-type well region PWL by a normal implantation technique using the stacked structure configured as described above as a mask. Further, after an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the laminated structure, patterning is performed as a sidewall insulating film SW covering the sidewall surface of the laminated structure by a normal photolithography technique and etching technique. Is done. Thereafter, an n-type impurity region is formed on the main surface of the semiconductor substrate SUB in the p-type well region PWL by a normal implantation technique. The n-type impurity region thus formed becomes the source / drain region S / D of the transistor TG. Thereafter, a liner film LF made of, for example, a silicon nitride film is formed by, for example, a CVD method so as to cover the laminated structure and the surface of the semiconductor substrate SUB. Through the above steps, the transistor TG is formed in both the active region and the gate connection region.

  The insulating film IL, the side wall insulating film SW, and the liner film LF are formed as a stopper film when the interlayer insulating layer II1 to be formed later is etched. For this reason, each of the insulating films is not limited to the above-described material, and is preferably made of a material different from the interlayer insulating layer II1, particularly an insulating film material having a high etching selectivity with the interlayer insulating layer II1.

  Referring to FIG. 8, interlayer insulating layer II1 made of a silicon oxide film (boron-phosphorous tetraethylorthosilicate (BPTEOS) film) is formed by using, for example, a CVD method. Interlayer insulating layer II1 is formed on the main surface of semiconductor substrate SUB so as to cover the stacked structure of FIG. Thereafter, the top surface of the interlayer insulating layer II1 is planarized by heat treatment. Thereafter, the uppermost surface of the interlayer insulating layer II1 is polished by a planarization process called CMP (Chemical Mechanical Polishing), for example. This polishing is preferably stopped (terminated) by reaching (in terms of height (thickness)) the liner film LF or the insulating film IL formed of a material different from that of the interlayer insulating layer II1.

  Referring to FIG. 9, a preliminary insulating film RI made of, for example, a silicon oxide film is formed on the uppermost surface polished in FIG. The preliminary insulating film RI is for suppressing the etching of the insulating film IL together with the interlayer insulating layer II1 in a so-called breakthrough process in which the insulating film is removed as an initial stage in dry etching shown in FIG. is there. Therefore, the preliminary insulating film RI is preferably formed of a silicon oxide film which is an insulating film material different from the insulating film IL (having a high etching selectivity with the insulating film IL).

  Next, referring to FIG. 9 and FIG. 10, after the resist pattern PHR is formed, first, in the breakthrough process, the preliminary insulating film RI that is not covered with the resist pattern PHR (that is, in the active region) is etched. Removed. Subsequent to the preliminary insulating film RI, the interlayer insulating layer II1 in the region sandwiched between the adjacent transistors TG in the active region is removed by etching.

  Referring to FIGS. 10 and 11, liner film LF in the region where interlayer insulating layer II1 is removed in FIG. 10 is removed. By this processing, a first opening CV1 for later forming the plug CT is formed. The preliminary insulating film RI that has not been removed in the process of FIG. 10 is removed, for example, when the liner film LF is removed after the resist pattern PHR is removed. In this case, both are removed by using the condition that the preliminary insulating film RI is removed together with the liner film LF. Further, the preliminary insulating film RI may be removed by performing wet etching before forming the polycrystalline silicon layer in a later step.

  Referring to FIG. 12, the main surface of semiconductor substrate SUB is formed by CVD, for example, so as to cover the inner wall surface forming first opening CV1 formed in FIG. 11, that is, the side wall surface of transistor TG in the active region. An insulating film such as a silicon nitride film is formed on upper and interlayer insulating layer II1. Thereafter, a frame made of the insulating film is formed so as to cover the inner wall surface constituting the first opening CV1 formed in FIG. 11, that is, the side wall surface of the transistor TG in the active region, by a normal photolithography technique and etching technique. The attached insulating film WSW is formed.

  Referring to FIG. 13, first conductive layer PP1 made of, for example, polycrystalline silicon and containing conductive impurities is formed by, eg, CVD. The first conductive layer PP1 is formed so as to fill the first opening CV1 in which the frame insulating film WSW is formed.

  Referring to FIG. 14, a resist for forming a plug SNC (see FIG. 5) for electrically connecting the gate electrode GE of the transistor TG in the gate connection region and the upper layer by a normal photolithography technique. A pattern PHR (photosensitive agent) is formed.

  Referring to FIG. 15, second opening CV2 for forming plug SNC later is formed by a normal etching technique using resist pattern PHR in FIG. Specifically, the second opening CV2 is preferably formed by the following procedure. First, the resist pattern PHR is patterned so that the first conductive layer PP1 in a region overlapping the gate electrode GE in the gate connection region in plan view is removed. Next, after the resist pattern PHR is removed, by using the pattern of the first conductive layer PP1 as a mask, the insulating film IL and the interlayer insulating layer II1 just under the removed first conductive layer PP1 are removed. The At least a part of the bottom surface of the second opening CV2 to be formed reaches the uppermost surface of the gate electrode GE from the layer in contact with the lower side of the first conductive layer PP1 so that the uppermost surface of the gate electrode GE is reached. It is preferable that a part of each layer arrange | positioned between is removed.

  The second opening CV2 is preferably formed so that at least a part thereof is in contact with the gate electrode GE. The second opening CV2 may be formed so as to reach, for example, the insulating layer SI by being over-etched in a part of the region.

  Referring to FIG. 16, after the step of FIG. 15, a part of gate electrode GE is further removed by etching. For this reason, the second opening CV2 is formed such that the inner wall surface thereof bites into the gate electrode GE. By doing so, the second opening portion is configured such that the contact area between the inner wall surface of the second opening portion CV2 and the inside of the gate electrode GE is larger than the area of the second opening portion CV2 in plan view. More preferably, CV2 is formed.

  When the gate electrode GE in the gate connection region is etched, a part (upper part) of the first conductive layer PP1 formed so as to fill the first opening CV1 is also removed in the active region. Is done. This is because the etching selectivity between WSi (polycide structure) constituting the gate electrode GE and the first conductive layer PP1 is low. However, a part of the first conductive layer PP1 in the first opening CV1 may be removed by a process different from the etching removal for forming the second opening CV2. Thus, by removing a part of the first conductive layer PP1 inside the first opening, the first conductive portion PP1a is formed.

  As described above, the resist pattern PHR is used only for etching the uppermost first conductive layer PP1, and the lower layers are etched using the pattern of the first conductive layer PP1 as a mask. Have That is, since only the first conductive layer PP1 is etched away using the resist pattern PHR, the resist pattern PHR can be formed thinner. If the resist pattern PHR is formed thin, the width of the opening of the formed resist pattern PHR is also reduced from the viewpoint of suppressing an excessive increase in the aspect ratio of the opening of the resist pattern PHR. Therefore, the second opening CV2 having a smaller width can be formed.

  Further, by performing additional etching after removing the resist pattern PHR, it is possible to prevent deposits (deposits) due to the resist pattern PHR from adhering to the inner wall surface of the opening formed by the etching. Can do.

  Referring to FIG. 17, for example, the first opening CV <b> 1 in which the first conductive layer PP <b> 1 is removed (on the first conductive portion) and the second opening CV <b> 2 are filled. The second conductive layer PP2 is formed by the CVD method.

  Second conductive layer PP2 is preferably made of, for example, polycrystalline silicon and contains conductive impurities. Here, the conductive impurities contained in the first conductive layer PP1 and the second conductive layer PP2 can be set to an optimum concentration according to the design specifications of the semiconductor device to be formed. Therefore, the concentrations of the first conductive layer PP1 and the second conductive layer PP2 may be different. For example, the concentration of the conductive impurities contained in the second conductive layer PP2 is higher than that of the first conductive layer PP1. May be higher.

  Thereafter, the second conductive layer PP2 formed approximately above the height of the uppermost surface of the transistor TG (insulating film IL) is etched back. In this way, as shown in FIG. 5, the second conductive layer PP2 is formed as the second conductive portion PP2a in the first opening CV1, and the third conductive layer PP2a in the second opening CV2. It is formed as a conductive part PP2b. For example, if the concentration of conductive impurities contained in the second conductive layer PP2 is higher than that in the first conductive layer PP1, the second and third conductive portions PP2a and PP2b are more conductive than the first conductive portion PP1a. The concentration of ionic impurities increases. As a result, since the plug SNC including the third conductive portion PP2b as a whole has a higher concentration of conductive impurities than the plug CT including the first and second conductive portions PP1a and PP2a as a whole, the electrical resistance is increased. Lower.

  Next, the effect of this Embodiment is demonstrated, referring FIGS. 18-24 which are comparative examples. First, the configuration of the region shown in FIG. 5 of the present embodiment in the comparative example will be described with reference to FIG.

  Referring to FIG. 18, in the region shown in FIG. 5 of the present embodiment in the comparative example, both plug CT and plug SNC include only a single conductive portion PP1a. The conductive part PP2a may be used instead of the conductive part PP1a included therein. That is, in the comparative example, unlike the present embodiment, the conductive portion in the plug CT is not two layers.

  Further, the frame insulating film WSW is not formed in each of the transistors TG formed in the active region. A liner film LF is formed on the upper surface of the insulating film IL, and an interlayer insulating layer II1 is formed with the liner film LF interposed therebetween. One of the source / drain regions S / D of the driver transistor includes a low concentration n-type impurity region S / D1 and a high concentration n-type impurity region S / D having a higher concentration than the low concentration n-type impurity region S / D1. You may have two area | regions with D2.

  In this way, the value of the so-called β ratio indicating the ratio of the driving capability of the driver transistor to the driving capability of the access transistor can be improved, and the function of the entire SRAM can be improved. In addition, leakage current at the junction between the plug CT and the impurity region S / D due to diffusion of conductive impurities from the plug CT to the impurity region S / D can be reduced. Although not described above, the present embodiment may have a structure having impurity regions S / D1 and S / D2 as in FIG.

  In the above points, the comparative example is different from the present embodiment. Next, a method for manufacturing the region shown in FIG. 18 of the semiconductor device (Advanced SRAM) of the comparative example will be described with reference to FIGS.

  Referring to FIG. 19, basically the same processing as that shown in FIGS. 6 to 7 of the present embodiment is performed, and then interlayer insulating layer II1 is formed as in the step of FIG. Thereafter, the upper surface of the interlayer insulating layer II1 is not polished, and a resist pattern PHR (photosensitive agent) for forming the plug SNC (see FIG. 5) is formed on the interlayer insulating layer II1 as in the step of FIG. It is formed. Referring to FIGS. 20 to 21, the second opening CV <b> 2 is formed by performing the same processing as the steps of FIGS. 15 to 16 thereafter.

  Referring to FIG. 22, after formation of resist pattern PHR, interlayer insulating layer II1 in the region sandwiched between adjacent transistors TG in the active region is removed by etching, and first opening CV1 is formed. Referring to FIG. 23, after the resist pattern PHR is removed, the exposed liner film LF is removed by etching.

  Referring to FIG. 24, a single type of conductive layer PP1 is formed so as to fill almost the entire first opening CV1 and second opening CV2. Thereafter, the conductive layer PP1 is etched back, whereby the configuration shown in FIG. 18 having the plug CT including the conductive portion PP1a is formed.

  In the comparative examples of FIGS. 18 to 24, as in the present embodiment, both the source / drain regions S / D of the driver transistor are single impurities (without S / D1 and S / D2). A configuration having only a region may be used.

Hereinafter, the function and effect of the present embodiment will be described.
As described above, when the second opening CV2 in the gate connection region is formed before the first opening CV1, the inside of the second opening CV2 is formed after the first opening CV1 is formed. If the frame insulating film WSW (see FIG. 12) is formed in the first opening CV1 with the wall surface exposed, the insulating film WSW is unintentionally formed on the inner wall surface of the second opening CV2. There is. The second opening CV2 (plug SNC) is formed so as to etch a part of the gate electrode GE for the purpose of increasing the contact area with the gate electrode GE and reducing the contact resistance with the gate electrode GE. For this reason, if the frame insulating film WSW is formed on the inner wall surface of the second opening CV2, the contact resistance with the gate electrode of the plug SNC increases remarkably, and the function of the transistor TG in the gate connection region may be impaired. There is. In order to avoid such a problem, the frame insulating film WSW is not formed in FIGS. Therefore, if the width of the first opening CV1 becomes narrow due to miniaturization, the formed plug CT can be short-circuited with the gate electrode GE when the stopper film of the transistor TG is excessively etched by an error exceeding the short margin. There is sex.

  Therefore, in the present embodiment, the first opening CV1 is formed first, and the framed insulating film WSW is formed. For this reason, even if the first opening CV1 is formed so as to etch the insulating film excessively, the conductive part constituting the plug CT and the gate electrode GE are formed by the additionally formed framed insulating film WSW. The short circuit is suppressed.

  Further, since the second opening CV2 is formed in a state where the inside of the first opening CV1 is filled with the first conductive layer PP1, the first opening CV2 is formed along with the etching for forming the second opening CV2. Generation | occurrence | production of malfunctions, such as the semiconductor substrate SUB directly under opening CV1, being etched, can be suppressed. This is because the first conductive layer PP1 protects the surface of the semiconductor substrate SUB. A part of the first conductive layer PP1 formed in the first opening CV1 is removed along with the etching for forming the second opening CV2. For this reason, the inside of the first opening CV1 is removed. In addition, it is possible to form the second conductive layer PP2, which is rather convenient.

  In the present embodiment, the plug CT in the active region has two layers of conductive portions, ie, a conductive portion PP1a and a conductive portion PP2a. This is because the first conductive layer PP1 (conductive portion PP1a) is formed after the first opening CV1 is formed, and then the first opening CV1 (and second) after the second opening CV2 is formed. This is because the second conductive layer PP2 (conductive portion PP2a) is formed in the opening CV2). Thus, by forming the conductive layers PP1 and PP2 in the first opening CV1 and the second opening CV2 as separate steps, the conductive portion constituting the plug CT can have a two-layer structure.

  When the conductive portion has a two-layer structure, the concentration of conductive impurities contained in each conductive portion can be changed as appropriate. Therefore, it is possible to increase the degree of freedom for adjusting the electrical characteristics such as the electrical resistance of the plug CT and the contact resistance with the transistor TG according to the design specifications of the semiconductor device.

  For example, in the present embodiment, the concentration of conductive impurities in the conductive portion PP2a formed on the upper side of the plug CT is higher than the concentration of conductive impurities in the conductive portion PP1a formed on the lower side of the plug CT. Yes. That is, the concentration of conductive impurities is lower on the lower side of the plug CT than on the upper side. For this reason, there is a possibility that a conductive impurity diffuses from the lower conductive portion PP1a of the plug CT to the source / drain region S / D connected thereto, thereby causing a problem that affects the electrical characteristics of the transistor TG. Can be reduced.

  Further, in order to obtain the above configuration, if the concentration of the conductive impurity in the second conductive layer PP2 is made higher than that in the first conductive layer PP1, the contact resistance between the plug SNC and the gate electrode GE in the gate connection region is reduced. It can be made smaller. For this reason, the driving capability of the transistor TG in the gate connection region can be further increased.

  As described above, the plug CT preferably has a lower concentration of conductive impurities particularly in the lower portion connected to the source / drain region S / D, and the plug SNC is electrically conductive in the lower portion connected to the gate electrode GE. It is preferable that the impurity concentration is higher. That is, it is more preferable that the electrical resistance of the plug SNC is lower than the electrical resistance of the plug CT.

(Embodiment 2)
The present embodiment is different from the first embodiment in the configuration of the conductive parts of the plugs CT and SNC and the manufacturing method thereof. First, with reference to FIG. 25, the aspect of the semiconductor device of this embodiment, in particular, the layer in which the transistor TG is formed will be described in more detail.

  Referring to FIG. 25, in the present embodiment, plug CT has one conductive portion of conductive portion PP2a (fourth conductive portion), and the source / drain region of transistor TG in the active region. Extends to reach S / D. In this way, the plug CT is electrically connected to the source / drain region S / D. On the other hand, the plug SNC has a two-layer conductive portion of a conductive portion PP1a (fifth conductive portion) and a conductive portion PP2b (sixth conductive portion), and is electrically connected to the gate electrode GE of the transistor TG. It is connected.

  Also in the present embodiment, it is preferable that all of the conductive portions PP1a, PP2a, PP2b constituting the plugs CT, SNC are made of polycrystalline silicon. The concentration of the conductive impurities (polycrystalline silicon) contained in the conductive portion PP1a is preferably higher than the concentration of the conductive impurities (polycrystalline silicon) contained in the conductive portions PP2a and PP2b. In other words, it is preferable that the concentration of the conductive impurities contained in the conductive portions PP2a and PP2b is lower than the concentration of the conductive impurities contained in the conductive portion PP1a. In the present embodiment, the conductive part PP2b is formed above the conductive part PP1a. For this reason, in the plug SNC in which the two-layer conductive portions PP1a and PP2b are formed, the concentration of the conductive impurity in the lower conductive portion is preferably higher than the concentration of the conductive impurity in the upper conductive portion.

  For example, the concentration of the conductive impurity contained in the conductive portion PP1a is more preferably twice or more the concentration of the conductive impurity contained in the conductive portions PP2a and PP2b. However, the relationship of the concentration of conductive impurities contained in the conductive portions PP2a, PP2b and the conductive portion PP1a can be arbitrarily adjusted according to the design specifications and required functions of the semiconductor device. For example, the conductive portion PP2a , PP2b and conductive portion PP1a may have substantially the same concentration of conductive impurities.

  With the above configuration, also in the present embodiment, it is preferable that the plug SNC as a whole has a higher concentration of conductive impurities and a lower electric resistance than the plug CT.

  Also in the present embodiment, the crystal grains of the conductive material (polycrystalline silicon) included in the conductive portion PP1a are larger than the crystal grains of the conductive material (polycrystalline silicon) included in the conductive portions PP2a and Pp2b. preferable.

  The configuration of the present embodiment shown in FIG. 25 differs from the configuration of the first embodiment shown in FIG. 5 in the above points, and the configuration of the first embodiment shown in FIG. 5 in other points. Therefore, the same elements are denoted by the same reference numerals, and the description thereof will not be repeated.

  Next, a method for manufacturing the region shown in FIG. 25 of the semiconductor device (Advanced SRAM) of the present embodiment will be described with reference to FIGS.

  Referring to FIG. 26, basically the same processing as that shown in FIGS. 6 to 8 of the present embodiment is performed, and then preliminary insulating film RI is formed in the same manner as in the step of FIG. Next, a resist pattern PHR is formed on the preliminary insulating film RI as in the step of FIG.

  Referring to FIG. 27, the second opening CV <b> 2 is formed by performing the same process as that in FIGS. 15 to 16.

  Referring to FIG. 28, third conductive layer PP1 made of, for example, polycrystalline silicon and containing conductive impurities is formed on preliminary insulation film RI by, for example, the CVD method so as to fill second opening CV2. Is done.

  Referring to FIG. 29, third conductive layer PP1 formed approximately above the height of the uppermost surface of transistor TG (insulating film IL) is etched back. The top surface of the third conductive layer PP1 may be etched back so as to be slightly lower than the height of the top surface of the transistor TG (insulating film IL). However, it is preferable that the third conductive layer PP1 remains in at least a region in contact with the gate electrode GE in the third conductive layer PP1.

  Referring to FIGS. 30 and 31, a resist pattern PHR is formed in the same manner as in the steps of FIGS. 9 and 10 in a state in which at least part of second opening CV2 is filled with third conductive layer PP1. Thereafter, in the breakthrough process, the preliminary insulating film RI that is not covered with the resist pattern PHR (that is, in the active region) is removed by etching, and subsequently, the interlayer insulating layer II1 in a region sandwiched between adjacent transistors TG in the active region. Are removed by etching. Next, the liner film LF in the region where the interlayer insulating layer II1 has been removed is removed. By this processing, the first opening CV1 is formed. Note that the preliminary insulating film RI that has not been removed in the breakthrough process (covered by the resist pattern PHR) is removed, for example, when the liner film LF is removed after the resist pattern PHR is removed.

  In addition, when almost the entire second opening CV2 is filled with the third conductive layer PP1 at this time, at least the upper part of the second opening CV2 is not filled with the third conductive layer PP1. It is preferable that a part of the third conductive layer PP1 is removed by etching so that However, in the etch-back step shown in FIG. 29, this process may not be performed if the upper portion of the second opening CV2 has already been etched. As described above, it is preferable that the third conductive layer PP1 remains at least in a region in contact with the gate electrode GE after the etching. By etching a part of the third conductive layer PP1, the remaining third conductive layer PP1 becomes the fifth conductive portion PP1a.

Referring to FIG. 32, framed insulating film WSW is formed in the same manner as in the process of FIG.
After that, the fourth opening CV2 is filled with the region where the first conductive layer PP1 is removed (upper portion of the first conductive portion) and the second opening CV2 by, for example, the CVD method. Conductive layer PP2 is formed.

  Fourth conductive layer PP2 is preferably made of, for example, polycrystalline silicon and contains conductive impurities. Here, the conductive impurities contained in the third conductive layer PP1 and the fourth conductive layer PP2 can have an optimum concentration according to the design specifications of the semiconductor device to be formed. For this reason, the third conductive layer PP1 and the fourth conductive layer PP2 may have different concentrations. For example, the third conductive layer PP1 has a higher concentration of conductive impurities than the fourth conductive layer PP2. May be higher.

  Thereafter, the fourth conductive layer PP2 formed approximately above the height of the uppermost surface of the transistor TG (insulating film IL) is etched back. In this way, as shown in FIG. 25, the fourth conductive layer PP2 is formed as the fourth conductive portion PP2a in the first opening CV1, and the sixth conductive layer PP2a in the second opening CV2. It is formed as a conductive part PP2b. For example, if the concentration of conductive impurities contained in the third conductive layer PP1 is higher than that in the fourth conductive layer PP2, the fifth conductive portion PP1a is included more than the fourth conductive portion PP2a and the sixth conductive portion PP2b. The concentration of conductive impurities to be increased. As a result, since the plug SNC including the fifth and sixth conductive portions PP1a and PP2b as a whole has a higher concentration of conductive impurities than the plug CT including the fourth conductive portion PP2a as a whole, the electrical resistance is increased. Lower.

Next, the effect of this Embodiment is demonstrated.
In the present embodiment, unlike the first embodiment, the second opening CV2 in the gate connection region is formed before the first opening CV1. However, in this embodiment, immediately after the second opening CV2 is formed, the inside (a part of) the second opening CV2 is filled with the third conductive layer PP1. In this manner, the first opening CV1 is formed in a state where the inner wall surface (a part) of the second opening CV2 is covered with the third conductive layer PP1, and the frame insulating film WSW is formed. Therefore, the possibility that the framed insulating film WSW is unintentionally formed on the inner wall surface of the second opening CV2 and the electrical characteristics of the plug SNC are impaired can be reduced. Therefore, even if the plug CT is thinned, the effect of suppressing a short circuit with the adjacent gate electrode GE can be enhanced.

  In the manufacturing method of the comparative example shown in FIGS. 19 to 24, after the second opening CV2 is formed before the first opening CV1, the inside of the second opening as shown in FIG. Is covered with a resist pattern PHR. However, it is necessary to remove the resist pattern PHR before forming an insulating film such as a silicon nitride film for forming the framed insulating film WSW. That is, it is necessary to form the framed insulating film WSW in the state shown in FIG. For this reason, the frame insulating film WSW is also formed inside the second opening CV2.

  In addition, since the first opening CV1 is not formed at the time when the second opening CV2 is formed, the semiconductor substrate immediately below the first opening CV1 accompanies the etching for forming the second opening CV2. Generation | occurrence | production of malfunctions, such as SUB being etched, can be suppressed.

  In the present embodiment, the plug SNC in the gate connection region has two layers of conductive portions, that is, a conductive portion PP1a and a conductive portion PP2b. This is because the third conductive layer PP1 (conductive portion PP1a) is formed after the second opening CV2 is formed, and then the first opening CV1 (and the second opening CV1 is formed after the first opening CV1 is formed). This is because the fourth conductive layer PP2 (conductive portion PP2a and conductive portion PP2b) is formed in the opening CV2). Thus, by forming the conductive layers PP1 and PP2 in the first opening CV1 and the second opening CV2 as separate steps, the conductive portion constituting the plug SNC can have a two-layer structure.

  When the conductive portion has a two-layer structure, the concentration of conductive impurities contained in each conductive portion can be changed as appropriate. Therefore, it is possible to increase the degree of freedom for adjusting the electrical characteristics such as the electrical resistance of the plug SNC and the contact resistance with the transistor TG according to the design specifications of the semiconductor device.

  For example, in the present embodiment, the concentration of conductive impurities in the conductive portion PP1a of the plug SNC is higher than the concentration of conductive impurities in the conductive portion PP2a formed in the plug CT. That is, the concentration of conductive impurities is lower on the lower side of the plug CT than on the lower side of the plug SNC. For this reason, there is a possibility that a conductive impurity diffuses from the conductive part PP2a below the plug CT to the source / drain region S / D connected to the conductive part PP2a, thereby causing a problem that affects the electrical characteristics of the transistor TG. Can be reduced.

  Further, in order to obtain the above configuration, if the concentration of the conductive impurity in the third conductive layer PP1 is made higher than that in the fourth conductive layer PP2, the contact resistance between the plug SNC and the gate electrode GE in the gate connection region is reduced. It can be made smaller. For this reason, the driving capability of the transistor TG in the gate connection region can be further increased. This is because the lower side of the plug SNC (that is, the region in contact with the gate electrode GE) is in contact with the conductive portion PP1a having a higher concentration of conductive impurities.

  As described above, the plug CT preferably has a lower concentration of conductive impurities particularly in the lower portion connected to the source / drain region S / D, and the plug SNC is electrically conductive in the lower portion connected to the gate electrode GE. It is preferable that the impurity concentration is higher. That is, it is more preferable that the electrical resistance of the plug SNC is lower than the electrical resistance of the plug CT.

  The second embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like not described above for the second embodiment of the present invention are all the same as those of the first embodiment of the present invention.

  In the above description, an advanced SRAM using so-called TFTs as load transistors T3 and T4 (see FIG. 3) has been described. However, a multi-layer connection layer between the upper layer and the lower layer is used regardless of the use of TFTs. The present invention may be applied to a semiconductor device using a connection layer made of crystalline silicon.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be particularly advantageously applied to a semiconductor device using polycrystalline silicon as a connection layer between an upper layer and a lower layer.

  1F active region, 2G lower layer wiring, BL, ZBL bit line, C1, C2 capacitor, CT, SNC plug, CTC, SC contact conductive layer, CV1 first opening, CV2 second opening, D drain electrode, DB Data node contact, ETI additional insulating film, GE gate electrode, GI gate insulating film, I1, II1-II10 interlayer insulating layer, IL insulating film, LF liner film, MCT metal contact conductive layer, MTL metal wiring, PHR resist pattern, PP1 First (third) conductive layer, PP2 Second (fourth) conductive layer, PP1a, PP2a, PP2b conductive portion, PWL p-type well region, RI preliminary insulating film, S source electrode, SI insulating layer, SUB semiconductor Substrate, SW sidewall insulating film, T1, T2 driver transistor, T3, T4 negative Transistors, T5, T6 access transistor, TD gate electrode layer, TG transistor, TP polycrystalline silicon layer, WL the word line, WSW frame with insulating film.

Claims (17)

A semiconductor substrate having a main surface;
An active region formed on the main surface of the semiconductor substrate;
A gate connection region formed around the active region in plan view;
A first for electrically connecting the first transistor and a layer above the first transistor, which is formed in a region sandwiched between the plurality of first transistors formed on the active region. A connection layer of
A second transistor formed on the gate connection region; and a second connection layer for electrically connecting a layer above the second transistor;
The semiconductor device, wherein the first connection layer includes a first conductive portion and a second conductive portion, and the second connection layer includes a third conductive portion.   2. The semiconductor device according to claim 1, wherein a concentration of conductive impurities contained in the second and third conductive portions is higher than a concentration of conductive impurities contained in the first conductive portion.   The semiconductor device according to claim 2, wherein the second conductive portion is formed on the first conductive portion in the first connection layer.   The crystal grain of the conductive material contained in the first conductive part is larger than the crystal grain of the conductive material contained in the second and third conductive parts. Semiconductor device. A semiconductor substrate having a main surface;
An active region formed on the main surface of the semiconductor substrate;
A gate connection region formed around the active region in plan view;
A first for electrically connecting the first transistor and a layer above the first transistor, which is formed in a region sandwiched between the plurality of first transistors formed on the active region. A connection layer of
A second transistor formed on the gate connection region; and a second connection layer for electrically connecting a layer above the second transistor;
The semiconductor device, wherein the first connection layer includes a fourth conductive portion, and the second connection layer includes a fifth conductive portion and a sixth conductive portion.   The semiconductor device according to claim 5, wherein the concentration of the conductive impurity contained in the fifth conductive portion is higher than the concentration of the conductive impurity contained in the fourth and sixth conductive portions.   The semiconductor device according to claim 6, wherein in the second connection layer, the sixth conductive portion is formed on the fifth conductive portion.   The crystal grain of the conductive material contained in the fifth conductive part is larger than the crystal grain of the conductive material contained in the fourth and sixth conductive parts. Semiconductor device.   The semiconductor device according to claim 1, wherein an electric resistance of the second connection layer is lower than an electric resistance of the first connection layer.   The semiconductor device according to claim 1, wherein a sidewall insulating film and a framed insulating film that covers the sidewall insulating film are formed on the sidewall of the first transistor. Preparing a semiconductor substrate having a main surface;
Forming on the main surface of the semiconductor substrate an active region and a gate connection region disposed around the active region in plan view;
A step of forming a first opening by removing an interlayer insulating layer formed in a region sandwiched between a plurality of first transistors formed on the active region;
Forming a framed insulating film so as to cover the sidewall of the first transistor exposed by forming the first opening;
Forming a first conductive layer to fill the first opening;
After the step of forming the first conductive layer, forming a second opening so as to remove a part of the gate electrode of the second transistor formed in the gate connection region;
Removing a portion of the first conductive layer in the first opening to form a first conductive portion;
Forming a second conductive layer on the first conductive portion in the first opening and filling the second opening;
Removing the second conductive layer on the first and second openings to include the first conductive portion and a second conductive portion as a part of the second conductive layer; A first connection layer for electrically connecting the first transistor and a layer above the first transistor; and a third conductive portion as a part of the second conductive layer; Forming a second connection layer for electrically connecting the second transistor and a layer above the second transistor. A method for manufacturing a semiconductor device. The step of forming the second opening includes the step of patterning the first conductive layer with a pattern of a photosensitive agent covering a region other than a region overlapping the second opening in plan view.
After removing the pattern of the photosensitive agent, the first conductive layer in the step of patterning the first conductive layer using the pattern of the first conductive layer formed in the step of patterning the first conductive layer. Removing a part of each layer from a layer in contact with the lower side of the first conductive layer to a region reaching the gate electrode of the second transistor, which overlaps the etched region of the conductive layer in a plane. The manufacturing method of the semiconductor device of Claim 11 containing this.   The method for manufacturing a semiconductor device according to claim 11, wherein a concentration of the conductive impurity contained in the second conductive layer is higher than a concentration of the conductive impurity contained in the first conductive layer.   The method of manufacturing a semiconductor device according to claim 13, wherein the second conductive portion is formed on the first conductive portion in the first connection layer. Preparing a semiconductor substrate having a main surface;
Forming on the main surface of the semiconductor substrate an active region and a gate connection region disposed around the active region in plan view;
Forming a second opening so as to remove a part of the gate electrode of the second transistor formed in the gate connection region;
Forming a third conductive layer to fill the second opening;
After the step of forming the third conductive layer, an interlayer insulating layer formed in a region sandwiched between the plurality of first transistors formed on the active region is removed, so that the first opening is formed. Forming a step;
Forming a framed insulating film so as to cover the sidewall of the first transistor exposed by forming the first opening;
Removing a portion of the third conductive layer in the second opening to form a fifth conductive portion;
Forming a fourth conductive layer on the fifth conductive portion in the second opening and filling the first opening;
The fourth conductive layer as a part of the fourth conductive layer is removed by removing the fourth conductive layer on the first and second openings, and the first transistor and the first transistor A first connection layer for electrically connecting a layer above one transistor; a sixth conductive portion as a part of the fifth conductive portion and the fourth conductive layer; Forming a second connection layer for electrically connecting the second transistor and a layer above the second transistor. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 15, wherein the concentration of the conductive impurity contained in the third conductive layer is higher than the concentration of the conductive impurity contained in the fourth conductive layer.   The method of manufacturing a semiconductor device according to claim 16, wherein the sixth conductive portion is formed on the fifth conductive portion in the second connection layer.

Images