JP2013015416A - Inspection method of semiconductor element, and semiconductor inspection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly determine presence/absence of occurrence of current collapse in a field effect transistor.SOLUTION: An inspection method of a semiconductor element includes a first step of calculating a first on-resistance of a field effect transistor 101 under a state where the field effect transistor 101 is in an on-state and a first voltage is applied to the drain of the field effect transistor 101; a second step of applying a second voltage larger than the first voltage is applied to the drain of the field effect transistor 101 while the field effect transistor 101 is in an off-state; and calculating a second on-resistance of the field effect transistor 101 under a state where the field effect transistor 101 is in the on-state and the second voltage is applied to the drain of the field effect transistor 101.

Description

  The present invention relates to a field effect transistor inspection method and a semiconductor inspection apparatus.

  A nitride semiconductor has a larger band gap, breakdown electric field, and saturation drift velocity of electrons than silicon (Si) or gallium arsenide (GaAs). In addition, in the heterostructure (AlGaN / GaN) of aluminum gallium nitride (AlGaN) and gallium nitride (GaN) formed on a substrate with the (0001) plane as the main surface, the heterointerface is two-dimensional due to spontaneous polarization and piezoelectric polarization. Electron gas is generated.

For this reason, a sheet carrier concentration of about 1 × 10 ¹³ cm ⁻² or more can be obtained without doping impurities. Transistors using this high-concentration two-dimensional electron gas as a carrier (see Non-Patent Documents 1 and 2) have recently attracted attention.

  In a field effect transistor using a GaN HEMT structure, a so-called current collapse phenomenon occurs, which adversely affects device applications. Current collapse is a phenomenon in which, when a high voltage is applied between the drain and source when the field effect transistor is off, the on-resistance when the field effect transistor is on increases compared to before the high voltage is applied. A device in which current collapse occurs is not suitable for practical use. Therefore, it is necessary to remove a device having a large current collapse by inspection.

  Non-Patent Document 3 discloses a current collapse inspection method for a field effect transistor (hereinafter also referred to as a conventional current collapse inspection method) using a semiconductor test system. In the conventional current collapse inspection method, first, the initial on-resistance of the field effect transistor is calculated (measured). Next, a high voltage is applied to the field effect transistor, and then the on-resistance of the field effect transistor is calculated (measured) again after an interval of about 10 seconds. Then, the current collapse is evaluated based on the on-resistance ratio before and after the high voltage application (see Non-Patent Document 3).

J. Z. Li, H. X. Jiang, M. A. Khan, Q. Chen, “Two-dimensional electron gas in AlGaN / GaN heterostructures”, Journal of Vacuum Science and Technology, 1997, B15, p. 1117-1120 S.C. Binari, W. Kruppa, H.B. Dietrich, G. Kelner, A.E.Wickenden, and J.A. Freitas Jr., “Fabrication and characterization of GaN FETs”, Solid State Electronics, 1997, 41, p. 1549-1554 Ikeda Naruaki, 10 others, “Development of high power GaN HFET on Si substrate”, Furukawa Electric Times, Furukawa Electric Co., Ltd., September 2008, No. 122, p22-28

  However, the conventional current collapse inspection method requires a long interval of 10 seconds, and thus there is a problem in that it is not possible to quickly determine whether or not a current collapse has occurred.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide an inspection method and a semiconductor inspection apparatus capable of quickly determining whether or not a current collapse occurs in a field effect transistor. And

  In order to achieve the above object, a semiconductor element inspection method according to one embodiment of the present invention is an inspection method for inspecting a field-effect transistor as a semiconductor element. In the inspection method, the field effect transistor is turned on by applying a voltage to the gate of the field effect transistor, and the first voltage is applied to the drain of the field effect transistor. A first step of calculating a first on-resistance which is an on-resistance; and after the first step, the application of the voltage to the gate of the field-effect transistor is stopped to turn off the field-effect transistor, and A second step of applying a second voltage greater than the first voltage to the drain of the field effect transistor; and after applying the voltage to the gate of the field effect transistor after the second step, the field effect transistor. And the second voltage is applied to the drain of the field effect transistor. In pressurized state, and a third step of calculating a second on-resistance is the on resistance of the field effect transistor.

  That is, in the semiconductor element inspection method according to one embodiment of the present invention, the field effect transistor is actively switched between the on state and the off state. Also, the first on-resistance is calculated before the field effect transistor is turned off, and after the field effect transistor is turned off, a second voltage higher than the first voltage is applied to the field effect transistor. Thereafter, a second on-resistance which is the on-resistance of the field effect transistor is calculated.

  As a result, the first on-resistance and the second on-resistance can be calculated quickly. Therefore, for example, by comparing the first on-resistance and the second on-resistance, it is possible to quickly determine whether or not the current collapse occurs in the field effect transistor.

  Preferably, in the first step, a current flowing between the drain and the source in the field effect transistor in the on state and a voltage applied between the drain and the source in the field effect transistor in the on state. And calculating the first on-resistance, and in the third step, the current flowing between the drain and the source in the field effect transistor in the on state, the drain in the field effect transistor in the on state, The second on-resistance is calculated using a voltage applied between the source and the source.

  Preferably, the inspection method further includes a step of calculating a ratio of the second on-resistance to the first on-resistance as an on-resistance ratio of the field effect transistor.

  Preferably, in the inspection method, the first step and the second step are repeated twice or more, and the third step includes the first step and the second step twice or more. It is done after repeated.

  The semiconductor inspection apparatus which concerns on 1 aspect of this invention is a semiconductor inspection apparatus which performs the said inspection method. The semiconductor inspection apparatus includes: a first drive circuit that controls supply of a voltage to a gate of the field effect transistor; and a first drive circuit that applies the first voltage or the second voltage to a drain of the field effect transistor. 2 drive circuit.

  Preferably, the first drive circuit supplies a pulse voltage to the gate of the field effect transistor.

  Preferably, the second drive circuit has a configuration capable of controlling an amount of drain current in the field effect transistor.

  According to the present invention, it is possible to quickly determine whether or not a current collapse occurs in a field effect transistor.

1 is a diagram showing a configuration of a semiconductor inspection apparatus according to a first embodiment of the present invention. It is a timing chart which shows the inspection method of the field effect transistor based on the 1st Embodiment of this invention. It is a flowchart of the test | inspection method for test | inspecting the field effect transistor as a semiconductor element. It is a figure which shows the structure of the semiconductor inspection apparatus which concerns on the 2nd Embodiment of this invention. It is a timing chart which shows the inspection method of the field effect transistor based on the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor inspection apparatus which concerns on the 3rd Embodiment of this invention. It is a timing chart which shows the inspection method of the field effect transistor based on the 3rd Embodiment of this invention. It is a figure which shows the structure of the semiconductor inspection apparatus which concerns on the 4th Embodiment of this invention. It is a timing chart which shows the inspection method of the field effect transistor based on the 4th Embodiment of this invention. It is a figure which shows the structure of the semiconductor inspection apparatus which concerns on the 5th Embodiment of this invention. It is a timing chart which shows the inspection method of the field effect transistor based on the 5th Embodiment of this invention. It is a figure which shows the structure of the semiconductor inspection apparatus which concerns on the 6th Embodiment of this invention. It is a timing chart which shows the inspection method of the field effect transistor based on the 6th Embodiment of this invention.

  In the following description, the same components are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof may be omitted.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A is a diagram showing a configuration of a semiconductor inspection apparatus 100 according to the first embodiment of the present invention.

  As illustrated in FIG. 1A, the semiconductor inspection apparatus 100 includes a gate drive circuit 102, a drive circuit 103, a measurement unit 120, and a determination unit 130.

  The field effect transistor 101 is a transistor to be inspected. The field effect transistor 101 is not included in the semiconductor inspection apparatus 100. The field effect transistor 101 is a high electron mobility transistor (HEMT).

  The field effect transistor 101 is not limited to the HEMT, and may be a field effect transistor having another structure. The conductivity type of the field effect transistor 101 may be either N-type or P-type.

  The field effect transistor 101 has a gate G1, a drain D1, and a source S1. Hereinafter, the gate G1, the drain D1, and the source S1 of the field effect transistor 101 are also simply referred to as a gate, a drain, and a source, respectively.

  The gate drive circuit 102 is composed of, for example, a pulse generator or a function generator. The gate drive circuit 102 controls the supply of voltage to the gate of the field effect transistor. Specifically, the gate driving circuit 102 supplies a pulse voltage.

  The drive circuit 103 includes a low voltage power source 104, a low load resistor 105, a power source protection diode 107, a high voltage power source 108, and a high load resistor 106.

  In other words, the drive circuit 103 includes two types of power supplies, that is, a first power supply and a second power supply.

  The first power source includes a low voltage power source 104, a low load resistor 105, and a power source protection diode 107. The second power source includes a high voltage power source 108 and a high load resistor 106.

  The power source protection diode 107, the low load resistor 105, and the low voltage power source 104 are connected in series. The cathode of the power protection diode 107 is connected to the drain D 1 of the field effect transistor 101.

  The low voltage power supply 104 supplies a voltage for calculating (measuring) the on-resistance of the field effect transistor 101. The low load resistor 105 is a resistor for limiting the amount of drain current directed to the field effect transistor 101. The power supply protection diode 107 is a diode for protecting the low voltage power supply 104.

  The high load resistor 106 and the high voltage power source 108 are connected in series. The second power source (high voltage power source 108) applies a high voltage between the drain and source of the field effect transistor 101.

  The voltage level supplied by the high voltage power supply 108 is higher than the voltage level supplied by the low voltage power supply 104. The voltage supplied by the high voltage power supply 108 is a high level voltage (high voltage) for determining whether or not the current collapse occurs in the field effect transistor 101 to be inspected. Hereinafter, a high level voltage for determining whether or not current collapse has occurred is also referred to as a high voltage for inspection.

  Hereinafter, the voltage supplied from the low voltage power source 104 via the low load resistor 105 and the power source protection diode 107 is also referred to as a first voltage. That is, the voltage supplied by the first power supply is the first voltage.

  In the following, the voltage that the high voltage power supply 108 supplies via the high load resistor 106 is also referred to as a second voltage. That is, the voltage supplied by the second power supply is the second voltage.

  The second voltage is greater than the first voltage. The second voltage is a high voltage for inspection.

  The high load resistor 106 is a resistor for limiting the amount of drain current directed to the field effect transistor 101. That is, the drive circuit 103 including the high load resistor 106 has a configuration capable of controlling the amount of drain current in the field effect transistor 101.

  Drive circuit 103 further includes a current probe 109 and a switch 110. The drive circuit 103 performs on / off control of the switch 110. When the switch 110 is turned on, one end of the high load resistor 106 and the drain D1 of the field effect transistor 101 are electrically connected. When the switch 110 is turned off, one end of the high load resistor 106 and the drain D1 of the field effect transistor 101 are electrically disconnected.

  A gate drive circuit 102 is connected to the gate G 1 of the field effect transistor 101. A drive circuit 103 is connected to the drain D1 of the field effect transistor 101. The source S1 of the field effect transistor 101 is grounded.

  The measuring unit 120 has a function of measuring a current using the current probe 109 and a function of measuring a drain-source voltage (Vds) of the field effect transistor 101, as will be described in detail later. In addition, although the connection line is not shown for simplification of the drawing, the measurement unit 120 is connected to the current probe 109, the drain D1, and the source S1.

  Although details will be described later, the determination unit 130 determines whether or not a current collapse has occurred.

  FIG. 1B is a timing chart showing an inspection method of the field effect transistor 101 according to the first embodiment of the present invention. In FIG. 1B, Vgs is a gate-source voltage of the field effect transistor 101. Vd is the drain voltage of the field effect transistor 101. Ids is a drain current flowing between the drain and source of the field effect transistor 101. Vds is a drain-source voltage of the field effect transistor 101.

  Hereinafter, the on-resistance calculated (measured) in the period T1 is also referred to as a first on-resistance. In the following, the on-resistance calculated (measured) in the period T3 is also referred to as a second on-resistance.

  Next, processing for inspecting the field effect transistor 101 will be described.

  FIG. 1C is a flowchart of an inspection method for inspecting a field effect transistor as a semiconductor element.

  As shown in FIG. 1B, the voltage (first voltage) supplied by the low voltage power supply 104 via the low load resistor 105 and the power supply protection diode 107 in the period T1 is supplied to the drain D1 of the field effect transistor 101. The

  In the period T <b> 1, the gate driver circuit 102 supplies a pulse voltage for turning on the field effect transistor 101 to the gate G <b> 1 of the field effect transistor 101. Accordingly, in the period T1, the field effect transistor 101 is turned on. Hereinafter, a pulse voltage for turning on the field effect transistor 101 is also referred to as an on-pulse voltage.

  A voltage (first voltage) supplied from the low voltage power supply 104 via the low load resistor 105 and the power supply protection diode 107 is applied to the drain D1 of the field effect transistor 101 in the on state. That is, the semiconductor inspection apparatus 100 applies a first voltage to the drain D1 of the field effect transistor 101 using the low voltage power supply 104. That is, the semiconductor inspection apparatus 100 calculates (measures) the on-resistance of the field-effect transistor 101 after applying the first voltage to the drain D1 of the field-effect transistor 101 and turning on the field-effect transistor 101 ( S110).

  Calculation (measurement) of the on-resistance during the period T1 is performed as follows. For example, the measurement unit 120 measures the drain voltage Vds and the drain current Ids when 30 μs (microseconds) have elapsed since the field-effect transistor 101 is turned on. The drain current Ids is measured using the current probe 109, for example. Then, the measurement unit 120 calculates (measures) the on-resistance from the measured Vds and Ids according to the on-resistance = Vds / Ids (S110).

  That is, the process of step S110 is performed by applying a voltage to the gate of the field effect transistor to turn on the field effect transistor and applying the first voltage to the drain of the field effect transistor. This is a step of calculating a first on-resistance which is an on-resistance of the effect transistor.

  In the process of step S110, the measurement unit 120 is applied between the current flowing between the drain and the source in the field effect transistor in the on state and the drain and the source in the field effect transistor in the on state. The first on-resistance is calculated using the voltage.

  Next, in the period T <b> 2, the gate drive circuit 102 turns off the field effect transistor 101 by stopping supply of voltage (pulse voltage) to the gate G <b> 1 of the field effect transistor 101. Then, the drive circuit 103 turns on the switch 110. As a result, a voltage (second voltage) supplied from the high voltage power supply 108 via the high load resistor 106 is applied to the drain D1 of the field effect transistor 101. That is, the semiconductor inspection apparatus 100 applies a high voltage (second voltage) between the drain and the source of the field effect transistor 101 in the off state using the high voltage power supply 108 (S120).

  That is, the process of step S120 turns off the field effect transistor by stopping the application of the voltage to the gate of the field effect transistor, and applies a second voltage higher than the first voltage to the field effect transistor. This is a step of applying to the drain.

  Next, in the period T <b> 3, the gate drive circuit 102 turns on the field effect transistor 101 by supplying an on-pulse voltage to the gate G <b> 1 of the field effect transistor 101. At this time, a high voltage is applied from the high voltage power supply 108 to the drain D1 of the field effect transistor 101 in the on state. That is, the semiconductor inspection apparatus 100 calculates (measures) the on-resistance of the field effect transistor 101 using the high voltage power supply 108 (S130).

  Calculation (measurement) of the on-resistance in the period T3 is performed similarly to the calculation of the on-resistance in the period T1. That is, the measurement unit 120 measures, for example, the drain voltage Vds and the drain current Ids after 30 μs have elapsed since the field effect transistor 101 is turned on, and calculates (measures) the on-resistance from the Vds and Ids. To do.

  That is, in the process of step S130, the field effect transistor is turned on by applying a voltage to the gate of the field effect transistor, and the second voltage is applied to the drain of the field effect transistor. This is a step of calculating a second on-resistance which is an on-resistance of the field effect transistor.

  In the process of step S130, the measurement unit 120 is applied between the current flowing between the drain and the source in the field effect transistor in the on state and the drain and the source in the field effect transistor in the on state. The second on-resistance is calculated using the voltage.

  Then, the measuring unit 120 calculates the ratio of the second on-resistance to the first on-resistance as the on-resistance ratio of the field effect transistor (S140). The field effect transistor is the field effect transistor 101. The on-resistance ratio is calculated by the second on-resistance / first on-resistance.

  When the on-resistance ratio is greater than 1, the determination unit 130 determines that a current collapse has occurred. Further, the determination unit 130 may simply compare the first on-resistance with the second on-resistance, and may determine that a current collapse has occurred when the second on-resistance is greater than the first on-resistance.

  However, in the determination of the on-resistance ratio, for example, when the on-resistance ratio of the transistor to be inspected is less than 1.2, it is assumed that the transistor is an acceptable non-defective product. In this case, all transistors to be inspected with an on-resistance ratio of 1.2 or less are determined to be non-defective products even if current collapse occurs.

  As described above, according to the present embodiment, the field effect transistor is actively switched between the on state and the off state. Also, the first on-resistance is calculated before the field effect transistor is turned off, and after the field effect transistor is turned off, a second voltage higher than the first voltage is applied to the field effect transistor. Thereafter, a second on-resistance which is the on-resistance of the field effect transistor is calculated.

  As a result, the first on-resistance and the second on-resistance can be calculated quickly. Therefore, by calculating the on-resistance ratio or comparing the first on-resistance and the second on-resistance, it is possible to quickly determine whether or not the current collapse occurs in the field effect transistor.

  Conventionally, there is no report on a method for evaluating current collapse in an early time region of several μs to 100 μs which is practically important for an inverter or the like. Therefore, as described above, the inventors of the present application have applied the electric field after several μs to 100 μs have elapsed since a high voltage was applied between the drain and the source in order to determine whether or not the current collapse of the field effect transistor has occurred. A method for calculating (measuring) the current-voltage characteristics of the effect transistor has been devised. As a result, it is possible to evaluate the on-resistance in a time as short as several μs, and the current collapse of the field effect transistor can be evaluated.

  Note that the second on-resistance used for calculating the on-resistance ratio is not the second on-resistance, but the field-effect transistor 101 after switching between the on-state and the off-state a plurality of times (for example, 100 times). The on-resistance of may be sufficient. That is, the semiconductor inspection apparatus 100 may perform the processes of steps S130 and S140 after repeatedly performing the processes of steps S110 and S120 twice or more.

  In this case, the inspection method of FIG. 1C repeats the first step (S110) and the second step (S120) two or more times. In this case, the third step (S130) is performed after the first step and the second step are repeated twice or more.

(Second Embodiment)
Below, the 2nd Embodiment of this invention is described, referring drawings.

  FIG. 2A is a diagram showing a configuration of a semiconductor inspection apparatus 100A according to the second embodiment of the present invention.

  As shown in FIG. 2A, the semiconductor inspection apparatus 100A is different from the semiconductor inspection apparatus 100 of FIG. 1A in that a drive circuit 103A is provided instead of the drive circuit 103. Since the other configuration of semiconductor inspection apparatus 100A is the same as that of semiconductor inspection apparatus 100, detailed description will not be repeated.

  Drive circuit 103 </ b> A includes a power supply 111 and a load resistor 112.

  In other words, the drive circuit 103A includes one power source, that is, the power source A. The power source A is composed of a power source 111 and a load resistor 112. The power source 111 has a function of supplying both a high voltage and a low voltage. The load resistor 112 is a resistor for limiting the amount of drain current directed to the field effect transistor 101.

  In addition, the drive circuit 103A further includes a current probe 109.

  A drive circuit 103 </ b> A is connected to the drain D <b> 1 of the field effect transistor 101.

  FIG. 2B is a timing chart showing the inspection method of the field effect transistor 101 according to the second embodiment of the present invention. Vgs, Vd, Ids, and Vds are the same as described in FIG. 1B.

  As illustrated in FIG. 2B, in the period T1A, the gate drive circuit 102 supplies the on-pulse voltage to the gate G1 of the field effect transistor 101, thereby turning on the field effect transistor 101. In the period T <b> 1 </ b> A, the voltage supplied from the power source A, that is, the voltage supplied from the power source 111 via the load resistor 112 is applied to the drain D <b> 1 of the field effect transistor 101. That is, the semiconductor inspection apparatus 100 </ b> A applies a voltage to the drain D <b> 1 of the field effect transistor 101 using the power source 111. That is, the semiconductor inspection apparatus 100A calculates (measures) the on-resistance of the field-effect transistor 101 after turning on the field-effect transistor 101 and applying a voltage to the drain of the field-effect transistor 101 (S110).

  Since the calculation (measurement) of the on-resistance in the period T1A is the same as the on-resistance calculation method in the period T1 described in the first embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T1A is also referred to as a first on-resistance.

  Next, in the period T <b> 2 </ b> A, the gate drive circuit 102 turns off the field effect transistor 101 by stopping the supply of voltage (on-pulse voltage) to the gate G <b> 1 of the field effect transistor 101. At this time, a high voltage supplied from the power source 111 via the load resistor 112 is applied to the drain D1 of the field effect transistor 101 in the off state. That is, the semiconductor inspection apparatus 100A applies a high voltage between the drain and source of the field effect transistor 101 using the power supply 111 (S120).

  Next, in the period T <b> 3 </ b> A, the gate drive circuit 102 supplies the pulse voltage to the gate G <b> 1 of the field effect transistor 101 to turn on the field effect transistor 101. At this time, a high voltage is applied from the power supply 111 to the drain D1 of the field effect transistor 101 in the on state. That is, the semiconductor inspection apparatus 100A calculates (measures) the on-resistance of the field effect transistor 101 using the power supply 111 (S130).

  Since the calculation (measurement) of the on-resistance in the period T3A is the same as the method for calculating the on-resistance in the period T3 described in the first embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T3A is also referred to as a second on-resistance.

  Then, the measurement unit 120 of the semiconductor inspection apparatus 100A calculates the on-resistance ratio of the field effect transistor 101 as in the first embodiment (S140).

  And the determination part 130 determines whether the current collapse has arisen similarly to 1st Embodiment.

  By performing the processing described above, the present embodiment can provide the same effects as those of the first embodiment. That is, it is possible to quickly determine whether or not a current collapse occurs in the field effect transistor.

  Note that the second on-resistance used for calculating the on-resistance ratio is not the second on-resistance, but the field-effect transistor 101 after switching between the on-state and the off-state a plurality of times (for example, 100 times). The on-resistance of may be sufficient. That is, the semiconductor inspection apparatus 100A may perform the processes in steps S130 and S140 after repeatedly performing the processes in steps S110 and S120 twice or more.

(Third embodiment)
Below, the 3rd Embodiment of this invention is described, referring drawings.

  FIG. 3A is a diagram showing a configuration of a semiconductor inspection apparatus 100B according to the third embodiment of the present invention.

  As shown in FIG. 3A, the semiconductor inspection apparatus 100B is different from the semiconductor inspection apparatus 100 of FIG. 1A in that a drive circuit 103B is provided instead of the drive circuit 103. Since the other configuration of semiconductor inspection apparatus 100B is the same as that of semiconductor inspection apparatus 100, detailed description will not be repeated.

  The drive circuit 103B is different from the drive circuit 103A of FIG. 2A in that it does not include the load resistor 112, and further includes a low load resistor 105, a high load resistor 106, and a switch 113. Since the other configuration of drive circuit 103B is the same as that of drive circuit 103A, detailed description will not be repeated.

  Drive circuit 103B includes one power source, that is, power source B. The power source B includes a power source 111, a low load resistor 105, and a high load resistor 106. Each of the low load resistor 105 and the high load resistor 106 is a resistor for limiting the amount of drain current.

  The switch 113 is a three-point switch. The drive circuit 103B controls the switch 113. The switch 113 has a function of electrically connecting the power source 111 and the low load resistor 105 and a function of electrically connecting the power source 111 and the high load resistor 106.

  A drive circuit 103B is connected to the drain D1 of the field effect transistor 101.

  FIG. 3B is a timing chart showing an inspection method of the field effect transistor 101 according to the third embodiment of the present invention. Vgs, Vd, Ids, and Vds are the same as described in FIG. 1B.

  As illustrated in FIG. 3B, in the period T1B, the gate drive circuit 102 supplies the on-pulse voltage to the gate G1 of the field effect transistor 101, thereby turning on the field effect transistor 101. In the period T1B, the driver circuit 103B controls the switch 113 so that the low load resistor 105 and the power source 111 are electrically connected. As a result, the voltage supplied from the power supply 111 is applied to the drain D1 of the field effect transistor 101 in the on state via the low load resistor 105.

  That is, in the period T1B, the semiconductor inspection apparatus 100B turns on the field effect transistor 101, applies a voltage to the drain of the field effect transistor 101, and measures (calculates) the on-resistance of the field effect transistor 101 ( S110).

  Since the calculation (measurement) of the on-resistance in the period T1B is the same as the method for calculating the on-resistance in the period T1 described in the first embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T1B is also referred to as a first on-resistance.

  Next, in the period T <b> 2 </ b> B, the gate driver circuit 102 turns off the field effect transistor 101 by stopping supply of voltage (on-pulse voltage) to the gate of the field effect transistor 101.

  In the period T2B, the drive circuit 103B controls the switch 113 so that the high load resistor 106 and the power source 111 are electrically connected. As a result, the voltage supplied from the power source 111 is applied to the drain D1 of the field effect transistor 101 via the high load resistor 106 (S120). That is, the semiconductor inspection apparatus 100B applies a high voltage between the drain and source of the field effect transistor 101 using the power supply 111 (S120).

  Next, in the period T <b> 3 </ b> B, the gate driver circuit 102 supplies the pulse voltage to the gate of the field effect transistor 101 to turn on the field effect transistor 101. At this time, a voltage supplied from the power supply 111 via the high load resistor 106 is applied to the drain D1 of the field effect transistor 101 in the on state. That is, the semiconductor inspection apparatus 100B calculates (measures) the on-resistance of the field effect transistor 101 using the power supply 111 (S130).

  Since the calculation (measurement) of the on-resistance in the period T3B is the same as the method for calculating the on-resistance in the period T3 described in the first embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T3B is also referred to as a second on-resistance.

  Then, the measurement unit 120 of the semiconductor inspection apparatus 100B calculates the on-resistance ratio of the field effect transistor 101 as in the first embodiment (S140).

  And the determination part 130 determines whether the current collapse has arisen similarly to 1st Embodiment.

  By performing the processing described above, the present embodiment can provide the same effects as those of the first embodiment. That is, it is possible to quickly determine whether or not a current collapse occurs in the field effect transistor.

  Note that the second on-resistance used for calculating the on-resistance ratio is not the second on-resistance, but the field-effect transistor 101 after switching between the on-state and the off-state a plurality of times (for example, 100 times). The on-resistance of may be sufficient. That is, the semiconductor inspection apparatus 100B may perform the processes of steps S130 and S140 after repeatedly performing the processes of steps S110 and S120 twice or more.

(Fourth embodiment)
Below, the 4th Embodiment of this invention is described, referring drawings.

  FIG. 4A is a diagram showing a configuration of a semiconductor inspection apparatus 100C according to the fourth embodiment of the present invention.

  As shown in FIG. 4A, the semiconductor inspection apparatus 100C includes a first gate drive circuit 115, a second gate drive circuit 116, a drive circuit 103, a measurement unit 120, and a determination unit 130.

  The field effect transistor 114 is a transistor to be inspected. The field effect transistor 114 is not included in the semiconductor inspection apparatus 100C. The field effect transistor 114 is a dual gate type field effect transistor. The conductivity type of the field effect transistor 114 may be either N-type or P-type.

  The field effect transistor 114 is a high electron mobility transistor (HEMT). Note that the field effect transistor 114 is not limited to the HEMT, and may be a field effect transistor having another structure.

  The field effect transistor 114 includes a first gate G11, a second gate G12, a first ohmic electrode OM1, and a second ohmic electrode OM2. The first ohmic electrode OM1 functions as a source. The second ohmic electrode OM2 functions as a drain.

  However, the field effect transistor 114 can be energized from either the first ohmic electrode OM1 or the second ohmic electrode OM2. Therefore, each of the first ohmic electrode OM1 and the second ohmic electrode OM2 has a function of both a drain and a source.

  Hereinafter, the first gate G11, the second gate G12, the first ohmic electrode OM1, and the second ohmic electrode OM2 are also referred to as a first gate, a second gate, a first ohmic electrode, and a second ohmic electrode, respectively.

  Each of the first gate drive circuit 115 and the second gate drive circuit 116 is constituted by, for example, a pulse generator or a function generator. Each of the first gate driving circuit 115 and the second gate driving circuit 116 supplies a pulse voltage.

  A first gate drive circuit 115 is connected to the first gate G11 of the field effect transistor 114. A second gate drive circuit 116 is connected to the second gate G12 of the field effect transistor 114. The second gate driving circuit 116 is connected to the second ohmic electrode OM2.

  A drive circuit 103 is connected to the second ohmic electrode OM2.

  Since the configuration of drive circuit 103 is the same as the configuration of drive circuit 103 described with reference to FIG. 1A, detailed description will not be repeated. A brief description is given below.

  The low voltage power supply 104 supplies a voltage for calculating (measuring) the on-resistance of the field effect transistor 114. The low load resistor 105 is a resistor for limiting the amount of current between the second ohmic electrode OM2 and the first ohmic electrode OM1. The power supply protection diode 107 is a diode for protecting the low voltage power supply 104.

  The high voltage power supply 108 applies a high voltage between the second ohmic electrode OM2 and the first ohmic electrode OM1 of the field effect transistor 114. The voltage level supplied by the high voltage power supply 108 is higher than the voltage level supplied by the low voltage power supply 104.

  Hereinafter, the voltage supplied from the low voltage power source 104 via the low load resistor 105 and the power source protection diode 107 is also referred to as a first voltage. In the following, the voltage that the high voltage power supply 108 supplies via the high load resistor 106 is also referred to as a second voltage. The second voltage is higher than the first voltage. That is, the second voltage is greater than the first voltage.

  The high load resistor 106 is a resistor for limiting the amount of drain current directed to the field effect transistor 114.

  Drive circuit 103 further includes a current probe 109 and a switch 110. The drive circuit 103 performs on / off control of the switch 110. When the switch 110 is turned on, one end of the high load resistor 106 and the second ohmic electrode OM2 of the field effect transistor 114 are electrically connected. When the switch 110 is turned off, one end of the high load resistor 106 and the second ohmic electrode OM2 of the field effect transistor 114 are electrically disconnected.

  The measurement unit 120 has a function of measuring a current using the current probe 109 and a function of measuring a voltage between the second ohmic electrode OM2 and the first ohmic electrode OM1 of the field effect transistor 114, as in the first embodiment. And have. Note that, for simplification of the drawing, connection lines are not shown, but the measurement unit 120 is connected to the current probe 109, the second ohmic electrode OM2, and the first ohmic electrode OM1.

  As in the first embodiment, the determination unit 130 determines whether or not a current collapse has occurred.

  FIG. 4B is a timing chart showing an inspection method of the field effect transistor 114 according to the fourth embodiment of the present invention. In FIG. 4B, Vg2s2 is a voltage between the second gate G12 and the second ohmic electrode OM2 in the field effect transistor 114. Vg1s1 is a voltage between the first gate G11 and the first ohmic electrode OM1 in the field effect transistor 114.

  Vd is a voltage at the second ohmic electrode OM2. Is2s1 is a current flowing between the second ohmic electrode OM2 and the first ohmic electrode OM1 in the field effect transistor 114. Vs2s1 is a voltage between the second ohmic electrode OM2 and the first ohmic electrode OM1 in the field effect transistor 114.

  Hereinafter, the on-resistance measured in the period T1C is also referred to as a first on-resistance. Hereinafter, the on-resistance measured in the period T3C is also referred to as a second on-resistance.

  Next, a process for inspecting the field effect transistor 114 will be described.

  As shown in FIG. 4B, in the period T1C, the voltage supplied by the low voltage power supply 104 is supplied to the second ohmic electrode OM2 via the low load resistor 105 and the power supply protection diode 107.

  Each of the first gate driving circuit 115 and the second gate driving circuit 116 supplies a pulse voltage for turning on the field effect transistor 114 at the same time. Hereinafter, a pulse voltage for turning on the field effect transistor 114 is also referred to as an on-pulse voltage.

  Specifically, the first gate drive circuit 115 supplies an on-pulse voltage to the first gate G11 of the field effect transistor 114. The second gate drive circuit 116 supplies an on-pulse voltage to the second gate G12 of the field effect transistor 114. Accordingly, the field-effect transistor 114 is turned on in the period T1C.

  A voltage (first voltage) supplied from the low voltage power supply 104 via the low load resistor 105 and the power supply protection diode 107 is applied to the second ohmic electrode OM2 of the field effect transistor 114 in the on state. That is, the semiconductor inspection apparatus 100C applies a voltage (first voltage) to the second ohmic electrode OM2 using the low voltage power supply 104. That is, in the field effect transistor 114, a voltage is applied between the second ohmic electrode and the first ohmic electrode. That is, the semiconductor inspection apparatus 100C calculates (measures) the on-resistance of the field-effect transistor 114 after simultaneously applying a pulse voltage to the first gate G11 and the second gate G12 to turn on the field-effect transistor 114 ( S110).

  Calculation (measurement) of the on-resistance in the period T1C is performed as follows. For example, the measurement unit 120 measures the voltage Vs2s1 and the current Is2s1 between the second ohmic electrode and the first ohmic electrode when 30 μs has elapsed since the field-effect transistor 114 is turned on. The current Is2s1 is measured using the current probe 109, for example. Then, the measurement unit 120 calculates (measures) the on-resistance from the measured Vs2s1 and Is2s1 using the on-resistance = Vs2s1 / Is2s1 (S110).

  Next, in the period T2C, each of the first gate driving circuit 115 and the second gate driving circuit 116 stops supplying the pulse voltage at the same time. As a result, the field effect transistor 114 is turned off. Then, the drive circuit 103 turns on the switch 110. As a result, the voltage (second voltage) supplied from the high voltage power supply 108 via the high load resistor 106 is applied to the second ohmic electrode OM2 of the field effect transistor 114. That is, the semiconductor inspection apparatus 100C applies a high voltage between the second ohmic electrode and the first ohmic electrode of the field effect transistor 114 in the off state using the high voltage power supply 108 (S120).

  Next, in the period T3C, each of the first gate driving circuit 115 and the second gate driving circuit 116 starts supplying the on-pulse voltage at the same time. Specifically, the first gate drive circuit 115 supplies an on-pulse voltage to the first gate G11 of the field effect transistor 114. The second gate drive circuit 116 supplies an on-pulse voltage to the second gate G12 of the field effect transistor 114.

  Accordingly, the field-effect transistor 114 is turned on in the period T3C. A voltage supplied from the high voltage power supply 108 via the high load resistor 106 is applied to the second ohmic electrode OM2 of the field effect transistor 114 in the on state. That is, the semiconductor inspection apparatus 100C calculates (measures) the on-resistance of the field effect transistor 114 using the high voltage power supply 108 (S130).

  Calculation (measurement) of the on-resistance in the period T3C is performed similarly to the calculation of the on-resistance in the period T1C. That is, the measurement unit 120 measures the voltage Vs2s1 and the current Is2s1 between the second ohmic electrode and the first ohmic electrode when, for example, 30 μs elapses after the field effect transistor 114 is turned on. Then, the measurement unit 120 calculates (measures) the on-resistance from the measured Vs2s1 and Is2s1.

  And the measurement part 120 calculates the on-resistance ratio of a field effect transistor similarly to 1st Embodiment (S140). The on-resistance ratio is calculated by the second on-resistance / first on-resistance.

  When the on-resistance ratio is greater than 1, the determination unit 130 determines that a current collapse has occurred. In addition, the determination unit 130 may determine that a current collapse has occurred when the second on-resistance is larger than the first on-resistance.

  However, in the determination of the on-resistance ratio, for example, when the on-resistance ratio of the transistor to be inspected is less than 1.2, it is assumed that the transistor is an acceptable non-defective product. In this case, all transistors to be inspected with an on-resistance ratio of 1.2 or less are determined to be non-defective products even if current collapse occurs.

  By performing the processing described above, the present embodiment can provide the same effects as those of the first embodiment. That is, it is possible to quickly determine whether or not a current collapse occurs in the field effect transistor.

  Note that the driving timing of the first gate and the second gate is not necessarily the same timing. Note that the second on-resistance used for calculating the on-resistance ratio is not the second on-resistance, but the field-effect transistor 114 after the switching between the on-state and the off-state is performed a plurality of times (for example, 100 times). The on-resistance of may be sufficient. That is, the semiconductor inspection apparatus 100C may perform the processes in steps S130 and S140 after repeatedly performing the processes in steps S110 and S120 twice or more.

(Fifth embodiment)
Below, the 5th Embodiment of this invention is described, referring drawings.

  FIG. 5A is a diagram showing a configuration of a semiconductor inspection apparatus 100D according to the fifth embodiment of the present invention.

  As shown in FIG. 5A, the semiconductor inspection apparatus 100D is different from the semiconductor inspection apparatus 100C in FIG. 4A in that a driving circuit 103A in FIG. Since the other configuration of semiconductor inspection apparatus 100D is the same as that of semiconductor inspection apparatus 100C, detailed description will not be repeated.

  Since drive circuit 103A is similar to drive circuit 103A in FIG. 2A, detailed description will not be repeated. The load resistor 112 is a resistor for limiting the amount of current between the second ohmic electrode and the first ohmic electrode. Vg2s2, Vg1s1, Vd, Is2s1, and Vs2s1 are the same as those described with reference to FIG. 4B.

  FIG. 5B is a timing chart showing an inspection method of the field effect transistor 114 according to the fifth embodiment of the present invention.

  As shown in FIG. 5B, in the period T1D, as in the period T1C in FIG. 4B, the first gate drive circuit 115 supplies the on-pulse voltage to the first gate G11 of the field effect transistor 114. The second gate drive circuit 116 supplies an on-pulse voltage to the second gate G12 of the field effect transistor 114. Accordingly, the field-effect transistor 114 is turned on in the period T1D.

  A voltage supplied from the power supply 111 via the load resistor 112 is applied to the second ohmic electrode OM2 of the field effect transistor 114 in the on state. That is, the semiconductor inspection apparatus 100D applies a voltage between the second ohmic electrode and the first ohmic electrode using the power source 111. That is, the semiconductor inspection apparatus 100D calculates (measures) the on-resistance of the field-effect transistor 114 after simultaneously applying the on-pulse voltage to the first gate G11 and the second gate G12 to turn on the field-effect transistor 114 ( S110).

  Since the calculation (measurement) of the on-resistance during the period T1D is the same as the method for calculating the on-resistance during the period T1C described in the fourth embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T1D is also referred to as a first on-resistance.

  Next, in the period T2D, each of the first gate driving circuit 115 and the second gate driving circuit 116 stops supplying the on-pulse voltage at the same time. As a result, the field effect transistor 114 is turned off. A voltage supplied from the power supply 111 via the load resistor 112 is applied to the second ohmic electrode OM2 of the field effect transistor 114 in the off state. That is, the semiconductor inspection apparatus 100D applies a high voltage between the second ohmic electrode and the first ohmic electrode of the field effect transistor 114 using the power source 111 (S120).

  Next, in the period T3D, each of the first gate driving circuit 115 and the second gate driving circuit 116 starts supplying the on-pulse voltage at the same time. Specifically, the first gate drive circuit 115 supplies an on-pulse voltage to the first gate G11 of the field effect transistor 114. The second gate drive circuit 116 supplies an on-pulse voltage to the second gate G12 of the field effect transistor 114.

  Accordingly, the field-effect transistor 114 is turned on in the period T3D. A voltage supplied from the power supply 111 via the load resistor 112 is applied to the second ohmic electrode OM2 of the field effect transistor 114 in the on state. That is, the semiconductor inspection apparatus 100D calculates (measures) the on-resistance of the field effect transistor 114 using the power supply 111 (S130).

  Since the calculation (measurement) of the on-resistance in the period T3D is the same as the method for calculating the on-resistance in the period T3C described in the fourth embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T3C is also referred to as a second on-resistance.

  Then, the measurement unit 120 of the semiconductor inspection apparatus 100D calculates the on-resistance ratio of the field effect transistor 114 as in the fourth embodiment (S140).

  And the determination part 130 determines whether the current collapse has arisen similarly to 4th Embodiment.

  By performing the processing described above, the present embodiment can provide the same effects as those of the first embodiment. That is, it is possible to quickly determine whether or not a current collapse occurs in the field effect transistor.

  Note that the driving timing of the first gate and the second gate is not necessarily the same timing. Note that the second on-resistance used for calculating the on-resistance ratio is not the second on-resistance, but the field-effect transistor 114 after the switching between the on-state and the off-state is performed a plurality of times (for example, 100 times). The on-resistance of may be sufficient. That is, the semiconductor inspection apparatus 100D may perform the processes in steps S130 and S140 after repeatedly performing the processes in steps S110 and S120 twice or more.

(Sixth embodiment)
Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

  FIG. 6A is a diagram showing a configuration of a semiconductor inspection apparatus 100E according to the sixth embodiment of the present invention.

  As shown in FIG. 6A, the semiconductor inspection apparatus 100E is different from the semiconductor inspection apparatus 100C of FIG. 4A in that a drive circuit 103B is provided instead of the drive circuit 103. Since the other configuration of semiconductor inspection apparatus 100E is the same as that of semiconductor inspection apparatus 100C, detailed description will not be repeated.

  A drive circuit 103B is connected to the second ohmic electrode OM2. Since drive circuit 103B is similar to drive circuit 103B in FIG. 3A, detailed description will not be repeated. The low load resistor 105 and the high load resistor 106 are resistors for limiting the amount of current between the second ohmic electrode and the first ohmic electrode. Vg2s2, Vg1s1, Vd, Is2s1, and Vs2s1 are the same as those described with reference to FIG. 4B.

  FIG. 6B is a timing chart showing an inspection method for the field effect transistor 114 according to the sixth embodiment of the present invention.

  As shown in FIG. 6B, in the period T1E, as in the period T1C in FIG. 4B, the first gate drive circuit 115 supplies the on-pulse voltage to the first gate G11 of the field effect transistor 114. The second gate drive circuit 116 supplies an on-pulse voltage to the second gate G12 of the field effect transistor 114. Accordingly, in the period T1E, the field-effect transistor 114 is turned on.

  In the period T1E, the drive circuit 103B controls the switch 113 so that the low load resistor 105 and the power source 111 are electrically connected. As a result, the voltage supplied from the power supply 111 is applied to the second ohmic electrode OM2 of the field-effect transistor 114 in the on state via the low load resistor 105.

  That is, in the period T1E, the semiconductor inspection apparatus 100E calculates the on-resistance of the field-effect transistor 114 after turning on the field-effect transistor 114 and applying a voltage to the second ohmic electrode OM2 of the field-effect transistor 114 ( Measurement) (S110).

  Since the calculation (measurement) of the on-resistance during the period T1E is the same as the method for calculating the on-resistance during the period T1C described in the fourth embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T1E is also referred to as a first on-resistance.

  Next, in the period T2E, each of the first gate driving circuit 115 and the second gate driving circuit 116 stops supplying the on-pulse voltage at the same time. As a result, the field effect transistor 114 is turned off. In the period T2E, the drive circuit 103B controls the switch 113 so that the high load resistor 106 and the power source 111 are electrically connected. As a result, the voltage supplied from the power supply 111 is applied to the second ohmic electrode OM2 of the field effect transistor 114 via the high load resistor 106. That is, the semiconductor inspection apparatus 100E applies a high voltage between the second ohmic electrode and the first ohmic electrode of the field effect transistor 114 using the power supply 111 (S120).

  Next, in the period T3E, as in the period T3C in FIG. 4B, each of the first gate driving circuit 115 and the second gate driving circuit 116 starts supplying the on-pulse voltage at the same time. Accordingly, the field-effect transistor 114 is turned on in the period T3C. A voltage supplied from the power supply 111 via the high load resistor 106 is applied to the second ohmic electrode OM2 of the field effect transistor 114 in the on state. That is, the semiconductor inspection apparatus 100D calculates (measures) the on-resistance of the field effect transistor 114 using the power supply 111 (S130).

  Since the calculation (measurement) of the on-resistance in the period T3E is the same as the method for calculating the on-resistance in the period T3C described in the fourth embodiment, detailed description will not be repeated. Hereinafter, the on-resistance calculated (measured) in the period T3E is also referred to as a second on-resistance.

  Then, the measurement unit 120 of the semiconductor inspection apparatus 100E calculates the on-resistance ratio of the field effect transistor 114 as in the fourth embodiment (S140).

  And the determination part 130 determines whether the current collapse has arisen similarly to 4th Embodiment.

  By performing the processing described above, the present embodiment can provide the same effects as those of the first embodiment. That is, it is possible to quickly determine whether or not a current collapse occurs in the field effect transistor.

  Note that the drive timing of the first gate and the second gate is not necessarily the same timing. Note that the second on-resistance used for calculating the on-resistance ratio is not the second on-resistance, but the field-effect transistor 114 after the switching between the on-state and the off-state is performed a plurality of times (for example, 100 times). The on-resistance of may be sufficient. That is, the semiconductor inspection apparatus 100E may perform the processes of steps S130 and S140 after repeatedly performing the processes of steps S110 and S120 twice or more.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The inspection method and semiconductor inspection apparatus for a field effect transistor as a semiconductor element described in the present invention provide a method for efficiently sorting defective products, and are industrially useful.

100, 100A, 100B, 100C, 100D, 100E Semiconductor inspection apparatus 101, 114 Field effect transistor 102 Gate drive circuit 103, 103A, 103B Drive circuit 104 Low voltage power supply 105 Low load resistance 106 High load resistance 107 Power supply protection diode 108 High Voltage power source 109 Current probe 110, 113 Switch 111 Power source 112 Load resistance 115 First gate drive circuit 116 Second gate drive circuit 120 Measuring unit 130 Determination unit

Claims (7)

An inspection method for inspecting a field effect transistor as a semiconductor element,
The field effect transistor is turned on by applying a voltage to the gate of the field effect transistor, and the on-resistance of the field effect transistor in a state where the first voltage is applied to the drain of the field effect transistor. A first step of calculating a 1-on resistance;
After the first step, the application of the voltage to the gate of the field effect transistor is stopped to turn off the field effect transistor, and a second voltage higher than the first voltage is applied to the drain of the field effect transistor. A second step of applying to
After the second step, the field effect transistor is turned on by applying a voltage to the gate of the field effect transistor, and the electric field is applied in a state where the second voltage is applied to the drain of the field effect transistor. And a third step of calculating a second on-resistance which is an on-resistance of the effect transistor. In the first step, using a current flowing between the drain and the source in the field effect transistor in the on state and a voltage applied between the drain and the source in the field effect transistor in the on state, Calculating the first on-resistance;
In the third step, using a current flowing between the drain and source in the field effect transistor in the on state and a voltage applied between the drain and source in the field effect transistor in the on state, The semiconductor element inspection method according to claim 1, wherein the second on-resistance is calculated. The semiconductor device inspection method according to claim 1, wherein the inspection method further includes a step of calculating a ratio of the second on-resistance to the first on-resistance as an on-resistance ratio of the field effect transistor. The inspection method is:
The first step and the second step are repeated twice or more,
The method for inspecting a semiconductor element according to claim 1, wherein the third step is performed after the first step and the second step are repeatedly performed twice or more. A semiconductor inspection apparatus for performing the inspection method according to claim 1,
The semiconductor inspection apparatus includes:
A first drive circuit for controlling the supply of voltage to the gate of the field effect transistor;
A semiconductor inspection apparatus comprising: a second drive circuit for applying the first voltage or the second voltage to a drain of the field effect transistor. The semiconductor inspection apparatus according to claim 5, wherein the first drive circuit supplies a pulse voltage to a gate of the field effect transistor. The semiconductor inspection apparatus according to claim 5, wherein the second drive circuit has a configuration capable of controlling an amount of drain current in the field effect transistor.

Images