JP2013012985A - Power amplifier circuit and circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power amplifier circuit that keeps the phase of an output signal intact even when a supply voltage drops.SOLUTION: The power amplifier circuit comprises: a power supply VDD; MOS transistors Tr, Trx connected to the power supply; and compensation capacitances Cxgd, Cxgdx connected between gates and drains of the MOS transistors. The compensation capacitances have a characteristic of capacitance value depending on a voltage change in the power supply so as to cancel changes in gate-drain capacitances Cgd, Cgdx of the MOS transistors depending on a voltage change in the power supply.

Description

  The present invention relates to a power amplifier circuit having a MOS transistor and a circuit device having a power amplifier circuit.

  A compound semiconductor transistor such as GaAs has been used for many years for a power amplifier (PA), which is a high-frequency amplifier at the last stage of a transmission circuit of a portable terminal. However, in recent years, the high frequency characteristics of MOS transistors have improved, and power amplifiers have been designed even for MOS transistors.

  In a transmission circuit of a portable terminal or the like, a power amplifier (PA) is a high-frequency amplifier (amplifier) that sends a signal to a base station that is distant through an antenna. In some cases, most of the power consumption of the mobile terminal is occupied by the power consumption of the power amplifier, and various attempts have been made to reduce the power consumption of the power amplifier.

  For example, when the base station is at a long distance from the mobile terminal, so that the power amplifier outputs a signal at a large output, and when the base station is at a short / medium distance from the mobile terminal, the power amplifier is a signal at a small / medium output. May be output, and in the actual operation, the latter frequency is high. Focusing on this, attempts have been made to reduce the power consumption by reducing the bias of the power amplifier in the case of small and medium outputs. However, in this method, since the power supply voltage is always high, the power consumption cannot be reduced much. Therefore, attempts have been made to lower the power consumption by lowering the power supply voltage of the power amplifier during small and medium outputs.

  However, when the power supply voltage is lowered by the power amplifier circuit, the gain and phase of the output signal change greatly. Since the transmission signal is an amplitude-phase modulation signal, if the gain and phase change, a failure occurs in signal reception at the base station. Therefore, there is a need for a measure that does not change the gain and phase even when the power supply voltage is changed. Actually, the change in gain is not a problem, and the phase delay itself is not a problem, but the problem is that the amount of phase delay changes.

Therefore, there has been a demand for a power amplifier circuit in which the phase of the output signal does not change even when the power supply voltage decreases.
Further, when a power amplifier element is actually manufactured, there is a problem that the element characteristics are different due to the manufacturing variation of the element and the secular change, and the phase of the output signal in the power amplifier circuit varies.
Therefore, there has been a demand for a power amplifier circuit in which the phase of the output signal is constant even when the element characteristics are not constant due to variations in element manufacturing and aging.

JP-A-6-252797 JP 2009-232445 A JP 2002-344304 A

According to the embodiment, a power amplifier circuit is realized in which the phase of the output signal does not change even when the power supply voltage decreases.
According to the embodiment, a power amplifier circuit in which the phase of the output signal is constant is realized even when the element characteristics are not constant due to manufacturing variations of the elements and aging.

  According to a first aspect of the present invention, a power source, a MOS transistor connected to the power source, and a compensation capacitor connected between the gate and drain of the MOS transistor, the compensation capacitor is a voltage change of the power source. There is provided a power amplifier circuit having a characteristic in which a capacitance value changes in accordance with a voltage change of a power supply so as to cancel a change in gate-drain capacitance of a MOS transistor that changes in accordance with the voltage.

  According to the second aspect of the present invention, the power supply, the MOS transistor connected to the power supply, and the variable capacitor connected between the gate and drain of the MOS transistor are provided, and the power supply responds to a voltage change of the power supply. Thus, a power amplifier circuit is provided in which the capacitance value of the variable capacitor is changed so as to cancel the change in the capacitance between the gate and drain of the changing MOS transistor.

According to the embodiment, a power amplifier circuit in which the phase of the output signal does not change regardless of the change of the power supply voltage is realized.
In addition, according to the embodiment, a power amplifier circuit in which the phase of the output signal is constant for a long time regardless of the element to be used is realized.

FIG. 1 is a diagram showing a schematic configuration of a transmission circuit using a power amplifier circuit. FIG. 2 is a diagram showing a change example of the gain and phase of the output signal when the power supply voltage VDD is changed in a power amplifier circuit using MOS transistors. FIG. 3 is a diagram illustrating a configuration of the power amplifier circuit. FIG. 4 is a diagram illustrating a configuration example and a characteristic example of an RLC resonant load power amplifier circuit forming a differential pair. FIG. 5 is a diagram showing changes in the parasitic capacitance and characteristics of the transistor when the voltage of the power supply VDD is changed. FIG. 6 is a diagram illustrating a configuration of the differential power amplifier circuit according to the first embodiment. FIG. 7 is a diagram showing the element structure of the varactor and the capacitance change characteristic with respect to the applied voltage. FIG. 8 is a diagram showing a specific circuit configuration in which a varactor is connected as a compensation capacitor. FIG. 9 is a diagram illustrating changes in capacitance values of parasitic capacitance, compensation capacitance (varactor), and cross coupling capacitance with respect to changes in VDD. FIG. 10 is a Bode diagram of gain and phase with respect to frequency when VDD is changed in the differential power amplifier circuit of the first embodiment. FIG. 11 is a diagram illustrating a configuration of the differential power amplifier circuit according to the second embodiment. FIG. 12 is a diagram illustrating an example in which the switch of the differential power amplifier circuit according to the second embodiment is realized by a combination of a MOS transistor and a feeding resistor. FIG. 13 is a diagram illustrating the configuration of the differential power amplifier circuit according to the third embodiment. FIG. 14 is a diagram illustrating a circuit example in which the feedback unit is formed by a flash AD converter and a thermometer code / capacitance code conversion circuit in the differential power amplifier circuit of the third embodiment. FIG. 15 is a diagram illustrating a configuration of a circuit device according to the fourth embodiment. FIG. 16 is a diagram illustrating a circuit configuration of the phase difference / digital conversion circuit. FIG. 17 is a diagram showing a circuit diagram of the complementary circuit (AUX). FIG. 18 is a diagram illustrating a circuit configuration of the control unit. FIG. 19 is a flowchart showing the operation of the control unit. FIG. 20 is a diagram showing a configuration of a modification of the circuit device using the analog control type DC / DC converter instead of the digital control type DC / DC converter in the circuit device of the fourth embodiment. FIG. 21 is a Bode diagram of gain and phase with respect to frequency when VDD is changed in the differential power amplifier circuits and circuit devices of the second to fourth embodiments. FIG. 22 is a diagram illustrating a configuration of a transmission / reception circuit of a general mobile terminal.

  FIG. 1 is a diagram showing a schematic configuration of a transmission circuit using a power amplifier circuit. Before describing the embodiment, a power amplifier circuit will be described.

  The transmission circuit 10 illustrated in FIG. 1 includes a variable attenuation circuit 10, a power amplifier circuit 12, an attenuation amount control circuit 13, and a bias control circuit 14. The variable attenuation circuit 10 attenuates the transmission signal and outputs it to the power amplifier circuit 12. The variable attenuation circuit 10 has a variable amount of attenuation according to a control signal from the attenuation amount control circuit 13. The power amplifier circuit 12 amplifies and outputs the transmission signal output from the variable attenuation circuit 10. The bias of the power amplifier circuit 12 is controlled by a bias control signal from the bias control circuit 14, thereby changing the amplification factor. The attenuation amount control circuit 13 generates and outputs a control signal for controlling the output level of the transmission signal based on the reception level of the reception signal from the transmission destination (base station) and the transmission power control information. The bias control circuit 14 generates a bias control signal according to the control signal from the attenuation control circuit 13 and outputs the bias control signal to the power amplifier circuit 12. By using a transmission circuit as shown in FIG. 1, for example, the power of the output signal can be adjusted according to the distance between the mobile terminal provided with the transmission circuit and the base station.

  On the other hand, power amplifier circuits using MOS transistors are being put into practical use. In a power amplifier circuit using MOS transistors, the power supply voltage of the power amplifier circuit 12 is always high simply by adjusting the bias as shown in FIG.

  Thus, attempts have been made to lower the power consumption by lowering the power supply voltage of the power amplifier circuit 12. For example, in a power amplifier circuit using a MOS transistor, the power supply voltage VDD is reduced to 3.3V at the time of large output, and the power supply voltage VDD is gradually reduced to 0.4V according to the output power at the time of small / medium output. Reduce power. However, when the power supply voltage VDD is lowered from 3.3V to 0.4V, the gain and phase of the output signal change greatly.

  FIG. 2 is a diagram showing a change example of the gain and phase of the output signal when the power supply voltage VDD is changed in a power amplifier circuit using MOS transistors. 2A shows the relationship between the frequency and gain when VDD = 3.3V, and FIG. 2B shows the relationship between the frequency and gain when VDD is changed stepwise from 3.3V to 0.4V. Indicates a change in relationship. Furthermore, in FIG. 2, (C) shows the relationship between the frequency and phase when VDD = 3.3V, and (D) shows the frequency when VDD is changed stepwise from 3.3V to 0.4V. Changes in the phase relationship are shown.

  Since the transmission signal is an amplitude phase modulation signal, if the gain and phase of the transmission signal change, a failure occurs in reception on the reception side (base station). Therefore, in the transmission circuit, a measure is required so that the gain and phase do not change in the transmission signal even if the power supply voltage VDD of the power amplifier circuit is changed. Actually, since the reception signal is amplified on the reception side, a change in gain is not a problem. Also, if the phase delay is constant, there is no problem, but if the phase changes, a problem occurs.

FIG. 3 is a diagram illustrating a configuration of the power amplifier circuit.
As shown in FIG. 3, the power amplifier circuit includes RLC resonant load amplifiers A1 and A2, and input / output matching circuits M1 and M2. Usually, the RLC resonant load amplifiers A1 and A2 are of a differential type and have two MOS transistors having the same characteristics forming a differential pair, and are identical between the drains of the two MOS transistors and the power supply terminal. And connect the source to ground potential. Thereby, a differential pair having symmetry is formed. A differential signal is applied to the gates of the two MOS transistors, and a differential output is obtained from the drains of the two MOS transistors.

  FIG. 4 is a diagram showing a configuration example and a characteristic example of an RLC resonant load power amplifier circuit forming a differential pair. FIG. 4A is a circuit configuration diagram, and FIG. 4B is a Bode line of gain with respect to frequency. (C) is a Bode diagram of phase with respect to frequency. FIG. 4 shows a single-phase RLC resonant load power amplifier circuit for simplicity of illustration.

  As shown in FIG. 4A, the RLC resonant load power amplifier circuit includes a MOS transistor Tr, the source of the MOS transistor Tr is grounded, and the drain of the MOS transistor Tr is connected to the power supply VDD via the RLC resonant load. Connected. An input signal in is input to the gate of the MOS transistor Tr, and an output out is output from the drain. The RLC resonant load includes a resistance load Rd, an inductance load Ld, a capacitive load Cd, and a gate-drain parasitic capacitance Cgd of the MOS transistor Tr.

As shown in FIGS. 4B and 4C, the RLC resonant load power amplifier circuit has a gain peak and a phase delay inflection point at the resonance frequency f0 = 1 / (2π (LdCd) ^1/2 ). The circuit normally operates at or near the resonant frequency f0. Here, the operating frequency is 1.8 GHz.

  FIG. 5 is a diagram showing changes in Cgd and characteristics when the voltage of the power supply VDD is changed. FIG. 5A shows a change in Cgd when the voltage of VDD is changed. (B) and (C) of FIG. 5 are Bode diagrams of gain and phase with respect to frequency when the voltage of VDD is changed. In the following description, the voltage of the power supply VDD may be represented by VDD.

  As shown in FIG. 5A, when the power supply voltage VDD decreases, Cgd increases greatly, and the capacitance C of the RLC resonant load amplifier increases. Therefore, as shown in FIG. 5B, the gain peak is also shifted to the low frequency side, and as shown in FIG. 5C, the inflection point at which the phase delay is greatly changed is also shifted to the low frequency side. . For this reason, the phase delay amount at the circuit operating frequency (1.8 GHz) greatly changes. Generally, on the receiving side, the phase delay itself is not a problem, but the problem is that the amount of phase delay changes.

  In general, the side using the power amplifier circuit requests the power amplifier circuit so that the phase falls within a certain range even when the output power changes. Therefore, a change in gain when VDD changes is not particularly taken into consideration, and the change in phase needs to be suppressed within a predetermined range. Therefore, the embodiment provides a power amplifier circuit with a small phase change even when the power supply voltage VDD changes.

  Further, when a power amplifier element is actually manufactured, the element characteristics are different due to the manufacturing variation of the element and the secular change, and the variation of the phase of the output signal in the power amplifier circuit is inevitable. The embodiment provides a power amplifier circuit whose phase change is within a predetermined range even in such a case.

FIG. 6 is a diagram illustrating a configuration of the differential power amplifier circuit according to the first embodiment.
The differential power amplifier circuit according to the first embodiment includes a first system that amplifies the normal phase input signal in and a second system that amplifies the negative phase input signal inx. This system has a configuration similar to that in FIG. The first system includes a MOS transistor Tr, the source of the MOS transistor Tr is grounded, and the drain of the MOS transistor Tr is connected to the power supply VDD via the inductance Ld. As described with reference to FIG. 4, the resistor Rd and the capacitor Cd that form the RLC resonant load exist, but since they are not directly related to the invention, the illustration is omitted hereinafter. A positive phase input signal in is input to the gate of the MOS transistor Tr, and a positive phase output out is output from the drain. Similarly, the second system includes a MOS transistor Trx, the source of the MOS transistor Trx is grounded, and the drain of the MOS transistor Trx is connected to the power supply VDD via the inductance Ldx. A negative phase input signal inx is input to the gate of the MOS transistor Trx, and a negative phase output outx is output from the drain. Further, a cross-coupled capacitor Cxc is provided between the drain of the first system MOS transistor Tr and the gate of the second system MOS transistor Trx. Further, a cross-coupled capacitor Cxcx is provided between the gate of the first system MOS transistor Tr and the gate of the second system MOS transistor Trx.

  As described above, the parasitic capacitance Cgd exists between the gate and drain of the MOS transistor Tr (that is, the input signal terminal and the output signal terminal), and the parasitic capacitance Cgdx exists between the gate and drain of the MOS transistor Trx. To do.

  In the differential power amplifier circuit of the first embodiment, a compensation capacitor Cxgd is provided between the gate and drain of the MOS transistor Tr, and a compensation capacitor Cxgdx is provided between the gate and drain of the MOS transistor Trx. The compensation capacitor Cxgd has a characteristic that changes so as to cancel the change in the parasitic capacitance Cgd when the power supply voltage VDD changes. Similarly, the compensation capacitor Cxgdx has a characteristic that changes so as to cancel the change in the parasitic capacitance Cgdx when the power supply voltage VDD changes.

  The compensation capacitors Cxgd and Cxgdx may be any ones as long as they have the above-described characteristics. For example, the compensation capacitors Cxgd and Cxgdx are realized by a widely known varactor (variable capacitor diode).

FIG. 7 is a diagram showing the element structure of the varactor and the capacitance change characteristic with respect to the applied voltage.
As shown in FIG. 7A, the varactor applies the same voltage V _{S / D} to the source / drain (S / D) of the MOS transistor, and applies the voltage V _G to the gate (G). As a result, the voltage V = V _G −V _{S / D} is applied between the gate (G) and the source / drain (S / D).

  As shown in FIG. 7B, the capacitance value C of the varactor changes according to the voltage V. As shown in FIG. 6, the gates (G) of the varactors Cxgd and Cxgdx are connected to the power supply VDD via Ld and Ldx. When the bias voltage Vbias is applied to the source / drain (S / D) of the varactor, the voltage VDD-Vbias is applied. When Vbias is set so that VDD−Vbias falls within the range shown in FIG. 7B when the power supply voltage VDD changes between the maximum value and the minimum value, the capacitance value C of the varactor is equal to VDD. When it is high, the capacitance value C is large, and when VDD is low, the capacitance value C is small. In other words, the capacitance value C of the varactor changes in reverse to the changes in the parasitic capacitance Cgd and the parasitic capacitance Cgdx with respect to the change in VDD.

  As shown in FIG. 6, the parasitic capacitance Cgd and the compensation capacitance (varactor) Cxgd are connected between the gate and drain of the MOS transistor Tr. Therefore, the gate-drain capacitance of the MOS transistor Tr is the sum of Cgd and Cxgd. Similarly, the capacitance between the gate and drain of the MOS transistor Trx is the sum of Cgdx and Cxgdx.

  In the circuit configuration of FIG. 6, the source / drain (S / D) of the varactor is connected to the input signal terminal, and the bias level of the input signal is input as Vbias of the varactor. It is possible to connect the varactor directly to the input signal terminal by appropriately selecting the characteristics of the varactor. However, in order to set and connect the bias voltage, the varactor is connected to the input signal terminal via a blocking capacitor.

FIG. 8 is a diagram showing a specific circuit configuration in which a varactor is connected as a compensation capacitor.
In the first system, a blocking capacitor Ccut and a compensation capacitor Cxgd are connected in series between the gate and drain of the MOS transistor Tr, and a bias voltage Vbias is applied to a connection node between Ccut and Cxgd via a power supply resistor Rbias. Similarly, in the second system, a blocking capacitor Ccutx and a compensation capacitor Cxgdx are connected in series between the gate and drain of the MOS transistor Trx, and a bias voltage Vbias is applied to a connection node between Ccutx and Cxgdx via a feeding resistor Rbiasx. Apply. The capacitance values of Ccut and Ccutx are sufficiently larger than the capacitance value of the varactor, for example, 20 pF. The resistance value of Rbias and Rbiasx is, for example, 10 kΩ. The bias voltage Vbias is set so that the voltage dependency of the varactor is opposite to the voltage dependency of the parasitic capacitance. Since Ccut and Ccutx connected in series are connected in parallel with the parasitic capacitance Cgd, it is desirable that the characteristics of Ccut and Ccutx connected in series with respect to the change in VDD are set to be opposite to those of Cgd. .

  However, when the compensation capacitor and the blocking capacitor are connected as described above, the total capacitance between the gate and drain (input signal terminal and output signal terminal) of the MOS transistor Tr increases, and the circuit characteristics deteriorate. Therefore, as shown in FIGS. 6 and 8, cross-coupled capacitors Cxc and Cxcx are connected. The capacitance value of Cxc is Cxc = Cgd + Cxgd, and the same applies to Cxcx.

  FIG. 9 is a diagram showing changes in capacitance values of parasitic capacitances Cgd and Cgdx, compensation capacitances (varactors) Cxgd and Cxgdx, and cross coupling capacitances Cxc and Cxcx with respect to changes in VDD. In FIG. 9, P shows changes in parasitic capacitances Cgd and Cgdx, Q shows changes in capacitance values of varactors Cxgd and Cxgdx, and R shows changes in cross coupling capacitances Cxc and Cxcx, respectively. P and Q change inversely with respect to the change of VDD, and their sum is almost constant. Thereby, even if VDD is changed, the phase does not change in the output signal.

  FIG. 10 is a Bode diagram of gain and phase with respect to frequency when VDD is changed in the differential power amplifier circuit of the first embodiment. For reference, changes in FIGS. 5B and 5C are indicated by broken lines. In FIG. 10A, it can be seen that even when the power supply voltage VDD is changed, the change in the frequency position at which the gain reaches a peak is small. In FIG. 10B, it can be seen that even when the power supply voltage VDD is changed, the change in the frequency position where the phase changes suddenly is small.

FIG. 11 is a diagram illustrating a configuration of the differential power amplifier circuit according to the second embodiment.
In the differential power amplifier circuit of the second embodiment, the variable capacitors 21 and 21x are provided instead of the compensation capacitors Cxgd and Cxgdx in the differential power amplifier circuit of the first embodiment shown in FIG. Different, the other parts are the same. In FIG. 11, the inductance loads Ld and Ldx are not shown.

  The variable capacitor 21 has four units connected in parallel, and each unit has a fixed capacitor and a switch connected in series. Specifically, the variable capacitor 21 has four units in which fixed capacitors Cxgd0 to Cxgd3 and switches SW0 to SW3 are respectively connected in series. The same applies to the variable capacitor 21x, and there are four units in which fixed capacitors Cxgdx0 to Cxgdx3 and switches SWx0 to SWx3 are connected in series. The switches SW0 to SW3 and SWx0 to SWx3 are controlled to be turned on / off by a capacitance code signal. The fixed capacitance is set so that the ratio of the capacitance values is Cxgd0: Cxgd1: Cxgd2: Cxgd3 = 1: 2: 4: 8 and Cxgdx0: Cxgdx1: Cxgdx2 = 1: 2: 4: 8. Therefore, by controlling the on / off of the switches SW0 to SW3 and SWx0 to SWx3 by the 4-bit capacity code signal, the capacity values of the variable capacitors 21 and 21x are changed stepwise in 16 steps from 0 to 15 levels. It is possible to change.

  Therefore, if the capacitance code is changed and the capacitance values of the variable capacitors 21 and 21x are changed so as to have a reverse characteristic to the voltage dependency of the parasitic capacitances Cgd and Cgdx, the phase does not change in the output signal.

  FIG. 12 shows an example in which the switches SW0 to SW3 and SWx0 to SWx3 of the differential power amplifier circuit of the second embodiment are realized by a combination of a MOS transistor and a feeding resistor. A corresponding set of MOS transistors M0 to M3 and fixed capacitors Cxgd0 to Cxgd3 is connected in series between the gate and drain (input terminal and output terminal) of the MOS transistor Tr. A bias voltage Vbias is applied to the connection node between the MOS transistors M0 to M3 and the fixed capacitors Cxgd0 to Cxgd3 via the feed resistors Rbias0 to Rbias3. In FIG. 12, the reference numerals in the variable capacitor 21x on the second system side are not shown.

  As described above, the capacitance value of the fixed capacitor is set to be Cxgd0: Cxgd1: Cxgd2: Cxgd3 = 1: 2: 4: 8, and the gate widths of the MOS transistors M0 to M3 are also M0: M1: M2: M3 = 1: 2: 4: 8. The bias voltage Vbias is the same voltage as the gate bias voltage of the amplifier transistors Tr and Trx.

  The capacity code may be set from the outside so that the power supply voltage VDD is detected externally and the phase of the output signal does not change accordingly, but the capacity code is determined by detecting the power supply voltage VDD internally. It is also possible. The differential power amplifier circuit according to the second embodiment adjusts the capacitances of the variable capacitors 21 and 21x within a predetermined range even when the parasitic capacitance between the gate and the drain of the MOS transistor varies due to manufacturing variation or the like. Is possible. Thereby, even when there is a manufacturing variation, a differential power amplifier circuit in which the phase of the output signal is within a predetermined range can be realized.

FIG. 13 is a diagram illustrating the configuration of the differential power amplifier circuit according to the third embodiment.
The differential power amplifier circuit according to the third embodiment is the same as the differential power amplifier circuit according to the second embodiment, in which the power supply voltage VDD is detected to determine the capacitance code and the capacitances of the variable capacitors 21 and 21x are set. The difference is that the portion 30 is provided, and the other portions are the same. For simplification of illustration, the load inductance Ld is shown only on one side in FIG.

  FIG. 14 is a diagram illustrating a circuit example in which the feedback unit 30 is formed of a flash AD converter and a thermometer code / capacitance code conversion circuit 31 in the differential power amplifier circuit of the third embodiment.

  In FIG. 14, the reference voltage VDDREF, the resistor strings R0 to R15, and the comparators C0 to C14 form a flash AD converter. The flash AD converter outputs a thermometer code in which the position at which “0” changes to “1” changes according to the voltage value of VDD. The thermometer code / capacity code conversion circuit 31 converts the thermometer code into a capacity code. The thermometer code / capacitance code conversion circuit 31 is realized by a combinational circuit, and outputs a capacitance code whose value is fixed when the power supply voltage VDD decreases and the thermometer code decreases. In other words, the thermometer code / capacitance code conversion circuit 31 stores conversion data for generating a capacitance code that cancels the change in parasitic capacitance in accordance with the change in the power supply voltage VDD. As a result, even when the power supply voltage VDD decreases, the gate-drain capacitance of the MOS transistors Tr and Trx, that is, the capacitance between the input signal terminal and the output signal terminal does not change, and the phase in the output signal does not change.

  As described above, in the differential power amplifier circuit of the third embodiment, the capacitance code is automatically set by the feedback circuit 30 according to the power supply voltage VDD. Thereby, even if the power supply voltage VDD changes, the capacitance is automatically compensated and the phase change is suppressed.

FIG. 15 is a diagram illustrating a configuration of a circuit device according to the fourth embodiment.
The circuit device of the fourth embodiment incorporates the differential power amplifier (PA) circuit 40 of the second embodiment and is realized in the form of a chip. The circuit device of the fourth embodiment further includes a DC / DC converter 43, a test oscillator 46, an oscillation signal buffer 47, an oscillation signal supply capacitor 48, a phase difference / digital conversion unit 50, and a control unit. 51 and an AD converter 52.

  When the element variation and the secular change are large, the differential power amplifier circuit according to the third embodiment cannot sufficiently compensate the voltage dependence of the parasitic capacitances Cgd and Cgdx. Therefore, in the circuit device of the fourth embodiment, the circuit device using the PA 40 has an automatic calibration function, and generates conversion data for generating a capacitance code that cancels a change in parasitic capacitance for each power supply voltage VDD. And remember. The operation during the automatic calibration operation will be described below.

  At the time of calibration, the PA 40, the DC / DC converter 43, the test oscillator 46, the phase difference / digital conversion unit 50, and the control unit 51 are put into an operation state. The DC / DC converter 43 is supplied with electric power from the battery 41 from the outside. The control unit 51 outputs a power supply control code (3 bits) that changes the power supply voltage VDD output from the DC / DC converter 43 in eight stages.

  The control unit 51 outputs a power supply control code corresponding to the minimum power supply voltage and a capacity code (4 bits) corresponding to the minimum variable capacity. In this state, an oscillation signal is output from the test oscillator 46 and input to the power amplifier circuit (PA) 40 through the oscillation signal buffer 47 and the oscillation signal supply capacitor 48 buffer. The PA 40 amplifies and outputs the input oscillation signal. The phase difference / digital conversion unit 50 detects the phase difference between the input signal and the output signal of the PA 40, converts the phase difference into a digital signal, and outputs the digital signal to the control unit 51. The control unit 51 stores the phase difference in this state as a reference value.

  Next, the control unit 51 gradually increases the power supply control code to change the power supply voltage VDD, and at each power supply voltage, until the phase difference output from the phase difference / digital conversion unit 50 becomes the reference value, the capacitance The code is changed, and the power control code and the capacity code at that time are stored correspondingly. Note that the AD converter 52 may be operated so that the value of the power supply voltage VDD detected by the AD converter 52 and the capacity code are stored correspondingly. This process is performed for all power control code values. As a result, a table of capacitance codes having the same phase at each power supply voltage VDD is formed. This completes the calibration process.

  During normal operation, the DC / DC converter 43, the test oscillator 46, and the phase difference / digital conversion unit 50 are stopped, and the PA 40, the control unit 51, and the AD converter 52 are set to an operation state. The DC / DC converter 44 is a digital control type in which the voltage value changes stepwise according to digital control data, and may be provided inside or outside the chip. Electric power is supplied to the DC / DC converter 44 by the battery 41 provided outside, and the DC / DC converter 44 outputs a power source having a voltage specified by the digital control data. The AD converter 52 detects the voltage output from the DC / DC converter 44 and sends it to the control unit 51. The control unit 51 determines a capacity code corresponding to the detected voltage from the stored table and outputs it to the PA 40. When an input signal is input from the input signal terminal IN in this state, the PA 40 amplifies the input signal and outputs an output signal from the output signal terminal OUT with a predetermined phase. Reference numerals 45 and 49 indicate termination resistors provided outside the chip.

FIG. 16 is a diagram illustrating a circuit configuration of the phase difference / digital conversion circuit.
Since the signal from the power amplifier circuit (PA) 40 is a sine wave, it is shaped into a rectangular wave by the clipping buffers 61 and 62. The XOR 63 outputs a pulse train. When the phase difference is ± 180 degrees, the pulse width becomes maximum, and when the phase difference is zero, the pulse width becomes minimum. The DC voltage component of the pulse train is 1 when the phase difference is ± 180 degrees, that is, the voltage VDDREF voltage, and is zero when the phase difference is zero, that is, the GND voltage. The LPF 65 extracts a DC voltage component having a pulse width in the pulse train. The AD converter 66 digitally converts the DC voltage component (here, 4-bit data). In the above processing, since it is not known whether the phase is delayed or advanced, the outputs of the clipping buffers 61 and 62 are input to the DEF 64 in parallel with the above processing. In DEF64, since the output signal from PA40 becomes the output of DEF64 when the input signal to power amplifier (PA) 40 rises, the output signal of PA40 is zero, that is, the phase is delayed, or the output signal of PA40 is 1. That is, it can be determined whether the phase is advanced. However, when the phase difference is exactly 0 degree or ± 180 degrees, the output of DEF64 becomes indefinite. However, when the phase difference is exactly 0 degrees, the output of the AD converter 66 is always 0000, and when the phase difference is exactly ± 180 degrees, the output of the AD converter 66 is always 1111. Therefore, the output of the AD converter 66 and the output of the DEF 64 are input to the complement circuit (AUX) 67. When the phase difference is exactly 0 degree, the complement circuit output is zero, and when the phase difference is exactly ± 180 degrees, the complement circuit. The output is set to 1, otherwise, the output of DEF64 is used as the output of AUX67 as it is. The output of the phase difference / digital conversion unit 50 is 5 bits including the output (4 bits) of the AD converter 66 and the output (1 bit) of the complementary circuit (AUX) 67.

  FIG. 17 shows a circuit diagram of the complement circuit (AUX) 67. As shown in the figure, this is a simple combinational circuit, and a description thereof will be omitted.

FIG. 18 is a diagram illustrating a circuit configuration of the control unit 51.
The control unit 51 includes a core control unit 81, a phase difference storage memory 82, a coincidence detector 83, an encoder 84, an address selector 85, a capacity code memory 86, a capacity code selector 87, and a decoder 88. Have.

FIG. 19 is a flowchart showing the operation of the control unit 51. The configuration and operation of the control unit 51 will be described with reference to FIGS. 18 and 19.
When the calibration process is started, in step S11, all the circuits in FIG.

  In step S12, the capacity code storage memory 86 is set in a state for writing, address data indicating the address ADDR = 0 is output, and a signal SEL = 0 to the address selector 85 and the capacity code selector 87 is set. As a result, the address selector 85 and the capacity code selector 87 are in a state of selecting the address data and the capacity code from the core control unit 81. Further, the capacity code storage memory 86 is in a state of accessing an address for storing the minimum VDD capacity code, and the decoder 88 outputs a digital signal indicating the minimum VDD.

In step 13, a 4-bit capacity code = 0000 is output. In this state, the DC / DC converter 43 outputs the minimum VDD, and the variable capacitance of the PA 40 is in the minimum capacitance value, and the phase difference / digital conversion unit 50 detects the phase difference in this state.
In step S <b> 14, the phase difference detected by the phase difference / digital conversion unit 50 is written in the phase difference storage memory 82. This phase difference becomes the reference phase difference.

  In step S15, reading from the phase difference storage memory 82 is performed. As a result, the phase difference storage memory 82 enters a state of outputting the reference phase difference.

  In step S16, address data obtained by incrementing the address ADDR of the capacity code storage memory 86 by 1 is output. As a result, the capacity code memory 86 is in a state of accessing the address storing the capacity code in the case of VDD increased by one stage from the previous stage, and the decoder 88 increases the VDD increased by one stage from the previous stage. Outputs the digital signal to be instructed. In this state, the DC / DC converter 43 outputs VDD increased by one step from the previous step.

  In step S17, a 4-bit capacity code = 0000 is output. In this state, the variable capacitance of the PA 40 is in a state where it has the minimum capacitance value, and the phase difference / digital conversion unit 50 detects the phase difference in this state.

  In step S18, the coincidence detector 83 determines whether or not the reference phase difference output from the phase difference storage memory 82 and the phase difference detected by the phase difference / digital conversion unit 50 coincide with each other. If not, the process proceeds to step S19.

  In step S19, the capacity code is incremented by one. As a result, the variable capacity of the PA 40 is increased by one step from the previous state.

  In step S20, it is determined whether or not the capacity code has reached the maximum value. If not, the process returns to step S18, and if it has reached, the process proceeds to step S21. By repeating steps S18 to S20, the capacity code is increased until it matches the reference phase difference.

  In step S21, the capacity code is stored at the address of the capacity code storage memory 86 in that state, and it is determined whether the address data has reached the maximum value. If not, the process returns to step S16. Proceed to By repeating steps S16 to S21, a capacity code matching the reference phase difference is stored in the capacity code storage memory 86 at an address indicating VDD at each stage.

  In step S2, the capacity code storage memory 86 is set to a state in which reading is performed, and SEL = 0 is set. As a result, the address selector 85 selects data from the encoder 84, and the capacity code selector 87 selects output data from the capacity code storage memory 86.

  In step S23, the core control unit 81, the phase difference storage memory 82, the coincidence detector 83, and the decoder 88 are stopped.

  In the normal operation state, the address selector 85 selects data indicating the stage of the power supply voltage VDD from the encoder 84. Data indicating the stage of the power supply voltage VDD selected by the address selector 85 is input to the address of the capacity code storage memory 86. The capacity code storage memory 86 reads the capacity code corresponding to the stage of the power supply voltage VDD and outputs it to the capacity code selector 87. The capacity code selector 87 outputs this capacity code to the PA 40, and the PA 40 sets the variable capacity to the value indicated by the capacity code. Thereby, even if VDD changes, the phase change in the output signal is small.

  FIG. 20 shows a configuration of a modification of the circuit device according to the fourth embodiment that uses an analog control type DC / DC converter 44 ′ instead of the digital control type DC / DC converter 44. An analog control voltage for controlling the power supply voltage VDD output from the DC / DC converter 44 ′ is input from the input terminal 54. Other parts are the same as those of the circuit device of the fourth embodiment.

  FIG. 21 is a Bode diagram of gain and phase with respect to frequency when VDD is changed in the differential power amplifier circuits and circuit devices of the second to fourth embodiments. In the second to fourth embodiments, FIG. The characteristics of are the same. For reference, changes in FIGS. 5B and 5C are indicated by broken lines. In FIG. 21A, it can be seen that even when the power supply voltage VDD is changed, the change in the frequency position where the gain reaches a peak is small. In FIG. 21B, it can be seen that even when the power supply voltage VDD is changed, the change in the frequency position where the phase changes suddenly is small.

  The circuit device according to the fourth embodiment adjusts the capacitances of the variable capacitors 21 and 21x within a predetermined range in the power amplifier circuit even when the parasitic capacitance between the gate and drain of the MOS transistor varies due to manufacturing variation or the like. It is possible. Thereby, even when there is a manufacturing variation, a differential power amplifier circuit in which the phase of the output signal is within a predetermined range can be realized.

  Although the differential power amplifier circuit and the circuit device of the first to fourth embodiments have been described above, the differential power amplifier circuit and the circuit device of the embodiment are, for example, a high-frequency amplifier at the last stage of a transmission circuit of a mobile terminal. Can be used as

FIG. 22 is a diagram illustrating a configuration of a transmission / reception circuit of a general mobile terminal.
A typical mobile terminal transmission / reception circuit includes an antenna 101, an antenna switch 102, a linear amplifier 103, a reception frequency bandpass filter 104, a downmixer 105, an intermediate frequency bandpass filter 106, a demodulation circuit 107, A baseband circuit 108, a modulation circuit 109, an upmixer 110, a transmission frequency bandpass filter 111, and a power amplifier 112 are included. Since the configuration of such a transmission / reception circuit is widely known, a description thereof will be omitted, but the differential power amplifier circuits and circuit devices of the first to fourth embodiments are suitable for use as the power amplifier 112.

  Since the power amplifier 112 is a high-frequency amplifier that sends a signal to the antenna 101, it basically has a large output and consumes a large amount of power. Therefore, a compound semiconductor transistor such as GaAs has been used so far. If the differential power amplifier circuit and the circuit device of the first to fourth embodiments are used as the power amplifier 112, it is possible to significantly reduce power consumption.

  Although the embodiments have been described above, it goes without saying that various modifications are possible. For example, the differential power amplifier circuit has been described as an example, but the configuration described in the embodiment can be applied to a single-phase power amplifier circuit. In the first embodiment, an example in which a varactor is used has been described. However, any element can be used as long as it can realize the same characteristics. Furthermore, in the fourth embodiment, the phase detected in the case of the minimum capacity code with the minimum VDD is set as the reference phase. However, the phase of the condition to be set as the reference phase is arbitrary, and it corresponds to the change in VDD. The capacity code determination method may have various modifications.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
Power supply,
A MOS transistor connected to the power source;
A compensation capacitor connected between the gate and drain of the MOS transistor,
The compensation capacitor has a characteristic that a capacitance value changes in accordance with a voltage change of the power supply so as to cancel a change in a gate-drain capacitance of the MOS transistor that changes in accordance with a voltage change of the power supply. A featured power amplifier circuit.
(Appendix 2)
The power amplifier circuit according to appendix 1, wherein the compensation capacitor is a varactor.
(Appendix 3)
A bias adjustment capacitor connected between a gate side terminal of the MOS transistor of the compensation capacitor and a gate of the MOS transistor;
The power amplifier circuit according to appendix 1 or 2, wherein a bias voltage is applied to a connection node between the compensation capacitor and the bias adjustment capacitor.
(Appendix 4)
A set of the MOS transistor and the compensation capacitor is further provided. A differential signal is input to the gates of the two MOS transistors, and a differential signal is output from the drains of the two MOS transistors. A power amplifier circuit according to any one of the above.
(Appendix 5)
Between one gate of the two MOS transistors and the other drain of the two MOS transistors, and between one drain of the two MOS transistors and the other gate of the two MOS transistors 5. The power amplifier circuit according to appendix 4, comprising two cross coupling capacitors (Cxc, Cxcx) connected to each other.
(Appendix 6)
Power supply,
A MOS transistor connected to the power source;
A variable capacitor connected between the gate and drain of the MOS transistor,
The power amplifier circuit, wherein the capacitance value of the variable capacitor is changed so as to cancel the change in the capacitance between the gate and drain of the MOS transistor which changes in accordance with the voltage change of the power supply.
(Appendix 7)
The variable capacity has a plurality of capacity units connected in parallel,
Each capacity unit has a fixed capacity and a switch connected in series,
The power amplifier circuit according to appendix 6, wherein the switch is turned on and off to control the number of the capacity units connected in parallel to change the capacity value of the variable capacity.
(Appendix 8)
The power amplifier circuit according to appendix 6 or 7, wherein a capacitance value of the variable capacitor is set from the outside in accordance with a voltage change of the power source.
(Appendix 9)
The power amplifier circuit according to appendix 6 or 7, further comprising a feedback circuit (30) for detecting a voltage value of the power source and setting a capacitance value of the variable capacitor according to the detected voltage value.
(Appendix 10)
The feedback circuit has a table that stores the capacitance value of the variable capacitor corresponding to the voltage value of the power supply, and reads and sets the capacitance value of the variable capacitor corresponding to the detected voltage value from the table. The power amplifier circuit described.
(Appendix 11)
Additional provisions 6 to 10 further comprising a set of the MOS transistor and the variable capacitor, wherein a differential signal is input to the gates of the two MOS transistors and a differential signal is output from the drains of the two MOS transistors. A power amplifier circuit according to any one of the above.
(Appendix 12)
Between one gate of the two MOS transistors and the other drain of the two MOS transistors, and between one drain of the two MOS transistors and the other gate of the two MOS transistors 12. The power amplifier circuit according to appendix 11, comprising two cross coupling capacitors connected to each other.
(Appendix 13)
A circuit device comprising the power amplifier circuit according to appendix 6 or 7,
Calibration power supply,
A test oscillator;
A phase difference digital converter for detecting a phase difference when the oscillation signal output from the test oscillator is input to the power amplifier circuit;
The phase difference detected by the phase difference digital conversion unit by changing the capacitance value of the variable capacitor at each voltage value by controlling the voltage value by operating the calibration dedicated power source as the power source during calibration. A controller that detects a capacitance value of the variable capacitor that becomes a predetermined value and creates a table that stores the variable capacitance value in association with the voltage value;
An AD converter for detecting the voltage value of the power supply as digital data,
In circuit operation, the control unit reads a capacitance value corresponding to a voltage value detected by the AD converter from the lookup table, and sets the variable capacitance to the read capacitance value.

21, 21x Variable capacitance Tr, Trx MOS transistor Cgd, Cgdx Parasitic capacitance Cxgd, Cxgdx Compensation capacitance

Claims (5)

Power supply,
A MOS transistor connected to the power source;
A compensation capacitor connected between the gate and drain of the MOS transistor,
The compensation capacitor has a characteristic that a capacitance value changes in accordance with a voltage change of the power supply so as to cancel a change in a gate-drain capacitance of the MOS transistor that changes in accordance with a voltage change of the power supply. A featured power amplifier circuit.   The power amplifier circuit according to claim 1, wherein the compensation capacitor is a varactor. Power supply,
A MOS transistor connected to the power source;
A variable capacitor connected between the gate and drain of the MOS transistor,
The power amplifier circuit, wherein the capacitance value of the variable capacitor is changed so as to cancel the change in the capacitance between the gate and drain of the MOS transistor which changes in accordance with the voltage change of the power supply.   The power amplifier circuit according to claim 3, further comprising: a feedback circuit that detects a voltage value of the power source and sets a capacitance value of the variable capacitor according to the detected voltage value. A circuit device comprising the power amplifier circuit according to claim 3,
Calibration power supply,
A test oscillator;
A phase difference digital converter for detecting a phase difference when the oscillation signal output from the test oscillator is input to the power amplifier circuit;
The phase difference detected by the phase difference digital conversion unit by changing the capacitance value of the variable capacitor at each voltage value by controlling the voltage value by operating the calibration dedicated power source as the power source during calibration. A control unit that detects a capacitance value of the variable capacitor that becomes a predetermined value and creates a lookup table that stores the capacitance value of the variable capacitor in association with the voltage value;
An AD converter for detecting the voltage value of the power supply as digital data,
In circuit operation, the control unit reads a capacitance value corresponding to a voltage value detected by the AD converter from the lookup table, and sets the variable capacitance to the read capacitance value.

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