JP2013009157A - Information processing device and method for controlling information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device that allows for high-speed communication while suppressing noise occurring at the time of communication.SOLUTION: An information processing device 1 includes: a signal line pair 7 formed by one set of two lines 7a, 7b; a driver 2 for setting a voltage level corresponding to data with plurality of binary bits input to the signal line pair 7; and a receiver 3 connected to the other end of the signal line pair 7 and for converting the voltage level of the signal line pair 7 into data with a corresponding plurality of binary bits. The driver 2 includes: a constant voltage source 4 for applying voltage to the signal line pair 7; switches SW6a, SW6b for adjusting input/output impedance of the signal line pair according to the data with the plurality of binary bits; and switches SW9a, SW9b, SW10a, SW10b for switching the direction of current to be flown into respective signal line of the signal line pair depending on the data with the plurality of binary bits.

Description

  The present invention relates to a small information processing apparatus in which the number of communication wires is limited and a method for controlling the information processing apparatus.

  Conventionally, serial communication and parallel communication have been used as data communication methods. Since parallel communication can communicate a plurality of data at a time, it has an advantage that the frequency of a clock signal used for communication can be set lower than that of serial communication. However, since multiple signal lines are required for parallel communication, multiple signal lines to be used are connected (wired) when trying to use them in devices that require downsizing, especially devices that communicate through a rotating hinge. Sometimes it is not possible. In addition, the cost increases as the number of signal lines to be connected (wired) increases.

  For this reason, serial communication is generally used as a communication method used for devices that need to be miniaturized, particularly devices that communicate through a rotating hinge or the like. Various transmission systems using serial communication, that is, serial communication have been proposed (for example, Patent Documents 1 and 2).

  As for the main thing of the serial communication, a single pair of signal lines, which are improved based on the problems of the single end system, are usually used instead of the single end system using only one signal line. There are differential serial communication systems such as LVDS (Low-Voltage Differential Signaling).

  The advantage of the differential serial communication system compared to the single-ended system is that, when external noise occurs, each of the two signal lines is similarly affected by the external noise, so that the two signal lines It is in the point which suppresses the change of the electric potential difference itself and improves the tolerance to external noise.

  Another merit is that by arranging and wiring two signal lines close to each other, the signal lines used in the differential serial communication system arranged in parallel flow in opposite directions. The current is to be a balanced differential line that is the same. In other words, signals of equal magnitude and opposite direction flow through each of the parallel signal lines, so that the concentric magnetic lines of force work in the direction to be canceled out, and the concentric electric lines of force work together, and as a result Therefore, the electromagnetic field energy (that is, noise) propagating to the magnetic field can be kept very small.

  In differential serial communication composed of two signal lines, a communication circuit is composed of one clock line and a plurality of data lines, and the two signal lines indicate “+” and “−” respectively. And connected to a differential serial input buffer (receiver). If the voltage level of the “+” signal line is higher than that of the “−” signal line, “1” is received, and if the voltage level is opposite, “0” is received. In other words, the information amount of a set of two data lines is 1 bit.

  That is, since only one bit of data amount can be expressed for one set of data lines, in order to perform high-speed data communication, the signal line is operated quickly or a plurality of sets of data lines Need to use.

  It is difficult to operate the signal line quickly due to problems of the process of the IC itself or problems such as external factors such as load capacity. Even when multiple sets of data lines are used, it is necessary to synchronize with the clock line. There arises a problem such as a certain problem or an increase in cost due to an increase in the number of signal lines connected.

  For this reason, in Patent Document 3, one signal line is represented in three states, that is, data represented by ternary data (data represented by the ternary system) depending on the potential of the signal line. A transmission device is proposed.

  That is, for example, when binary data (binary data) is transmitted through three signal lines, binary data for three signal lines is converted into ternary data. The data is transmitted through two signal lines, and the receiving side physically returns 2 to the state of binary data corresponding to the three signal lines by returning the ternary data corresponding to the two signal lines. The amount of information for three lines is transmitted through one signal line. As a result, the amount of information transmitted at a time can be increased.

JP-A-4-234249 JP 2010-166403 A Japanese Patent Laid-Open No. 11-177639

  However, in the data transmission device disclosed in Patent Document 3, a plurality of signal lines having different signal line potentials are used. Therefore, the flowing currents are the same, and signals in opposite directions cannot be generated in the respective signal lines. Therefore, there is a problem that noise generated from the signal line itself becomes large, as in the communication method using the single end method.

  The present invention is intended to solve the above-described problems, and provides an information processing apparatus and a control method for the information processing apparatus that enable high-speed communication while suppressing noise generated during communication. With the goal.

  An information processing apparatus according to an aspect of the present invention includes a signal line pair formed by a set of two signal lines, and a plurality of binary numbers connected to one end side of the signal line pair and input to the signal line pair. A driver for setting the voltage level according to the bit data, and a receiver connected to the other end of the signal line pair for converting into binary multi-bit data according to the voltage level of the signal line pair; Is provided. The driver includes a constant voltage source for applying a voltage to the signal line pair, an impedance adjusting unit that adjusts input / output impedance of the signal line pair according to binary multiple bit data, and binary multiple bit data And a switching unit that switches the direction of the current flowing through each signal line of the signal line pair.

  Preferably, the impedance adjustment unit includes a first resistance element provided between the constant voltage source and the first internal node connected to one of the signal line pairs, the constant voltage source, and the first internal node. Between the first switch element provided in parallel with the first resistance element and the second internal node connected to the fixed voltage and the other of the signal line pair. And a second switch element provided between the fixed voltage and the second internal node and provided in parallel with the second resistor element. The first and second switch elements are complementarily turned on / off in accordance with a plurality of binary bits of data.

  In particular, the switching unit includes third and fourth switch elements for connecting the first and second internal nodes to one and the other of the signal line pair, respectively, according to binary multi-bit data, and 2 The fifth and fifth elements operate in a complementary manner with the third and fourth switch elements in accordance with the data of a plurality of bits in the decimal number, and are connected to the first and second internal nodes and the other and one of the signal line pairs, respectively. A sixth switch element.

Preferably, the plurality of bits is 2 bits.
Preferably, the receiver has an intermediate voltage level between a signal line pair and a potential difference identifying unit that converts data into partial bits of a plurality of binary bits in accordance with a potential difference between the signal lines of the signal line pair. And a common signal identifying unit for converting into data of the remaining bits of the plurality of binary bits.

  A control method for an information processing device according to an aspect of the present invention is a control method for an information processing device that transmits a plurality of binary bits of data to a signal line pair composed of two signal lines. A step of applying a voltage to the signal line pair, a step of adjusting an input / output impedance of the signal line pair in accordance with binary binary data, and a signal line pair in accordance with binary binary data Switching the direction of the current flowing through the signal line, and converting the data into binary multiple-bit data according to the voltage level of the signal line pair.

  The information processing apparatus according to the present invention is provided with a signal line pair including a pair of signal lines, a driver, and a receiver, and the driver is a constant voltage source for applying a voltage to the signal line pair. And an impedance adjustment unit that adjusts the input / output impedance of the signal line pair according to binary multi-bit data, and the direction of current flowing through each signal line of the signal line pair according to binary multi-bit data And a switching unit for switching between. Therefore, it is possible to perform multi-bit data communication using a pair of two signal lines and to suppress noise generated during communication because a differential line in which the directions of currents flowing through the signal lines are opposite to each other is configured. It becomes possible to do.

It is a figure explaining the structure of the information processing apparatus 1 according to embodiment of this invention. It is a figure explaining the relationship between the electric potential of signal line 7a, 7b according to embodiment of this invention, a common voltage, and 2-bit information. It is another figure explaining the relationship between the electric potential of signal line 7a, 7b according to embodiment of this invention, a common voltage, and 2-bit information.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

FIG. 1 is a diagram illustrating a configuration of information processing apparatus 1 according to the embodiment of the present invention.
Referring to FIG. 1, information processing device 1 according to the embodiment of the present invention has a configuration in which a driver 2 on a signal transmitting side and a receiver (receiving device) 3 on a signal receiving side are provided. Between the driver 2 and the receiver 3, a signal line pair 7 including two signal lines as one set is connected. Here, the signal lines of the pair of two signal lines 7 are defined as signal lines 7a and 7b.

  Driver 2 includes a constant voltage source 4, resistance elements (impedance components) 5 and 8 on the upper potential side and lower potential side, and switches SW6a, SW6b, SW9a, SW9b, SW10a, and SW10b.

  Constant voltage source 4 is electrically coupled to node N0. In this example, the constant voltage source 4 supplies a voltage of 400 mV as an example.

  Resistance element 5 is connected between node N0 and node (internal node) N1. The switch SW6a is connected between the node N0 and the node N1 in parallel with the resistor element 5, and is provided to bypass the resistor element 5 so that no current flows.

Fixed voltage GND is electrically coupled to node N5.
Resistance element 8 is connected between node N5 and node (internal node) N3. The switch SW6b is connected between the node N5 and the node N3 in parallel with the resistance element 8, and is provided to bypass the resistance element 8 so that no current flows.

In this example, the switches SW6a and SW6b operate in a complementary manner.
Switch SW9a is connected between nodes N1 and N2, and receives the input of logic circuit 11a at its gate.

  Switch SW10a is connected between nodes N2 and N3, and receives the input of logic circuit 11b at its gate.

  Switch SW10b is connected between nodes N1 and N4, and receives the input of logic circuit 11b at its gate.

  Switch SW9b is connected between nodes N4 and N3, and receives an input of logic circuit 11a at its gate.

  The node N2 is a connection node connected to the signal line 7a. Node N4 is a connection node connected to signal line 7b.

  The switch SW9a and the switch SW9b operate in response to the input of the logic circuit 11a, and connect the node N1 and the node N2 when the input of the logic circuit 11a is at “H” level. Further, the node N3 and the node N4 are connected. That is, the signal lines 7a and 7b are electrically coupled to the nodes N1 and N3, respectively.

  The switch SW10a and the switch SW10b operate in response to the input of the logic circuit 11b, and connect the node N1 and the node N4 when the input of the logic circuit 11b is at “H” level. Further, the node N2 and the node N3 are connected. That is, the signal lines 7a and 7b are electrically coupled to the nodes N3 and N1, respectively.

  In this example, the switches SW9a and SW9b and the switches SW10a and 10b operate complementarily and function as a switching circuit that switches the flow of supplying current to the signal lines 7a and 7b.

  Specifically, when the input of the logic circuit 11a is at “H” level, the node N2 is at a high potential and the node N4 is at a low potential, and current is supplied from the signal line 7a to the signal line 7b. The

  On the other hand, when the input of the logic circuit 11b is at the “H” level, the node N2 has a low potential and the node N4 has a high potential, and current is supplied from the signal line 7b to the signal line 7a.

  The switch SW6a controlled by the logic circuit 11c is a switch that adjusts the voltage level of the node N1 applied by the constant voltage source 4.

  Specifically, when the switch SW6a is ON, the switch SW6a functions as a bypass path, and the voltage of the node (internal node) N1 drops according to the impedance component (for example, 0.1Ω or less) of the switch SW6a itself. Set to a value.

  On the other hand, when the switch SW6a is turned off, a voltage is applied to the node N1 via the resistance element 5. That is, the output current of the constant voltage source 4 flows through the resistance element 5 to the node N1. In this example, as an example, the impedance of the resistance element 5 is 300Ω. Therefore, the node (internal node) N1 is set to a voltage drop value according to the impedance component (300Ω) of the resistance element 5.

  Similarly, the switch SW6b controlled by the logic circuit 11d is a switch that controls the electrical coupling with the fixed voltage (GND) to adjust the voltage level of the node (internal node) N3.

  Specifically, when the switch SW6b is ON, the switch SW6b functions as a bypass path. That is, a current flows to the switch SW6b side. Therefore, the node (internal node) N3 is set to a voltage level higher than the fixed voltage (GND) by a voltage drop according to the impedance component (for example, 0.1Ω or less) of the switch SW6b itself.

  On the other hand, when the switch SW6b is OFF, a current flows through the resistance element 8 to the fixed voltage (GND). In this example, as an example, the impedance of the resistance element 8 is 300Ω. Therefore, the node (internal node) N3 is set to a voltage level higher than the fixed voltage (GND) by a voltage drop according to the impedance component (300Ω) of the resistance element 8.

Next, the configuration of the receiver 3 will be described.
The receiver 3 includes a resistance element 12, differential amplifiers 13 and 14, a decoder 15, a constant voltage source 16, and a resistance element 17.

  The resistance element 12 is provided between the signal line 7a and the signal line 7b. Therefore, a potential difference according to the impedance of the resistance element 12 is generated between the signal lines 7a and 7b. In this example, the impedance of the resistance element 12 is 100Ω.

  The differential amplifier 13 is connected to the signal lines 7a and 7b, respectively. Specifically, the input terminal on the “+” side and the signal line 7a are connected, the input terminal on the “−” side and the signal line 7b are connected, and a signal corresponding to the potential difference between the signal lines 7a and 7b is output. To do. As an example, if the potential of the signal line 7a is higher than that of the signal line 7b, an "H" level signal is output. On the other hand, if the potential of the signal line 7b is higher than that of the signal line 7a, an "L" level signal is output.

  The constant voltage source 16 is connected to a fixed voltage (GND) through the resistance element 17. Therefore, a constant current flows through the resistance element 17. It is assumed that the predetermined position of the resistance element 17 and the “−” side terminal of the differential amplifier 14 are electrically connected, and the predetermined position can be adjusted. In this example, the voltage level input to the differential amplifier 14 is adjusted as a common voltage threshold. In this example, the impedance of the resistance element 17 is 400Ω as an example. The constant voltage source 16 supplies a voltage of 400 mV as an example. In this example, the “−” side terminal of the differential amplifier 14 and the intermediate position of the resistance element 17 are connected, and the common voltage threshold V4 is set to 200 mV.

  The differential amplifier 14 is connected to an intermediate position of the resistance element 12 and a predetermined position of the resistance element 17. Specifically, the input terminal on the “+” side and the intermediate position of the resistance element 12 are connected, the input terminal on the “−” side and a predetermined position of the resistance element 17 are connected, and the potential difference at the connection position is determined. Output the signal. As an example, if the “+” side input terminal has a higher potential than the “−” side input terminal, an “H” level signal is output. On the other hand, if the “+” side input terminal is lower in potential than the “−” side input terminal, an “L” level signal is output.

  The decoder 15 converts the data output from the differential amplifiers 13 and 14 into binary multi-bit data (2 bits in this example) and outputs the data.

Hereinafter, the communication method of the information processing apparatus 1 will be described.
Next, a communication protocol in information processing apparatus 1 according to the embodiment of the present invention will be described.

  In the embodiment of the present invention, information obtained by combining the potential and potential difference of a pair of two signal lines 7 is expressed by a 2-bit value.

  As an example, for example, when an intermediate level between the potentials of two signal lines is a common voltage, a state in which the common voltage is higher than a certain voltage level (common voltage threshold V4) is “1”, and a lower potential is The state shown is defined as “0”. In this example, the value of the upper bit of the two bits corresponds.

  Further, a state where the signal line 7a shows a higher potential than the signal line 7b is defined as “1”, and a state where the signal line 7a shows a lower potential is defined as “0”. In this example, the value of the lower bit of the 2 bits corresponds.

  FIG. 2 is a diagram illustrating the relationship between the potentials of the signal lines 7a and 7b, the common voltage, and 2-bit information according to the embodiment of the present invention.

  With reference to FIG. 2, the case where information is transmitted at predetermined time intervals (for example, t1 to t2) will be described in this example.

  In this example, as an example, a case where information is transmitted in a period from time t1 to time t9 is shown.

  The state where the signal line 7a is at the voltage V1 level and the signal line 7b is at the voltage V3 level within a predetermined time from the time t1 is defined as “11”.

  The common voltage V2, which is an intermediate voltage between the signal line 7a and the signal line 7b, is higher than the common voltage threshold value V4. Therefore, 1-bit information represented by a common potential difference between the common voltage V2 and the common threshold voltage V4 is “1”.

  Further, the voltage V1 level of the signal line 7a is higher than the voltage V3 level of the signal line 7b. Therefore, 1-bit information represented by the two signal line potential difference is set to “1”.

That is, 2-bit information can be transmitted every predetermined time.
The state in which the signal line 7a is at the voltage V3 level and the signal line 7b is at the voltage V1 level within the predetermined time from the time t2 is defined as “10”.

  The common voltage V2, which is an intermediate voltage between the signal line 7a and the signal line 7b, is higher than the common voltage threshold value V4. Therefore, 1-bit information represented by the common potential difference between the common voltage V2 and the common threshold voltage V4 is “1”.

  Further, the voltage V1 level of the signal line 7b is higher than the voltage V3 level of the signal line 7a. Therefore, 1-bit information represented by the two signal line potential difference is set to “0”.

  The state in which the signal line 7a is at the voltage V5 level and the signal line 7b is at the voltage V7 level within a predetermined time from the time t3 is defined as “01”.

  The common voltage V6, which is an intermediate voltage between the signal line 7a and the signal line 7b, is at a voltage level lower than the common voltage threshold V4. Therefore, 1-bit information represented by the common potential difference between the common voltage V6 and the common threshold voltage V4 is “0”.

  Further, the voltage V5 level of the signal line 7a is higher than the voltage V7 level of the signal line 7b. Therefore, 1-bit information represented by the two signal line potential difference is set to “1”.

  The state in which the signal line 7a is at the voltage V7 level and the signal line 7b is at the voltage V5 level within a predetermined time from the time t4 is defined as “00”.

  The common voltage V6, which is an intermediate voltage between the signal line 7a and the signal line 7b, is at a voltage level lower than the common voltage threshold V4. Therefore, 1-bit information represented by the common potential difference between the common voltage V6 and the common threshold voltage V4 is “0”.

  Further, the voltage V5 level of the signal line 7b is higher than the voltage V7 level of the signal line 7a. Therefore, 1-bit information represented by the two signal line potential difference is set to “0”.

  Since the predetermined time from time t5, t6, t7, t8 is the same as time t1, t2, t3, t4, respectively, detailed description thereof will not be repeated.

  In this example, the voltage V1 is 400 mV, the voltage V2 is 350 mV, the voltage V3 is 300 mV, the voltage V4 is 200 mV, the voltage V5 is 100 mV, the voltage V6 is 50 mV, and the voltage V7 is 0V.

  The receiver 3 decodes and outputs binary 2-bit information according to the potential level and potential difference of the signal lines 7a and 7b.

  In this example, 2 bits × 8 = 16 bits of information can be transmitted in the period from time t1 to time t9.

Hereinafter, the operation of the driver 2 in accordance with binary 2-bit information will be described.
The driver 2 sets the signal lines 7a and 7b to the voltages V1 and V3, respectively, when the input binary 2-bit information is “11”. In this case, the logic circuit 11a outputs an “H” level signal, and the logic circuit 11b outputs an “L” level signal. The logic circuit 11c outputs an “H” level signal, and the logic circuit 11d outputs an “L” level signal.

  In the driver 2, the switch SW6a is turned on in response to the input of the “H” level signal of the logic circuit 11c. The switches SW9a and SW9b are turned on in response to the input of the “H” level signal to the logic circuit 11a. On the other hand, the switch SW6b and the switches SW10a and SW10b are off.

  In this state, the current path from the constant voltage source 4 to the fixed voltage GND is as follows: constant voltage source 4 to switch SW6a to switch SW9a to signal line 7a to resistor element 12 to signal line 7b to switch SW9b to resistor element 8 to fixed voltage. It becomes GND. The total impedance is 400Ω, which is the sum of the resistance element 12 and the resistance element 8. The impedance component such as the switch SW6a is omitted because it has a small value.

  If the voltage level of the constant voltage source 4 is 400 mV, the flowing current is 1 mA. The voltage level of the node N2 is set to 400 mV, and the voltage level of the node N4 is set to 300 mV. The common voltage between the node N2 and the node N4 is set to 350 mV.

  The driver 2 sets the signal lines 7a and 7b to voltages V3 and V1, respectively, when the input binary 2-bit information is "10". In this case, the logic circuit 11a outputs an “L” level signal, and the logic circuit 11b outputs an “H” level signal. The logic circuit 11c outputs an “H” level signal, and the logic circuit 11d outputs an “L” level signal.

  In the driver 2, the switch SW6a is turned on in response to the input of the “H” level signal of the logic circuit 11c. Then, the switches SW10a and SW10b are turned on in response to the input of the “H” level signal to the logic circuit 11b. On the other hand, the switch SW6b and the switches SW9a and SW9b are off.

  In this state, the current path from the constant voltage source 4 to the fixed voltage GND is as follows: constant voltage source 4 to switch SW6a to switch SW10b to signal line 7b to resistor element 12 to signal line 7a to switch SW10a to resistor element 8 to fixed voltage. It becomes GND. The total impedance is 400Ω, which is the sum of the resistance element 12 and the resistance element 8. The impedance component such as the switch SW6a is omitted because it has a small value.

  If the voltage level of the constant voltage source 4 is 400 mV, the flowing current is 1 mA. The voltage level of the node N4 is set to 400 mV, and the voltage level of the node N2 is set to 300 mV. The common voltage between the node N2 and the node N4 is set to 350 mV. That is, the direction of the current flowing through the signal lines 7a and 7b is reversed from the case where the 2-bit information is “11”.

  When the input binary 2-bit information is “01”, the driver 2 sets the signal lines 7a and 7b to voltages V5 and V7, respectively. In this case, the logic circuit 11a outputs an “H” level signal, and the logic circuit 11b outputs an “L” level signal. The logic circuit 11c outputs an “L” level signal, and the logic circuit 11d outputs an “H” level signal.

  In the driver 2, the switch SW6b is turned on in response to the input of the “H” level signal to the logic circuit 11d. The switches SW9a and SW9b are turned on in response to the input of the “H” level signal to the logic circuit 11a. On the other hand, the switch SW6a and the switches SW10a and SW10b are off.

  In this state, the current path from the constant voltage source 4 to the fixed voltage GND is as follows: constant voltage source 4 to resistance element 5 to switch SW9a to signal line 7a to resistance element 12 to signal line 7b to switch SW9b to switch SW6b to fixed voltage. It becomes GND. The total impedance is 400Ω which is the sum of the resistance element 12 and the resistance element 5. The impedance component such as the switch SW6b is omitted because it has a small value.

  If the voltage level of the constant voltage source 4 is 400 mV, the flowing current is 1 mA. The voltage level of the node N2 is set to 100 mV, and the voltage level of the node N4 is set to 0V. The common voltage between the node N2 and the node N4 is set to 50 mV.

  The driver 2 sets the signal lines 7a and 7b to voltages V7 and V5, respectively, when the input binary 2-bit information is "00". In this case, the logic circuit 11a outputs an “L” level signal, and the logic circuit 11b outputs an “H” level signal. The logic circuit 11c outputs an “L” level signal, and the logic circuit 11d outputs an “H” level signal.

  In the driver 2, the switch SW6b is turned on in response to the input of the “H” level signal to the logic circuit 11d. Then, the switches SW10a and SW10b are turned on in response to the input of the “H” level signal to the logic circuit 11b. On the other hand, the switch SW6a and the switches SW9a and SW9b are off.

  In this state, the current path from the constant voltage source 4 to the fixed voltage GND is as follows: constant voltage source 4 to resistance element 5 to switch SW10b to signal line 7b to resistance element 12 to signal line 7a to switch SW10a to switch SW6b to fixed voltage. It becomes GND. The total impedance is 400Ω, which is the sum of the resistance element 12 and the resistance element 8. The impedance component such as the switch SW6b is omitted because it has a small value.

  If the voltage level of the constant voltage source 4 is 400 mV, the flowing current is 1 mA. The voltage level of the node N4 is set to 100 mV, and the voltage level of the node N2 is set to 0V. The common voltage between the node N2 and the node N4 is set to 50 mV. That is, the direction of the current flowing through the signal lines 7a and 7b is reversed from the case where the 2-bit information is “01”.

  The receiver 3 decodes according to the potential difference between the signal lines 7a and 7b and the common voltage in accordance with the above-described method, and outputs binary 2-bit data (information).

  Specifically, when the signal lines 7a and 7b are at the voltages V1 and V3, respectively, the voltage V1 level of the signal line 7a is higher than the voltage V3 level of the signal line 7b. ”Level is output. Further, since the common voltage V2, which is an intermediate voltage between the signal lines 7a and 7b, is higher than the common voltage threshold V4, the differential amplifier 14 outputs an “H” level. The decoder 15 receives the “H” level signal from the differential amplifiers 13 and 14 and determines that the signal line 7a is at the voltage V1 level and the signal line 7b is at the voltage V3 level. Information "11" is output.

  Further, when the signal lines 7a and 7b are at the voltages V3 and V1, respectively, the voltage V1 level of the signal line 7b is higher than the voltage V3 level of the signal line 7a, so that the differential amplifier 13 has the “L” level. Output. Further, since the common voltage V2, which is an intermediate voltage between the signal lines 7a and 7b, is higher than the common voltage threshold V4, the differential amplifier 14 outputs an “H” level. The decoder 15 receives the "L" level signal from the differential amplifier 13 and the "H" level signal from the differential amplifier 14, and the signal line 7a is at the voltage V3 level and the signal line 7b is at the voltage V1 level. It is determined that there is a certain state, and information “10” is output.

  Further, when the signal lines 7a and 7b are at the voltages V5 and V7, respectively, the voltage V5 level of the signal line 7a is higher than the voltage V7 level of the signal line 7b, so that the differential amplifier 13 has the “H” level. Output. Further, since the common voltage V6, which is an intermediate voltage between the voltage levels of the signal lines 7a and 7b, is a voltage level lower than the common voltage threshold V4, the differential amplifier 14 outputs an “L” level. The decoder 15 receives the “H” level signal from the differential amplifier 13, receives the “L” level signal from the differential amplifier 14, the signal line 7a is at the voltage V5 level, and the signal line 7b is at the voltage V7. It is determined that the state is level, and information “01” is output.

  When the signal lines 7a and 7b are at the voltages V7 and V5, respectively, the voltage V5 level of the signal line 7b is higher than the voltage V7 level of the signal line 7a. Output. Further, since the common voltage V6, which is an intermediate voltage between the voltage levels of the signal lines 7a and 7b, is a voltage level lower than the common voltage threshold V4, the differential amplifier 14 outputs an “L” level. The decoder 15 receives the “L” level signal from the differential amplifiers 13 and 14 and determines that the signal line 7a is at the voltage V7 level and the signal line 7b is at the voltage V5 level. Information “00” is output.

  By using the circuit configuration as described above, it is possible to transmit binary information of multiple bits using a pair of two signal lines.

  As a method for transmitting a binary number of multiple bits of data to a signal line pair 7 composed of a pair of two signal lines, the driver 2 applies a voltage according to the constant voltage source 4 to the signal line pair 7. Apply. Then, the input / output impedance of the signal line pair 7 is adjusted using a switch in accordance with the binary number of bits of data. Further, the direction of the current flowing through each signal line of the signal line pair 7 is switched using a switch in accordance with the binary bit data. In the receiver 3, it is converted into binary plural bits of data according to the voltage level of the signal line pair 7 and output.

  In the embodiment of the present invention, the receiver 3 employs a configuration for identifying information using the differential amplifier as described above. However, the information is determined according to the voltage level using an AD converter. May be output.

  In the embodiment of the present invention, a circuit configuration using a constant voltage source is described. However, the circuit configuration is not necessarily limited to this, and a circuit configuration using a constant current source may be used.

  In the present embodiment, the configuration in which the input terminal on the + side of the differential amplifier 14 is connected to the vicinity of the middle of the impedance component of the resistance element 12 has been described. For example, it may be configured to connect to the node N2 or the node N4.

  In this example, a method of transmitting data by associating the four-state potentials of the signal lines 7a and 7b with binary 2-bit information is described, and the combination of the respective potential states and information. Can be set to any combination.

  In this embodiment, since the receiver can receive information of a plurality of bits using a pair of two signal lines, high-speed communication is possible. Further, as described above, the differential serial communication system is strong against the influence of external noise and has high noise resistance. Further, with respect to a pair of two signal lines, it is possible to make balanced differential lines in which the directions of the currents flowing in the signal lines are opposite to each other but the currents flowing are the same. In other words, signals of equal magnitude and opposite direction flow through each of the parallel signal lines, so that the concentric magnetic lines of force work in the direction to be canceled out, and the concentric electric lines of force work together, and as a result, It is possible to keep the electromagnetic field energy (ie noise) propagating to the very small. Therefore, it is possible to realize an information processing apparatus that can realize high-speed communication without increasing the number of signal lines in the communication path while suppressing the amount of noise generated during communication.

  In this example, the method of transmitting 2-bit information using one signal line pair has been described. However, it is also possible to transmit information of a plurality of bits using a plurality of signal line pairs. Is possible.

  In the information processing apparatus according to the embodiment of the present invention, the bit value can be expressed by switching the direction of the current flowing through each signal line of the pair of two signal lines. Therefore, twice as many bit values can be expressed as in the case where the bit value is expressed only by the amount of current. That is, even if the amount of current is halved, the same amount of bit values can be expressed. Therefore, since the current value can be reduced, the power consumption of the information processing apparatus can be reduced. In addition, since the configuration in which the direction of the current is switched can be realized by a cheaper circuit than the configuration in which the amount of current is switched to express the bit value, the cost of the information processing apparatus can be reduced.

  In FIG. 2, the case where the input signals from the logic circuits 11a and 11b and the input signals from the logic circuits 11c and 11d to the switch are input at the same timing has been described.

  On the other hand, the input timing may not be the same. That is, the switching timing between the switch SW6a and the switch SW6b in which the common voltage changes, the switching timing between the switches SW9a and SW9b and the switches SW10a and SW10b in which the potential difference (current direction) between the two signal lines is switched. It does not have to be simultaneous.

  FIG. 3 is another diagram illustrating the relationship between the potentials of signal lines 7a and 7b, the common voltage, and 2-bit information according to the embodiment of the present invention.

  Referring to FIG. 3, an example in which the common voltage switching time and the current path switching time are different from those in FIG. 2 is shown.

  Specifically, it is shown that the switching of the common voltage has a longer period than the switching time of the current path. In this example, the case where it switches to time t1, t3, t5, t7 is shown.

On the other hand, the current path is switched every predetermined time (for example, t1 to t2).
In this example, as an example, a case where information is transmitted in a period from time t1 to time t9 is shown.

  Specifically, within a predetermined time from time t1, the signal line 7a is at the voltage V1 level and the signal line 7b is at the voltage V3 level. Accordingly, 1-bit information represented by the two signal line potential difference is “1”.

  Next, within a predetermined time from time t2, the signal line 7a is at the voltage V3 level, and the signal line 7b is at the voltage V1 level. Therefore, 1-bit information represented by the two signal line potential difference is “0”.

  In the period from time t1 to time t3, the common voltage V2, which is an intermediate voltage between the signal line 7a and the signal line 7b, is higher than the common voltage threshold V4. Therefore, 1-bit information represented by the common potential difference between the common voltage V2 and the common threshold voltage V4 is “1”.

  Therefore, 3-bit information can be transmitted in the period from time t1 to time t3.

  Similarly, within a predetermined time from time t3, the signal line 7a is at the voltage V5 level, and the signal line 7b is at the voltage V7 level. Accordingly, 1-bit information represented by the two signal line potential difference is “1”.

  Here, since the signal line 7b transitions from the voltage V1 to the voltage V7, a case where a certain amount of time is required for the transition time of the voltage is shown, but the time between the time t3 and the time t4 is shown. In the period from t34 to time t4, a potential difference corresponding to the information is generated, so that it is possible to decode and output the information by taking in the signal during the period.

  Next, within a predetermined time from time t4, the signal line 7a is at the voltage V7 level, and the signal line 7b is at the voltage V5 level. Therefore, 1-bit information represented by the two signal line potential difference is “0”.

  In the period from time t3 to time t5, the common voltage V6 that is an intermediate voltage between the signal line 7a and the signal line 7b is at a voltage level lower than the common voltage threshold V4. Therefore, 1-bit information represented by the common potential difference between the common voltage V6 and the common threshold voltage V4 is “0”.

  Therefore, 3-bit information can be transmitted in the period from time t3 to t5.

The transmission of information after time t5 is performed in the same manner.
In this example, the information transmission period based on the comparison between the common voltage and the common threshold voltage is set to be long. It may take time until the voltage level of the signal line is changed from, for example, the voltage V1 to the voltage V7 to be in a stable state. That is, it may take time for the common voltage to stabilize. When information is transmitted every predetermined time, if the period of the predetermined time is short, it is necessary to set the voltage level at a high speed, but if the transition period is long, correct decoding that is information by comparison with the common threshold voltage I can't get results.

  Therefore, in this example, when information is transmitted according to the switching of the common voltage, the information is transmitted by securing a period twice as long as a predetermined period in order to stably transmit the information.

  In this example, it is possible to transmit information of 3 bits × 4 = 12 bits during the period from time t1 to time t9.

  In this example, since the switching period of the common voltage is longer than the switching period of the potential difference between a pair of signal lines, a differential serial communication environment with more stability and less noise is obtained.

  As described above, the information processing apparatus of the present invention provides an information processing apparatus that can realize high-speed communication without increasing the number of signal lines in the communication path while suppressing the amount of noise generated during communication. . Therefore, the present invention can be suitably used in an industrial field related to a portable device using a serial communication interface.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Information processing apparatus, 2 driver, 3 receiver, 4 constant voltage source, 5, 8, 12, 17 resistance element, 7 signal line pair, 7a, 7b signal line, 11a, 11b, 11c, 11d logic circuit, 13, 14 Differential amplifier, 15 decoder.

Claims (6)

A pair of signal lines composed of a set of two signal lines;
A driver connected to one end side of the signal line pair, and set to a voltage level corresponding to binary multiple bits of data input to the signal line pair;
A receiver that is connected to the other end of the signal line pair and converts the data into a plurality of binary bits according to the voltage level of the signal line pair;
The driver is
A constant voltage source for applying a voltage to the signal line pair;
An impedance adjustment unit for adjusting input / output impedance of the signal line pair according to the binary number of bits of data;
An information processing apparatus including: a switching unit that switches a direction of a current flowing through each signal line of the signal line pair in accordance with the binary plural-bit data. The impedance adjuster is
A first resistance element provided between the constant voltage source and a first internal node connected to one of the signal line pairs;
A first switch element provided between the constant voltage source and the first internal node and provided in parallel with the first resistance element;
A second resistance element provided between a fixed voltage and a second internal node connected to the other of the signal line pair;
A second switch element provided between the fixed voltage and the second internal node and provided in parallel with the second resistance element;
2. The information processing apparatus according to claim 1, wherein the first and second switch elements are complementarily turned on / off in accordance with a plurality of binary bits of data. The switching part
Third and fourth switch elements for connecting the first and second internal nodes to one and the other of the signal line pair, respectively, according to the binary number of bits of data;
According to the binary number of bits of data, the third and fourth switch elements operate in a complementary manner, and connect to the first and second internal nodes and the other and one of the signal line pairs, respectively. The information processing apparatus according to claim 2, further comprising: a fifth switching element and a sixth switching element.   The information processing apparatus according to claim 1, wherein the plurality of bits is 2 bits. The receiver is
A potential difference identifying unit that converts data into partial bits of the plurality of binary bits according to a potential difference between the signal lines of the signal line pair;
5. The information according to claim 1, further comprising: a common signal identification unit that converts data into the remaining bits of the plurality of binary bits according to an intermediate voltage level between the signal lines of the signal line pair. Processing equipment. A control method for an information processing apparatus for transmitting binary multi-bit data to a signal line pair composed of a pair of two signal lines,
Applying a voltage to the signal line pair;
Adjusting the input / output impedance of the signal line pair according to the binary number of bits of data;
Switching the direction of current flowing through each signal line of the signal line pair according to the binary number of bits of data;
A method of controlling the information processing apparatus, comprising: converting the data into binary binary data according to a voltage level of the signal line pair.

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