JP2013006465A - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the effect of the superimposed noise caused by the pulse output on the sampling of input signals in the electronic control device that obtains the input signal while outputting the pulse signal.SOLUTION: A microcomputer of an electronic control unit (ECU) includes: a first timer that generates a pulse output (a); and a second timer that generates the sampling timing of an input signal (b). When the sampling timing of the input signal agrees to the edge timing of the pulse output (c), and the input signal comes to strongly receive the superimposed noise. Then, the sampling timing of the input signal is adjusted by the first timer and the second timer not to agree to the edge timing of the pulse output (d). As a result, the effect of the superimposed noise exerts on the sampling of the input signal can be avoided.

Description

  The present invention relates to an electronic control device.

2. Description of the Related Art Conventionally, there is known an electronic control device that detects a failure in which an operation clock of a microcomputer (hereinafter referred to as “microcomputer” as appropriate) is abnormal and improves the reliability of the system. For example, Patent Document 1 discloses a “clock monitoring” method in which a signal synchronized with an operation clock is output from a microcomputer, and this is monitored by a microcomputer operating with another clock.
However, it is well known that high-frequency digital signals such as operation clocks generally superimpose pulsed noise on an input signal mounted in the vicinity thereof.

  Therefore, various methods have been proposed to reduce the influence of such superimposed noise. For example, the sampled input signal is smoothed by calculation using software. Alternatively, the high level digital output signal line and other signal lines are separately mounted to reduce the noise superposition level. Further, the noise detection device disclosed in Patent Document 2 includes a noise detection circuit that detects pulse noise included in an input signal, and removes the pulse noise during a period in which noise is detected by the noise detection circuit. .

JP 2009-202612 A JP 2008-277969 A

  However, with the above-described method, smoothing by software calculation has a problem of reducing the responsiveness of the signal and causing compression of the processing capacity of the microcomputer and the ROM / RAM used for the calculation. Further, the separate mounting of the signal lines can be a factor that hinders downsizing of the electronic control device because it deprives the freedom of layout. Furthermore, the noise removing device of Patent Document 2 has a problem of increasing the cost because a noise detection circuit is provided.

  The present invention was created in view of the above points, and its purpose is to superimpose noise generated by pulse output in sampling of the input signal in an electronic control device that acquires the input signal while outputting the pulse signal. It is to avoid the effect.

According to another aspect of the present invention, an electronic control device includes a microcomputer, an output signal line that transmits a pulse signal output from the microcomputer, and an input signal line that transmits an input signal to the microcomputer.
The microcomputer generates first timing generation means for generating edge timing which is periodic “rise and fall timing” of the pulse signal, and first sampling timing for periodically acquiring the value of the input signal. 2 timing generating means. The first timing generation unit and the second timing generation unit execute timing mismatch processing that causes a time difference between the edge timing of the pulse signal and the sampling timing of the input signal.

By this timing mismatch processing, the edge timing of the pulse signal and the sampling timing of the input signal are intentionally shifted, so that the influence of superimposed noise caused by the pulse output can be avoided in the sampling of the input signal.
This process can be realized with almost no pressure on the processing capacity of the microcomputer and the ROM / RAM. In addition, since it is not necessary to add a new circuit or smooth the signal, there is no increase in cost due to an increase in elements and a decrease in signal response. Further, since the output signal line and the input signal line are not separately mounted, the electronic control device is not hindered in size reduction.

In the electronic control device according to claim 2, after the output of the pulse signal is started by the first timing generation unit and the processing by the pulse signal is executed, the second timing generation unit “before starting the sampling of the input signal” The timing mismatch process is executed.
As described above, once arbitrary processing using the pulse signal is executed, the edge timing of the pulse signal is not determined to be “static” from the known information in the subsequent processing. Therefore, in the invention according to claim 2, “dynamic timing mismatch processing” is executed from “a state in which the temporal relationship between the already output edge timing and the sampling timing to be generated is unknown”. To do.
Here, “before starting” means, for example, a time in the order of “μs”, and practically means as close as possible to “at the same time as starting”.

The inventions according to claims 3 to 5 specifically show “dynamic timing mismatch processing” according to claim 2.
According to the third aspect of the present invention, the timer value output from the first timing generation means is rewritten to a predetermined value corresponding to the sampling timing of the input signal.
Here, the “predetermined value” is a time difference value corresponding to, for example, (1/4) of the pulse period. Thereby, simultaneously with the start of sampling of the input signal, the pulse signal is rewritten as a signal whose edge timing is advanced by 1/4 of the pulse period with respect to the sampling timing. That is, the sampling timing is generated at “a timing between a certain rising timing and the next falling timing” or “a timing between a certain falling timing and the next rising timing” of the pulse signal. . This process is called “rewritable process”.

  In “rewritable processing”, the second timing generation means does not change the timing generated by itself, but changes only the timing of the first timing generation means that is the counterpart. In addition, when changing the timing of the first timing generation means, it is always rewritten uniformly to a predetermined “predetermined value” regardless of the current value of the first timing generation means, so that the calculation load can be reduced. it can. Furthermore, unlike the “stand-by process” described later, the start of sampling of the input signal is not delayed, so that a quick process is possible.

According to the fourth aspect of the present invention, the second timing generation unit is activated after the timer value output from the first timing generation unit reaches a predetermined value.
Here, as the “predetermined value”, for example, the same value as the “predetermined value” described in claim 3, that is, a value corresponding to (1/4) of the pulse period can be adopted. As a result, after waiting for the edge timing of the pulse signal to deviate by a predetermined value, the second timing generation means starts generating the sampling timing. This processing is called “standby processing”.
In the “standby processing”, stable pulse output can be continued without changing the pulse signal already output. In addition, the calculation of the microcomputer is simplified.

According to the fifth aspect of the present invention, the second timing generation unit changes the sampling cycle of a specific number of times to a predetermined cycle based on the current value of the timer value output from the first timing generation unit. Here, “specific times” is, for example, a cycle of the first activation. The second timing generation means acquires the current value of the edge timing, and based on this, changes the sampling timing period only for the first time of activation, thereby shifting the second and subsequent sampling timings with respect to the edge timing. This process is referred to as “cycle change type process”.
In the “cycle changing type process”, the second timing generation unit calculates the cycle of the sampling timing “specific times” based on the current value of the edge timing generated by the first timing generation unit. Since the pulse signal that has already been output is not changed, stable pulse output can be continued.

In the electronic control device according to claim 6, after the output of the pulse signal is started by the first timing generation unit and the processing by the pulse signal is executed, the second timing generation unit further “starts sampling of the input signal After, timing mismatch processing is executed.
That is, the present invention is the same as that of the second aspect in that dynamic processing is performed. However, the sampling timing has already been output when the processing is executed, and the roles of the first timing generation means and the second timing generation means are reversed with respect to the invention according to claim 2.
Therefore, the invention according to claim 6 performs “dynamic timing mismatch processing” from “a state in which the temporal relationship between the sampling timing already output and the edge timing to be generated again is unknown”. Execute. Here, “after starting” means, for example, a time in the order of “μs”, and practically means “as soon as starting”.

The inventions according to claims 7 to 9 respectively correspond to the inventions according to claims 3 to 5, and specifically show “dynamic timing mismatch processing” according to claim 6.
In the seventh aspect of the invention, the timer value output from the second timing generation means is rewritten to a predetermined value corresponding to the edge timing of the pulse signal.
In the eighth aspect of the invention, the first timing generation means waits until the timer value output from the second timing generation means reaches a predetermined value and outputs it.
In the ninth aspect of the invention, the first timing generation unit changes the pulse cycle of a specific number of times to a predetermined cycle based on the current value of the timer value output from the second timing generation unit.
The technical features of these inventions are the same as those of the inventions described in claims 3-5.

  As described above, the electronic control device according to claims 2 to 9 executes “dynamic timing mismatch processing”, whereas the electronic control device according to claim 10 executes “static timing mismatch processing”. To do. That is, the first timing generation means and the second timing generation means are activated by shifting the edge timing of the pulse signal and the sampling timing of the input signal by a predetermined time in advance. As described above, the electronic control device of the present invention can be applied to both dynamic processing and static processing.

  According to an eleventh aspect of the present invention, in the electronic control device according to the first aspect, the sampling timing generated by the second timing generation means acquires the value of the input signal “periodically” with respect to the electronic control device according to the first aspect. Rather, it is for acquiring the value of the input signal “every time”.

In the timing mismatch processing in this case, in the invention described in claim 12, after the sampling timing is generated by the second timing generation unit, the timer value output from the first timing generation unit waits for a predetermined value. To get the value of the input signal. Here, the concept of “predetermined value” is in accordance with the third or fourth aspect described above.
As described above, the effect of “avoiding the influence of the superimposed noise caused by the pulse output” is similarly exerted even when the sampling of the input signal is not performed periodically but is performed each time.

The schematic block diagram of the electric power steering device to which ECU (electronic control unit) by 1st-3rd embodiment of this invention is applied. The system diagram of ECU by the 1st-3rd embodiment of the present invention. (A) Pulse output signal, (b) Waveform diagram of input signal. The timing chart explaining the sampling timing of ECU by the 1st-3rd embodiment of the present invention. The flowchart of the timing mismatch processing of ECU by 1st Embodiment of this invention. The flowchart of the timing mismatch processing of ECU by 2nd Embodiment of this invention. The flowchart of the timing mismatch processing of ECU by 3rd Embodiment of this invention. The timing chart explaining the sampling timing of ECU by 4th Embodiment of this invention.

An embodiment in which an electronic control device (hereinafter referred to as “ECU”) of the present invention is applied to an electric power steering device for assisting steering operation of an automobile or the like will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows the overall configuration of a steering system provided with an electric power steering device. In the electric power steering apparatus 1 provided in the steering system 90, a torque sensor 94 for detecting a steering torque is installed on a steering shaft 92 connected to a handle 91. A pinion gear 96 is provided at the tip of the steering shaft 92, and the pinion gear 96 meshes with the rack shaft 97. A pair of wheels 98 are rotatably connected to both ends of the rack shaft 97 via tie rods or the like.

  As a result, when the driver rotates the handle 91, the steering shaft 92 connected to the handle 91 rotates, and the rotational motion of the steering shaft 92 is converted into the linear motion of the rack shaft 97 by the pinion gear 96. The pair of wheels 98 are steered at an angle corresponding to 97 linear motion displacement.

The electric power steering apparatus 1 includes a motor 80 that generates a steering assist torque, a reduction gear 89 that reduces the rotation of the motor 80 and transmits the rotation to the steering shaft 92, and the motor driving apparatus 2. The motor 80 is a three-phase brushless motor, and rotates the reduction gear 89 forward and backward. The motor drive device 2 includes an ECU 10. The motor drive device 2 also includes a rotation angle sensor 85 that detects the rotation angle of the motor 80, the above-described torque sensor 94, and a vehicle speed sensor 95 that detects the vehicle speed.
With this configuration, the electric power steering apparatus 1 generates a steering assist torque for assisting the steering of the handle 91 and transmits the steering assist torque to the steering shaft 92.

  FIG. 2 shows a schematic system diagram of the ECU. The ECU 10 includes a microcomputer 11, a clock monitoring circuit 31, a drive circuit 32, and the like. The microcomputer 11 executes a program based on the signals input from the rotation angle sensor 85, the torque sensor 94, the vehicle speed sensor 95, and the like, and controls the drive circuit 32 for driving the motor 80. An input signal is input from the drive circuit 32 to the microcomputer 11 via the input signal line 22.

  The microcomputer 11 outputs a pulse signal synchronized with the operation clock to the clock monitoring circuit 31 via the output signal line 21. The clock monitoring circuit 31 monitors whether the operation clock of the microcomputer 11 is normal based on the pulse signal output from the microcomputer 11. This pulse signal is a high-frequency digital signal.

  The microcomputer 11 includes a CPU (central processing unit) 12 that executes a program, a ROM 13 that stores a program executed by the CPU 12, a RAM 14 that stores calculation results by the CPU 12, and an input circuit 17 that receives input signals. In addition, a first timer 15 and a second timer 16 are provided. These components are in communication with each other via a bus line 19.

The first timer 15 as “first timing generation means” corresponds to the “rising and falling timing” at which the pulse period of the pulse signal output to the clock monitoring circuit 31, that is, the HI / LO of the signal is periodically switched. Edge timing is generated.
The second timer 16 as “second timing generation means” generates a sampling timing for periodically acquiring the value of the input signal input to the input circuit 17.

Here, since the input signal line 22 and the output signal line 21 are mounted close to each other in the vicinity of the microcomputer 11, it is inevitable that pulse noise is superimposed on the input signal from the pulse signal that is a high-frequency digital signal. . As shown in FIG. 3 and FIGS. 4A and 4B, the superimposed noise occurs particularly at the edge timing of the pulse signal.
In FIG. 3B and FIG. 4B, the input signal is exemplified as a sine wave signal. However, the input signal is not limited to this, and the input signal may be a signal having any waveform.

If the sampling timing of the input signal coincides with the edge timing of the pulse signal as in the comparative example shown in FIG. 4C, the input signal is strongly affected by the superimposed noise. On the other hand, in this embodiment shown in FIG. 4D, the sampling timing of the input signal does not coincide with the edge timing of the pulse signal, so that the influence of the superimposed noise can be avoided. In other words, unlike the noise from a general noise source, the superimposed noise can be avoided by adjusting the timing.
In the present embodiment, the sampling period Ts is set to twice the pulse period Tp. This technical significance will be described in comparison with the fourth embodiment.

In this way, the ECU 10 executes a process of intentionally shifting the edge timing of the pulse signal generated by the first timer 15 and the sampling timing of the input signal generated by the second timer 16. This process is called “timing mismatch process”.
Next, the flow of the timing mismatch process of the first embodiment will be described with reference to the flowchart of FIG. In the description of the flowchart below, the symbol S indicates “step”.

In S1, the first timer 15 is activated to start outputting a pulse signal. In the subsequent S2, an arbitrary “processing X” is executed. The process X is a process such as device initialization.
In S31 after execution of process X, the microcomputer 11 rewrites the counter value of the first timer 15 to a predetermined value K, and in S4, the second timer 16 starts to start and starts sampling of the input signal. Hereinafter, the processing of the present embodiment is referred to as “rewritable processing”.
Here, the “counter value” is a value correlated with the “timer value” recited in the claims. That is, the “timer value” may be directly rewritten, or the “timer value” may be rewritten indirectly by rewriting the “counter value”.

The “value K” means a “time difference value” in which the edge timing of the pulse signal precedes the sampling timing of the input signal. In other words, sampling is performed at the time when the time corresponding to the value K has elapsed from the edge timing.
By the way, since one edge of the pulse period includes two edge timings of rising edge and falling edge, the edge timing period is represented by half of the pulse period (Tp / 2). Therefore, the value K is not 0 (K ≠ 0) and is different from “N × (Tp / 2) (N is a natural number) as shown in the following formula 1 (preferably a value that is not approximated as much as possible). ) ”, It is possible to avoid the coincidence between the edge timing and the sampling timing.
K ≠ ± N × (Tp / 2) = ± Tp / 2, ± Tp, ± 3 Tp / 2, ± 2 Tp
... (Formula 1)
Specifically, the value K may be set to “0.25 Tp”, for example. Alternatively, the value K is set to “0.25 Tp” as an “intermediate value” and has a predetermined width (in this example, “± 0.1 Tp”) within a range that is not affected by the superimposed noise. Can be set as follows.
0.15 Tp ≦ K ≦ 0.35 Tp (Formula 2)

  In this flow, the process X is executed halfway (S2), so that the current value of the counter value of the first timer 15 is not statically determined when the second timer 16 is activated. Therefore, it is necessary to adjust the temporal relationship between the first timer 15 and the second timer 16 to “dynamic” to avoid the coincidence between the edge timing and the sampling timing. Thereby, in the sampling of the input signal, it is possible to avoid the influence of the superimposed noise caused by the pulse output.

  In particular, in the “rewritable processing” of the present embodiment, the timing of the second timer 16 itself is not changed, but only the timing of the counterpart first timer 15 is changed. Further, when the timing of the first timer 15 is changed, regardless of the current value of the first timer 15, it is always rewritten uniformly to a predetermined value K, so that the calculation load can be reduced. Furthermore, unlike the “stand-by process” described later, the start of sampling of the input signal is not delayed, so that a quick process is possible.

(Second and third embodiments)
Other forms of timing mismatch processing will be described as second and third embodiments. In the following embodiment, the system configuration (see FIG. 2) of the ECU 10 is the same as that of the first embodiment.
In the first embodiment, the timing of the first timer 15 as the counterpart is changed without changing the timing of the second timer 16 itself. On the other hand, the second and third embodiments are characterized in that the timing of the second timer 16 itself is changed.

  The flow of the timing mismatch process of the second embodiment will be described with reference to the flowchart of FIG. Here, substantially the same steps as those in the first embodiment are denoted by the same step symbols. As shown in FIG. 6, S1, S2, and S4 are substantially the same as those in the first embodiment (FIG. 5), and only “S32” after execution of the process X (S2) is “ Different from S31 ".

In S32, the microcomputer 11 determines whether or not the counter value of the first timer 15 is a predetermined value K. If YES, the process proceeds to the next S4. If NO, the process returns to before S32 and the determination of S32 is performed again. That is, after the counter value of the first timer 15 reaches the predetermined value K, the process proceeds to S4. Hereinafter, the processing of this embodiment is referred to as “standby processing”.
The “counter value” is a value correlated with the “timer value”, as in the first embodiment.
In the “standby processing”, stable pulse output can be continued without changing the pulse signal already output. Further, the calculation of the microcomputer 11 is simplified.

The flow of the timing mismatch process of the third embodiment will be described with reference to the flowchart of FIG. Here, S1, S2, and S4 are substantially the same as those in the first and second embodiments, and only “S33” after execution of process X (S2) is different from that in the first and second embodiments. .
In S <b> 33, the microcomputer 11 acquires the counter current value Vp of the first timer 15. Then, based on the acquired current value Vp, the second timer 16 is activated while changing the sampling cycle of a specific number of times so as to shift the edge timing and the sampling timing (S4). “Changing the sampling cycle at a specific time” means, for example, changing the sampling cycle specially with respect to the normal cycle only in the first cycle of activation. Hereinafter, the processing according to the present embodiment is referred to as “period change processing”.
In the “cycle change type process”, the first sampling timing is determined by calculation based on the acquired counter current value Vp. Since the pulse signal that has already been output is not changed, stable pulse output can be continued.

(Fourth embodiment)
Next, the relationship between the pulse period Tp and the sampling period Ts will be described.
As shown in FIG. 4C, in the first embodiment, the sampling period Ts is set to twice the pulse period Tp. When N is a natural number, when the sampling period Ts is N times the pulse period Tp, the time difference (K value) from the edge timing of the pulse rise is constant at each sampling timing.

  Further, even when the sampling period Ts is (N / 2) times the pulse period Tp, the time difference (K value) from the rising edge or falling edge timing is alternately constant at each sampling timing. .

  In other words, “the sampling period Ts is (N / 2) times the pulse period Tp” is “the sampling period Ts is (N / 1) times half the pulse period (Tp / 2)”. Here, “N times” means “(N / 1) times” in order to emphasize that the denominator of the multiple is “1”. When the denominator of the multiple is “1”, as described above, the value K is set to “(1/4) Tp”, that is, “0.25 Tp”, or “0.25 Tp” is set as an intermediate value. If the value is set within this range, the time difference from the edge timing can be maintained substantially constant at each sampling timing, and timing coincidence can be avoided.

On the other hand, in the comparative example shown in FIG. 8C and the fourth embodiment shown in FIG. 8D, the sampling period Ts is 1.25 times the pulse period Tp, in other words, “half the pulse period ( It is set to (5/2) times Tp / 2). That is, the denominator of the multiple is “2”.
In this case, if the value K is set to “(1/8) Tp”, that is, “0.125 Tp”, or is set to a value in a predetermined range with “0.125 Tp” as an intermediate value, the sampling timing of each time Thus, it is possible to avoid the coincidence with the edge timing.

Generalizing the above contents, if Q is a rational number represented by Q = N / M (N and M are natural numbers and N / M is an irreducible fraction), the sampling period Ts is half the pulse period ( In the case of Q times Tp / 2), the following equation 3 is satisfied, which is a sufficient condition for avoiding coincidence with the edge timing.
K = (1 / 4M) Tp (Formula 3)

That is, the timing mismatch processing according to the above embodiment is theoretically applicable as long as the sampling period Ts is set to a rational multiple of the pulse period Tp. In other words, the case where the timing mismatch processing according to the above embodiment cannot be applied means that the sampling period Ts is set to an irrational multiple of the pulse period Tp. However, setting an irrational period is not practical.
Therefore, if the sampling period Ts and the pulse period Tp do not vary and are constant, the timing mismatch processing according to the above embodiment can be applied to virtually any case.

As described above, as described in the plurality of embodiments, the edge timing of the pulse signal output from the microcomputer 11 after executing “Process X” can be known by examining the counter value of the first timer 15. Then, it is easy to dynamically adjust the edge timing and the sampling timing, which can be realized with almost no pressure on the processing capacity of the microcomputer 11 and the ROM 13 / RAM 14.
In addition, since it is not necessary to add a new circuit or smooth the signal, there is no increase in cost due to an increase in elements and a decrease in signal response. Further, since the output signal line 21 and the input signal line 22 are not separately mounted, the ECU 10 is not hindered in size reduction.

  In particular, when the pulse output is a fixed duty output such as a clock signal and the sampling timing of the input signal is also periodically generated by the second timer 16, the above timing mismatch processing is performed only once at system startup. Just do it. Therefore, the present invention is extremely effective as a technique for reducing the influence of noise while suppressing the steady processing capability of the microcomputer 11.

(Other embodiments)
(A) In any of the first to third embodiments, the first timer 15 starts outputting the pulse signal, and after the “process X” is executed, the second timer 16 for sampling the input signal is provided. The timing mismatch process in the scene to start is shown (refer FIGS. 5-7). In other words, the second timer 16 is the main subject, and the processing executed by the second timer 16 that starts late with respect to the edge timing generated by the preceding first timer 15 is targeted.

  On the other hand, in another embodiment, the first timer 15 may be the main body, and the first timer 15 may perform the same timing mismatch process according to the sampling timing of the already operating second timer 16. Specifically, the timing mismatch processing of the following first to third modifications can be given corresponding to the first to third embodiments.

(First modification)
The counter value output from the second timer 16 is rewritten to a predetermined value corresponding to the edge timing of the pulse signal (rewritable processing).
(Second modification)
The first timer 15 waits for the counter value output from the second timer 16 to reach a predetermined value and outputs it (standby processing).
(Third Modification)
The first timer 15 changes the period of a specific number of pulse outputs (for example, the first activation) based on the current counter value output from the second timer 16 to a predetermined period (period change type process).

  (A) When “Processing X” in the above embodiment is not executed, the first timer 15 and the second timer 16 are started by shifting the edge timing of the pulse signal and the sampling timing of the input signal by a predetermined time in advance. May be. In this case, the edge timing of the pulse signal and the sampling timing of the input signal are adjusted to “static”.

(C) The pulse output signal is not limited to the signal used for clock monitoring exemplified in the above embodiment, and may be a signal used for communication with other ECUs, for example.
(D) The input signal is not limited to being input from the inside of the ECU 10 (in the above embodiment, the drive circuit 32), but may be input from the outside of the ECU 10.
(E) The first timing generation means and the second timing generation means do not necessarily need to be composed of two physically independent timer elements like the “first timer 15 and the second timer 16”. One timer element may have the functions of two timing generation means.
Further, the CPU 12 may function as a timing generation unit.

(F) In the above embodiment, the sampling of the input signal is periodically executed. In this case, if the timing mismatch processing is executed once at the start of sampling, the superimposed noise is continuously avoided as long as the pulse output is continued at a constant pulse period Tp.
On the other hand, the sampling of the input signal is not periodic and may be executed each time. In this case, the second timer 16 executes timing mismatch processing each time sampling is performed. As a specific example, after the sampling timing is generated by the second timer 16, the value of the input signal is acquired after waiting for the counter value output from the first timer 15 to become a predetermined value.
As described above, even when the sampling of the input signal is executed each time, the effect of “avoiding the influence of the superimposed noise caused by the pulse output” is similarly exhibited.

(G) The electronic control device of the present invention can be applied to various applications such as VGRS (variable gear ratio steering) and ARS (active rear steering) in addition to the electric power steering device.
As mentioned above, this invention is not limited to such embodiment, In the range which does not deviate from the meaning of invention, it can implement with a various form.

1 ... Electric power steering device,
10: ECU (electronic control unit),
11 ... microcomputer (microcomputer),
15 ... 1st timer (1st timing production | generation means),
16 ... 2nd timer (2nd timing production | generation means),
21 ... Output signal line,
22 ・ ・ ・ Input signal line,
Tp ... pulse period,
Ts: Sampling cycle.

Claims (12)

A microcomputer,
An output signal line for transmitting a pulse signal output from the microcomputer;
An input signal line for transmitting an input signal to the microcomputer,
The microcomputer generates first timing generation means for generating edge timings that are periodic rising and falling timings of the pulse signal, and sampling timing for periodically acquiring the value of the input signal. Having a second timing generation means;
The electronic control device, wherein the first timing generation unit and the second timing generation unit execute timing mismatch processing that causes a time difference between an edge timing of the pulse signal and a sampling timing of the input signal.   After the output of the pulse signal is started by the first timing generation means and the processing by the pulse signal is executed, the timing mismatch processing is executed before the second timing generation means starts sampling of the input signal The electronic control device according to claim 1.   3. The electronic control device according to claim 2, wherein, in the timing mismatch processing, the timer value output from the first timing generation unit is rewritten to a predetermined value corresponding to the sampling timing of the input signal.   3. The electronic control according to claim 2, wherein, in the timing mismatch processing, the second timing generation unit is activated after the timer value output from the first timing generation unit reaches a predetermined value. apparatus.   In the timing mismatch processing, the second timing generation unit changes a sampling cycle of a specific number of times to a predetermined cycle based on a current value of a timer value output from the first timing generation unit. Item 3. The electronic control device according to Item 2.   After the output of the pulse signal is started by the first timing generation means and the processing by the pulse signal is executed, the timing mismatch processing is executed after the second timing generation means starts sampling of the input signal The electronic control device according to claim 1.   The electronic control device according to claim 6, wherein in the timing mismatch processing, the timer value output from the second timing generation unit is rewritten to a predetermined value corresponding to an edge timing of the pulse signal.   7. The electronic control according to claim 6, wherein, in the timing mismatch processing, the first timing generation unit waits until the timer value output from the second timing generation unit reaches a predetermined value. apparatus.   In the timing mismatch processing, the first timing generation unit changes a pulse cycle of a specific number of times to a predetermined cycle based on a current value of a timer value output from the second timing generation unit. Item 7. The electronic control device according to Item 6.   The first timing generation unit and the second timing generation unit are started by shifting the edge timing of the pulse signal and the sampling timing of the input signal by a predetermined time in advance. Electronic control unit. A microcomputer,
An output signal line for transmitting a pulse signal output from the microcomputer;
An input signal line for transmitting an input signal to the microcomputer,
The microcomputer generates first timing generation means for generating edge timings that are periodic rising and falling timings of the pulse signal, and second sampling timing for acquiring the value of the input signal each time. Having timing generation means;
The electronic control device, wherein the first timing generation unit and the second timing generation unit execute timing mismatch processing that causes a time difference between an edge timing of the pulse signal and a sampling timing of the input signal.   In the timing mismatch processing, after the sampling timing is generated by the second timing generation unit, the value of the input signal is obtained after the timer value output from the first timing generation unit reaches a predetermined value. The electronic control device according to claim 11.

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