JP2013004842A - Variable capacitance device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable capacitance device capable of obtaining three or more capacitance values as well as reducing the size of the device and signal loss.SOLUTION: A drive capacitance C1 of a variable capacitance element 2 changes according to drive voltage Vd output from a drive voltage control circuit 31. The drive voltage control circuit 31 comprises a comparator 32 which compares a detection value and a target value of the drive capacitance C1; and a drive voltage generating circuit 34 which generates a drive voltage Vd according to the comparison result of the comparator 32. A current output type level conversion circuit 35 of the drive voltage generating circuit 34 causes a source current i10 or a sink current i20 to flow to a smoothing capacitance 45 according to the comparison result of the comparator 32 and steps up or down the drive voltage Vd. The current output type level conversion circuit 35 gradually reduces a current value of the source current i10 or the sink current i20 when shifting from a transient state to a steady state.

Description

  The present invention relates to a variable capacitance device including a variable capacitance element whose capacitance changes according to a driving voltage.

  In general, when using a variable capacitance element in a matching circuit for high frequency communication, it is better to obtain as many capacitance values as possible in order to widen the matching range or improve the capacitance setting resolution for matching. Good. Here, in order to obtain three or more capacitance values, it is necessary to connect a plurality of binary variable capacitance elements in parallel or to obtain a structure in which three or more capacitance values are obtained with one variable capacitance element. . For example, Patent Document 1 discloses a variable capacitance element that switches between two capacitance values. In such a variable capacitance element, the counter electrodes are brought into contact with or separated from each other via a dielectric layer by applying a driving voltage.

JP 2009-70940 A

  By the way, in order to obtain a large number of capacitance values using the variable capacitance element according to Patent Document 1, it is necessary to form a large number of variable capacitance elements and to form a connection pattern for connecting them, and the entire apparatus is There is a tendency to increase in size. In addition, there is a problem that signal loss due to the connection pattern becomes a value that cannot be ignored.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a variable capacitance device capable of obtaining three or more capacitance values and miniaturizing the device and reducing signal loss. It is in.

  In order to solve the above-mentioned problem, the invention of claim 1 is a variable capacitance element whose capacitance changes according to a drive voltage, a capacitance detection circuit for detecting the capacitance of the variable capacitance device, and the capacitance detection. And a drive voltage control circuit for controlling the drive voltage so that a detected value of capacitance by the circuit approaches a desired target value. The drive voltage control circuit includes the detected value of the capacitance. And a target value, a current output type level conversion circuit for supplying a source current or a sink current according to the comparison result of the comparator, and when the current output type level conversion circuit supplies a source current A current-voltage conversion circuit comprising a smoothing capacitor that boosts the drive voltage and reduces the drive voltage when a sink current flows, and the current output type level conversion circuit shifts from a transient state to a steady state. It is characterized in that a configuration in which gradually reduce the current value of the source current and sink current.

  According to a second aspect of the present invention, the drive voltage control circuit includes a counter circuit that counts switching of the comparison result of the comparator, and the counter circuit resets the drive voltage when the count number is reset by a reset signal. The current value of the control voltage is set to the magnitude of the transient state, and the current value of the drive voltage control circuit is reduced by decreasing the current value of the drive voltage control circuit every time the comparison result is counted. It is configured to converge to a steady state size smaller than the transient state size.

  According to a third aspect of the present invention, the current output type level conversion circuit includes a variable current source whose current value is set by the counter circuit, a current mirror circuit that copies a current flowing through the variable current source, and a comparator. According to the comparison result, either a source current circuit or a sink current circuit is operated, and a current output circuit for supplying a source current or a sink current corresponding to a current flowing through the current mirror circuit is provided.

  According to the first aspect of the present invention, the capacitance of the variable capacitance element can be continuously changed according to the driving voltage, and three or more capacitance values can be obtained. Further, it is not necessary to connect a plurality of variable capacitance elements, and signal loss can be reduced. Furthermore, since a source current or a sink current is caused to flow by a current output type level conversion circuit, and a drive voltage is changed by the source current and the sink current, as a general drive voltage generation means, for example, a voltage level conversion circuit, Compared with the case where the drive voltage is generated by a low-pass filter circuit composed of a resistor and a capacitor, the resistance of the low-pass filter circuit becomes unnecessary, and the entire apparatus can be miniaturized.

  Further, the current output type level conversion circuit is configured to gradually reduce the current values of the source current and the sink current when shifting from the transient state to the steady state. For this reason, in the transient state, the current values of the source current and the sink current can be increased to increase the charge amount and the discharge amount of the smoothing capacitor. As a result, the capacitance of the variable capacitance element can be quickly brought close to the target value, and the stabilization time until the capacitance converges to the target value can be shortened. On the other hand, when shifting from the transient state to the steady state, the current values of the source current and the sink current can be gradually reduced to reduce the charge amount and the discharge amount of the smoothing capacitor. As a result, in the steady state, the current values of the source current and the sink current can be reduced to reduce the variation in capacitance with respect to the target value, and the capacitance accuracy can be improved.

  In the invention according to claim 2, when the count number is reset by the reset signal, the counter circuit sets the current value of the current output type level conversion circuit to the magnitude of the transient state. For this reason, immediately after the count number is reset, the current values of the source current and the sink current can be increased, and the detection value of the capacitance can be quickly changed toward the target value.

  Further, the counter circuit can gradually reduce the current values of the source current and the sink current each time the comparison result is switched, thereby gradually reducing the fluctuation range of the capacitance with respect to the target value. Finally, since the current values of the source current and the sink current are converged to the steady state magnitude smaller than the magnitude of the transient state, the current values of the source current and the sink current are reduced in the steady state, and the target value is reduced. The variation in capacitance can be reduced, and the capacitance accuracy can be increased.

  According to a third aspect of the present invention, the current output type level conversion circuit includes a variable current source, a current mirror circuit, and a current output circuit. Therefore, the current value of the variable current source can be set by the counter circuit, and the current flowing through the variable current source can be copied by the current mirror circuit. Since the current output circuit operates either the source current circuit or the sink current circuit according to the comparison result of the comparator, the source current corresponding to the current flowing through the current mirror circuit during the operation of the source current circuit. When the sink current circuit is in operation, a sink current corresponding to the current flowing through the current mirror circuit can be passed.

1 is an overall configuration diagram showing a variable capacitance device according to an embodiment of the present invention. It is a top view which shows the variable capacitance element in FIG. FIG. 3 is a cross-sectional view of the variable capacitor when viewed from the direction of arrows III-III in FIG. FIG. 2 is a circuit diagram showing a drive voltage generation circuit in FIG. 1. FIG. 10 is a characteristic diagram showing temporal changes in drive capacity, drive voltage, comparison result signal, and current control signal when the capacitance value of the drive capacity at the start of setting is smaller than the target value. FIG. 6 is a characteristic diagram showing temporal changes in drive capacity, drive voltage, comparison result signal, and current control signal when the capacitance value of the drive capacity at the start of setting is larger than the target value.

  Hereinafter, a variable capacity device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a variable capacitance device 1 according to an embodiment. The variable capacitance device 1 includes a variable capacitance element 2, a capacitance detection circuit 21, and a drive voltage control circuit 31.

  First, the variable capacitance element 2 will be described with reference to FIGS. 2 and 3.

  The variable capacitance element 2 is configured by MEMS (Micro Electro Mechanical Systems) driven by electrostatic force. The variable capacitance element 2 includes a substrate 3, lower drive electrodes 4A, 4B, and 5, a dielectric film 6, a beam portion 7, pad electrodes 8, 9A, 9B, 10A, and 10B, and resistance patterns 10C and 10D.

  The substrate 3 is made of, for example, a rectangular glass substrate. The beam portion 7 is formed in a rectangular flat plate shape in a plan view and an L shape in a side view. The beam portion 7 is a movable structure having a cantilever structure (spring structure) in which the right end portion in FIG. 2 is a support portion joined to the substrate 3 and the main portion is supported while being separated from the substrate 3. Part. The beam portion 7 is made of, for example, a low-resistance Si substrate (silicon substrate) having a resistivity of 0.01 Ωcm or less as a conductive substrate, and uses, for example, P (phosphorus), As (arsenic), B (boron), or the like as a dopant. ing.

  The lower drive electrodes 4A and 4B are each L-shaped and formed on the upper surface of the substrate 3, and have long line-shaped end portions along the axial direction of the beam portion 7 (left and right directions in FIG. 2). . The lower drive electrode 5 is formed in a U-shape on the upper surface of the substrate 3, and is arranged so that both sides of the lower drive electrodes 4A and 4B are sandwiched between both ends of a line shape that is long along the axial direction of the beam portion 7. To do. The dielectric film 6 is formed of, for example, a rectangular tantalum pentoxide having a thickness of about 200 nm, and is laminated on the substrate 3 so as to cover the end portions of the lower drive electrodes 4A and 4B and the both end portions of the lower drive electrode 5. The lower drive electrode 4A is connected to an input terminal (or output terminal) of an RF signal (high frequency signal) via a pad electrode 9A, and the lower drive electrode 4B is connected to an output terminal (or input terminal) of the RF signal. Connected through. The lower drive electrode 5 is connected to an input terminal of a DC voltage (DC voltage) that becomes the drive voltage Vd via the pad electrode 10A and the resistance pattern 10C. The beam portion 7 is connected to the ground via the pad electrodes 8 and 10B and the resistance pattern 10D. The resistance patterns 10C and 10D are formed using, for example, a titanium oxide thin film having a thickness of about 5 nm and have a resistance of about 200 kΩ.

  Both end portions of the lower drive electrode 5 are arranged to face the beam portion 7 with the dielectric film 6 therebetween, and the lower drive electrode 5 and the beam portion 7 constitute a drive capacitor portion 11. When the drive voltage Vd is applied from the drive voltage control circuit 31, the drive capacity unit 11 generates a drive capacity C 1 (electrostatic capacity) between both ends of the lower drive electrode 5 and the beam part 7. The drive capacitor C1 deforms the beam portion 7 by electrostatic attraction and brings the beam portion 7 into contact with the dielectric film 6 from the tip. The higher the driving voltage Vd, the larger the contact area between the beam portion 7 and the dielectric film 6.

  The lower drive electrodes 4A and 4B are arranged to face the beam portion 7 with the dielectric film 6 therebetween, and the lower drive electrodes 4A and 4B and the beam portion 7 constitute a variable capacitance unit 12. The variable capacitance unit 12 is used in a circuit that handles radio frequencies of, for example, several hundred MHz to several GHz, and varies according to the contact area between the beam portion 7 and the dielectric film 6 (capacitance). Produce. Since there is a possibility that a high-frequency signal leaks from the variable capacitance section 12 to the drive voltage control circuit 31 or the ground via the beam section 7, the resistance patterns 10C and 10D are formed here for the purpose of blocking the leakage high-frequency signal. ing.

  2 has a structure in which a signal (voltage) is directly applied between an electrode pair including the lower drive electrode 5 and the beam portion 7 (hereinafter, this structure is referred to as an MIM structure). In addition, the structure of the variable capacitor 12 is such that two sets of electrode pairs consisting of the lower drive electrode 4A and the beam 7 and the lower drive electrode 4B and the beam 7 are connected in series, and a signal (voltage) is directly applied. This is a structure (hereinafter, this structure is referred to as a MIMIM structure). The MIMIM structure has an electrostatic attraction per area as small as about 1/4 compared with the MIM structure, and is advantageous in suppressing deformation of the beam portion 7 due to self-actuation. On the other hand, the MIM structure has a larger electrostatic attraction per area than the MIMIM structure, and is advantageous in reducing the electrode area. Therefore, it is preferable to employ the MIM structure for the drive capacitor unit 11 that requires a large electrostatic attraction and the MIMIM structure for the variable capacitor 12 that needs to suppress the electrostatic attraction.

  Note that the drive capacitor unit 11 and the variable capacitor unit 12 may adopt either the MIM structure or the MIMIM structure, respectively. Further, the drive capacity C1 of the drive capacity section 11 and the variable capacity C2 of the variable capacity section 12 change together. For this reason, the capacitance value of the drive capacitor C1 becomes a value corresponding to the capacitance value of the variable capacitor C2.

  Next, the capacitance detection circuit 21 will be described with reference to FIG.

  The capacitance detection circuit 21 includes a capacitance detection AC signal source 22, an amplifier circuit 23, and a rectifier circuit 24. The capacitance detection AC signal source 22 serves as an AC source, and outputs a capacitance detection AC signal (AC signal) of about 10 MHz, for example, to a DC cutoff capacitor C3 (about 100 pF). The output terminal of the capacitor C3 is connected to a drive voltage generating circuit 34 serving as a DC source via an AC blocking resistor R1. For this reason, an AC signal for capacitance detection is superimposed on the DC signal (drive voltage Vd) from the drive voltage generation circuit 34 at the connection point between the resistor R1 and the capacitor C3. This superimposed signal is input to a parallel circuit composed of a DC bypass resistor R2 and a reference capacitor C4. A drive capacitor C1 of the variable capacitor 2 is connected to the output terminal of the parallel circuit, and a capacitor circuit including a resistor R2, a reference capacitor C4, and a drive capacitor C1 is configured.

  The drive voltage Vd, which is a DC component of the superimposed signal, is applied to the drive capacitor C1 via the DC bypass resistor R2, and the beam portion 7 of the variable capacitor 2 is deformed by electrostatic attraction. The AC component of the superimposed signal is voltage-distributed by the reference capacitor C4 and the drive capacitor C1, and is output from the connection point between the reference capacitor C4 and the drive capacitor C1 to the DC blocking capacitor C5 as an amplitude corresponding to the capacity ratio between them. Is done.

  An amplifier circuit 23 is connected to the output terminal of the DC blocking capacitor C5. The amplifier circuit 23 amplifies the voltage level of the AC output from the voltage distribution point in the capacitor circuit and outputs an amplified voltage Vamp. A voltage follower (not shown) having a very high input impedance is provided at the input portion of the amplifier circuit 23, and the AC output of the capacitor circuit is set to a voltage level obtained by simply dividing the voltage between the reference capacitor C4 and the drive capacitor C1. ing. The amplified voltage Vamp amplified by the amplifier circuit 23 is rectified by the rectifier circuit 24. If the amplification factor of the amplifier circuit 23, the reference capacitor C4, and the voltage level of the capacitance detection AC signal source 22 are known, the DC voltage output from the rectifier circuit 24 is a voltage level that uniquely reflects the capacitance of the drive capacitor C1. Thus, the larger the drive capacity C1, the lower the voltage level. Therefore, the DC voltage output from the rectifier circuit 24 becomes the detection signal Sc that detects the drive capacitor C1, and the voltage level of the detection signal Sc corresponds to the detected value of the drive capacitor C1.

  Next, the drive voltage control circuit 31 will be described with reference to FIG.

  The drive voltage control circuit 31 includes a comparator 32, a sample hold circuit 33, and a drive voltage generation circuit 34.

  The comparator 32 receives the target signal Sr for indicating the target value of the drive capacitor C1 as an external input voltage and the detection signal Sc from the rectifier circuit 24. The comparator 32 compares the voltage level of the target signal Sr with the voltage level of the detection signal Sc and outputs a comparison result signal Se corresponding to the comparison result. For this reason, the comparison result signal Se switches to the Low level or the High level according to the comparison result between the detection value of the drive capacitor C1 and the target value. For example, when the detection signal Sc is at a voltage level smaller than the target signal Sr, that is, when the drive capacity C1 is larger than the target value, the comparison result signal Se is at a high level. Conversely, when the detection signal Sc is at a voltage level greater than the target signal Sr, that is, when the drive capacity C1 is smaller than the target value, the comparison result signal Se is at the Low level. The output terminal of the comparator 32 is input to the drive voltage generation circuit 34 via the sample hold circuit 33 that holds the comparison result signal Se for a predetermined time.

  The drive voltage generation circuit 34 increases or decreases the drive voltage Vd according to the comparison result signal Se of the comparator 32. If the comparison result signal Se of the comparator 32 is at a high level, the drive voltage Vd is lowered to adjust the drive capacity C1. On the contrary, if the comparison result signal Se of the comparator 32 is at the low level, the drive voltage Vd is increased and the drive capacitance C1 is adjusted to increase.

  Next, the drive voltage generation circuit 34 will be described with reference to FIG.

  The drive voltage control circuit 34 includes a current output type level conversion circuit 35 and a current-voltage conversion circuit 44.

  The current output type level conversion circuit 35 includes a counter circuit 36, a variable current source 37, a current mirror circuit 38, and a current output circuit 39. The counter circuit 36 counts the switching of the comparison result of the comparator 32 and outputs current control signals X0 to X5 corresponding to the count number. Here, in a transient state in which the drive capacity C1 is changing toward the target value, any of the current control signals X0 to X4 is at a high level, and the current control signal X5 is at a low level. On the other hand, in a steady state where the drive capacity C1 is stable near the target value, the current control signals X0 to X4 are at the low level, and the current control signal X5 is at the high level. The counter circuit 36 includes an input terminal for a reset signal RS, and resets the count when the reset signal RS is input.

  The variable current source 37 is set to any one of the current values Ia to If according to the current control signals X0 to X5 from the counter circuit 36, and flows the current i according to the current values Ia to If. Here, the current values Ia to If are sequentially set to smaller values from the current value Ia to the current value If, as shown in the following formula 1.

  The current values Ia to Ie are the magnitude of the current i that flows in the transient state, and the current value If is the magnitude of the current i that flows in the steady state. For this reason, the current values Ia to Ie are set when any of the current control signals X0 to X4 becomes a high level in accordance with the transient state. On the other hand, the current value If is set when the current control signal X5 is at a high level according to the steady state. The steady state current value If is smaller than any of the transient state current values Ia to Ie (If <Ia to Ie).

  The current mirror circuit 38 is configured by using three MOS switches MP1 to MP3, and copies the current i flowing through the variable current source 37. The MOS switches MP1 to MP3 are made of p-channel MOSFETs, the sources are connected to each other, and the gates are connected to each other. The drain of the MOS switch MP1 is connected to the variable current source 37 and to the gates of the MOS switches MP1 to MP3. Thereby, when the current i of the variable current source 37 flows to the MOS switch MP1, the currents i1 and i2 having the same magnitude as the current i of the variable current source 37 also flow between the drains and the sources of the MOS switches MP2 and MP3. .

  The current output circuit 39 includes a selection circuit 40, a source current circuit 42, and a sink current circuit 43. The selection circuit 40 selectively operates one of the source current circuit 42 and the sink current circuit 43 according to the comparison result signal Se. Specifically, the selection circuit 40 includes two MOS switches MN1 and MN2 that selectively operate, and a NOT circuit 41.

  The MOS switches MN1 and MN2 are n-channel MOSFETs and are connected in series to the MOS switches MP2 and MP3, respectively. Specifically, the drain of the MOS switch MN1 is connected to the drain of the MOS switch MP2. Therefore, the same current i1 as that of the MOS switch MP2 flows between the drain and source of the MOS switch MN1. The drain of the MOS switch MN2 is connected to the drain of the MOS switch MP3. For this reason, the same current i2 as that of the MOS switch MP3 flows between the drain and source of the MOS switch MN2.

  The comparison result signal Se is input to the gate of the MOS switch MN1 through the NOT circuit 41. For this reason, the MOS switch MN1 is turned off when the comparison result signal Se is at a high level, and is turned on when the comparison result signal Se is at a low level. On the other hand, the comparison result signal Se is directly input to the gate of the MOS switch MN2. For this reason, the MOS switch MN1 is turned on when the comparison result signal Se is at a high level, and is turned off when the comparison result signal Se is at a low level. As a result, the two MOS switches MN1 and MN2 are in the opposite operating state and operate as an inverter.

  The source current circuit 42 includes a first current mirror circuit 42A and a second current mirror circuit 42B. The first current mirror circuit 42A is composed of two MOS switches MN3 and MN4. The MOS switches MN3 and MN4 are each composed of an n-channel MOSFET, and both sources are connected to the ground and gates are connected to each other. The drain of the MOS switch MN3 is connected to the source of the MOS switch MN1 and to the gates of the MOS switches MN3 and MN4. As a result, when the MOS switch MN1 is turned on and the current i1 of the MOS switch MP2 flows, a current having the same magnitude as the current i1 of the MOS switch MP2 flows between the drain and source of the MOS switches MN3 and MN4.

  The second current mirror circuit 42B is composed of two MOS switches MP4 and MP5. The MOS switches MP4 and MP5 are composed of p-channel MOSFETs, and both sources are connected to a high voltage source (not shown) and gates are connected to each other. At this time, a voltage Vh higher than the maximum value of the drive voltage Vd is applied to the sources of the MOS switches MP4 and MP5. The drain of the MOS switch MP4 is connected to the drain of the MOS switch MN4 and to the gates of the MOS switches MP4 and MP5. As a result, the current flowing through the MOS switch MN4 is copied to the MOS switch MP5 through the MOS switch MP4.

  Further, the drain of the MOS switch MP5 is connected to the smoothing capacitor 45 of the current-voltage conversion circuit 44. Thereby, when the MOS switch MN1 is turned on, the source current circuit 42 copies the current i1 of the MOS switch MP2 by the first and second current mirror circuits 42A and 42B, and has the same magnitude as the current i1. The source current i10 is caused to flow toward the smoothing capacitor 45.

  The sink current circuit 43 includes two MOS switches MN5 and MN6, and is configured in substantially the same manner as the first current mirror circuit 42A of the source current circuit 42. For this reason, the MOS switches MN5 and MN6 are each composed of an n-channel MOSFET, and the sources are both connected to the ground and the gates are connected to each other. The drain of the MOS switch MN5 is connected to the source of the MOS switch MN2 and to the gates of the MOS switches MN5 and MN6. As a result, when the MOS switch MN2 is turned ON and the current i2 of the MOS switch MP3 flows, a current having the same magnitude as the current i2 of the MOS switch MP3 flows between the drains and sources of the MOS switches MN5 and MN6.

  Further, the drain of the MOS switch MN6 is connected to the smoothing capacitor 45 of the current-voltage conversion circuit 44. Thereby, when the MOS switch MN2 is turned on, the source current circuit 42 copies the current i2 of the MOS switch MP3 by the MOS switches MN5 and MN6, and the sink current i20 having the same magnitude as the current i2 is smoothed. Drain from 45.

  The current-voltage conversion circuit 44 includes a smoothing capacitor 45. The smoothing capacitor 45 has one end connected to the output end of the current output circuit 39 and the other end connected to the ground. One end of the smoothing capacitor 45 is connected to the drive capacitor C1 through resistors R1 and R2. As a result, the smoothing capacitor 45 outputs the drive voltage Vd toward the drive capacitor C1. The smoothing capacitor 45 is charged by the source current i10 and discharged by the sink current i20. For this reason, when the current output type level conversion circuit 35 supplies the source current i10, the drive voltage Vd is boosted, and when the sink current i20 is supplied, the drive voltage Vd is decreased.

  The variable capacitance device 1 according to the embodiment of the present invention has the above-described configuration. Next, the setting operation of the drive capacitance C1 will be described.

  FIG. 5 shows a case where the capacitance value of the drive capacitor C1 at the start of setting is smaller than the target value. The operation from time t0 when the reset signal RS is input to the counter circuit 36 to time t1 when the first comparison result is switched is as follows.

  When the setting of the drive capacitor C1 is started, the reset signal RS is input to the counter circuit 36, and the counter circuit 36 sets the current control signal X0 to the high level and the current control signals X1 to X5 to the low level. Thereby, the variable current source 37 flows the current i having the maximum current value Ia in the transient state.

  In addition, since the capacitance value of the drive capacitor C1 is smaller than the target value at the start of setting, the comparator 32 outputs a Low level comparison result signal Se. Therefore, the source current circuit 42 is selected by the selection circuit 40, and the source current i10 corresponding to the current value Ia flows. As a result, the smoothing capacitor 45 is charged. Since the current value Ia in the transient state is larger than the current value If in the steady state, a larger source current i10 flows than in the steady state, and the drive capacity C1 changes rapidly toward the target value.

  Here, even if the drive voltage Vd reaches the target voltage value corresponding to the target value of the drive capacitor C1, the drive capacitor C1 does not reach the target value due to the operation delay of the variable capacitance element 2 and the signal response delay of the capacitance detection circuit 21. . For this reason, the drive voltage Vd increases beyond the target voltage value, and an overshoot voltage is generated. When the drive capacitance C1 exceeds the target value and the detection value Sc of the detection signal Sc by the capacitance detection circuit 21 becomes larger than the target value of the target signal Sr, the comparison result signal Se by the comparator 32 changes from the low level to the high level. Switch to the next phase.

  The operation from time t1 when the first comparison result is switched to time t2 when the second comparison result is switched is as follows.

  When the comparison result signal Se is switched from the Low level to the High level, the count number of the counter circuit 36 increases by one. At this time, the counter circuit 36 outputs the current control signal X1 which has become High level, and sets the current control signals X0, X2 to X5 to Low level. Therefore, the counter circuit 36 switches the current value Ib to be smaller than the current value Ia, and the variable current source 37 flows the current i having the current value Ib.

  The comparator 32 outputs a comparison result signal Se having a high level. For this reason, the sink current circuit 43 is selected by the selection circuit 40, and the sink current i20 corresponding to the current value Ib flows. As a result, the smoothing capacitor 45 is discharged, the drive voltage Vd decreases beyond the target voltage value, and an undershoot voltage is generated. At this time, since the current value Ib is smaller than the current value Ia, the undershoot voltage at the time point t2 is smaller than the overshoot voltage at the time point t1. Then, when the drive capacity C1 exceeds the target value and the detection value Sc of the detection signal Sc by the capacity detection circuit 21 becomes smaller than the target value of the target signal Sr, the comparison result signal Se by the comparator 32 is switched from High level to Low level. Instead, it moves to the next phase.

  The operation from time t2 when the second comparison result is switched to time t5 when the fifth comparison result is switched is as follows.

  At the time point t2 when the second comparison result is switched, the counter circuit 36 sets the current control signal X2 to the high level and the current control signals X0, X1, and X3 to X5 to the low level. Therefore, the counter circuit 36 switches to a current value Ic smaller than the current value Ib, and the variable current source 37 flows the current i having the current value Ic. At this time, since the comparator 32 outputs the comparison result signal Se at the low level, the source current circuit 42 is selected by the selection circuit 40, and the source current i10 corresponding to the current value Ic flows. As a result, the drive voltage Vd increases beyond the target voltage value.

  At a time point t3 when the third comparison result is switched, the counter circuit 36 sets the current control signal X3 to the high level and sets the current control signals X0 to X2, X4, and X5 to the low level. Therefore, the counter circuit 36 switches the current value Id to be smaller than the current value Ic, and the variable current source 37 flows the current i having the current value Id. At this time, since the comparator 32 outputs the comparison result signal Se at the high level, the selection circuit 40 selects the sink current circuit 43, and the sink current i20 corresponding to the current value Id flows. As a result, the drive voltage Vd decreases beyond the target voltage value.

  At a time point t4 when the fourth comparison result is switched, the counter circuit 36 sets the current control signal X4 to the high level and sets the current control signals X0 to X3 and X5 to the low level. For this reason, the counter circuit 36 switches to a current value Ie smaller than the current value Id, and the variable current source 37 flows the current i having the current value Ie. At this time, since the comparator 32 outputs the comparison result signal Se at the low level, the source current circuit 42 is selected by the selection circuit 40, and the source current i10 corresponding to the current value Ie flows. As a result, the drive voltage Vd increases beyond the target voltage value.

  At the time t5 when the fifth comparison result is switched, the counter circuit 36 sets the current control signal X5 to the high level and the current control signals X0 to X4 to the low level. Therefore, the counter circuit 36 switches to a current value If smaller than the current value Ie, and the variable current source 37 flows the current i having the current value If. At this time, since the comparator 32 outputs the comparison result signal Se at the high level, the selection circuit 40 selects the sink current circuit 43, and the sink current i20 corresponding to the current value If flows. As a result, the drive voltage Vd decreases beyond the target voltage value. Then, the overshoot voltage and the undershoot voltage are gradually reduced as the time point t2 to t5 is shifted.

  The operation after time t5 when the comparison result of the fifth comparison occurs is as follows.

  The counter circuit 36 outputs the current control signal X5 which has become High level, and sets the current control signals X0 to X4 to Low level. For this reason, since the counter circuit 36 sets a steady state current value If smaller than the transient state current values Ia to Ie, the variable current source 37 flows the current i having the current value If. At this time, the current output type level conversion circuit 35 selectively operates one of the source current circuit 42 and the sink current circuit 43 according to the comparison result signal Se, and when the comparison result signal Se is at the low level. A source current i10 having a current value If is supplied, and a sink current i20 having a current value If is supplied when the comparison result signal Se is at a high level. Since the steady-state current value If is smaller than the transient current values Ia to Ie, the fluctuation range of the drive voltage Vd with respect to the target value is reduced, and high capacity accuracy can be obtained. Thus, the current output type level conversion circuit 35 performs a feedback operation so that the drive voltage Vd approaches the target voltage value.

  FIG. 6 shows a case where the capacitance value of the drive capacitor C1 at the start of setting is larger than the target value. Even in this case, the operation is almost the same as the case where the capacitance value of the drive capacitor C1 at the start of the setting is smaller than the target value.

  As described above, according to the variable capacitance device 1 of the present embodiment, the capacitance values of the drive capacitance C1 and the variable capacitance C2 can be continuously changed according to the drive voltage Vd, and three or more capacitance values can be changed. Can be obtained. In addition, since the drive voltage Vd is changed by the source current i10 and the sink current i20, the entire device is made smaller than when the drive voltage is generated using, for example, a low-pass filter circuit composed of a resistor and a capacitor. Can be

  More specifically, in general, in an integrated circuit, resistors and capacitors that are passive elements tend to be larger. In the variable capacitance device 1 according to the present embodiment, such a passive element can be omitted, and the entire device can be miniaturized.

  In general, there is a trade-off relationship between the stabilization time until the transition from the transient state to the steady state and the capacity accuracy of the drive capacity C1. For this reason, when the resistance value of the low-pass filter circuit is reduced or the capacitance value is increased to shorten the stabilization time, the capacitance accuracy is lowered. Conversely, if the resistance value of the low-pass filter circuit is increased or the capacitance value is decreased to increase the capacitance accuracy, the stabilization time becomes longer.

  In contrast, in the present embodiment, the current output type level conversion circuit 35 is configured to gradually decrease the current values of the source current i10 and the sink current i20 when shifting from the transient state to the steady state. For this reason, the current value Ia of the source current i10 and the sink current i20 can be increased at the initial stage of the transient state, for example, at the start of setting, and the charge amount and the discharge amount of the smoothing capacitor can be increased. As a result, the drive capacity C1 of the variable capacitance element 2 can be quickly brought close to the target value, and the stabilization time until the drive capacity C1 converges to the target value can be shortened. On the other hand, when transitioning from the transient state to the steady state, the current values Ia to If are sequentially switched, so that the current values of the source current i10 and the sink current i20 are gradually reduced to reduce the charge amount and the discharge amount of the smoothing capacitor. Can be made. In the steady state, since the current values of the source current i10 and the sink current i20 are set to the smallest current value If, the fluctuation of the drive capacity C1 with respect to the target value can be reduced, and the capacity accuracy can be improved. As a result, it is possible to shorten the stabilization time until convergence to the target value while realizing high capacity accuracy.

  In the above-described embodiment, the current output type level conversion circuit 35 is configured using a MOSFET, but may be configured using another switch element such as a bipolar transistor die.

  In the above embodiment, the drive capacitance C1 of the variable capacitance element 2 is detected to change the drive capacitance C1, but the variable capacitance C2 may be detected to change the drive capacitance C1. Alternatively, a single variable capacitor in which the drive capacitor C1 and the variable capacitor C2 are shared may be provided, and this variable capacitor may be detected and changed.

  In the embodiment, the current value If is converged to the steady-state current If at the time t5 when the fifth comparison result is switched. However, the present invention is not limited to this. For example, the present invention may be configured to converge to a steady-state current value at time points t2 to t4 when switching of the second to fourth comparison results occurs, and any nth time after the sixth time. Alternatively, the current value may be converged to a steady-state current value at a time tn when the comparison result is switched.

  In the above-described embodiment, the source current i10 and the sink current i20 are changed by changing the current i of the variable current source 37. However, the source current i10 and the sink current are fixed while the current value of the current source is fixed. The current i20 may be changed. In this case, for example, a plurality of current mirror circuits 42B of the source current circuit 42 are connected in parallel, and the source current i10 is changed by increasing or decreasing the number of the current mirror circuits 42B that operate. Also good. Similarly, a configuration may be adopted in which a plurality of current mirror circuits forming the sink current circuit 43 are connected in parallel, and the sink current i20 is changed by increasing or decreasing the number of operating current mirror circuits among the plurality of current mirror circuits. .

DESCRIPTION OF SYMBOLS 1 Variable capacity apparatus 2 Variable capacity element 21 Capacity detection circuit 31 Drive voltage control circuit 32 Comparator 35 Current output type level conversion circuit 36 Counter circuit 37 Variable current source 38 Current mirror circuit 39 Current output circuit 40 Selection circuit 42 Source current circuit 43 Sink current circuit 44 Current-voltage conversion circuit 45 Smoothing capacitor

Claims (3)

A variable capacitance element whose capacitance changes according to the drive voltage, a capacitance detection circuit that detects the capacitance of the variable capacitance element, and a capacitance detection value by the capacitance detection circuit approaches a desired target value In a variable capacitance device comprising a drive voltage control circuit for controlling the drive voltage as described above,
The drive voltage control circuit includes a comparator that compares the detected value of the capacitance with a target value, a current output type level conversion circuit that causes a source current or a sink current to flow according to a comparison result of the comparator, A current output level conversion circuit comprising a smoothing capacitor that boosts the drive voltage when a source current flows and reduces the drive voltage when a sink current flows;
The current output type level conversion circuit is configured to gradually reduce the current values of the source current and the sink current when shifting from a transient state to a steady state. The drive voltage control circuit includes a counter circuit that counts switching of the comparison result of the comparator,
When the count number is reset by a reset signal, the counter circuit sets the current value of the drive voltage control circuit to the magnitude of the transient state, and each time the comparison result is switched, the counter voltage of the drive voltage control circuit is set. The variable capacitance device according to claim 1, wherein the variable capacitance device is configured to reduce a current value and finally converge a current value of the drive voltage control circuit to a steady state magnitude smaller than a transient magnitude.   The current output type level conversion circuit includes a variable current source whose current value is set by the counter circuit, a current mirror circuit that copies a current flowing through the variable current source, and a source current according to a comparison result of the comparator 3. The variable capacitance device according to claim 2, further comprising: a current output circuit that operates either one of the circuit and the sink current circuit to flow a source current or a sink current corresponding to a current flowing through the current mirror circuit.

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