JP2013004736A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of suppressing metal contamination of a substrate.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: forming a protection film on a rear surface on the side opposite to a semiconductor element formation surface of a substrate on which a semiconductor element is provided and at an end of the substrate; processing a metal-containing film provided on the semiconductor element formation surface; and removing the protection film after processing the metal-containing film.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Semiconductor devices, including silicon devices, have been integrated and reduced in power by miniaturizing the scaling law known by Moore's law, and development has been progressing at a pace of "4 times integration in 3 years" It was. In recent years, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have gate lengths of 20 nm or less, and device performance has been improved with approaches different from previous scaling laws due to rising costs in lithography processes and physical limitations in device dimensions. Is required. The increase in cost in the lithography process includes an increase in the price of the manufacturing apparatus and the mask set. In addition, physical limits of device dimensions include operating limits and dimensional variation limits.

  In recent years, as one method for improving the performance of a semiconductor device, an active element other than a semiconductor element, such as a resistance change element, is provided as a memory or a switch in the semiconductor device.

  Examples of such a resistance change element include RRAM (Resistance RAM [Random Access Memory]) using a transition metal oxide and a solid electrolyte switch using an ion conductor. An ionic conductor is a solid in which ions can move freely by application of an electric field or the like. In addition, developments such as FRAM (Ferro Electric RAM), MRAM (Magnetic RAM), and PRAM (Phase-change RAM) are underway (Non-Patent Document 1).

  Since such a switching element is smaller in size than a semiconductor element such as a MOSFET, the occupied area for realizing the same function can be reduced, and power consumption during operation due to charge / discharge of the gate and wiring ( Dynamic power) can be reduced. Furthermore, SRAM (Static RAM) and DRAM (Dynamic RAM) are volatile elements whose stored state is erased when the power is turned off, whereas the resistance change element is in a stored state even when the power is turned off. Since this is a non-volatile element that holds, the standby power consumption (Static power) can also be reduced.

  In addition, the solid electrolyte switch has a feature of lower on-resistance. Therefore, the solid electrolytic switch is considered promising for application to a nonvolatile programmable logic device that uses the switch itself as a signal line (Non-patent Document 2).

  On the other hand, in Patent Document 1, in the method of manufacturing a semiconductor device, in order to prevent sublimation of semiconductor constituent atoms (silicon) from the back side of the semiconductor substrate (silicon substrate) during heat treatment, the front side and back side of the semiconductor substrate are disclosed. An insulating film is formed so as to cover the side, the insulating film on the front surface side of the semiconductor substrate is removed by etching, and the semiconductor substrate is heat-treated in a state where the insulating film exists on the back surface side of the semiconductor substrate. Yes.

JP 2004-152920 A

R. Nebashi, et al., "A 90nm 12ns 32Mb 2T1MTJ MRAM", IEEE Solid-State Circuits Conference-Digest of Technical Papers, 8-12 Feb. 2009, pp.462-463,463a. M. Tada, et al., "Nonvolatile Crossbar Switch Using TiOx / TaSiOy Solid-Electrolyte", IEEE Transactions on Electron Devices, vol. 57, no.8, pp.1987-1995 2010.

  In recent years, films made of heavy metals or noble metals (for example, Fe, Ru, Mg) that are not used in normal silicon semiconductor processes have been used for resistance change elements represented by the above RRAM, MRAM, and PRAM. Such a film is usually processed by reactive dry etching (RIE) when processed in a semiconductor process. However, when the vapor pressure of the reaction product is low, or when a metal that does not form the reaction product is included, the metal of the film forming material is easily formed on the back surface or bevel (end face) portion of the silicon substrate on which the semiconductor element is formed. Adhere to. The metal adhering to the silicon substrate causes dust generation during the process, diffuses in the silicon substrate by the application of heat in the subsequent process, forms a deep level in the silicon, and has a gate insulating film. It causes a malfunction due to a change in the threshold voltage of the silicon semiconductor element and a decrease in reliability due to a lifetime deterioration. Further, when heating is performed in the process apparatus with the metal adhered, the sublimated metal adheres to a temperature sensor or the like, and the malfunction of the process apparatus is likely to occur.

  In order to solve such a problem, a process in which the metal of the film forming material does not adhere to the back surface or bevel (end surface) of the silicon substrate other than the semiconductor element formation region, or a technique that can be easily removed even if it adheres is necessary. is there.

  However, metals such as Ni, Pd, Co, Fe, and Pt are difficult to remove with a chemical solution. Such a metal can be removed by using a chemical solution having a strong detergency such as aqua regia (mixed solution of concentrated hydrochloric acid and concentrated nitric acid in a volume ratio of 3: 1), but the ability to remove attached metal is enhanced. On the other hand, the back surface of the silicon substrate, which is the base material, becomes rough, and the depth of focus in the advanced fine semiconductor exposure apparatus becomes unstable.

On the other hand, an insulating film such as a silicon nitride film or a silicon oxide film is formed on the substrate surface, and the metal adhering to the insulating film surface is removed by HPM (mixed solution containing HCl, H ₂ O ₂ , H ₂ O), There is known a technique of removing (lifting off) the metal adhering to the entire insulating film by FPM (mixed liquid containing HF, H ₂ O ₂ , and H ₂ O). However, in order to apply this technique to a substrate on which a semiconductor element is formed, it is necessary to selectively form an insulating film only on the surface where the semiconductor element is not formed (the back surface of the substrate).

  In order to provide the insulating film only on the back surface of the substrate, for example, as described in Patent Document 1, after the insulating film is simultaneously grown on the front and back surfaces of the substrate using a thermal CVD method, the insulation on the front surface side of the substrate is performed. There is a method of selectively removing (wet etching) a film with a chemical solution. However, in the process of forming the resistance change element on the upper layer side of the semiconductor element, a multilayer wiring structure including a metal such as copper and an interlayer insulating film is formed in advance on the semiconductor substrate. When removed, the metal of the multilayer wiring structure and the interlayer insulating film deteriorate.

  An object of the present invention is to solve the above-described problems and suppress metal contamination of a substrate in the manufacture of a semiconductor device.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a protective film on a back surface and an end of a substrate provided with a semiconductor element on the side opposite to the semiconductor element formation surface;
Processing the metal-containing film provided on the semiconductor element formation surface;
Removing the protective film after processing the metal-containing film.

A semiconductor manufacturing apparatus according to another aspect of the present invention is a manufacturing apparatus used in the above manufacturing method,
A film forming chamber for forming the protective film under reduced pressure;
A stage for mounting the substrate;
An arm for transporting the substrate to the film formation chamber;
The stage has a shape having a concave portion on the substrate mounting surface, and an outer peripheral portion surrounding the concave portion can contact an outer peripheral position surrounding the element forming region so as not to contact the element forming region of the substrate,
The arm includes a mechanism that contacts the back surface of the substrate, flips the substrate by rotating the arm, and places the semiconductor element formation surface of the substrate toward the substrate mounting surface of the stage. It is characterized by that.

  ADVANTAGE OF THE INVENTION According to this invention, the metal contamination of a semiconductor substrate can be suppressed in manufacture of a semiconductor device.

It is the schematic for demonstrating the structure of the semiconductor manufacturing apparatus in embodiment of this invention. It is a figure for demonstrating the structure of the insulating film growth apparatus in embodiment of this invention. It is a figure for demonstrating the shape of the concave stage in embodiment of this invention. It is a figure for demonstrating the state which installed the silicon substrate in the concave stage in embodiment of this invention, and the state which grew the protective insulating film. It is a figure for demonstrating the state which installed the silicon substrate on the concave stage in embodiment of this invention, and the state which grew the protective insulating film. It is a figure for demonstrating the vacuum chuck line provided in the concave stage in embodiment of this invention. It is sectional drawing for demonstrating the solid electrolyte switch element in embodiment of this invention. It is sectional drawing for demonstrating the MRAM element in embodiment of this invention. It is a process flow figure including a protective insulating film formation process and a protective insulating film removal process in the embodiment of the present invention. It is sectional drawing of the silicon substrate in which the semiconductor element before resistance change element formation in the embodiment of this invention was formed. It is sectional drawing of the silicon substrate in which the resistance change element and the semiconductor element were formed in embodiment of this invention. It is an expanded sectional view of the resistance change element shown in FIG.

  A manufacturing method of a semiconductor device according to an embodiment of the present invention is provided on a back surface and an end portion (bevel portion) of a substrate (for example, a semiconductor substrate such as a wafer) on which a semiconductor element is formed, opposite to a semiconductor element formation surface. Forming a protective film; processing a metal-containing film provided on a semiconductor element formation surface; and removing the protective film after processing the metal-containing film.

  The metal-containing film can be processed by dry etching such as RIE.

  In the protective film removal step, the protective film can be removed together with the metal component derived from the metal-containing film attached to the protective film.

  According to the present embodiment, it is possible to mount the variable resistance element while maintaining the reliability of the semiconductor element high, and it is possible to achieve high functionality and low power of the semiconductor device.

  The protective film is preferably formed at 400 ° C. or lower. As a result, it is possible to suppress deterioration due to heat of a semiconductor element or a multilayer wiring formed in advance on the substrate.

  In the protective film formation step, the substrate can be placed on a film formation stage (substrate stage) with the semiconductor element formation surface facing the substrate mounting surface of the film formation stage. At this time, the film formation stage has a concave portion on the substrate mounting surface, and the element forming region of the substrate mounting surface of the film forming stage so that the outer peripheral portion surrounding the concave portion does not contact the element forming region of the substrate. Can be in contact with the outer peripheral position surrounding the. Hereinafter, such a film forming stage is referred to as a “concave stage”. Accordingly, the protective film can be selectively formed on the back surface and the end of the substrate without forming the protective film in the semiconductor element type region. In addition, since the element formation region is not in direct contact with the stage, adhesion of particles and metal contaminants from the stage can be suppressed, and mechanical damage such as scratches can be prevented.

  In forming the protective film, it is preferable to use a CVD method, a plasma CVD method, an ALD method, or a plasma ALD method. When the concave stage is used, the contact area between the semiconductor substrate and the concave stage is reduced, and it is difficult to maintain the substrate temperature higher than that of a normal stage. By using a plasma CVD method or a plasma ALD method using a plasma source, a dense protective film can be formed even if the substrate temperature is low.

  In the formation of the protective film using the concave stage, it is preferable that the substrate is heated to a predetermined temperature in another stage in advance and then transported to the concave stage to form the protective film. In that case, a board | substrate can be conveyed to a heating stage with the conveyance arm which contacts the back surface of a board | substrate, and it heats to predetermined temperature, and can take out a board | substrate from a heating stage with the arm contacted with the back surface of the board | substrate after that.

  When placing the substrate on the concave stage, the substrate is flipped by rotating the arm that is in contact with the back surface of the substrate, so that the surface on which the semiconductor element is formed has a concave surface (substrate mounting surface). It is preferable to place it on a concave stage so as to face each other, and to form a protective film in the reaction chamber (film formation chamber) in this state.

  As the protective film, a silicon oxide film, a silicon nitride film, or a silicon carbonitride film can be formed.

  The removal of the protective film can be carried out by single wafer spin cleaning using a chemical solution.

  In the manufacturing method of this embodiment, the metal-containing film is at least one metal selected from Pt, Pd, Ni, Fe, Co, Ru, Mn, Mg, Ta, Ir, B, Ge, Te, Se, and Sb. It is more effective when including.

  The manufacturing method of the present embodiment is more effective when it includes a process of forming a resistance change element such as an MRAM, PRAM, RRAM, FRAM, solid electrolyte switch, etc., including the processing step of the metal-containing film.

  Hereinafter, preferred embodiments of the present invention will be further described.

  A multilayer wiring structure including a multilayer wiring layer and an interlayer insulating film can be provided on a silicon substrate (wafer) on which a semiconductor element is formed. A variable resistance element can be provided in the multilayer wiring structure.

  In the present embodiment, the protective film is formed before the metal-containing film dry etching step (hereinafter referred to as “resistance change element processing step”) in the resistance change element formation process.

  The protective film can be formed using an insulating film growth apparatus, for example, as follows.

  The insulating film growth apparatus includes a concave stage as a substrate stage, and the concave stage is installed with a surface having a dent facing upward. The silicon substrate is placed on the concave stage so that the element forming surface and the surface of the concave stage having the recesses face each other (that is, the element forming surface faces downward and the back surface faces upward). At that time, only the outer periphery of the concave stage is in contact with the silicon substrate, and the semiconductor element formation region is not in contact with the concave stage. By performing the film formation process in this state, the protective insulating film is not formed in the semiconductor element formation region, and the protective insulating film is formed on the back surface and the bevel of the substrate.

  The transfer of the silicon substrate onto the concave stage is performed by an arm that contacts the back surface of the silicon substrate. By rotating the arm, the silicon substrate is flipped, and the semiconductor element formation surface is opposed to the surface having the recess of the concave stage. To be placed.

A protective insulating film is grown on the back surface and the bevel portion of the silicon substrate transferred to the reaction chamber by using, for example, a plasma CVD method. As the protective insulating film, a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN), a silicon carbonitride film (SiCN), or the like can be used. As a raw material for growing the protective insulating film, TEOS, SiH ₄ , 4MS, 3MS, organosilane, organosiloxane, NH _3, or the like can be used. The film thickness of the protective insulating film can be set in the range of about 10 nm to 1 μm. The type and thickness of the protective insulating film can be set as appropriate in consideration of the type and concentration of the deposited metal, the etching rate with the cleaning solution, the diffusion coefficient of the deposited metal in silicon, the diffusion coefficient in the insulating film, etc. it can. For example, the insulating film may be changed to a SiC film, a SiOC film, or the like in order to change the etching rate with a chemical solution. When forming the SiOC film, an organic siloxane raw material can be used.

  The resistance change element in this embodiment can be formed as follows, for example.

  First, through holes for forming plugs electrically connected to semiconductor elements on the silicon substrate are formed in the interlayer insulating layer on the silicon substrate by using lithography and dry etching. At this time, since the material to be processed is a material used in a normal semiconductor process (material made of Si, O, C, N, etc.), contaminated metal adheres to the back surface or bevel (end surface) of the silicon substrate. Never do.

  Subsequently, a metal layer for forming a resistance change element and a resistance change material layer are grown on the entire surface of the silicon substrate including the through holes. For example, when forming a solid electrolyte switch, the polymer solid electrolyte, Pt, and Ta are laminated in this order. If Pt or Ta adheres outside the predetermined range of the surface of the silicon substrate (that is, the back surface or bevel (end surface)), it is transferred to the apparatus as a contaminated metal in the subsequent process, and another silicon substrate to be processed subsequently Contaminated. As described above, when forming the metal layer for forming the variable resistance element or the variable resistance material layer, these materials wrap around the back surface or bevel (end surface) of the silicon substrate and cause contamination, but the protective insulating film is made of silicon. When formed on the back surface and bevel (end surface) of the substrate, the contaminated metal does not directly adhere to the silicon substrate.

  Subsequently, in order to remove the contaminated metal, the contaminated metal is removed (lift-off cleaning) together with the protective insulating film by, for example, FPM cleaning using a back surface cleaning apparatus. The conditions for the cleaning treatment can be appropriately set while confirming the etching rate of the formed protective insulating film and the metal contamination level after the treatment.

  Thereafter, a protective insulating film is formed again on the back surface and bevel (end surface) of the silicon substrate by the insulating film growth apparatus.

  Subsequently, lithography for processing the metal layer and the resistance change material layer is performed. At this time, the contaminated metal adhering to the back surface and the bevel (end surface) of the silicon substrate during the formation of the metal layer and the resistance change layer has been removed by the lift-off cleaning described above, so that the contaminated metal is transferred into the lithographic apparatus. There is no.

  Subsequently, dry etching of the metal layer and the resistance change material layer is performed. For example, when etching Ta, Ta can be etched by vaporizing a reaction product by reactive dry etching (RIE) using a chlorine-based gas. However, since the vapor pressure of the reaction product is low, a dry etching apparatus is used. Adhere inside. Further, when etching Pt, a reaction product is not generated, so physical etching is performed, and most of it is scattered in the reaction chamber and adheres to the inside of the reaction chamber. The contaminated metal thus deposited is transferred to another subsequent processed silicon substrate which is then transported to be etched. At this time, by forming the protective insulating film in advance, it is possible to prevent the contaminated metal from directly attaching to the silicon substrate.

  Subsequently, lift-off cleaning is performed using a back surface cleaning device in order to remove the contaminated metal attached due to the dry etching process together with the protective insulating film.

  By the above process, the direct adhesion of the contaminating metal to the silicon substrate accompanying the formation and processing of the metal layer for forming the resistance change element and the resistance change layer is prevented, and another silicon substrate to be subsequently processed is prevented. Contamination can also be prevented. Therefore, after the formation of the resistance change element is completed and the protective insulating film is removed by lift-off cleaning, a normal semiconductor manufacturing process can be performed.

  The process described above corresponds to the process shown in FIG. 9D among the processes described later with reference to FIG. The present invention is not limited to the above-described process, and according to another embodiment of the present invention, for example, the processes shown in FIGS. 9A, 9B, and 9C are performed. A manufacturing method can be provided.

[Semiconductor manufacturing apparatus and processing method using the same]
Next, a semiconductor manufacturing apparatus including an insulating film growth apparatus and a processing method using the same will be described with reference to the drawings.

  FIG. 1 is a diagram schematically showing a configuration example of a semiconductor manufacturing apparatus used in the present embodiment.

  This apparatus has a cluster structure in which a plurality of processes can be performed under reduced pressure. The silicon substrate is moved from the cassette box 100 to the load lock chamber 102 by the atmospheric robot 101. Thereafter, the silicon substrate is transferred to the heating stage module 105 by the central handler 104 provided in the central platform chamber 103 for heat treatment. The heating stage is heated so that the substrate temperature is in the range of 200 to 400 ° C. In order to raise the substrate temperature by heating and to remove organic substances adhering to the substrate surface, it is preferable to carry out in an inert gas atmosphere under reduced pressure.

  Subsequently, the silicon substrate is transferred to the protective insulating film growth module 106 under vacuum, and the insulating film is grown. Here, when the silicon substrate comes into contact with the atmosphere, components in the atmosphere adhere to it, so the substrate is transferred under reduced pressure. At this time, the pressure in the central platform chamber 103 is preferably set higher than that of the heating stage module 105 and the protective insulating film growth module 106 in order to prevent gas mixture from the heating stage module 105 and the protective insulating film growth module 106. For example, about 500 mTorr (66.66 Pa) is preferable.

  FIG. 2 is a block diagram showing a configuration example of a plasma CVD apparatus used for forming a protective insulating film in the present embodiment.

  As shown in FIG. 2, the plasma CVD apparatus includes a reaction chamber 210, a gas supply unit 220, a vacuum pump 230, and a radio frequency (RF) power supply 240. The gas supply unit 220 is connected to the reaction chamber 210 via a gas supply pipe 222. The vacuum pump 230 is connected to the reaction chamber 210 via a gas discharge pipe 236. The high frequency power supply 240 is connected to the reaction chamber 210 via a high frequency cable 244. The high frequency cable 244 is provided with a matching box 242.

  A substrate stage 203 and a shower head 205 are provided in the reaction chamber 210, and these are arranged in a state of facing each other. A ground wire 207 is connected to the substrate stage 203. The substrate stage 203 is provided with a heater (not shown). The substrate stage 203 holds a film formation member 201 such as a semiconductor substrate and heats the film formation member 201. The shower head 205 is connected to a gas supply pipe 222 and functions as a gas ejection unit that injects a gas supplied through the gas supply pipe 222 onto the deposition target member 201. A high frequency cable 244 is connected to the shower head 205.

  A raw material gas or the like is supplied from the gas supply unit 220 to the shower head 205 via the gas supply pipe 222, and high-frequency power generated by the high-frequency power supply 240 is supplied to the shower head 205 by a matching box 242 disposed in the middle of the high-frequency cable 244. The frequency is supplied to the shower head 5. Thereby, the gas in the space between the substrate stage 203 and the shower head 205 is turned into plasma.

  The gas supply unit 220 is provided with a number of source supply tanks corresponding to the number of types of source gases to be used and a gas supply tank for additive gas (hereinafter referred to as “gas supply tank”). FIG. 2 shows a case where the gas supply unit 220 is provided with a raw material supply tank 211 filled with a TEOS (tetraethoxysilane) raw material. Other liquid siloxane raw materials may be used as liquid raw materials other than TOES.

  The raw material supply tank 211 is provided with a flow rate control unit 214 and a vaporizer 219. The flow rate control unit 214 includes two valves 218a and 218b, and a flow rate controller 218 provided between these valves. The flow control unit 214 is connected to the vaporizer via the pipe 212. The vaporizer 219 may be a type that supplies an inert gas or the like as a carrier gas. The vaporizer 219 vaporizes the liquid raw material supplied from the raw material supply tank 211 and supplies it to the reaction chamber 210.

As shown in FIG. 2, a cleaning gas supply pipe 228 is connected to the gas supply pipe 222. The cleaning gas supply pipe 228 is provided with a remote plasma unit 224 and a valve 226. As the cleaning gas, NF ₃ , O ₂ , C _x F _y , or a mixed gas containing two or more of them can be used.

  Further, in order to prevent each gas from being liquefied during the transfer process, heaters (not shown) are provided around the pipe 212 and around the gas supply pipe 222, and the pipe 212 and the gas supply pipe 222 are connected to the heater (not shown). It can also be heated. For the same reason, a heater (not shown) is also provided around the reaction chamber 210 to prevent the gas molecules supplied to the reaction chamber 210 from being liquefied before being excited. Can also be heated.

  Next, a procedure of a protective insulating film forming method using the plasma CVD apparatus will be described.

  After the deposition target member 201 is placed on the substrate stage 203, the vacuum pump 230 is operated, the valve 232 is opened to depressurize the reaction chamber 210, and the initial vacuum in the reaction chamber 210 is set to several Torr (1 Torr = About 133 Pa). The substrate stage 203 heats the film forming member 201 so that the surface temperature of the film forming member 201 falls within a predetermined temperature range.

  Subsequently, a gas obtained by mixing a source gas (here, TEOS gas) and a carrier gas is supplied to the reaction chamber 210 through the gas supply pipe 222, and the high frequency power supply 240 and the matching box 242 are operated to perform a predetermined operation. A high frequency power having a frequency is supplied to the reaction chamber 210.

The partial pressure of the source gas in the reaction chamber 210 is preferably maintained in the range of about 0.1 to 3 Torr (13.3 to 400 Pa). Further, by controlling the operation of the vacuum pump 230, it is preferable to maintain the atmospheric pressure in the reaction chamber 10 at the time of forming the SiO ₂ film in a range of about 1 to 6 Torr (13.3 to 800 Pa).

  In addition, the surface temperature of the deposition target member 201 is preferably maintained in the range of 100 to 500 ° C. by heating the substrate stage 203. In particular, it is preferable that the temperature at which the semiconductor element or multilayer wiring formed in advance on the film forming member is not deteriorated is maintained at 400 ° C. or lower in consideration of the heat resistance limit of a general multilayer copper wiring.

Under such processing conditions, the TEOS raw material, which is a raw material gas, and oxygen are excited by the plasma, and the activated raw material reacts with oxygen and reaches the surface of the deposition target member 201, where SiO 2 _Two films are formed.

As typical film forming conditions using TEOS raw material in a 300 mm film forming apparatus, TEOS = 160 sccm (standard cm ³ / min), O ₂ = 200 sccm, He = 100 sccm, reaction chamber pressure 400 Pa, heating stage temperature 300 ° C., RF-power = 500 W can be used.

When a silicon oxide film is formed as a protective insulating film, an oxidizing gas is usually used. However, when a silicon nitride film is formed, NH ₃ can be used as an additive gas. When forming a silicon carbonitride film (SiCN film), it is preferable to add NH ₃ using 4MS (tetramethylsilane) or 3MS (trimethylsilane) as a source gas.

  Although FIG. 2 shows a case where there is one raw material supply tank 211, a plurality of raw material supply tanks may be provided, and a protective insulating film may be formed using a plurality of types of raw material gases. The source gas used is not limited to two types, and may be three or more types.

  A program describing operation instruction contents according to the procedure of the method for forming the protective insulating film for the substrate stage 203, the vacuum pump 230, the flow rate controller 218, the high frequency power supply 240, the matching box 242 and the valves 218a, 218b, and 226. The protective insulating film may be formed by controlling the plasma CVD apparatus by causing the microcomputer to execute processing according to the program.

  When forming the protective insulating film, the silicon substrate (film formation member 201) is flipped (upside down) and placed on the substrate stage 203. A concave dedicated stage (concave stage) is used for the substrate stage 203 so that the concave surface of the concave stage faces the element formation surface of the silicon substrate, that is, the back surface of the silicon substrate (element is formed). It is placed so that the surface not facing is facing upward. By forming the film in such a state, the protective insulating film can be formed on the back surface and the bevel (end surface) of the silicon substrate without forming the protective insulating film in the element formation region of the silicon substrate.

  Next, the concave stage will be described.

  FIG. 3 shows a sectional view (FIG. 3A) and a top view (FIG. 3B) of the concave stage. The concave stage 300 has a concave portion on its substrate mounting surface, and an outer peripheral position surrounding the concave portion (that is, a frame-shaped convex portion) surrounds an element formation region of a predetermined silicon substrate (wafer) placed. It has a structure in contact with. That is, when the silicon substrate is placed on the concave stage, the concave stage can be brought into contact only with the outer peripheral portion of the substrate so that the concave stage does not contact the element forming region of the silicon substrate. For example, when a 300 mm wafer is used as the silicon substrate, the dimensions of the concave stage are, for example, an outer diameter a = 296 mm, a width c = 3 mm of a contact portion (outer peripheral portion of the concave portion) 301 and a depth of the concave portion (frame-like convexity). Part height) d = 5 mm. It is preferable that the concave stage itself is appropriately heated. The dimensions of each component can be set as appropriate in view of the error range of conveyance and the state of the insulating film wrapping around the bevel (end face) depending on the film forming conditions.

  Next, the arrangement of the silicon substrate (wafer) on the concave stage will be described with reference to FIGS. 4A and 5A are cross-sectional views, and FIGS. 4B and 5B are top views. In FIG. 4B, a circle indicated by a dotted line indicates the outline of a contact position between the silicon substrate 400 and the concave stage 300, and in FIG. 5B, a circle indicated by a dotted line indicates the silicon substrate 400 and the concave stage. The outline inside the contact position with 300 is shown. The concave stage may have an outer periphery that is smaller than the outer periphery of the silicon substrate as shown in FIG. 4 or larger as shown in FIG.

  The silicon substrate (wafer) 400 before the formation of the protective insulating film has a semiconductor element formation region 401 on the surface. The silicon substrate 400 is disposed so that the surface of the concave stage having the concave portion and the semiconductor element formation region face each other, and is in contact with the outer peripheral portion of the concave stage. By performing film formation in this state, a protective insulating film is formed on the back surface 402 and the bevel 403 of the substrate. The concave stage 300 is designed so that the semiconductor element formation region 401 of the silicon substrate and the outer peripheral portion (the portion that contacts the silicon substrate) 301 of the concave stage do not come into contact with each other when the predetermined silicon substrate 400 is placed. Is preferred. At this time, the silicon substrate may be transported after an insulating film is previously grown on the concave stage. By protecting with a clean insulating film, transfer of metal contamination to the silicon substrate through the contact surface can be prevented.

  When film formation is performed in the state shown in FIGS. 4A and 5A, the protective insulating film 410 is formed on the back surface of the silicon substrate 400 as shown in FIGS. 4C and 5C, respectively. 402 and bevel 403. At this time, no protective insulating film is formed in the element formation region 401 covered with the concave stage 300. The silicon substrate on which the protective insulating film is formed is attracted to the central handler 104 by the operation of the concave stage, transferred to the load lock chamber 102, and loaded by the atmospheric pressure robot 101 after the load lock chamber 102 is released to the atmosphere. The lock chamber 102 returns to the cassette box 100.

  A method of chucking the silicon substrate on the concave stage will be described with reference to FIG. 6A is a cross-sectional view, FIG. 6B is a top view, and FIG. 6C is an enlarged view of a portion surrounded by a dotted line in FIG. 6A.

  As shown in FIGS. 6A and 6C, a vacuum chuck line 600 is provided on the outer peripheral portion of the concave stage 300 (a portion in contact with the silicon substrate 400), so that the silicon substrate can be fixed on the concave stage. it can. The vacuum chuck portions 601, 602, and 603 on the outer peripheral portion of the concave stage can be provided as shown in FIG. 6B, but are not limited to the number and position shown in the drawing.

  In the above description, in the case of forming the protective insulating film on the back surface and the bevel (end surface) of the silicon substrate, TEOS was used as a raw material, and the case of plasma CVD using an RF power source as a film forming method was described in detail. It is not limited. Since a denser film is desirable as a protective insulating film for preventing the diffusion of metal contamination, it is possible to form a denser insulating film even at a low substrate temperature. It is also possible to use a film forming method such as a method.

[Method of forming solid electrolyte switch]
Next, as a method for forming the resistance change element in the present embodiment, a case of a solid electrolyte switch will be described as an example.

  FIG. 7 is a schematic diagram showing a cross-sectional structure of the solid electrolyte switch. This solid electrolyte switch includes an active electrode 701, an inactive electrode 702, and a solid electrolyte (ion conductive layer) 703 sandwiched therebetween. An example of the solid electrolyte switch having such a structure is NanoBridge (registered trademark).

  The active electrode 701 is an electrode that supplies a metal for forming a metal bridge during a resistance change operation, and Cu (copper), Ag (silver), or the like is used. The inert electrode 702 is an electrode to which a metal bridge is connected during a resistance change operation, and is preferably an electrode that does not cause a chemical reaction with the metal bridge, and Pt (platinum) or Ru (ruthenium) is used. The solid electrolyte 703 is a medium for moving an ionized metal and forming a metal bridge therein, and includes tantalum oxide, hafnium oxide, zirconium oxide, silicon oxide, an organic polymer, and two or more kinds selected from these. A mixture or the like can be used.

  Such a solid electrolyte switch can be formed, for example, as follows when Cu for active electrode, polymer solid electrolyte, and Pt for inactive electrode are used.

  Pt for an inert electrode has a high melting point and boiling point, and does not produce a reaction product, so that it is difficult to remove. Therefore, a protective insulating film is formed in advance on the back surface and bevel (end surface) of the silicon substrate by the method for forming a protective insulating film according to the present embodiment.

  Cu for the active electrode uses copper wiring provided on a silicon substrate on which a semiconductor element is provided. A through hole is formed in the insulating film on the copper wiring, a polymer solid electrolyte is formed on the surface including the through hole by a plasma CVD method, and Pt (10 nm) is deposited thereon by a sputtering method. At this time, when the edge cut ring is mounted in the sputtering chamber to avoid the contamination metal from entering the back surface of the substrate and the bevel (end surface), the protective insulating film according to the present embodiment is not formed. May be. The polymer solid electrolyte is a film composed of a hydrocarbon and may contain SiO.

  Subsequently, the Pt and polymer solid electrolyte are patterned into a predetermined shape by lithography and dry etching techniques.

  Thereafter, the protective insulating film on the back surface and the bevel is removed by a spin cleaning machine.

  As described above, by forming the protective insulating film according to the embodiment of the present invention at the time of forming the variable resistance element, it is possible to prevent the metal from directly attaching to the silicon substrate.

[Method of forming MRAM]
Next, as a method for forming the variable resistance element in the present embodiment, the case of MRAM will be described as an example.

  FIG. 8 is a schematic diagram showing a cross-sectional structure of the MRAM memory element. The memory element (resistance change element) includes a lower magnetic layer 801, an upper magnetic layer 802, and a tunnel insulating layer 803 sandwiched therebetween.

  The lower magnetic layer is a fixed magnetic layer whose magnetization direction does not change. The upper magnetic layer is a free magnetic layer that can be switched so that its magnetization direction can change the bit state of the cell. When the magnetization of the upper magnetic layer is parallel to the magnetization of the lower magnetic layer, the resistance of the cell is low, and when it is antiparallel, it is high.

  The lower magnetic layer 801 is, for example, an initial magnetic layer formed of permalloy (Ni—Fe) in order from the bottom, an antiferromagnetic layer formed of Ir—Mn, and a fixed layer formed of Co—Fe—B. It is formed of a ferromagnetic layer. The typical initial magnetic layer, antiferromagnetic layer, and fixed ferromagnet thickness can be selected to be about 2 nm, 10 nm, and 3 nm, respectively.

The tunnel insulating layer 803 is made of alumina (Al ₂ O ₃ ), magnesia (MgO), or the like, and the thickness can be set to about 1 to 3 nm.

  The upper magnetic layer can be formed of, for example, a free magnetic layer formed of Ni—Fe, a first tantalum layer, an aluminum layer, and a second tantalum layer in order from the bottom.

  Before forming these layers, the protective insulating film according to the embodiment is formed in the present invention.

  After these layers are formed, they are patterned into a predetermined shape by a lithography technique and a dry etching technique.

  Thereafter, the insulating film on the back surface and the bevel is removed by a spin cleaning machine.

  As described above, by forming the protective insulating film according to the embodiment of the present invention at the time of forming the variable resistance element, it is possible to prevent the metal from directly attaching to the silicon substrate.

[Process including protective insulating film formation and lift-off cleaning]
As described above, metal adheres to the back surface and bevel (end surface) of the substrate in the film forming process and the processing (dry etching) process of the resistance change element. A process for solving this problem (formation of a protective insulating film, lift-off cleaning step) will be further described with reference to FIG. FIG. 9 is a process flow diagram including formation of a protective insulating film and lift-off cleaning.

  FIG. 9A shows a process flow in the case of preventing the adhesion of contaminating metal in the variable resistance element film forming process by a method other than the protective insulating film formation (for example, edge cut ring during sputtering). In this process flow, the protective insulating film is formed after the variable resistance element is formed. Subsequently, the variable resistance element is processed by lithography and dry etching, and then the protective insulating film is removed by lift-off (lift-off cleaning). In this case, the protective insulating film formation and the lift-off cleaning are performed once.

  In the process flow of FIG. 9B, after the protective insulating film is formed, the variable resistance element film forming process is performed. Subsequently, the variable resistance element processing step is performed following the variable resistance element film forming step, and then the protective insulating film is removed by lift-off (lift-off cleaning). In this case, the protective insulating film formation and the lift-off cleaning are performed once.

  In FIG. 9C, similarly to FIG. 9B, after forming the protective insulating film, the film forming process of the variable resistance element is performed. At this time, when no metal adhesion prevention measures are taken at the time of film formation, metal adheres to the back surface or bevel (end surface) of the substrate. Subsequently, a protective insulating film is formed without cleaning the substrate. At that time, the metal adhering to the substrate is trapped inside the protective insulating film. Subsequently, the resistance change element processing step is performed, and then the protective insulating film is removed by lift-off (lift-off cleaning). In this case, the protective insulating film is formed twice and the lift-off cleaning is performed once.

  In FIG. 9D, similarly to FIG. 9B and FIG. 9C, after the protective insulating film is formed, the variable resistance element is formed. Subsequently, after removing the protective insulating film by lift-off (lift-off cleaning), a protective insulating film is formed again. Subsequently, the resistance change element processing step is performed, and then the protective insulating film is removed by lift-off (lift-off cleaning). In this case, the protective insulating film formation and the lift-off cleaning are performed once for the resistance change element film forming process, and the protective insulating film formation and the lift-off cleaning are performed once for the resistance change element processing process. Become. According to such a process flow, there is an advantage that the substrate can always be maintained in a clean state.

For lift-off cleaning, using a single wafer spin cleaning machine and FPM cleaning liquid (0.1-0.5% HF, 0.1-0.5% H ₂ O ₂ ), the back surface and bevel (end surface) part of the substrate. Can be cleaned. While spraying dry nitrogen or pure water onto the substrate surface from above the rotating substrate surface, the cleaning liquid is sprayed on the back surface of the substrate and the edge of the back surface of the substrate. Backside cleaning can be performed while preventing wraparound to the substrate surface. After cleaning, the chemical liquid adhering to the substrate can be removed by spraying pure water. In addition to FPM, chemicals commonly used in semiconductor processes, such as HPM cleaning solution (HCl / H ₂ O ₂ / H ₂ O), SPM cleaning solution (H ₂ SO ₄ / H ₂ O ₂ ), FPM cleaning solution (HF / H ₂ O ₂ / H ₂ O), DHF cleaning liquid (HF / H ₂ O), BHF cleaning liquid (HF / NH ₄ F / H ₂ O) and the like may be appropriately combined.

  By measuring the metal contamination level on the back surface of the substrate in advance for each process, by applying the process flow in any one of FIGS. 9A to 9D, or a process flow based on any of them, A manufacturing process that suppresses an increase in the number of steps can be provided.

  Hereinafter, the present invention will be described more specifically with reference to examples.

(Example 1) Method for Manufacturing Semiconductor Device Including Solid Electrolyte Switch In this example, a method for manufacturing a semiconductor device including a solid electrolyte switch as a resistance change element will be described.

  FIG. 10 is a schematic cross-sectional view of a silicon substrate on which a semiconductor element is formed before forming a solid electrolyte switch and a protective insulating film.

  A MOSFET 599 is formed on the silicon substrate 500, and the gate, source, and drain of the MOSFET 599 are connected to the copper wiring on the upper layer side by tungsten plugs 532 covered with TiN531, respectively. The copper wiring is composed of Cu534 and Ta / TaN533 (laminated barrier metal) surrounding Cu. As the wiring interlayer insulating film, a SiOCH film 513 having a relative dielectric constant of 3 or less is used. A SiCN film 514 formed by plasma CVD is provided as a protective film on the upper surface of the copper wiring. A SiCN film 520 is formed as a protective film on the uppermost copper wiring, and a silicon oxide film 520a for through-hole processing is formed thereon.

  Here, since the outermost surface of the substrate is covered with the silicon oxide film 520a, there is no problem even if it is exposed to dry nitrogen or pure water during the back surface spin cleaning.

  Subsequently, by using the insulating film growth apparatus according to the embodiment of the present invention, a protective insulating film (silicon oxide film) (not shown) was grown by 1 μm on the back surface and bevel (end surface) of the substrate. At this time, since the protective insulating film does not grow in the semiconductor element formation region, there is no change in the cross-sectional structure of FIG.

  Next, FIG. 11 shows a cross-sectional view of a silicon substrate in which a resistance change element 598 is provided in a multilayer wiring structure. FIG. 12 shows an enlarged view of the variable resistance element 598 shown in FIG. 11 and its peripheral part.

  A hole is formed on the silicon oxide film 520a by lithography and dry etching, and a laminated film for forming a resistance change element is formed on the entire surface of the silicon substrate including the hole. When the solid electrolyte switch shown in FIG. 12 is formed, each layer of the laminated film corresponds to the polymer solid electrolyte 591, the Pt electrode 592, and the Ta electrode 593 from the bottom. The Pt electrode layer and the Ta electrode layer were formed by sputtering, and the film thicknesses were 10 nm and 25 nm, respectively. At this time, the width of the edge cut ring shield in sputtering was set to 5 mm to prevent Pt and Ta from adhering to the back surface and bevel (end surface) of the substrate.

Subsequently, a laminated film for forming a resistance change element was processed by lithography and dry etching. For example, using an RIE apparatus using an ECR plasma source, setting the source / bias power 400 W / 200 W, Ar = 100 sccm, reaction chamber pressure 0.3 Pa, substrate temperature 150 ° C., performing RIE, and for the organic polymer layer RIE was performed at CF ₄ = 100 sccm.

  Thereafter, lift-off cleaning using FPM was performed, and the protective insulating film was removed.

After processing by the above RIE, another subsequent substrate (wafer) is transferred to the reaction chamber, and the substrate taken out from the reaction chamber without any work other than this transfer operation is not subjected to lift-off cleaning, but is totally reflected. When the metal contamination concentration on the back surface of the substrate was analyzed using X-ray analysis (TREX), contamination of 1 × 10 ¹⁶ atoms / cm ² level or more was detected from the back surface of this substrate.

  On the other hand, after the above processing, another subsequent substrate (wafer) is transferred to the reaction chamber, and the substrate taken out from the reaction chamber without any work other than this transfer operation is lifted off using FPM. And the protective insulating film was removed. Thereafter, when the metal contamination concentration on the back surface of the substrate was measured in the same manner as described above, Pt was below the lower limit of detection. That is, by forming a protective insulating film according to the embodiment of the present invention, and performing lift-off cleaning to remove the protective insulating film, it is possible to prevent metal contamination of the substrate due to the processing step of the resistance change element. confirmed.

(Example 2) Manufacturing method of semiconductor device including MRAM In this example, a manufacturing method of a semiconductor device including an MRAM using a TMR element as a variable resistance element will be described. In this example, a semiconductor device can be manufactured in the same manner as Example 1 except that the configuration of the variable resistance element is different.

  On the lower electrode, Ta (10 nm) / PtMn (10 nm) / Co90Fe10 (2.5 nm) / Ru (0.85 nm) / Co40Fe40B20 (5 nm) / MgO (2.5 nm) / Co40Fe40B20 (3 nm) / Ta (10 nm) / Ru (7 nm) / NiFe (20 nm) / Ta (5 nm) was formed by sputtering. At this time, by mounting the edge cut ring in the sputtering chamber, it is possible to avoid adhesion of contaminating metal to the back surface and the bevel (end surface) of the substrate.

Next, in order to avoid the following problems after performing the above film forming process, a protective insulating film (on the back surface and bevel (end face) of the substrate is used by using the insulating film growth apparatus according to the embodiment of the present invention. SiO ₂ ) was formed. Thereafter, the laminated film formed by the film forming process is processed by lithography and dry etching.

Since materials used in ordinary semiconductor processes such as Si and Al have low melting point and boiling point of their chlorides and high vapor pressure, they are processed by RIE using chlorine gas to form elements. be able to. On the other hand, chlorides of Fe, Co, and Ni, which are ferromagnetic metal materials, have a high melting point, a high boiling point, and a low vapor pressure, making it difficult to remove reaction products. In general, temperature rising RIE in which the temperature of the workpiece is raised and RIE using a CO / NH ₃ mixed gas have been proposed, but the workability is improved, but the etching product is reattached in the reaction chamber. Transfer to a silicon substrate is a problem.

After the formation of the protective insulating film, the laminated film is processed into a predetermined shape by lithography and dry etching. For example, using an RIE apparatus using an ECR plasma source, source / bias power 800 W / 200 W, CO = 100 sccm, NH ₃ = 100 sccm, reaction chamber pressure: 0.5 Pa, substrate temperature: room temperature, NiFe, CoFeB RIE was performed, and the other layers were subjected to RIE at Cl ₂ = 120 sccm.

  Thereafter, lift-off cleaning using FPM was performed, and the protective insulating film was removed.

After processing by the above RIE, another subsequent substrate (wafer) is transferred to the reaction chamber, and the substrate taken out from the reaction chamber without any work other than this transfer operation is not subjected to lift-off cleaning, but is totally reflected. When the metal contamination concentration on the back surface of the substrate was analyzed using X-ray analysis (TREX), 1 × 10 ¹⁶ atom / cm ² level contamination of Fe was detected from the back surface of the substrate.

  On the other hand, after the above processing, another subsequent substrate (wafer) is transferred to the reaction chamber, and the substrate taken out from the reaction chamber without any work other than this transfer operation is lifted off using FPM. And the protective insulating film was removed. Then, when the metal contamination density | concentration of the board | substrate back surface was measured like the above, it was below the lower limit of detection about all the evaluation metals. That is, it is confirmed that the metal contamination of the substrate caused by the process of the resistance change element can be prevented by forming the protective insulating film according to the embodiment of the present invention and performing the lift-off cleaning to remove the protective insulating film. did.

It was also confirmed that the same effect can be obtained when a SiN film is used instead of the SiO ₂ film as the protective insulating film.

  In the above description, the present invention has been described with reference to preferred embodiments and examples. However, these embodiments and examples are intended to explain the present invention and mean that the present invention is not limited thereto. Not what you want. Although the solid electrolyte switch and the MRAM have been described as examples of the variable resistance element formed on the semiconductor substrate, the present invention is not limited thereto.

  The present invention can prevent the adhesion / transfer of metal to the back surface or bevel (end surface) of a substrate when forming a semiconductor device. For example, DRAM (Dynamic (RAM), FRAM (Ferro Electric RAM), PRAM (Phase-change RAM), RRAM (Resistive RAM), manufacturing method of semiconductor product, and manufacturing method of semiconductor product having logic circuit such as microprocessor it can. In addition, taking advantage of the feature that an insulating film can be grown on the back surface of the substrate of the present invention, it is also used in the manufacture of electronic circuit devices, optical circuit devices, quantum circuit devices, micromachines, MEMS (Micro Electro Mechanical Systems), etc. Can be applied.

  As mentioned above, although this invention was demonstrated with reference to embodiment and an Example, this invention is not limited to the said embodiment and Example. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 Cassette box 101 Atmospheric robot 102 Load lock room 103 Central platform room 104 Central handler 105 Heating stage module 106 Protective insulating film growth module 201 Film-forming member 203 Substrate stage 205 Shower head 207 Earth line 210 Reaction chamber 211 Material supply tank 212 Piping 214 Flow controller 218 Flow controller 218a, 218b Valve 219 Vaporizer 220 Gas supply unit 222 Gas supply pipe 224 Remote plasma unit 226 Valve 228 Cleaning gas supply pipe 230 Vacuum pump 232 Valve 236 Gas discharge pipe 240 High frequency power supply 242 Matching box 244 High-frequency cable 300 Recessed stage 301 Contact portion 400 Silicon substrate 401 Semiconductor element formation region 02 Substrate back surface 403 Bevel 410 Protective insulating film 500 Silicon substrate 511,526 Silicon oxide film 512,514,516,518,520,521,523 SiCN film 513,515,517,519,524,525,522 SiOCH film 520a Silicon Oxide film 520b SiN
526 Silicon oxide film 527 Silicon oxynitride film 531 TiN
532 Tungsten 533, 535, 539, 541, 543, 545, 547, 549 Ta / TaN
534, 536, 540, 542, 544, 546, 548 Cu
550 Al-Cu
591 Polymer solid electrolyte 592 Ta
593 Pt
598 Resistance change element 599 MOSFET
600 Vacuum chuck line 601 602 603 Vacuum chuck portion 701 Active electrode 702 Inactive electrode 703 Solid electrolyte 801 Lower magnetic layer 802 Upper magnetic layer 803 Tunnel insulating layer

Claims (13)

Forming a protective film on a back surface and an end of the substrate provided with the semiconductor element opposite to the semiconductor element forming surface;
Processing the metal-containing film provided on the semiconductor element formation surface;
Removing the protective film after processing the metal-containing film;
A method of manufacturing a semiconductor device including: In the processing step of the metal-containing film,
The metal-containing film is processed by dry etching,
In the protective film removing step,
The manufacturing method of Claim 1 which removes the said protective film with the metal component originating in the said metal containing film | membrane adhering to the said protective film. In the step of forming the protective film,
The substrate is placed on the film formation stage with the semiconductor element formation surface facing the substrate mounting surface of the film formation stage,
The film formation stage has a recess on the substrate mounting surface,
The protective film is formed in a state where an outer peripheral portion surrounding the concave portion of the substrate mounting surface of the film forming stage is in contact with an outer peripheral position surrounding the element forming region so as not to contact the element forming region of the substrate. The manufacturing method of Claim 1 or 2 which performs.   The manufacturing method according to claim 3, wherein the substrate is heated to a predetermined temperature on a heating stage and then transported onto the film forming stage to form a protective film. In the step of forming the protective film,
The manufacturing method as described in any one of Claim 1 to 4 which forms into a film by 400 degreeC or less by CVD method, plasma CVD method, ALD method, or plasma ALD method.   The manufacturing method according to any one of claims 1 to 5, wherein a silicon oxide film, a silicon nitride film, or a silicon carbonitride film is formed as the protective film. In the protective film removing step,
The manufacturing method according to any one of claims 1 to 6, wherein the protective film is removed by single wafer spin cleaning using a chemical solution.   The metal-containing film includes at least one metal selected from Pt, Pd, Ni, Fe, Co, Ru, Mn, Mg, Ta, Ir, B, Ge, Te, Se, and Sb. The manufacturing method as described in any one of these. Forming a resistance change element;
The manufacturing method according to claim 1, wherein the step of forming the variable resistance element includes a step of processing the metal-containing film.   The manufacturing method according to claim 9, wherein an MRAM, PRAM, RRAM, FRAM, or solid electrolyte switch is formed as the variable resistance element. Forming a first protective film and a second protective film as the protective film;
Forming the first protective film before forming the metal-containing film;
Forming the second protective film on the first protective film after forming the metal-containing film;
The manufacturing method according to claim 1, wherein the first protective film and the second protective film are removed after processing the metal-containing film. Forming a first protective film and a second protective film as the protective film;
Forming the first protective film before forming the metal-containing film;
Removing the first protective film after forming the metal-containing film;
Forming the second protective film after removing the first protective film;
The manufacturing method according to claim 1, wherein the second protective film is removed after processing the metal-containing film. It is a manufacturing apparatus used for the manufacturing method according to any one of claims 1 to 12,
A film forming chamber for forming the protective film under reduced pressure;
A stage for mounting the substrate;
An arm for transporting the substrate to the film formation chamber;
The stage has a shape having a concave portion on the substrate mounting surface, and an outer peripheral portion surrounding the concave portion can contact an outer peripheral position surrounding the element forming region so as not to contact the element forming region of the substrate,
The arm includes a mechanism that contacts the back surface of the substrate, flips the substrate by rotating the arm, and places the semiconductor element formation surface of the substrate toward the substrate mounting surface of the stage. A semiconductor manufacturing apparatus.

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