JP2013004628A - Method for designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately predict characteristic variation due to transistor deterioration caused by analog circuit operation.SOLUTION: After transistors included in a semiconductor integrated circuit are extracted, stress bias conditions to be applied to the transistors are classified on the basis of levels of electric field strength applied to gate insulating films of the extracted transistors. Next, deteriorated characteristics of the transistors are determined in accordance with classification of the stress bias conditions. Thereafter, circuit simulation of the semiconductor integrated circuit is performed using the deteriorated transistor characteristics.

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a method for designing a semiconductor integrated circuit in consideration of characteristic variation due to deterioration of a transistor that is a component of an analog circuit.

  Along with higher integration and higher density of semiconductor integrated circuits, miniaturization of element patterns constituting the integrated circuit has made remarkable progress. Under such circumstances, a change in characteristics over time due to deterioration of a transistor which is a circuit constituent element has become a serious problem in reliability.

  Due to transistor deterioration, for example, the threshold voltage (absolute value) increases as the circuit operation time increases, while the drain current (absolute value) decreases as the circuit operation time increases. As a result, the delay time of the circuit increases as the operation time increases, so that an operation timing error occurs in an input / output signal within or outside the semiconductor integrated circuit, and further, a system in which the semiconductor integrated circuit is incorporated A malfunction occurs in the whole.

  Therefore, in designing a semiconductor integrated circuit, it is necessary to secure a design margin so that a problem does not occur in the operation speed and timing of the input / output signals of the circuit even if the characteristics change due to transistor deterioration.

  However, with the recent miniaturization of element patterns of semiconductor integrated circuits, characteristic fluctuations due to transistor deterioration are likely to occur, and the design margin is forced to decrease. Therefore, circuit design technology incorporating prediction of characteristic fluctuation due to transistor deterioration has become very important.

  Conventionally, a method for designing a semiconductor integrated circuit incorporating a characteristic variation due to transistor degradation has mainly assumed a logic circuit operation. In the logic circuit operation, the operation bias voltage of the transistor is uniquely determined, and depending on the operation bias voltage, the transistor deterioration includes, for example, NBTI (Negative Bias Temperature Instability) deterioration and HC (Hot Carrier) deterioration (for example, Channel Hot Carrier deterioration). , Isubmax degradation (transistor degradation under stress conditions that result in maximum substrate current), etc. Many studies have been conducted on the characteristic fluctuation due to transistor degradation assuming such logic circuit operation. Models have also been proposed.

  For example, Patent Document 1 discloses a pulse in AC (alternating current) operation of a transistor as a circuit design method that incorporates characteristic variation due to NBTI degradation in a PMOS (P-channel Metal Oxide Semiconductor) transistor, which is one of transistor degradation. A method for simulating transistor characteristic fluctuations has been proposed taking into account the NBTI recovery phenomenon that occurs when the gate voltage is not applied during the pause.

JP 2004-200461 A

  However, in a transistor used for an analog circuit, unlike a logic circuit, an operation bias voltage is not uniquely determined. While logic circuit transistors operate primarily in the saturation region, analog circuit transistors operate in the linear region. For this reason, an intermediate bias is applied to a transistor that operates in an analog circuit, so that a mode in which the potentials of the gate, source, drain, and substrate terminals are different from each other is dominant. In addition, transistors of various sizes are incorporated in the analog circuit, and the operation of the analog circuit is easily affected by the linear region characteristics of the transistor and noise.

  In a transistor used in such an analog circuit, it is not possible to simply apply a characteristic variation prediction method using a conventional degradation model assuming a unique bias voltage in a logic circuit. For example, even if the method disclosed in Patent Document 1 is used, it is difficult to accurately predict characteristic fluctuation due to deterioration of a transistor used in an analog circuit. If characteristic variation due to transistor degradation cannot be accurately predicted, there is a risk that a design margin that guarantees circuit operation cannot be properly secured against characteristic variation due to transistor degradation.

  Specifically, if the characteristic variation due to transistor deterioration is overestimated, an attempt to secure a design margin that is larger than necessary will cause an increase in transistor dimensions and an increase in chip area. On the other hand, if the characteristic variation due to transistor deterioration is underestimated, circuit design is performed with a design margin smaller than the originally required margin, which shortens the life of the semiconductor integrated circuit device or decreases the yield. End up.

  In view of the above, an object of the present invention is to provide a semiconductor integrated circuit design method capable of accurately predicting a characteristic variation due to transistor degradation that occurs in an analog circuit operation.

  In order to achieve the above object, a method for designing a semiconductor integrated circuit according to the present invention includes a step (a) of extracting a transistor included in the semiconductor integrated circuit, and a gate insulation of the transistor extracted in the step (a). (B) classifying stress bias conditions to be applied to the transistor based on the magnitude of the electric field strength applied to the film, and depending on the classification of the stress bias conditions in the step (b) The step (c) for obtaining the characteristics after degradation of the semiconductor integrated circuit and the step (d) for performing a circuit simulation of the semiconductor integrated circuit using the transistor characteristics after degradation obtained in the step (c) are provided.

  In the method of designing a semiconductor integrated circuit according to the present invention, in the step (b), the first electric field strength region and the first electric field strength region are used as an index of the electric field strength applied to the gate insulating film. A second electric field strength region smaller than the second electric field strength region and a third electric field strength region smaller than the second electric field strength region may be set, and the stress bias conditions may be classified for each electric field strength region.

  In the method of designing a semiconductor integrated circuit according to the present invention, in the step (c), the transistor characteristics after the deterioration may be obtained using measured data of the transistor characteristics deterioration.

  In the method of designing a semiconductor integrated circuit according to the present invention, in the step (c), the transistor characteristics after the deterioration may be obtained using a model expression for the transistor characteristics deterioration. Here, the model formula may be a function of an accumulated time after the application of the stress bias condition to the transistor is started.

  In the method for designing a semiconductor integrated circuit according to the present invention, in the step (c), a threshold voltage of the transistor may be obtained as the transistor characteristics after the deterioration.

  In the method of designing a semiconductor integrated circuit according to the present invention, in the step (c), a value of a current flowing through the transistor may be obtained as the transistor characteristics after the deterioration.

  According to the present invention, the stress bias condition applied to the transistor is classified based on the magnitude of the electric field strength applied to the gate insulating film of the transistor included in the analog circuit, and according to the classification of the stress bias condition. Thus, it is possible to obtain the transistor characteristics after deterioration. For this reason, compared to the conventional case of predicting characteristic fluctuations due to transistor degradation assuming a unique bias voltage, the transistor characteristics after degradation can be predicted more accurately, ensuring a design margin that guarantees circuit operation. can do. Therefore, an increase in transistor size, that is, an increase in chip area can be prevented, and the reliability of the semiconductor integrated circuit device can be improved.

FIG. 1 is a flowchart of a method for designing a semiconductor integrated circuit according to an embodiment. FIG. 2 schematically shows an example of how the stress bias conditions applied to the transistors in the analog circuit are classified based on the magnitude of the electric field strength of the gate insulating film in the semiconductor integrated circuit design method according to the embodiment. FIG. FIG. 3 is a diagram illustrating transistor characteristic variation under a stress bias condition in an intermediate electric field region, which is considered in the method for designing a semiconductor integrated circuit according to the embodiment. FIG. 4A is an equivalent circuit diagram of a differential pair circuit using a PMOS transistor, to which the method for designing a semiconductor integrated circuit according to one embodiment is applied, and FIG. FIG. 4C is a diagram showing the relationship between the input voltage of the transistors M1 and M2 shown in a) and the current flowing in the transistors M1 and M2, and FIG. 4C shows the input voltage of the transistors M1 and M2 and FIG. FIG. 4D is a diagram showing the relationship between the voltage Vp at the point P, and FIG. 4D is a diagram showing the relationship between the input voltages of the transistors M1 and M2 and the output voltage of the differential pair circuit shown in FIG. It is. FIG. 5 is a flowchart of a method for designing a semiconductor integrated circuit according to a comparative example. FIG. 6 is a diagram schematically illustrating the relationship between the stress bias voltage applied to the transistor in the logic circuit operation and the transistor degradation, which is taken into consideration in the method for designing a semiconductor integrated circuit according to the comparative example. FIG. 7 is a diagram illustrating a characteristic variation due to NBTI degradation, which is an example of transistor degradation in a DC (direct current) operation of a logic circuit, which is taken into consideration in the method for designing a semiconductor integrated circuit according to the comparative example. FIG. 8 is a diagram showing a schematic configuration of an example of a computer system used for carrying out a method for designing a semiconductor integrated circuit according to an embodiment.

  Hereinafter, a method for designing a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a flowchart of a method for designing a semiconductor integrated circuit according to the present embodiment. FIG. 8 shows a schematic configuration of an example of a computer system used for carrying out the semiconductor integrated circuit design method according to the present embodiment. Here, the computer system shown in FIG. 8 includes, for example, a central processing unit (CPU) 1 that performs calculation and control such as circuit simulation, a memory 2 that stores various simulation models and data necessary for the model, and a simulation. 2 includes an input unit 3 for inputting data such as necessary conditions, an output unit 4 for outputting simulation results, and a bus 5 for connecting the CPU 1, the memory 2, the input unit 3 and the output unit 4 to each other.

  First, in step S11, a semiconductor integrated circuit (hereinafter referred to as a target circuit) is designed, a net list of the target circuit is generated, and the net list is input to the input unit 3. Further, the use conditions of the target circuit are set based on the input / output signals of the target circuit, and the use conditions are input to the input unit 3.

  Subsequently, in step S12, a transistor incorporated in the semiconductor integrated circuit is searched and extracted. Specifically, the transistor is searched and extracted from the net list input in step S11.

  Next, in step S13, the stress bias condition of each transistor is extracted based on the circuit use condition input in step S11. Specifically, for example, a SPICE (Simulation Program with Integrated Circuit Emphasis) simulation is performed based on the circuit use conditions to obtain the stress bias condition applied to each transistor.

  Next, in step S14, a circuit simulation of the target circuit is performed in a state where there is no characteristic variation due to transistor deterioration.

  Here, in parallel with step S14, the stress applied to each transistor in step S15 based on the magnitude of the electric field strength applied to the gate insulating film of each transistor (hereinafter referred to as the gate insulating film electric field strength). Classify bias conditions. Here, the magnitude of the electric field strength may be calculated using, for example, a TCAD (Technology Computer Aided Design) simulation technique.

  Next, in step S <b> 16, a characteristic variation model due to transistor degradation (hereinafter referred to as a characteristic variation model) is input to the input unit 3 in accordance with the classification of the stress bias condition based on the gate insulating film electric field strength. At this time, a model corresponding to the classification of the stress bias condition may be selected from a plurality of models stored in the memory 2 in advance.

  Next, in step S17, using the circuit simulation result in step S14 (result of circuit simulation in the absence of characteristic variation due to transistor degradation) and the characteristic variation model selected in step S16, the characteristic degradation of each transistor. Perform a simulation. Here, as a parameter indicating the characteristics of the transistor, for example, a threshold voltage of the transistor, a current value flowing through the transistor, or the like can be used.

  Next, in step S18, circuit simulation of the target circuit (target circuit after characteristic change due to transistor deterioration) is performed using the transistor characteristics after deterioration obtained in step S17.

  Next, in step S19, it is determined whether a circuit operation margin can be secured for each of the initial transistor characteristics and the deteriorated transistor characteristics. If the determination is OK, the target circuit is designed as having no problem. finish. On the other hand, if the determination in step S19 is NG, the circuit design is performed again.

  When redoing the circuit design, it is determined in step S20 whether or not the reliability design margin (design margin) can be corrected. If the correction is possible, the initial design is performed based on the reliability design margin after the correction. The circuit operation determination in step S19 is performed again for each of the transistor characteristics and the transistor characteristics after deterioration (that is, the simulation results of steps S14, S17, and S18). On the other hand, if it is determined in step S20 that the reliability design margin cannot be corrected, in step S21, the circuit configuration, transistor dimensions, etc. are reviewed, and then the circuit design is restarted from step S11. .

  In this embodiment, in step S16, a characteristic variation model (characteristic variation model) due to transistor degradation is selected according to the classification of the stress bias condition based on the electric field strength of the gate insulating film, and the selected characteristic variation model is selected. Thus, the characteristic deterioration simulation of each transistor was performed to determine the transistor characteristics after deterioration. However, instead of this, in accordance with the classification of the stress bias condition based on the electric field strength of the gate insulating film, actual measurement data of transistor characteristic degradation is obtained in advance, and the transistor characteristics after degradation are obtained using the actual measurement data. May be.

  The difference between the semiconductor integrated circuit design method according to this embodiment shown in the flowchart of FIG. 1 and the semiconductor integrated circuit design method according to the comparative example shown in the flowchart of FIG. 5 will be described below.

  In steps S51 to S54 and S56 to S61 in the flowchart of the comparative example shown in FIG. 5, the same processes as steps S11 to S14 and S16 to S21 in the flowchart of the present embodiment shown in FIG.

  That is, the difference between the flowchart of this embodiment shown in FIG. 1 and the flowchart of the comparative example shown in FIG. 5 is that, in the flowchart of the comparative example shown in FIG. 5, step S15 of the flowchart of this embodiment shown in FIG. That is, there is no processing for classifying stress bias conditions based on the electric field strength of the gate insulating film.

  Specifically, in the comparative example, after extracting the stress bias condition of each transistor in step S53, when inputting the characteristic variation model due to transistor deterioration in step S56, the characteristic variation model is used regardless of the content of the stress bias condition. Determine unambiguously. That is, in the comparative example, a characteristic variation model due to transistor deterioration assuming a logic circuit operation is input.

  FIG. 6 schematically shows the relationship between the stress bias voltage applied to the transistor in the logic circuit operation and the transistor deterioration. The three axes in FIG. 6 are the gate-substrate voltage Vgb, the drain-substrate voltage Vdb, and the source-substrate voltage Vsb, respectively. Further, “Vrat” on each axis in FIG. 6 represents a maximum rated voltage (Rating Voltage). As shown in FIG. 6, the transistor degradation in the logic circuit operation includes NBTI degradation and HC degradation (specifically, Channel Hot Carrier (HC-CHC) degradation and Isubmax (Isubmax)) depending on the stress bias voltage applied to the transistor. HC-Isubmax) degradation).

  FIG. 7 shows characteristic variation due to NBTI degradation as an example of characteristic variation due to transistor degradation in the DC (direct current) operation of the logic circuit. As shown in FIG. 7, the dependence of the stress time (Time) on the exponential function strongly appears in the threshold voltage fluctuation (absolute value (−ΔVth)) due to the NBTI degradation of the PMOS transistor. This dependence can be modeled as (Equation 1) below.

ΔVth (t) = C ₁ × t ⁿ (Equation 1)
Here, C ₁ and n are constants, and t is a stress time (accumulated time since the start of applying a stress bias voltage to the transistor).

  However, if the semiconductor integrated circuit design method according to the comparative example described above is applied to analog circuit design, the characteristic fluctuation due to transistor deterioration is overestimated in the intermediate gate insulating film field strength region (see the intermediate field region in FIG. 2). Will end up. For this reason, reliability is ensured based on an excessive amount of deterioration prediction, so an excessive deterioration margin is set more than necessary for actual circuit operation. A large transistor is arranged to increase the chip area.

  In contrast, in this embodiment, before inputting the characteristic variation model due to transistor degradation in step S16, the stress bias condition of each transistor is extracted in step S13 in advance, and then in step S15 based on the gate insulating film electric field strength. Classify stress bias conditions. At this time, when classifying the stress bias conditions in step S15, it is efficient to obtain the relationship between the stress bias conditions and the gate insulating film electric field strength in advance. For example, in the case of a MOS type transistor, the gate insulating film electric field strength is the gate channel impurity concentration (impurity concentration of the channel region below the gate electrode), gate oxide film thickness, stress bias conditions (gate voltage, source voltage, drain voltage). , Substrate voltage) and the like. In a normal MOS transistor, it is difficult to analytically determine the gate insulating film electric field strength using a model formula due to non-uniformity of the impurity concentration under the gate channel, but gate insulation using, for example, TCAD simulation technology. It is possible to obtain the film electric field strength numerically.

  FIG. 2 schematically shows an example of a state in which the stress bias conditions applied to the transistors in the analog circuit are classified based on the magnitude of the electric field strength of the gate insulating film. The three axes in FIG. 2 are the gate-substrate voltage Vgb, the drain-substrate voltage Vdb, and the source-substrate voltage Vsb, respectively. Further, “Vrat” in each axis in FIG. 2 represents the maximum rated voltage. Although the gate insulating film electric field strength changes depending on the stress bias condition applied to each transistor, as shown in FIG. 2, in this embodiment, the stress bias condition is based on the magnitude of the gate insulating film electric field strength. Are classified into, for example, (1) a high electric field region, (2) an intermediate electric field region, and (3) a low electric field region, and a characteristic variation model due to transistor degradation is defined for each of the classifications. Note that the stress bias condition classification method (that is, the range of each electric field region) varies depending on process conditions, device structure, ambient temperature during circuit operation, and the like.

  The stress bias condition in the high electric field region shown in FIG. 2 includes a condition that causes NBTI degradation (NBTI condition) and a condition that causes HC-CHC degradation (HC-CHC condition) in logic circuit operation (see FIG. 6). ). In the characteristic variation due to transistor deterioration under the stress bias condition in the high electric field region, the exponential function dependence of the stress time shown in FIG. 7 and (Equation 1) appears strongly.

  On the other hand, under the stress bias condition in the low electric field region shown in FIG. 2, the characteristic fluctuation due to transistor degradation is small and can be ignored.

  In addition, in the transistor characteristic fluctuation under the stress bias condition in the intermediate electric field region shown in FIG. 2, for example, as shown in FIG. Here, FIG. 3 shows an example of transistor characteristic fluctuation that occurs in an analog circuit operation under a stress bias condition in an intermediate electric field region.

  Hereinafter, a mechanism of transistor characteristic variation under the above-described stress bias condition in the intermediate electric field region will be described. First, in the transistor immediately after the stress bias condition in the intermediate electric field region is applied, as shown in FIG. 3, characteristic fluctuation due to normal NBTI degradation appears. Thereafter, with the passage of stress time (Time), in the case of a PMOS transistor, the influence of electron trapping starts to appear, and the transistor characteristics turn to be improved. The occurrence of this electron trapping is considered to be due to the influence of the gate current as described below. The gate current is composed of an electron current component that flows from the gate electrode to the channel region (substrate) and a hole current component that flows from the substrate-side inversion layer (channel region) to the gate electrode. Among these, the electron current component causes electron trapping to occur at a trap site previously formed in the process step of the gate insulating film, and as a result, transistor characteristics are considered to be improved. Thereafter, when the stress time further elapses, the electron trapping is saturated and characteristic fluctuation due to NBTI degradation appears again.

  In consideration of the above-described mechanism of variation in transistor characteristics under the stress bias condition in the intermediate electric field region, in this embodiment, the variation in the threshold voltage of the transistor under the stress bias condition in the intermediate electric field region is expressed by the following (Equation 2). Model as follows.

ΔVth (t) = C ₁ × t ⁿ¹ (where t ≦ t ₁ )
C ₂ × exp (C ₃ × (log (t) −log (t ₁ ))) − C ₂₀ (where t ₁ ≦ t ≦ t ₂ )
C ₄ × t ⁿ² −C ₄₀ (where t ₂ ≦ t) (Formula 2)
Here, C ₁ , n 1, C ₂ , C ₃ , C ₂₀ , C ₄ , n 2, C ₄₀ , t ₁ , t ₂ are constants, and t is a stress time (starting to apply a stress bias condition to the transistor). Accumulated time).

In (Expression 2), the range of the stress time t is divided according to the dominant deterioration factor of the transistor characteristic fluctuation. Specifically, when t ≦ t ₁ , the transistor characteristic fluctuation component due to NBTI degradation is dominant as in (Formula 1). In addition, in t ₁ ≦ t ≦ t ₂ , the transistor characteristic fluctuation component due to electron trapping is dominant. Further, when t ₂ ≦ t, the electron trapping component is saturated, and the transistor characteristic fluctuation component due to NBTI degradation becomes dominant again.

  Each constant of (Equation 2) is determined by process conditions, device structure, ambient temperature during circuit operation, stress bias conditions (gate insulating film electric field strength), and the like. Each of these constants can be obtained by fitting data measured for each condition such as process conditions, device structure, ambient temperature, and gate insulating film electric field strength. As a result, it is possible to express the influence of transistor characteristic improvement due to electron trapping, and thus it is possible to accurately represent transistor characteristic fluctuations in the intermediate electric field region.

  Hereinafter, referring to FIGS. 4A to 4D, the semiconductor integrated circuit design method according to this embodiment (particularly, the classification of stress bias conditions based on the electric field strength of the gate insulating film, which is a feature of this embodiment (FIG. A specific procedure of one example of step S15)) will be described. FIG. 4A shows an equivalent circuit diagram of a differential pair circuit using a PMOS transistor as an example of an analog circuit to be designed.

  First, as shown in FIG. 4B, when the input voltage Vin of the transistors M1 and M2 shown in FIG. 4A is in the vicinity of the power supply voltage Vdd, the transistors M1 and M2 are cut off and current flows in the circuit. Absent. Here, Id1 and Id2 on the vertical axis in FIG. 4B indicate currents flowing through the transistors M1 and M2. The input voltage Vb of the transistor M3 shown in FIG. 4A is independent of the input voltage Vin. However, when the input voltage Vb is near the power supply voltage Vdd, the transistor M3 is cut off and the circuit is turned on. No current flows. On the other hand, as shown in FIG. 4B, when the input voltages Vin and Vb become Vdd− | Vth3 | or less, current begins to flow through the circuit, and a stress bias voltage is applied to each of the transistors M1, M2, and M3. Is done. Here, as shown in FIG. 4C, the voltage Vp at the point P shown in FIG. 4A changes linearly with respect to Vin at Vin <Vdd− | Vth3 |, and Vin> Vdd− | At Vth3 |, Vdd becomes a constant value. Note that | Vgs1 | in FIG. 4C is the value of Vp when Vin = 0V, and that at point P, the potential increases by the amount of the voltage (Vgs1) applied to the transistor M1. I mean. Further, as shown in FIG. 4D, the constant current Iss / 2 flows through each load resistance Rd shown in FIG. 4A below the voltage (Vdd− | Vth3 |) where the transistor M3 enters the saturation region. Therefore, the output voltages Vout1 and Vout2 are Iss × Rd / 2 and have a constant value.

  Here, assuming that the threshold voltage of the transistors M1 and M2 is Vth12 and | Vth12 | <Iss × Rd / 2, when the input voltage Vin is a voltage near the ground point (0 V), the transistor M1 And M2 operate in the linear region. That is, under a stress bias condition in which | Vth12 | <Iss × Rd / 2 and the input voltage Vin is near the ground point (0 V), the transistor M3 operates in saturation, and the stress bias condition is a stress bias condition in a high electric field region. On the other hand, the transistors M1 and M2 operate linearly, and the stress bias condition is classified as a stress bias condition in an intermediate electric field region. Therefore, for example, Equation 1 may be used as the threshold voltage variation model of the transistor M3, and Equation 2 may be used as the threshold voltage variation model of the transistors M1 and M2.

  In the above description, the characteristic variation due to NBTI degradation in the PMOS transistor is assumed, but the same applies to the characteristic variation due to PBTI (Positive Bias Temperature Instability) degradation of the NMOS (N-channel Metal Oxide Semiconductor) transistor. Can be applied. In this case, in the transistor characteristic fluctuation under the stress bias condition in the intermediate electric field region, hole trapping is performed on the trap site of the gate insulating film due to the hole current component flowing from the gate electrode to the channel region (substrate) in the gate current. As a result, a phenomenon occurs in which the characteristics of the NMOS transistor are improved.

  As described above, according to the present embodiment, the stress bias conditions applied to the transistor are classified based on the magnitude of the electric field strength applied to the gate insulating film of the transistor included in the analog circuit. According to the classification of the stress bias condition, it becomes possible to obtain the transistor characteristics after deterioration. For this reason, compared to the conventional case of predicting characteristic fluctuations due to transistor degradation assuming a unique bias voltage, the transistor characteristics after degradation can be predicted more accurately, ensuring a design margin that guarantees circuit operation. can do. Therefore, an increase in transistor size, that is, an increase in chip area can be prevented, and the reliability of the semiconductor integrated circuit device can be improved.

  As described above, the semiconductor integrated circuit design method according to the present invention can accurately predict characteristic variation due to transistor degradation that occurs in analog circuit operation, and in particular, a transistor that is a component of an analog circuit. This is useful as a method for designing a semiconductor integrated circuit in consideration of characteristic variation due to deterioration.

1 Central processing unit (CPU)
2 Memory 3 Input unit 4 Output unit 5 Bus S11, S51 Circuit net list and circuit use condition input step S12, S52 In-circuit transistor search / extraction step S13, S53 In-circuit transistor stress bias condition extraction step S14, S54 Circuit simulation execution step without transistor characteristic deterioration S15 Stress bias condition classification step based on gate insulating film electric field strength S16, S56 Transistor characteristic variation model input step S17, S57 Transistor characteristic deterioration simulation execution step S18, S58 Transistor characteristic deterioration Subsequent circuit simulation execution step S19, S59 Circuit operation determination step S20, S60 Reliability design margin correction possibility determination step S21, S61 Review step of the transistor

Claims (7)

Extracting a transistor included in the semiconductor integrated circuit (a);
Classifying a stress bias condition to be applied to the transistor based on the magnitude of the electric field strength applied to the gate insulating film of the transistor extracted in the step (a);
(C) obtaining a post-degradation characteristic of the transistor according to the classification of the stress bias condition in the step (b);
And (d) performing circuit simulation of the semiconductor integrated circuit using the degraded transistor characteristics obtained in the step (c). The method for designing a semiconductor integrated circuit according to claim 1,
In the step (b), as an index of the magnitude of the electric field strength applied to the gate insulating film, a first electric field strength region, a second electric field strength region smaller than the first electric field strength region, and the A design method of a semiconductor integrated circuit, wherein a third electric field strength region smaller than the second electric field strength region is set, and the stress bias condition is classified for each electric field strength region. The method for designing a semiconductor integrated circuit according to claim 1 or 2,
In the step (c), the transistor characteristic after the deterioration is obtained by using the measured data of the characteristic deterioration of the transistor. The method for designing a semiconductor integrated circuit according to claim 1 or 2,
A method for designing a semiconductor integrated circuit, wherein, in the step (c), a transistor characteristic after the deterioration is obtained using a model expression of the characteristic deterioration of the transistor. The method of designing a semiconductor integrated circuit according to claim 4,
The method of designing a semiconductor integrated circuit, wherein the model formula is a function of an accumulated time since the application of the stress bias condition to the transistor is started. In the design method of the semiconductor integrated circuit of any one of Claims 1-5,
In the step (c), a threshold voltage of the transistor is obtained as the transistor characteristics after the deterioration. In the design method of the semiconductor integrated circuit of any one of Claims 1-5,
In the step (c), a value of a current flowing through the transistor is obtained as the transistor characteristics after the deterioration.

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