JP2013003479A - Liquid crystal display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which prevents a screen beat noise due to interference of a dimming frequency of a back light at low cost without interfering with a radio bandwidth, and its driving method.SOLUTION: The liquid crystal display device includes: a liquid crystal display part 170 for displaying a video by driving each pixel by TFT; a backlight unit 160 for supplying light to the liquid crystal display part 170 on the basis of a back light dimming signal; a gate control part 150 for supplying a gate voltage of TFT of each pixel; a first signal control part 110 for generating a gate clock signal which controls an output period of the gate control part 150; and a second signal control part 120 for supplying a control signal which corrects a voltage of a pixel electrode of each pixel of the liquid crystal display part 170 on the basis of the back light dimming signal and the gate clock signal.

Description

  The present invention relates to a liquid crystal display device such as a liquid crystal display module and a driving method thereof, and more particularly to a liquid crystal display device and a driving method thereof that can reduce interference noise when a high-brightness backlight is used.

  When dimming the brightness of the backlight in a liquid crystal display, screen beat noise occurs due to interference between the dimming frequency of the backlight driver (PWM pulse frequency) and the frame frequency of the drive signal input to the liquid crystal display. Sometimes. Screen beat noise refers to noise in which wavy or horizontal stripes appear on the entire screen.

  In recent years, the number of in-vehicle devices with a liquid crystal display has increased, and many of them are compatible with inputs of a plurality of systems such as the NTSC system and the PAL system. Since the frequency of the drive signal of the liquid crystal display is different in each method, there is a problem that the frequency of the drive signal in a certain method interferes with the dimming frequency of the inverter and a beat occurs on the screen.

  There are several causes of this screen beat noise, and one of them is the optical characteristics of TFT (Thin Film Transistor). A TFT is a switching (driving) element disposed in each pixel of a liquid crystal display. Generally, a-Si (Amorphous Silicon) used for this has a property of reacting to light. The a-Si TFT has a conductor property when irradiated with light, and has a non-conductor property when not irradiated with light. Due to this property, when light is applied to the a-Si TFT, the parasitic capacitance in the pixel increases and the luminance changes. When the brightness changes in one screen due to ON / OFF of the backlight, screen beat noise appears.

  When the light from the backlight unit is irradiated constantly, the light spreads over the entire surface of the liquid crystal panel, so there is no change in luminance within one screen and there is no problem of screen beat noise. However, when adjusting the luminance of the backlight by a PWM (Pulse-Width Modulation) method in which the backlight is periodically turned on / off in order to adjust the luminance, the above-described problem occurs.

  If the frame frequency of the drive signal and the PWM dimming frequency are not synchronized, regular movement of the band is observed for each frame, resulting in a screen beat flowing on the screen, and conversely, the frame frequency of the drive signal and the PWM dimming frequency are When there is a multiplication relationship and synchronization, the screen beat appears at a fixed position in the screen.

  Regarding the screen beat noise caused by the optical characteristics of the TFT, there are countermeasures in the TFT manufacturing process, but the number of manufacturing processes increases, leading to a decrease in production capacity and an increase in cost. Therefore, various countermeasures have been studied in the liquid crystal display driving circuit.

  In order to suppress the occurrence of screen beat noise in LCD TVs for Europe, etc., the dimming frequency of the backlight driver is set to the optimal dimming frequency, which is the least likely to cause screen beat noise, according to the frame frequency of the input drive signal. We are taking measures to switch. Patent Documents 1 and 2 are cited as documents disclosing techniques for controlling the dimming frequency of the backlight driver in order to suppress screen beat noise, for example.

JP 2010-152337 A JP 2007-171609 A

  However, the conventional dimming frequency variable measure and the method of synchronizing the dimming frequency with the video synchronization signal have a problem that harmonic components are generated as interference noise in a frequency band such as a radio. This is a problem for devices with a radio function.

  The present invention has been made to solve the conventional problems, and avoids an increase in the cost of the liquid crystal display such as a change in the manufacturing method of the TFT, and maintains a frequency that does not affect other frequency bands such as a radio while maintaining screen beat noise. An object of the present invention is to provide a liquid crystal display device and a driving method thereof that can prevent the above-described problem.

  In order to achieve the above object, a first aspect of the present invention is directed to a liquid crystal display device. The liquid crystal display device of the present invention includes a liquid crystal display unit that displays an image by driving each pixel by a TFT, a backlight unit that supplies light to the liquid crystal display unit based on a backlight dimming signal, and each pixel. A liquid crystal display based on a gate control unit for supplying a gate voltage of the TFT, a first signal control unit for generating a gate clock signal for controlling an output cycle of the gate control unit, a backlight dimming signal, and a gate clock signal And a second signal control unit that supplies a control signal for correcting the voltage of the pixel electrode of each pixel of the unit.

  The second signal control unit is level-adjusted with a drive signal generation unit that generates a drive signal based on the backlight dimming signal and the gate clock signal, a voltage level adjustment unit that adjusts the voltage level of the drive signal, A current amplifying unit configured to generate the control signal obtained by amplifying the drive signal;

  The drive signal generation unit outputs a drive signal having the same phase and the same frequency as the gate clock signal while the backlight dimming signal is on.

  Here, the voltage level adjustment unit is configured to be able to adjust the voltage level from the outside.

  The second aspect of the present invention is directed to a driving method of a liquid crystal display device that displays an image by driving each pixel by a TFT. The driving method of the liquid crystal display device of the present invention includes a backlight dimming signal for dimming light supplied to the liquid crystal display unit of the liquid crystal display device, and a gate control unit for supplying a gate voltage to the TFT of each pixel. Based on the gate clock signal for controlling the output period, a control signal for correcting the voltage of the pixel electrode of each pixel is generated and supplied.

  Here, the voltage level of the control signal is adjusted from the outside.

  According to the liquid crystal display device and the driving method thereof of the present invention, the screen is maintained while maintaining a frequency that does not affect other frequency bands such as a radio by eliminating the luminance difference in one screen due to ON / OFF of the backlight. Beat noise can be prevented.

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. Schematic configuration diagram of one pixel of the liquid crystal display device shown in FIG. Equivalent circuit diagram of schematic configuration of one pixel shown in FIG. A cross-sectional view of the TFT 210 shown in FIG. The figure explaining the change of pixel electrode voltage Detailed block diagram of the second signal control unit 120 shown in FIG. 6 is a circuit diagram of the second signal control unit 120 in FIG. The timing chart which shows the relationship between the input signal and output signal of the 2nd signal control part 120 shown in FIG.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a schematic configuration diagram of one pixel of the liquid crystal display device shown in FIG. As shown in FIG. 1, the liquid crystal display device according to the present embodiment includes a first signal control unit 110, a second signal control unit 120, a backlight control unit 130, a source control unit 140, a gate control unit 150, and a backlight unit. 160, a display unit 170, and a gradation voltage generation unit 180.

  Referring to FIG. 1, the first signal control unit 110 is connected to a drawing microcomputer (not shown) that outputs an input video signal (R, G, B) and an input control signal to the first signal control unit 110. Then, a signal for driving the source control unit 140 and the gate control unit 150 is generated using the input control signal. Examples of the input control signal include a horizontal synchronization signal (HSYNC), a vertical synchronization signal (VSYNC), a clock signal (CLK), and a data enable signal (DE). For the first signal control unit 110, for example, a timing controller is used.

  The second signal control unit 120 receives the backlight dimming signal (hereinafter referred to as BLPWM) and the gate clock signal (hereinafter referred to as GSC) from the first signal control unit 110, and supplies the control signal Vst to the display unit 170. To do. Here, BLPWM is a signal for dimming the backlight, and is a signal periodically turned on / off having a predetermined duty ratio by a pulse width modulation (PWM) method. GSC is a signal for controlling the shift timing of the gate-on voltage (VGH) output by the gate control unit 150, which will be described later, for each line or every plurality of lines.

  The backlight control unit 130 supplies power and current periodically turned on / off to the backlight unit 160. For the backlight control unit 130, for example, an LED driver circuit or an inverter circuit is used.

  The display unit 170 includes, on an equivalent circuit, a plurality of signal lines (S1 to Sm, G1 to Gn) and a plurality of pixels (Pix) connected to these and arranged in a matrix shape. Referring to FIG. 2, each pixel (Pix) of the display unit 170 includes a pixel electrode 240 and a common electrode 220 facing each other and a liquid crystal layer 230 interposed therebetween.

  The signal lines S1 to Sm and G1 to Gn indicate source lines (S1 to Sm) that transmit source voltages and gate lines (G1 to Gn) that transmit gate signals (also referred to as “scanning signals”), respectively. The source lines (S1 to Sm) extend in the column direction and are parallel to each other, and the gate lines (G1 to Gn) extend in the row direction and are parallel to each other.

  Each pixel (Pix) includes a switching element (TFT) 210 connected to the signal lines (S1 to Sm, G1 to Gn), a liquid crystal capacitor (Clc) 230 connected thereto, and a storage capacitor (Cst) 250. The switching element (TFT) 210 has a control terminal connected to a gate line, an input terminal connected to a source line, and an output terminal connected to a liquid crystal capacitor (Clc) 230 and a storage capacitor (Cst) 250.

  The liquid crystal capacitor (Clc) 230 is connected to the pixel electrode 240 and the common electrode 220. The pixel electrode 230 is connected to the switching element (TFT) 210 and receives the source voltage from the source line, and the common electrode 220 receives the common voltage (Vcom). Unlike FIG. 2, the common electrode 220 may be disposed on the same side as the pixel electrode 240 when viewed from the liquid crystal capacitor (Clc) 230. Further, the two electrodes 220 and 240 may be formed in a bar shape instead of a flat plate.

  The storage capacitor (Cst) 250 serves as an auxiliary to the liquid crystal capacitor (Clc) 230 and has a function of assisting in maintaining the pixel voltage.

  Color display includes a space division method and a time division method. In the space division method, each pixel (Pix) has a basic color, and a color is expressed by a combination of basic colors. For example, the three primary colors of red, green, and blue are used as basic colors, and pixels are arranged in vertical and horizontal stripes to express the color as a spatial sum. The spatial arrangement of the basic colors is realized by, for example, arrangement of a color filter (not shown) of the basic color in a region above or below the common electrode 220 corresponding to each pixel (Pix). The color filter may be disposed above or below the pixel electrode 240. In the time division method, pixels (Pix) alternately display basic colors according to time and display a desired color as a temporal sum.

  The display unit 170 may be provided with a polarizer (not shown) on one or both of the pixel electrode 240 side and the common electrode 220 side.

  The gradation voltage generator 180 generates a gradation voltage (hereinafter referred to as Vref) related to the transmittance of the pixel (Pix). The generated Vref is supplied to the source control unit 140. The gradation voltage may include a positive voltage and a negative voltage with respect to the common voltage (Vcom).

  The source control unit 140 is connected to the source lines (S1 to Sm) of the display unit 170, selects the grayscale voltage from the grayscale voltage generation unit 180, and uses the grayscale voltage as the source voltage (S1 to Sm). Apply to. However, the gray voltage generator 180 may provide only some reference gray voltages instead of all gray voltages. In such a case, the source controller 140 may divide the reference gray voltages and desire them. Generate a source voltage.

  The gate control unit 150 is connected to the gate lines (G1 to Gn) of the display unit 170, and applies either a gate-on voltage (VGH) or a gate-off voltage (VGL) to the gate lines (G1 to Gn).

  The backlight unit 160 receives a backlight signal (BLCONT) from the backlight control unit 130 and supplies light to the display unit 170. The backlight unit 160 may include a plurality of light elements (not shown), and the light elements may be LEDs (Light Emitting Diodes) or CCFLs (Cold Cathode Fluorescent Lamps).

  The first signal control unit 110 controls the source control unit 140 and the gate control unit 150. The second signal control unit 120 supplies the Vst signal to the storage capacitor (Cst) 250 of the display unit 170 and corrects the voltage applied to the pixel electrode 240. The backlight control unit 130 controls the backlight unit 160.

  There are several methods for mounting the first signal control unit 110, the second signal control unit 120, the backlight control unit 130, the source control unit 140, the gate control unit 150, and the gradation voltage generation unit 180. For example, a COG (Chip On Glass), which is directly mounted on the display unit 170 in the form of at least one integrated circuit chip, or a flexible printed circuit film (not shown) attached to the display unit 170. There is a COF (Chip On Film) implemented on

  Moreover, you may mount on a separate circuit board (Printed Circuit Board) (not shown). Unlike this, the first signal control unit 110, the second signal control unit 120, the backlight control unit 130, the source control unit 140, the gate control unit 150, and the gradation voltage generation unit 180 are connected to the signal lines (G1 to G1). Gn, S1 to Sm) and the switching element (TFT) 210 may be integrated in the display unit 170.

The operation of the liquid crystal display device configured as described above will be described below.
The first signal control unit 110 receives an input video signal (R, G, B) and an input control signal for controlling the display from an external drawing microcomputer or graphic controller (not shown). The input video signal (R, G, B) includes gradation (brightness level) information of each pixel (Pix), and the number of gradations is expressed in digital bits. For example, a 10-bit input video signal has a gradation of 2 10 (= 1024), and an 8-bit input video signal has a power of 2 (= 256) and a 6-bit input video signal. For example, it has 2 6 (= 64) gradations. Input video signals (R, G, B) and input control signals in the present embodiment may be supplied by a low voltage differential signal transmission method (hereinafter referred to as LVDS).

  Further, the first signal control unit 110 matches the input video signal (R, G, B) with the operation condition of the display unit 170 based on the input video signal (R, G, B) and the input control signal. Appropriate processing is performed to generate a video signal (R, G, B), a source control signal (Logic 1), and a gate control signal (Logic 2). Thereafter, the first signal control unit 110 transmits the source control signal (Logic 1) and the processed video signals (R, G, B) to the source control unit 140 and the gate control signal (Logic 2) to the gate control unit 150.

  The source control signal (Logic 1) is input of a clock (SSC) for informing the timing of capturing the video signal (R, G, B) and the video signal (R, G, B) for one line to the source control unit 140. A horizontal synchronization start signal (SSP) for informing timing and a load signal (LOAD) for informing the output timing of the analog source voltage to the source lines (S1 to Sm) are included. The source control signal (Logic 1) is inverted when the inverted signal (POL) for inverting the polarity of the analog source voltage with respect to the common voltage (Vcom) or when the source control unit 140 captures the video signal (R, G, B). A signal (REV) to be generated may be included.

  The gate control signal (Logic 2) includes a scanning start signal (GSP) for instructing the start of scanning and a GSC for controlling the output cycle of the gate-on voltage (VGH). Further, the gate control signal (Logic2) may further include a signal (XON) for setting the total output voltage of the gate control unit 150 to the gate-on voltage (VGH) and an enable signal (GOE) for setting the total output voltage to the gate-off voltage (VGL). Good.

  The source control unit 140 receives the video signal (R, G, B), selects a gradation voltage (Vref) corresponding to the received video signal (R, G, B), and generates a corresponding analog source voltage. Then, this is applied to the corresponding source lines (S1 to Sm) at the timing of the load signal (LOAD).

  The gate control unit 150 applies a gate-on voltage (VGH) to the gate lines (G1 to Gn) according to the gate control signal (Logic2) from the first signal control unit 110, and applies to the gate lines (G1 to Gn). The connected switching element (TFT) 210 is turned on. In the display unit 170, the analog source voltage applied to the source lines (S1 to Sm) is applied to the corresponding pixel (Pix) through the switching element (TFT) that is turned on.

  The difference between the analog source voltage applied to the pixel (Pix) and the common voltage (Vcom) appears as the pixel voltage of the liquid crystal capacitor (Clc). The amount of light transmitted from the backlight unit 160 is determined by the magnitude of the pixel voltage. Specifically, it is as follows. The orientation of the liquid crystal molecules in the liquid crystal layer changes depending on the magnitude of the pixel voltage.

  The light emitted from the backlight unit 160 passes through the polarizer and becomes linearly polarized light, and then passes through the liquid crystal layer. The direction of linearly polarized light changes depending on the alignment state of the liquid crystal molecules that pass therethrough. The light whose direction of linearly polarized light has changed passes through the polarizer again, and thus appears as a change in light transmittance. Through the above operation, the pixel (Pix) displays the luminance indicated by the gradation of the digital video signal (R, G, B). Note that light that has passed through the polarizer and the liquid crystal layer can pass through the color filter to display a color.

  The above-described process is performed for one line from the first gate line G1 to the gate line Gn with one horizontal period (also called 1H, the same period as one period of the horizontal synchronization signal (HSYNC) and the data enable signal (DE)) as one unit. A gate-on voltage (VGH) is sequentially applied, a source voltage is applied to all the pixels (Pix), and one frame of video is displayed.

  When one frame ends, the next frame starts and the output state of the source control unit 140 is controlled so that the polarity of the source voltage applied to each pixel (Pix) is opposite to the polarity in the previous frame ( Frame inversion). For example, this inversion operation is controlled by an inversion signal (POL) applied to the source control unit 140. Also, within one frame, the polarity of the analog source voltage applied through the source line periodically changes (line inversion or dot inversion) according to the characteristics of the inversion signal (POL), or one adjacent pixel The applied analog source voltages may have different polarities (column inversion or dot inversion).

  FIG. 3 is an equivalent circuit diagram of a schematic configuration of one pixel shown in FIG. 4 is a cross-sectional view of the switching element (TFT) 210 of FIG. FIG. 5 is a diagram for explaining a change in the voltage of the pixel electrode 240.

  Referring to FIG. 3, each pixel includes a parasitic capacitor (Cgd) 310 in addition to the switching element (TFT) 210, the liquid crystal capacitor (Clc) 230, and the storage capacitor (Cst) 250 described above.

  According to FIG. 4, the value of the parasitic capacitor (Cgd) 310 changes depending on whether light is applied to the switching element (TFT) 210. This is due to the influence of a-Si 410 and a-Si (n +) 420 used in the switching element (TFT) 210. The a-Si 410 and the a-Si (n +) 420 have a conductive property when irradiated with light, and have a non-conductive property when not irradiated with light. Due to this property, the value of the storage capacitor (Cgd) 310 changes depending on the presence or absence of light irradiation.

  According to FIG. 5, after an analog source voltage is applied to each pixel (Pix) on the gate line Gi through the switching element (TFT) 210, the gate voltage of the switching element (TFT) 210 is changed to the gate-on voltage (voltage holding). VGH) changes to gate-off voltage (VGL). At this time, the pixel voltage is reduced by ΔV due to the influence of the parasitic capacitor (Cgd) 310.

  ΔV is expressed by the following equation.

ΔV = ΔVg × {Cgd / (Cgd + Clc + Cst)}
However, ΔVg: gate voltage change amount (VGH−VGL)
Cgd: Parasitic capacitor between gate and drain Cst: Storage capacitor Clc: Liquid crystal capacitor When Cgd_off is a parasitic capacitor when the backlight is off and Cgd_on is a parasitic capacitor when the backlight is on, the relationship is Cgd_on> Cgd_off. Therefore, the relationship between ΔV_on when the backlight is on and ΔV_off when the backlight is off is ΔV_on> ΔV_off.

  6 is a detailed block diagram of the second signal control unit 120 shown in FIG. 1, and FIG. 7 is a circuit diagram thereof. FIG. 8 is a timing chart of input signals and output signals of the second signal control unit 120 shown in FIG. In addition, the horizontal broken line in FIG. 8 has shown the GND level of each signal.

  In FIG. 6, the second signal control unit 120 includes a drive signal generation unit 121 such as a counter or a flip-flop, a level adjustment unit 122, and a current amplification unit 123.

  The drive signal generation unit 121 uses BLPWM and GSC as input signals, and transmits an output corresponding to these signals to the voltage level adjustment unit 122. The voltage level adjustment unit 122 is configured to convert the signal from the drive signal generation unit 121 into a negative voltage, and includes a negative voltage generation circuit. A signal (voltage) generated by the negative voltage generation circuit is assumed to be Vsig. Note that the negative voltage generation circuit has a function capable of adjusting the voltage level of Vsig from the outside. For example, voltage level adjustment methods include voltage division using a variable resistor and a method using a DAC. The final stage current amplifier 123 includes, for example, an operational amplifier, a push-pull circuit, and the like.

  The drive signal generation unit 121 outputs a rectangular wave having the same phase and the same frequency as the input GSC only during a period when BLPWM is on. This drive signal is referred to as CONT1. The voltage level adjustment unit 122 receives the CONT1 signal, and outputs a negative voltage when the CONT1 is off (low) and a signal (CONT2) that becomes the GND level when the CONT1 is on (high) to the current amplification unit 123. The current amplifying unit 123 receives CONT2, and outputs a control signal (Vst) for correction to the Vst line with a sufficiently large current capacity that functions for luminance correction through the storage capacitor (Cst).

  The shift amount of ΔV can be corrected by supplying the Vst signal shown in FIG. 8 to the pixel electrode 240 through the storage capacitor (Cst). The correction voltage (ΔV−correction) is expressed by the following equation.

ΔV-correction = ΔVst × {Cst / (Cgd + Clc + Cst)}
However, ΔVst: Vst voltage change amount (difference between Vst signal high and low)
Cgd: parasitic capacitor between gate and drain Cst: storage capacitor Clc: liquid crystal capacitor The above ΔVst is a negative voltage (Vsig) generated by the negative voltage generation circuit in the voltage level adjustment unit 122 of the second signal control unit 120. It is the difference in GND. The negative voltage (Vsig) generated by the voltage level adjustment unit 122 is variable as described above.

  By correcting ΔV (ΔV_on) when the backlight is on with this correction voltage (ΔV-correction), ΔV (ΔV_on and ΔV_off in FIG. 5) is the same when the backlight is on and off, and screen beat noise is reduced. It becomes possible to prevent.

  Note that ΔV (including ΔV_on and ΔV_off) varies due to variations in TFT characteristics. In response to the variation, the negative voltage generation circuit in the voltage level adjustment unit 122 is configured to be able to adjust the voltage level linearly from the outside. Note that the negative voltage generation circuit in the voltage level adjustment unit 122 is changed to a positive voltage generation circuit, and the generated voltage may be a positive voltage.

  7, a portion corresponding to the drive signal generation unit 121 in FIG. 6 corresponds to a logic IC (AND Gate) 710, a portion corresponding to the voltage level adjustment unit 122 corresponds to an analog switch (A-SW) 720, and a current amplification unit 123. The location to be used is a voltage follower circuit (op-amp) 730. With this configuration, the logic IC 710 outputs a high voltage only when both BLPWM and GSC are on (high), so that a desired CONT1 signal can be obtained. In the analog switch 720, CONT2 can be obtained by using a configuration in which a negative voltage is output when the GND level is low when CONT1 is high. The negative voltage (Vsig) is variable in voltage level. The voltage follower circuit 730 at the final stage performs current amplification and outputs it as a Vst signal.

  In the example of FIG. 8, the Vst signal is set to the GND level when BLPWM is high, but the polarity of Vst is not questioned during the low period of BLPWM (it may be high or low).

  As described above, according to the present embodiment, the storage capacitor (Cst) is provided and one end is connected to the Vst line, and the second signal control unit 120 includes the Vst signal supply circuit. Since the difference in ΔV due to the backlight on / off can be corrected, the luminance change at the time of backlight on and off can be corrected and made uniform. Thereby, screen beat noise can be prevented.

  According to the liquid crystal display device of the present invention, since the backlight dimming frequency can be made constant regardless of the video system, the dimming frequency can be fixed to a frequency that does not interfere with the radio band, and further reduction of radio noise. An effect is obtained.

  In addition, by taking measures against screen beat noise by the drive circuit without changing the structure of the switching element (TFT) of the liquid crystal cell, it is possible to prevent an increase in the number of liquid crystal cell production processes and mask development costs. A good-quality liquid crystal display device can be obtained.

  The liquid crystal display device and the driving method thereof according to the present invention eliminates the luminance difference within one screen due to ON / OFF of the backlight, thereby maintaining the screen beat noise while maintaining a frequency that does not affect other frequency bands such as a radio. This is useful for TVs, in-vehicle devices with displays, monitors, mobile phones, and the like.

110 First signal control unit 120 Second signal control unit 121 Drive signal generation unit 122 Voltage level adjustment unit 123 Current amplification unit 130 Backlight control unit 140 Source control unit 150 Gate control unit 160 Backlight unit 170 Display unit 180 Gradation voltage Generator 210 Switching element (TFT)
220 Common electrode 230 Liquid crystal capacitor (Clc)
240 pixel electrode 250 storage capacitor (Cst)
310 Parasitic capacitor (Cgd)
410 a-Si
420 a-Si (n +)
430 Drain electrode 440 Gate
710 Logic IC (AND Gate)
720 Analog switch (A-SW)
730 Voltage Follower Circuit

Claims (6)

A liquid crystal display unit that displays an image by driving each pixel by a TFT, a backlight unit that supplies light to the liquid crystal display unit based on a backlight dimming signal, and a gate voltage of the TFT of each pixel The liquid crystal display unit based on the gate control unit to be supplied, the first signal control unit for generating a gate clock signal for controlling the output cycle of the gate control unit, the backlight dimming signal and the gate clock signal. A liquid crystal display device comprising: a second signal control unit that supplies a control signal for correcting a voltage of a pixel electrode of each pixel. The second signal control unit includes a drive signal generation unit that generates a drive signal based on a backlight dimming signal and a gate clock signal, a voltage level adjustment unit that adjusts a voltage level of the drive signal, and the level adjustment. The liquid crystal display device according to claim 1, further comprising a current amplifying unit that generates the control signal obtained by amplifying the drive signal. 3. The liquid crystal display device according to claim 2, wherein the drive signal generation unit outputs a drive signal having the same phase and the same frequency as the gate clock signal during a period in which the backlight dimming signal is on. 4. The liquid crystal display device according to claim 2, wherein the voltage level adjustment unit can adjust the voltage level from the outside. A driving method of a liquid crystal display device that displays an image by driving each pixel by a TFT, the backlight dimming signal for dimming light supplied to the liquid crystal display unit of the liquid crystal display device, A control signal for correcting the voltage of the pixel electrode of each pixel is generated and supplied based on a gate clock signal for controlling an output cycle of a gate control unit that supplies a gate voltage to the TFT of each pixel. For driving a liquid crystal display device. 6. The method of driving a liquid crystal display device according to claim 5, wherein the voltage level of the control signal is adjusted from the outside.

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