JP2012529874A - Optical interconnection structure for high-speed and high-density communication systems - Google Patents

Abstract

By using a pulse amplitude modulation (PAM) technique to represent optical domain data, while using separate channels to transmit the optical clock signal, large serialization / parallelization (SERDES) functions An optical interconnect configuration for use in high speed data applications that eliminates the need is provided, eliminating the need for a clock recovery circuit at the receiving end of such a configuration.
[Selection] Figure 5

Description

  This application claims the benefit of US Provisional Application No. 61 / 186,718, filed Jun. 12, 2009 and incorporated herein by reference.

  This application relates to optical coupling arrangements, and more particularly to arrangements that reduce the need for extensive serialization / parallelization (SERDES) functionality by utilizing pulse amplitude modulation (PAM) techniques with separate transmission channels for clock signals.

  The constant demand for computing and networking applications has increased the demand for high performance computing (HPC) platforms along with large data centers. In either case, the coupling between computer servers or network nodes has not kept pace with the growth of computing power within the chip or server. The obstacles are communication power, size, and waiting time between chips as well as communication power, size, and waiting time between servers, but are not limited thereto. In more recent applications, optical fibers are used as physical links between chips (or servers) because the bandwidth of optical fibers is significantly greater than standard copper interconnects.

  Processing on the chip itself is typically performed using parallel words that are multiple bits wide (a typical parallel word has a width of 8, 16, 32, or 64 bits). Transferring such information from the first chip to the second chip usually requires converting parallel words to serial form to reduce pin count at the edge of the chip, otherwise The physical package probably needs to handle parallel numbers with high output loads.

  For this reason, serialization processing is usually performed at the edge of the chip, generating serial data from parallel words. At the receiving end of the communication path, the parallelization function needs to reformat the incoming serial data to return to the parallel word structure used in the receiving chip of the process. Such a combination of serialization and parallelization processing is often referred to in the art as “SERDES”. Furthermore, the receiving end of the system needs to perform clock recovery on the incoming serialized data stream in order to properly regenerate the parallel words.

  SERDES and clock recovery processes are problematic in that they consume significant amounts of power, while requiring high speed operation and additional latency for processes where this is expected.

  Thus, there remains a need in the art for a light-based interconnect system with improved operating characteristics.

  The need left by the prior art relates to optical cross-coupling configurations, in particular using pulse amplitude modulation (PAM) technology, and further incorporating a separate transmission channel for the clock signal, The present invention deals with a configuration that reduces the need for the parallelization (SERDES) function and eliminates the need for a clock recovery circuit at the receiving end of this configuration.

In accordance with the present invention, a multi-level PAM signal is generated from parallel data words to generate an encoded stream that can simultaneously transmit multiple bits, and the parallel data words are completely serialized at the end of the chip. Eliminate the need for The PAM may be performed on the entire word or a partial PAM technique may be employed. For example, 4 bits can be transmitted simultaneously using PAM-16 light modulation technology. Generally, N bits of data are transmitted simultaneously using the PAM-N ² modulation technique.

  In the preferred embodiment of the present invention, an optical Mach-Zehnder interferometer (MZI) is used to generate a PAM output signal from a parallel word input signal. Then, using the second MZI, the clock signal is transmitted separately in parallel with the PAM signal, eliminating the need to perform clock recovery at the receiving end. The optical clock signal can be transmitted over the same signal path (generally a fiber) as a PAM output data signal using a different wavelength, or the optical clock signal can be transmitted over a second separate optical fiber using the same wavelength.

  Conveniently, further, the generated optical clock signal can be distributed across the chip, providing a frequency locked clock configuration.

  Other embodiments and further embodiments and advantages of the present invention will become apparent in the course of the following description and with reference to the accompanying drawings, in which some of the same numbers indicate similar parts.

FIG. 1 is a block diagram of a typical data communication configuration between a first chip and a second chip, each with parallel data and serial data transmission; a conventional optical-based interconnection configuration using SERDES functionality. It has a processing core that utilizes the mutual bond to be utilized. FIG. 2 is a typical prior art embodiment of an optical-based interconnected configuration using SERDES functionality for use in the configuration of FIG. FIG. 3 is a block diagram of a typical data communication configuration, in which the SERDES function shown in FIG. 1 is replaced with a direct optical interconnection configuration. FIG. 4 shows a typical direct optical cross-coupled configuration that can be used in the configuration of FIG. 3, using a pulse amplitude modulation (PAM) scheme to transmit multiple data bits simultaneously. FIG. 5 includes an exemplary embodiment of the optical cross-coupling configuration of the present invention, using a first MZI to encode a PAM optical signal in parallel electrical data and using a second MZI. Then, a clock signal is transmitted to eliminate the need for CDR at the receiving end. FIG. 6 shows an alternative embodiment of the optical interconnection structure of the present invention that uses the same wavelength to transmit both PAM data and an optical clock and provides separate optical fibers to transmit both signals. FIG. 7 shows an alternative optical clock configuration that can be used in the configuration of FIG. 5 or 6, which is used to distribute frequency-locked optical signals to various regions of the computing chip. A second (spare) clock source is included with the optical branching configuration.

  As noted above, today's data centers rely on thousands of compute nodes coupled to high-speed interconnections to achieve the performance criteria in today's applications. Each compute node consists of an IC (chip) processor core that is used to perform various functions. The processing power of each node continues to increase rapidly. However, the need to join nodes with high speed, low power and short latency outperforms the technology available today.

  FIG. 1 shows a conventional optical interconnection structure between a first chip 1 and a second chip 2. The chip 1 has a processing core 3 that functions to handle large amounts of data in the format of parallel words. A similar processing core 4 is included in chip 2 and needs to communicate between chip 1 and chip 2 via an optical interconnection link 5. It will be appreciated that only one link 5 is shown for clarity. A reasonably complex system will have tens of thousands of such links. In addition, while FIG. 1 shows four output sets from chips 1 and 2, it will be appreciated that there may be additional output sets that couple these chips to five or more other nodes.

  As shown, parallel word data entering and exiting each processing core first passes through the associated SERDES device, while SERDES 6 is associated with processing core 3 and a separate SERDES 7 is associated with processing core 4. Assuming a communication path from the first chip 1 to the second chip 2, parallel data words exiting the processing core 3 are then serialized in the SERDES 6, for example from the electrical connection pin P1 to the first chip 1 Exit. The serialized electrical signal is then converted into an optical replica in an electrical / optical (E / O) conversion device 8 and coupled to the optical coupling link 5 for transmission to the second chip 2. Around the second chip 2, the optical signal is then converted into an electrical form in an optical / electrical (O / E) conversion device 9 to parallelize the data and reconstruct it into a parallel word form. It is applied as an input to the functioning "parallelization" part 7-D of SERDES 7.

  Although not shown in detail, it is clear that a similar transmission path in the reverse direction for returning data from the second chip 2 to the first chip 1 is used. In fact, all interconnections are assumed to be formally bidirectional.

  As mentioned above, SERDES 6, 7 and E / O, O / E conversion devices 8, 9 are known to consume considerable power and add latency to the overall system. Furthermore, in high data rate applications, the bandwidth of these various components is very large and requires more power.

  FIG. 2 shows a schematic diagram of a conventional optical cross-coupling configuration as deployed in the system of FIG. In this case, it is necessary to transmit a wide parallel data word of 4 bits, each bit operating at a data transfer rate of eg 5 Gb / s (of course any other data transfer rate can be used). Four parallel data bits are applied to separate inputs to the serializer 6-S of SERDES 6. Thus, four separate streams operating at a typical rate of 5 Gb / s are combined to form one output data stream operating at a data rate of 20 Gb / s. In the particular embodiment of FIG. 2, a Mach-Zehnder interferometer in which E / O conversion is formed in E / O device 8 when continuous wave (CW) optical input signal I is applied to separate inputs. The modulated light output signal O is generated using the electrical data signal that occurs in (MZI). The optical output signal O is then combined and propagates along an optical channel 5 (which can be a fiber-like integrated optical waveguide or other suitable optical communication medium). Then, the O / E conversion device 9 arranged around the second chip 2 reconverts the received 20 Gb / s optical signal into a serial electrical data signal (20 Gb / s). Then, the parallel part of SERDES 7 (indicated by 7-D in FIG. 2) operates at the same data transfer rate as its signal set, each signal leaving the first chip 1 such as 5 Gb / s in this case 4 Transform along one output data path. At such a specific data transfer rate, the bandwidth of the modulator 8, the O / E converter 9, the serializer 6-S and the parallelizer 7-D is (input data of 5 Gb / s for four channels). (Assuming speed) all need to be on the order of 20 GHz and require considerable power.

By changing the light modulation technique so that N ² level signals can be used for simultaneous transmission of N data bits, eliminating the need for SERDES operations at the outputs at processing cores 3 and 4, FIG. 2 can be realized. FIG. 3 includes a block diagram of a typical N ² level direct optical configuration. Further, assuming a communication path of N = 4 (ie, a 4-bit parallel word exits processing core 3), the 4-bit parallel word is a 16-level light transmitted later along the internal coupling link 5. It is applied directly as an input to an appropriate type of E / O conversion device 10 for encoding all four bits in the output signal. At the receiving end, O / E conversion is first performed, followed by conversion of 16 level signals into separate data signals for use in the second processing core 4.

FIG. 4 shows a specific example of the N ² level type of processing utilized in the configuration of FIG. As shown in such specific embodiments, a 4-bit parallel word is applied as an input to the optical modulator 12 (various other configurations such as, but not limited to, 8-bit, 16-bit, 64-bit, etc.) Can also be used). Similar to the above prior art configuration, data can be streamed at a rate of 5 Gb / s, but any other data transfer rate can be used. Unlike the conventional configuration of FIG. 2, four separate bits are not initially serialized but are applied as simultaneous inputs to the optical modulator 12. In such a specific embodiment, optical modulator 12 includes a pulse amplitude modulator (PAM) that utilizes four input signals to generate a PAM-16 optical output signal. A complete discussion of the use of optical PAM with respect to this application was made See U.S. Pat. No. 7,483,597, assigned to Shastri et al. And assigned to the assignee of the present application, which is hereby incorporated by reference. In such a case, the length of a plurality of modulation segments 13-1, 13-2, 13-3 and 13-4 formed along a modulator 12 with four parallel bits coupled to separate modulation segments 13 By controlling the length, a PAM-16 modulated optical output signal that maintains the original input data transfer rate (eg, 5 Gb / s) is formed. Other multi-segment configurations of modulator 12 can be used if increasing the number of segments can increase the linearity of the output signal. Furthermore, as noted above, a data transfer rate of 5 Gb / s is considered merely exemplary; any other suitable data transfer rate can be used in the system of the present invention.

  By maintaining the data rate of the input data stream, the optical channel is not subject to much dispersion-based loss, and the O / E conversion device 9 is not very good at performing O / E conversion on the second chip 2. Does not consume power. In such a specific application, a 4-bit A / D converter and clock data recovery (CDR) circuit 14 can be used instead of a parallelizer to recover four separate data bits.

  In improving the configuration of FIGS. 1 and 2, the “direct optical” embodiment of FIGS. 3 and 4 requires the use of CDRs on the receiving side of the communication path, and still consumes a significant amount of power. Leads to errors and all takes a long time.

  According to the present invention, each optical coupling is performed by simultaneously transmitting a parallel optical clock signal including a PAM optical data signal by controlling the A / D converter on the receiving side using the transmitted clock signal. It has been found that the need for CDR on the receiving side of the path is eliminated. By eliminating CDR activity along each link, significant power savings are realized while further reducing system latency.

FIG. 5 is a schematic diagram illustrating an exemplary optical interconnection formed in accordance with the present invention, including a second signal path for transmitting parallel optical clock signals with PAM optical data signals. Similar to the configuration described above with respect to FIGS. 3 and 4, the PAM modulator 12 is used to transmit an N ² level optical signal based on parallel N-bit data input. An example of such a case is N = 4, but obviously any other suitable N value can be used.

  As shown, a 4 bit parallel bit word is applied as an input to the phase aligner 20 (for purposes of explanation, assume that each data bit operates at a rate of 5 Gb / s, but obviously it is arbitrary Other suitable data transfer rates can be used). Separate clock inputs are applied to the phase aligner 20 and are used to hold the simultaneous operation of four separate data streams. In one exemplary embodiment, a set of D flip-flops is used to form phase aligner 20. The “clocked” data signal is then applied as a separate input to the PAM modulator 12 and the CW optical input signal I of the first wavelength λ 1 is used as the optical input to the modulator 12. In addition, the optical modulator 12 comprises a multi-segment modulator that can form a PAM output signal, where the number of segments contributes to the linearity of the output (ie, increasing the number of segments appropriately adjusts the output. Performance to follow the phase conversion function of the modulator well). Thus, the output from the modulator 12 is a pulse amplitude modulated optical signal (also referred to as a “PAM optical data signal”), which represents all N-bit input data signals.

  In accordance with the present invention, an electrical clock signal is applied as an input to another modulator 22. In a specific embodiment, such as in FIG. 5, an output optical clock signal OC is generated by using a second CW light source operating at the second wavelength λ 2 as an optical input to the modulator 22. As shown in FIG. 5, a modulator 22 is formed so as to basically show the same dimensions as the PAM modulator 12, and an optical signal propagating along the modulator 22 is an optical signal propagating along the modulator 12. By basically allowing the same propagation delay, the optical clock signal OC can remain synchronized with the PAM modulated optical data signal.

  As shown in FIG. 5, separate inputs to an optical multiplexer 24 where the PAM optical data signal and the optical clock signal OC combine the λ 1 and λ 2 signals into the optical channel 5 for transmission to the second chip 2. As applied afterwards. Upon reception at the chip 2, the PAM data and the clock signal are separated in the optical demultiplexer 26, and the PAM optical data signal having the wavelength λ1 is applied as an input to the first O / E converter device 9-1. And an optical clock signal OC of wavelength λ2 is applied as an input to the second O / E converter device 9-2. The converted electrical data signal output from device 9-1 is then applied as an input to A / D converter 28, and the electrical clock signal output from O / E converter device 9-2 is applied to A / D 28. Directly applied as the clock input.

  The simultaneous transmission of the clock signal with the data signal along the optical channel 5 allows the clock to directly synchronize the received data and implements “clock recovery” from the PAM optical data signal at the receiving side of the channel Preventing the need to do so is an important aspect of the configuration of the present invention. By eliminating the need for CDRs, the overall power consumed by this configuration is reduced and system latency is reduced.

  FIG. 6 shows an alternative embodiment of the optical coupling arrangement of the present invention. In such a case, an optical clock is generated at the same wavelength λ1 as the PAM optical data signal and then transmitted over separate optical fibers between the first chip 1 and the second chip 2. Referring to FIG. 6, in which like components are numbered the same, the clock data output from the phase aligner 20 is applied as an electrical input to the modulator 12, and similar to the embodiment of FIG. Are applied as inputs to the second modulator 22. However, in such a case, the same CW laser source is used to provide an optical input signal to both modulators 12 and 22. That is, the output from the CW laser source passes through optical splitter 29 and is coupled to the optical inputs of both modulators 12 and 22. For this reason, the outputs of the modulators 12 and 22 are optical signals having different modulation characteristics but operating at the same wavelength. According to such an embodiment of the invention, no multiplexer is required; instead, an optical channel 5 is formed to include a pair of optical fibers 5-1 and 5-2, and the PAM optical data signal is An optical clock signal OC is coupled to the first fiber 5-1 and the second fiber 5-2. Then, the signal pair propagates along the path to the second chip 2, and then the PAM optical data signal along the fiber 5-1 is applied as an input to the first O / E conversion device 9-1. The optical clock signal OC along the fiber 5-2 is applied as an input to the second O / E conversion device 9-2. The subsequent processing is basically the same as that described above with reference to FIG.

  The embodiment of FIG. 6 eliminates the need for a second optical laser of another wavelength and wavelength multiplexer / demultiplexer components and provides the required coupling at both ends of the second optical fiber and such a configuration. It has a tradeoff with eliminating the need for use.

  Further, the use of the generated optical clock signal can be extended to provide a clock signal that is distributed to various optical elements or combinations of elements in the system. FIG. 7 shows one exemplary optical clock distribution configuration 30 that can be used as the modulator 22, where one output from configuration 30 is, for example, an optical clock input to optical multiplexer 24 or optical fiber 5-2. And the remaining optical clock signal is distributed to other optical system components.

  Referring to FIG. 7, a configuration 30 is shown in which a second light source of a CW optical input signal shown as a second light source 32 can be used for use as a backup source in recognizing a failure of the original light source (“ "Failure" can also be defined as the output power from the first light source below a predetermined threshold). In such a balanced configuration, an electrical clock signal and its inverted signals (shown as CLK and CLK in FIG. 7) are applied as inputs to the MZI 34 and can be used to modulate the CW optical signal, and the optical clock OC output The signal and its inverted signal shown as OC are generated.

  As shown in FIG. 7, the configuration 30 further comprises an optical branching configuration 36 formed of a plurality of branching waveguides, and the optical splitter 36 is coupled to the output of the MZI 34. Thus, each of the waveguide sections carries an optical clock signal OC that propagates at wavelength λ2. One output waveguide 38 is shown for later use as used as an OC input to the optical multiplexer 24 (see FIG. 5). The remaining OC signals can be used for distribution to various other optical systems on the same chip, and these signals retain frequency lock. Advantageously, the ability to distribute frequency-locked optical clocks eliminates the need for CDRs at various locations in the optical system. Although not explicitly shown, it will be appreciated that the PAM optical data signal can pass through a similar optical branching configuration and distribute the chip towards the various optical nodes that use such data.

  Although the invention has been described with reference to several embodiments of the invention, those skilled in the art will recognize various changes that may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not limited to that shown in the drawings and described in the detailed description, but only by the claims appended hereto.

Claims (10)

An optical cross-coupled configuration for transmitting high-speed data signals, wherein the configuration is
A transmission component associated with the first processing node for converting the electrical high speed data signal into an optical data signal;
An optical transmission channel coupled to the output of the transmission component;
A receiving component associated with a second processing node and coupled to the output of the optical transmission channel for reconverting the received optical data signal into the original electrical high speed data signal. When;
And wherein the transmitting component is
A phase alignment element that generates a plurality of parallel phase aligned data signals as outputs in response to the plurality of N parallel data signals and the electrical clock signal;
Pulse amplitude modulated (PAM) light indicative of the plurality of N parallel phase aligned data signals in response to the plurality of N parallel phase aligned data signals and continuous wave (CW) optical signals A first optical modulator for generating a data signal;
A second optical modulator that generates an optical clock output signal in response to the electrical clock signal and the CW optical signal;
And the receiving component is
A first optical / electrical (O / E) conversion device that generates an electronic version thereof in response to the received PAM optical data signal;
A second O / E device that generates an electronic version thereof in response to the received optical clock signal;
An A / D converter for recovering the original plurality of N parallel data signals therefrom in response to outputs of the first and second O / E conversion devices;
An optical interconnection structure characterized by comprising.   The optical configuration of claim 1, wherein the first and second optical modulators of the transmission component comprise first and second Mach-Zehnder interferometers, respectively.   The optical configuration of claim 2, wherein the first Mach-Zehnder interferometer is a multi-segment interferometer. 4. The optical configuration of claim 3, wherein the first Mach-Zehnder interferometer generates a PAM-N ² output signal from a plurality of N parallel data signals. Further, the transmission component is
A first optical signal source coupled to the input of the first optical modulator and operating at a first wavelength λ1;
A second optical signal source coupled to the input of the second optical modulator and operating at a second wavelength λ2;
An optical multiplexer for combining the optical output signals from the first and second optical modulators into one optical output signal path;
And wherein the receiving component is
2. An optical demultiplexer for separating the PAM data signal propagating at wavelength [lambda] 1 and the optical clock signal propagating at wavelength [lambda] 2 and coupling the signals to separate optical signal paths. The optical configuration described in 1. Further, the transmission component is
A light source operating at a wavelength λ1;
An optical splitter for directing a first portion of the output from the light source to the light input of the first light modulator and directing a second portion of the output from the light source to the light input of the second light modulator; ;
With
The optical transmission channel comprises a pair of optical fibers;
The optical configuration of claim 1, wherein a first fiber supports propagation of the PAM optical data signal and a second fiber supports propagation of the optical clock signal.   2. The optical clock distribution arrangement of claim 1, wherein the second optical modulator further comprises an optical clock distribution arrangement for distributing a plurality of frequency locked optical clock signals across the first processing node. Light configuration. The optical clock distribution arrangement comprises an optical splitter coupled to the output of the second optical modulator;
8. The optical arrangement of claim 7, wherein the optical splitter comprises a plurality of branch waveguides for distributing the plurality of frequency locked optical clock signals across the first processing node.   8. The second optical modulator further comprises a second CW optical input signal source for use as a backup source upon recognizing a failure of the original CW source. Light configuration. Further, the first optical modulator comprises a pair of CW optical input signal sources for providing optical signals thereto,
The second CW optical input signal source of the pair of signal sources is used as a backup source when recognizing a failure of the first CW optical input signal source of the pair of CW optical input signal sources. The optical configuration of claim 1, wherein:

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