JP2012503301A - Circuit assembly and manufacturing method thereof - Google Patents

Abstract

  The present invention relates to an electronic assembly 400 and a method 800, 900, 1000, 1200, 1400, 1500, 1700 for manufacturing the same. The assembly 400 does not use solder. A component 406 or component package 402, 802, 804, 806 having an I / O lead 412 is disposed 800 on a planar substrate 808. This assembly is encapsulated 900 using an electrically insulating material 908 and vias 420, 1002 are formed or drilled 1000 through substrate 808 to component leads 412. The assembly is then plated 1200 and the encapsulation and drilling process 1500 is repeated to build the desired layers 422, 1502, 1702. With the planar substrate 808 as the flexible substrate 2016, the assembly 2000 can be bent to fit various housings.

Description

  The present invention relates to a circuit assembly and a method for manufacturing the circuit assembly, and more particularly, to a solderless electronic assembly and a method for manufacturing the same, and a manufacturing and assembly of an electronic product that does not use solder.

(Cross-reference of related applications)
This application is a continuation of US Provisional Application No. 12 / 163,870, filed June 27, 2008. US Provisional Patent Application No. 12/163870 is filed with US Patent Provisional Application No. 60/929467, filed May 8, 2007, entitled “ELECTRONIC ASSEMBLY WITHOUT SOLDER”, “ELECTRONIC ASSEMBLY WITHOUT SOLDER AND METHODS FOR US Patent Provisional Application No. 60 / 932,200 filed May 29, 2007 entitled "THEIR MANUFACTURE", US Patent filed July 5, 2007, named "SOLDERLESS FLEXIBLE ELECTRONIC ASSEMBLIES AND METHODS FOR THEIR MANUFACTURE" Provisional Application No. 60/958385, US Provisional Application No. 60/959148, filed July 10, 2007 entitled “ELECTRONIC ASSEMBLIES WITHOUT SOLDER AND METHODS FOR THEIR MANUFACTURE”, “MASS ASSEMBLY OF ENCAPULSATED ELECTRONIC COMPONENTS TO A PRINTED CIRCUIT BOARD BY MEANS OF AN ADHESIVE LAYER HAVING EMBEDDED CONDUCTIVE JOINING MATERIALS US Provisional Application No. 60 / 96,626 filed July 31, 2007, US Provisional Application No. 60/96, filed August 6, 2007, entitled “SYSTEM FOR THE MANUFACTURE OF ELECTRONIC ASSEMBLIES WITHOUT SOLDER”. No. 963822, US Provisional Application No. 60/966663, filed August 28, 2007, entitled “ELECTRONIC ASSEMBLIES WITHOUT SOLDER AND METHODS FOR THEIR MANUFACTURE”, “MONOLITHIC MOLDED SOLDERLESS FLEXIBLE ELECTRONIC ASSEMBLIES AND METHODS FOR THEIR” US Provisional Patent Application No. 61/038564, filed March 21, 2008, entitled “MANUFACTURE”, and March 24, 2008, named “THE OCCAM ™ PROCESS SOLDERLESS ASSEMBLY AND INTERCONNECTION OF ELECTRONIC PACKAGES” 2008 claiming priority to US Provisional Patent Application No. 61/039059 8 is a continuation-in-part application of PCT Application No. PCT / US08 / 63123 Pat filed, claiming the benefit. The entirety of these applications is incorporated herein by reference.

  This application is further described in US Provisional Application No. 60/958385 filed July 5, 2007, entitled “SOLDERLESS FLEXIBLE ELECTRONIC ASSEMBLIES AND METHODS FOR THEIR MANUFACTURE”, “ELECTRONIC ASSEMBLIES WITHOUT SOLDER AND METHODS FOR THEIR MANUFACTURE”. No. 60/959148, filed July 10, 2007, entitled “MASS ASSEMBLY OF ENCAPULSATED ELECTRONIC COMPONENTS TO A PRINTED CIRCUIT BOARD BY MEANS OF AN ADHESIVE LAYER HAVING EMBEDDED CONDUCTIVE JOINING MATERIALS” US Provisional Patent Application No. 60 / 96,626 filed July 31, 2007, US Provisional Application No. 60/963822, filed Aug. 6, 2007, entitled “SYSTEM FOR THE MANUFACTURE OF ELECTRONIC ASSEMBLIES WITHOUT SOLDER”. No. 20 named “ELECTRONIC ASSEMBLIES WITHOUT SOLDER AND METHODS FOR THEIR MANUFACTURE” US Provisional Patent Application No. 60/966663, filed August 28, 2007, US Provisional Patent Application No. 61, filed March 21, 2008, entitled “MONOLITHIC MOLDED SOLDERLESS FLEXIBLE ELECTRONIC ASSEMBLIES AND METHODS FOR THEIR MANUFACTURE” No. 0/03564, US Provisional Application No. 61/039059, filed Mar. 24, 2008, entitled “THE OCCAM ™ PROCESS SOLDERLESS ASSEMBLY AND INTERCONNECTION OF ELECTRONIC PACKAGES”, and “ELECTRONIC ASSEMBLIES WITHOUT SOLDER” Claims priority to US Provisional Application No. 61/075238, filed June 24, 2008, entitled “ON TEMPORARY SUBSTRATES AND METHODS FOR THEIR MANUFACTURE”. The entirety of these applications is incorporated herein by reference.

(Copyright notice / permission)
Part of the disclosure of this patent document includes material that is subject to copyright protection. The copyright owner will not object to copying this patent document or patent disclosure as it appears in the Patent and Trademark Office patent file or record, otherwise it will retain all copyrights. .

  Since the early days of the electronics industry, the assembly of electronic products, and more particularly the permanent assembly of electronic components on a printed circuit board, has some form of relatively low temperature solder alloys (e.g. tin / lead or With the use of Sn63 / Pb37). The reasons can vary, but the most important reason is that it facilitates mass bonding of thousands of electronic interconnections between printed circuits and the leads of many electronic components.

  Lead is a highly toxic substance, and exposure to lead can have a wide range of well-known adverse effects on health. In this context, it is important that the gas generated from the soldering operation is dangerous for the operator. This process may produce a gas that combines lead oxide (from lead-based solder) and colophoni (from solder flux). Each of these components has been found to be potentially harmful. In addition, reducing the amount of lead in electronic equipment should also reduce the pressure to mine and smelt lead. Mining lead can contaminate the local groundwater supply. Smelting can lead to pollution of factories, workers, and the environment.

  Reducing lead flow should also reduce the amount of lead in discarded electronic devices and reduce the level of lead in landfills and other less secure locations. Due to the difficulty and cost of collecting used electronic resources, and the slow enforcement of waste export laws, many used electronic devices have lower environmental standards such as China, India, and Kenya. They are also sent to countries with worse working conditions.

  Thus, there is market pressure and legal pressure to reduce tin / lead solder. Specifically, in February 2003, the European Union issued a directive on the use of the Electric of Hazardous Substances in Electrical and Electronic (Directive on the Restriction of Electric Substances) (Restriction of Hazardous Subdirectives Direct) or RoHS) was adopted. The RoHS Directive came into effect on July 1, 2006, and is required to be legislated and enforced in each member country. This directive limits the use of six harmful materials, including lead, in the manufacture of various types of electronic and electrical equipment. The Directive is a waste electrical and electronic equipment directive that is part of a legal effort to solve the problem of large amounts of toxic electronic device waste that sets goals for electrical product collection, resource recovery, and recycling. (Waste Electrical and Electronic Equipment Direct) (WEEE) 2002/96 / EC closely related.

  RoHS does not eliminate the use of lead in all electronic devices. Certain devices that require high reliability, such as medical devices, are allowed to continue to use lead alloys. Therefore, lead in electronic equipment continues to be a problem. The electronics industry has sought a practical alternative to tin / lead solder. The most common alternative currently in use is the type of SAC, which is an alloy containing tin (Sn), silver (Ag), and copper (Cu).

  SAC solder also has serious consequences for the environment. For example, tin mining causes disasters both locally and globally. A large tin deposit has been found in the Amazon rainforest. In Brazil, this discovery led to the introduction of roads, clear-cut forests, forced eviction of indigenous people, soil degradation, and the formation of dams, tailings ponds, and embankment and smelting projects. Perhaps the most serious environmental impact of tin mining in Brazil is that the river becomes silt and shallow. This degradation forever changes the ecological profile of animals and plants, destroys gene banks, alters soil structure, leads to pests and diseases, and causes irreparable ecological losses.

  Global ecological problems stemming from incorrect management of the Brazilian environment are well known. These problems range from pressures from rainforest destruction to global warming to long-term damage to the pharmaceutical industry due to destruction of animal and plant biodiversity. Mining in Brazil is just one example of the disruptive impact of the tin industry. Large deposits and mining operations also exist in Indonesia, Malaysia and China. These are developing countries where attitudes towards economic development overwhelm interest in ecosystem protection.

  There are additional problems with SAC solder. SAC solder requires high temperatures, wastes energy, is brittle and causes reliability problems. The melting temperature is the temperature at which components and circuit boards can be damaged. The exact amount of the individual alloy component compounds is still under investigation and long-term stability is unknown. Furthermore, SAC solder processing is prone to short circuits (eg, “tin whiskers”) and opens if the surface is not properly processed. Whether tin / lead solder or a type of SAC is used, a high concentration of metal increases the weight and height of the circuit assembly.

US Pat. No. 6,160,714

  Therefore, there is a need for an alternative to the soldering process and the attendant environmental and practical drawbacks.

  Solder alloys are the most common, but other joining materials such as so-called “polymer solders” in the form of conductive adhesives have also been proposed and / or used. Furthermore, efforts have been made to make the connection separable by providing sockets for the components. Also, electrical and electronic connectors have been developed for connecting conductors carrying power and signals described in various elastic contact structures. All of these require a certain force or pressure to be applied.

  At the same time, constant efforts have been made to put more electronic equipment into smaller volumes. As a result, in the past few years, there has been interest in various methods for stacking integrated circuit (IC) chips in a package and stacking the IC package itself within the electronics industry. All of these are for reducing the size of the assembly in the Z or vertical direction. There is also an ongoing effort to reduce the number of surface mount components on a printed circuit board (PCB) by embedding certain components, primarily passive devices, in the circuit board.

  In the creation of IC packages, active devices are formed by interconnecting these IC devices by placing unpackaged IC devices directly in the substrate and by drilling and plating the chip contacts directly. Efforts have also been made to embed. Such a solution provides benefits in certain application areas, but the input / output (I / O) terminals of the chip are very small and it can be very difficult to make such a connection precisely. In addition, the device after manufacture may not pass the burn-in test, which may waste all effort after completion.

  Another area of concern is heat management. This is because an IC packaged with a high density may have a high energy density, which may reduce the reliability of the electronic product.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a solderless circuit assembly and a method for manufacturing the same.

  The present invention provides an electronic assembly and a method for manufacturing the same. Pre-burn-in components including electrical, electronic, electro-optic, electromechanical, and user interface devices with external I / O contacts are placed on a planar base. The assembly is encapsulated with a solder mask, dielectric, or electrically insulating material (collectively referred to as “insulating material” in this application, including the claims), and the component leads, conductors, And through the terminal (collectively “lead” in this application, including the claims), a hole called a via is formed or drilled. The assembly is then plated and the encapsulation and drilling process is repeated to build the desired layer. Vias need only expose a small portion of the component lead area, so that the traces can be densely arranged. The substrate to which these components are attached can be a flexible substrate and the assembly can be adapted to various shapes within the electronic device.

  Assemblies built with a novel reverse-interconnection process (RIP) do not use solder, thus avoiding problems associated with lead usage, tin, and heat. The term “reverse” refers to the assembly order being reversed, rather than first making the PCB and then attaching the components, the components are first placed and then the circuit layers are manufactured. . Conventional PCBs are not required (and can optionally be incorporated), thereby reducing manufacturing cycle time, reducing cost and complexity, and mitigating PCB reliability issues.

  RIP products are robust against failures due to mechanical shock and thermal cycle fatigue. Compared to conventional products placed on a PCB substrate, the components incorporated in the RIP product do not require isolation from the surface and are therefore lower in height and placed in higher density Can do. In addition, RIP products are less costly because they do not require a solderable finish and require fewer materials and processing steps. In addition, RIP products are suitable for in-place heat enhancement (including improved heat dissipation materials and methods) that can also provide integrated electromagnetic interference (EMI) shielding. Further, this structure can be assembled with embedded electrical and optical components.

The present invention
Avoiding the need for circuit boards,
Avoiding the need for soldering,
Avoiding the problem of "Suzu Whisker"
Avoiding the need for difficult cleaning between fine pitch component leads,
Avoiding the need for suitable leads or suitable solder connections;
Many of the prior arts have been avoided by avoiding many of the problems associated with e-waste at many different manufacturing levels and end of life, as well as avoiding the thermal problems associated with the use of high temperature lead-free solders on fragile components. Overcoming the drawbacks.

The effects (benefits) of the present invention include
The structure is almost completely additive, so there is less manufacturing waste,
Less material used in construction,
Environmentally friendly because it doesn't require potentially toxic metals,
Fewer processing steps,
Reducing test requirements,
Processing at low temperature and thus saving energy,
Lower cost,
Lower assembly height,
High reliability,
Potentially higher performance or longer battery life,
Better protection of the IC from mechanical shock, vibration, and physical damage,
The design security is improved because the devices used cannot be seen directly,
The final metallization can be applied, so that the electronics are completely shielded,
Improved thermal performance,
An integrated edge card connector is possible,
Improved memory module design,
Improved phone module design,
Improved design of computer card modules,
This includes improved smart card and RFID card designs and improved lighting modules.

  The details of the structure and operation of the present invention, as well as many of the advantages associated with the present invention, can best be understood by referring to the following detailed description in conjunction with the accompanying drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified.

1 is a cross-sectional view of a conventional solder assembly that uses gull wing type components on a PCB. FIG. 1 is a cross-sectional view of a conventional solder assembly that uses either a ball grid array (BGA) component or a land grid array (LGA) component on a PCB. FIG. 1 is a cross-sectional view of a conventional solderless assembly that uses electrical components. FIG. 3 is a cross-sectional view of a portion of a RIP assembly that uses LGA components. FIG. 6 is a cross-sectional view of a portion of a RIP assembly that uses an LGA component with an optional heat spreader and heat sink. FIG. 3 is a cross-sectional view of a two-layer RIP assembly showing discrete, analog, and LGA components attached. FIG. 6 is a cross-sectional view of a pair of mated two-layer RIP subassemblies. FIG. 3 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. 1 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. 1 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. FIG. 6 is a perspective view of a RIP subassembly. 1 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. FIG. 6 is a perspective view of a RIP subassembly. FIG. 3 is a side cross-sectional view of a RIP subassembly. 1 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. 1 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. 1 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. FIG. 6 is a cross-sectional view of alignment and joining of two RIP subassemblies. FIG. 6 is a cross-sectional view of a pair of two RIP subassemblies completed by mating. FIG. 6 is a cross-sectional view of a portion of a RIP assembly that uses LGA components mounted on a flexible substrate. FIG. 6 is a cross-sectional view of a stage in the manufacture of an exemplary flexible substrate RIP assembly. FIG. 6 is a cross-sectional view of a stage in the manufacture of an exemplary flexible substrate RIP assembly. FIG. 6 is a cross-sectional view of a stage in the manufacture of an exemplary flexible substrate RIP assembly. FIG. 6 is a cross-sectional view of a stage in the manufacture of an exemplary flexible substrate RIP assembly. FIG. 6 is a cross-sectional view of a stage in the manufacture of an exemplary flexible substrate RIP assembly. FIG. 6 is a cross-sectional view of a stage in the manufacture of an exemplary flexible substrate RIP assembly. 1 is a cross-sectional view of an exemplary RIP assembly showing discrete, analog, and LGA components mounted on a flexible substrate. 2 is a cross-sectional view of an exemplary RIP assembly showing discrete, analog, and LGA components mounted on a flexible substrate and showing bending of the assembly. FIG. FIG. 5 is a perspective view of a single layer RIP subassembly showing trace connections. FIG. 6 is a top view of a single layer non-RIP subassembly. FIG. 6 is a view of a RIP subassembly. FIG. 6 is a top view of a single layer RIP subassembly. It is a figure which shows the photograph of the upper surface of a RIP subassembly. It is a figure which shows the photograph which looked at the RIP subassembly.

  In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth in order to provide a thorough understanding of the present invention. In some instances, these terms and symbols may suggest specific details that are not essential to the practice of the invention. For example, the interconnection between component conductor elements (ie, component I / O leads) can be a single lead or a single conductor signal line connected to multiple component contacts within or between devices. It may be illustrated or described as having a plurality of interconnected conductors. Thus, alternatively, each of the multiple conductor interconnects can be a single conductor signal transmission, control, power, or ground line, and vice versa. The circuit path shown or described as single-ended may be differential and vice versa. The interconnected assembly can be constructed from standard interconnects, and the microstrip or stripline interconnects and all signal lines of this assembly may or may not be shielded.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view of a conventional solder assembly that uses gull wing type components on a PCB, showing a solder joint 110 of a gull wing type component package 104 soldered on the PCB 102. A conventional completed assembly 100 is shown.

  Component package 104 includes electrical component 106. Component 106 may be an IC or another discrete component. A gull-wing type lead 108 extends from the package 104 to the flow solder 110, and the flow solder 110 connects the lead 108 to a pad 112 on the PCB 102. Insulating material 114 prevents flow solder 110 from flowing to component 106 and shorting component 106 to other components (not shown) on PCB 102. Pad 112 connects to through hole 118, which connects to a suitable trace, such as that shown at 116. In addition to the aforementioned problems with solder joints, this type of assembly, including the internal structure of the PCB 102, is complex and requires height space. In the present invention, this height space is reduced.

  FIG. 2 is a cross-sectional view of a conventional solder assembly that uses either a ball grid array (BGA) component or a land grid array (LGA) component on a PCB, with a BGA IC or LGA IC package 204 on the PCB 214. FIG. 2 shows a conventional completed assembly 200 having a solder joint 202. The main difference from FIG. 1 is that the ball solder 202 is used instead of the flow solder 110.

  The component package 204 includes a component 206. A lead 208 extends from the package 204 through the support 210 (typically comprised of a reinforced organic or ceramic material) to the ball solder 202, and the ball solder 202 attaches the lead 208 to a pad 212 on the PCB 214. Connect. Insulating material 216 prevents ball solder 202 from shorting other leads (not shown) contained within package 204. Insulating material 218 prevents ball solder 202 from flowing to component 206 and shorting component 206 to other components (not shown) on PCB 214. Pad 212 connects to through hole 220, which connects to a suitable trace, such as that shown at 222. With this configuration, the same problems as the assembly shown in FIG. 1 occur, and in addition to the aforementioned problems with solder joints, this type of assembly is particularly complex and requires height space for the PCB 214. In the present invention, this height space is reduced.

  FIG. 3 is a cross-sectional view of a conventional solderless assembly that uses electrical components and shows a conventional solderless connection device 300. See Patent Document 1 (Green). In this configuration, the substrate 302 supports the package 304. Package 304 includes electrical components (not shown), such as ICs or other discrete components. An insulating material 306 is located on the substrate 302. On the opposite side of the substrate 302 is a conductive polymer thick film ink 308. A thin copper film 310 is plated on the polymer thick film 308 to improve conductivity. Vias extend from the package 304 through the substrate 302. This via is filled with conductive adhesive 314. The point 316 attaching the package 304 to the adhesive 314 can be made of a soluble polymer thick film ink, a silver polymer thick film conductive ink, or a commercially available solder paste. One disadvantage of this prior art assembly for the present invention is that additional thickness is added by the adhesive 314, as shown by the ridges 318.

<RIP assembly>
FIG. 4 is a cross-sectional view of a portion of a RIP assembly that uses LGA components, where assembly 400 shows LGA component packages (402, 406, 408, 410, 412, 414) mounted on a substrate 416. ing. The substrate 416 need not be a PCB. It will be apparent to those skilled in the art that BGA, gull wing, or other IC package structures, or any type of discrete component can be used in place of the LGA component. Compared to the assembly shown in FIGS. 1-3, the connection is simpler, uses no solder, and is lower in height.

  An electrically insulating material 404 is attached to the package 402. Electrical insulating material 404 is shown as being attached to one side of package 402. However, the electrically insulating material 404 may be attached to two surfaces of the package 402, three or more surfaces of the package 402, or may actually wrap the package 402. When electrically insulating material 404 is applied, the assembly can be given strength, stability, structural integrity, toughness (ie, not brittle), and dimensional stability. The electrically insulating material 404 can be reinforced by including a suitable material such as a screen (see FIGS. 33 and 34) or glass cloth.

  The component package 402 includes an electrical component 406 (such as an IC, discrete, or analog device collectively referred to as a “component” in this application, including the claims), and supports 408 and 410 (reinforced). Preferably composed of an organic or ceramic material), a lead 412 and an insulating material 414. Often manufactured and shipped component package 402 incorporates insulating material 414, but this conventional feature can potentially be removed in the future, thus reducing the height of assembly 400. . Either the supports 408 and 410, or the insulating material 414, if present, is located on the substrate 416. The substrate 416 is preferably made from an insulating material. If it is desirable to short the leads (eg, 412) extending from the package 402, a portion or all of the substrate 416 can be made from an electrically conductive material.

  Attachment of leads 412 to insulating material 414 and substrate 416 can be accomplished by adhesive dots, as well as by other well-known techniques.

  A first set of vias extends through the substrate 416, extends through the insulating material 414 if present, and reaches leads such as leads 412 to expose them. An example of the first set of vias is a via 420. The first set of vias is an electrically conductive material (often copper (Cu) but silver (Ag), gold (Au), or aluminum (Al), as well as other suitable materials instead. Or may be plated or filled. This plating or filler melts with the lead 412 to form an electrical and mechanical bond.

  The substrate 416 can include a plated pattern mask (not shown), or a plating or filler introduced into the first set of vias (eg, via 420) extends under the substrate 416. The required first set of traces can also be provided. Other traces can be made. A layer 422, also made of an insulating material, can be placed under the substrate 416 and the first trace. The purpose of layer 422 is to provide a platform for the second set of traces (if necessary) and to electrically isolate the first set of traces from the second set of traces.

  A second set of vias extends through layer 422 to reach and expose traces and / or leads (eg, leads 428) under substrate 416. An example of the second set of vias is via 426. The second set of vias can be plated or filled as described above in connection with the first set of vias (eg, via 420), so that the second set of vias is under the substrate 416. To dissolve with the desired lead (eg, lead 428). As described above, one or more traces 430 can extend under the layer 422.

  This multi-layering continues as necessary. By repeating the above structure, multiple layers (not shown) as well as additional traces and vias can be constructed. The last layer is coated with a surface insulating material 432. This surface insulating material 432 can be selectively coated with a metal finish that does not interfere with electrical function to create a more airtight assembly and provide additional EMI protection. A lead or electrical connector (eg, lead 434) can extend beyond the surface insulating material 432. This provides a contact surface (eg, surface 436) to allow connection to other electrical components or circuit boards.

FIG. 5 is a cross-sectional view of a portion of a RIP assembly that uses an LGA component with an optional heat spreader and heat sink, and the assembly 500 illustrates optional heat dissipation features. The subassembly 400 described above in FIG. 4 can have a heat spreader 506 and / or a heat sink 508 on the package 402 and material 404 for dissipating heat generated by the component 406. A thermal interface material (not shown) can be used to join the heat sink to the heat spreader. Optionally, material 404 is thermally conductive (but electrically insulative) such as silicon dioxide (SiO ₂ ) or aluminum dioxide (AlO ₂ ) in its composition to enhance heat flow from package 402. ) Material can be included. The heat spreader 506 and heat sink 508, when made from one or more materials well known in the art, provide electromagnetic interference (EMI) protection to the subassembly 400 to help protect against electrostatic discharge. Can do.

  FIG. 6 is a cross-sectional view of a two-layer RIP assembly showing attached discrete, analog, and LGA components. FIG. 6 shows an assembly 600 with a set of sample components attached including a discrete gull-wing component 602, an analog component 604, and an LGA IC 606. Is shown.

  It will be apparent to those skilled in the art that the RIP assembly is not as complex as a PCB containing soldered components. That is, the PCB itself is a complex device that requires tens of manufacturing steps. This RIP assembly is simpler by not requiring a PCB substrate and requires fewer steps to produce a complete electronic assembly.

  FIG. 7 is a cross-sectional view of a pair of mated two-layer RIP subassemblies, optionally with the assembly 700 of FIG. 7 being plated and / or filled vias (eg, 706a, 706b), or Two RIP subassemblies 702 and 704 are shown joined together with / or leads (eg, 708a, 708b).

<RIP manufacturing method>
8 to 17 show a method for manufacturing the RIP assembly. It will be apparent to those skilled in the art that the order of the steps can be changed without departing from the scope and spirit of the invention.

  A stage 800 shown in FIG. 8 illustrates the step of first mounting packaged components 802, 804, and 806 on a substrate 808. These components may be applied by a number of different techniques and / or materials known in the art including applying a spot or non-conductive adhesive or bonding the adhesive film of the component leads to the substrate 808. , Can be held in place. The material for application or bonding may be suitable for holding the component and later releasing.

Stage 900 shown in FIG. 9 illustrates another step of the RIP manufacturing method. At this stage, the partial assembly of FIG. The initially installed packaged components 802, 804, and 806 are placed in an electrically insulating material 908. The electrically insulating material 908 supports the packaged components 802, 804, and 806 and is electrically isolated from each other. If the electrically insulating material 908 includes a thermally conductive but electrically insulating material such as AlO ₂ or SiO ₂ , the electrically insulating material 908 also serves to dissipate heat.

  Stage 1000 shown in FIG. 10 shows another step of the RIP manufacturing method. Vias (eg, 1002) are made through the substrate 808 to reach the leads of the packaged components 802, 804, and 806 to expose them. Vias (eg, 1002) can be formed or drilled (referred to collectively as “formation” in this application, including the claims), by any number of known techniques, including laser drilling.

  FIG. 11 is a perspective view of the RIP subassembly. The partial assembly 1100 of FIG. 11, showing the completion of stage 1000, is a top perspective view of the substrate 808 showing vias (eg, 1102).

  Step 1200 shown in FIG. 12 shows how direct printing of the circuit can be realized. Device 1206 allows vias (eg, 1202) to be plated or filled with an electrically conductive material, and traces and leads (eg, 1208) to be made on substrate 808. Using any number of techniques known in the art, apparatus 1206 may fill vias 1202, print leads and traces 1208, and / or plate leads and traces 1208 onto substrate 808. it can.

  FIG. 13 is a perspective view of the RIP subassembly. Traces (eg, 1302) and leads (eg, 1304) created on substrate 808 by step 1200 are shown in a perspective view of partial assembly 1300 in FIG.

  FIG. 14 is a side cross-sectional view of the RIP subassembly. A partial assembly 1400 made by stage 1200 is shown in the side view of FIG. Filled vias (eg, vias 1402) are shown as extending through substrate 808 to component leads (eg, leads 1406).

  FIG. 15 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. In FIG. 15 illustrating step 1500, an insulating material layer 1502 and a second set of vias (eg, vias 1504) are formed on the substrate 808. These vias extend to the leads (eg, 1506) on the substrate 808 to expose them.

  FIG. 16 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. In the stage showing fabrication of subassembly 1600 of FIG. 16, via (eg, 1602) plating and / or filling and trace (eg, 1604) fabrication on layer 1502 has been completed.

  FIG. 17 is a cross-sectional view of a stage in the manufacture of a representative RIP assembly. In this way, additional layers can be constructed. Finally, an insulating material 1702 is placed over the top layer of the subassembly 1600, as shown in step 1700 of FIG. Further, a heat spreader 1706 and a heat sink 1708 can be attached under the material 908.

  FIG. 18 is a cross-sectional view of alignment and bonding of two RIP subassemblies. Alternative means for placing the insulating material 1702 on the subassembly 1704 are shown in step 1800 of FIG. 18 and step 1900 of FIG. In FIG. 18, the leads, fillers, and traces of subassembly 1600 are aligned with each other and then joined.

  FIG. 19 is a cross-sectional view of a pair of two RIP subassemblies completed in mating, using any suitable process and material (e.g., applying an anisotropic conductive film). The step of adding 1908 and joining the subassemblies 1600 together is shown. Although not shown in FIG. 19, a heat spreader and heat sink may be added below the support material 1904 and above the support material 1906 as previously described for one subassembly and illustrated in FIG.

<Flexible substrate>
FIG. 20 is a cross-sectional view of a portion of a RIP assembly that uses LGA components mounted on a flexible substrate. Similar to FIG. 4, but with some notable differences, the partially shown assembly 2000 includes attachment of a flexible substrate 2016 (the flexible substrate 2016 includes first plane 2022 and Electrically insulating material 2004 does not extend across the substrate, and there is only one layer of vias (eg, via 2020) and trace (eg, trace 2028).

  The assembly 2000 of FIG. 20, illustrating the flexible variant of the present invention, is an LGA component package 2002 mounted on a flexible substrate 2016 made from an electrically insulating material of a type well known in the art. Sub-components 2006, 2008, 2010, 2012, 2014). It will be apparent to those skilled in the art that BGA, gull wing, or other IC package structures, or any type of discrete component can be used in place of the LGA component. Similar to the assembly shown in FIG. 4, compared to the assembly shown in FIGS. 1-3, the connection is simpler, no solder is used, and the height is lower.

  An electrically insulating material 2004 is attached to the package 2002. The electrically insulating material 2004 is shown as being attached to two sides of the package 2002. However, the electrically insulating material 2004 may be attached to one surface of the package 2002, three or more surfaces of the package 2002, or may actually wrap the package 2002. Once electrically insulating material 2004 is applied, the appropriate portions of the assembly can be given strength, stability, structural integrity, toughness (ie, not brittle), and dimensional stability. The electrically insulating material 2004 can be reinforced (also providing some EMI protection) by including a suitable material such as a glass cloth or metal screen.

  Component package 2002 includes an electrical component 2006 (such as an IC, discrete, or analog device collectively referred to in this application as claimed) and supports 2008 and 2010 (organic or ceramic materials). A lead 2012 and an insulating material 2014. Component packages 2002 that are often manufactured and shipped incorporate electrically insulating material 2014, but this conventional feature can potentially be removed in the future, thus reducing the height of assembly 2000. Can do. Either the supports 2008 and 2010, or the insulating material 2014, if present, are located on the flexible substrate 2016. The flexible substrate 2016 is preferably made from an electrically insulating material. If it is desirable to short the leads (eg, 2012) extending from the package 2002, a portion or all of the substrate 2016 can be made from an electrically conductive material.

  Attachment of leads 2012 and insulating material 2014 to substrate 2016 can be accomplished by adhesive dots and by other well known techniques.

  A set of vias extends through the substrate 2016, extends through the insulating material 2014 if insulating material 2014 is present, and reaches leads such as leads 2012 to expose them. An example of a set of vias is a via 2020. Via 2020 is an electrically conductive material (often copper (Cu), but silver (Ag), gold (Au), or aluminum (Al), as well as other suitable materials may be used instead. ) Is plated or filled. This plating or filler melts with the lead 2012 to form an electrical and mechanical bond.

  The substrate 2016 can include a plated pattern mask (not shown) or a plating or filler introduced into the set of vias (eg, via 2020) extends under the substrate 2016, A necessary set of traces can also be provided. Other traces can be made.

  The trace (eg, trace 2028) and flexible substrate 2016 are coated with a surface electrical insulation material 2032. Leads or electrical connectors can extend beyond the surface insulation material 2032. This provides a contact surface (not shown) to allow connection with other electrical components or circuit boards.

Although not shown in the figure, comparing FIG. 20 with FIG. 5, it is clear that assembly 2000 can include optional heat dissipation features. The assembly 2000 may have a heat spreader 506 and / or a heat sink 508 (both shown in FIG. 5) on the package 2002 and / or electrically insulating material 2004 for dissipating heat generated by the component 2006. A thermal interface material (not shown) can be used to join the heat sink to the heat spreader. Optionally, the electrically insulating material 2004 is thermally conductive (but electrically electrically insulating) such as silicon dioxide (SiO ₂ ) or aluminum dioxide (AlO ₂ ) in its composition to enhance the heat flow from the package 2002. Material). As shown in FIG. 5, heat spreader 506 and heat sink 508, when made from one or more materials well known in the art, provide electromagnetic interference (EMI) protection to assembly 2000 to protect against electrostatic discharge. Can help you.

  The electrically insulating material 2004 can have a tapered edge 2005 that provides strain relaxation (ie, transition from a rigid region to a bent region) when the assembly 2000 is bent.

  21 to 26 are views showing a method of manufacturing the flexible RIP assembly. It will be apparent to those skilled in the art that the order of the steps can be changed without departing from the scope and spirit of the invention.

  Referring again to FIG. 8, stage 800 shows the step of first mounting packaged components 802, 804, and 806 on substrate 808. This stage remains the same when mounting similar components on a flexible substrate (eg, components 2102, 2002, and 2104 and flexible substrate 2016 of FIG. 21). These components may be applied to a number of different techniques and / or known in the art, including applying a spot or non-conductive adhesive, or bonding the adhesive film of the component leads to the flexible substrate 2016. Or it can be held in place by the substance. The material for application or bonding can be suitable for permanently holding the component.

  Stage 2100 shown in FIG. 21 includes a typical set of packaged components (eg, gull-wing type component 2102, LGA component 2002, and analog component 2104) mounted on flexible substrate 2016. Shows the steps of wrapping. At this stage, the flexible substrate 2016 can be placed on a temporary base (not shown) or on an air cushion. On exemplary components 2102, 2002, and 2104, electrically insulating material 2004 and electrically insulating material 2004a are applied or overcoated. Materials 2004 and 2004a adhere to the flexible substrate 2016. Note that materials 2004 and 2004a can be attached to or encase a single component, such as 2102, two or more components, such as 2002 and 2104, or multiple components. As a result of step 2100, subassembly 2106 is completed.

  Stage 2200 shown in FIG. 22 shows the support element and / or molding device 2208 aligned and positioned on the subassembly 2106.

  As shown in FIG. 23, stage 2300 is the step of adding a support element and / or molding device 2208. Device 2208 contacts material 2004a and 2004 at undulations 2302 and 2304, respectively. Device 2208 supports and / or molds material 2004a and material 2004. Whether material 2004a and material 2004 are pre-formed or molded at this stage, device 2208 supports subassembly 2106 in a subsequent manufacturing stage (see FIGS. 21 and 22).

  If desired, following step 2300, the temporary base can be removed or the air cushion can be stopped. Again, if necessary, the position of the subassembly can be changed as shown in step 2400 of FIG. At this stage, a lead (such as the lead 2012) is exposed by drilling a hole through the flexible substrate 2016 (forming a via such as the via 2402). However, the order and process of forming the vias may be different, for example, the vias may be pre-formed by drilling or molding prior to step 2100 of FIG. In practice, vias can be formed by drilling through a temporary base or air cushion.

  In step 2500 shown in FIG. 25, via plating or filling is performed using, for example, an electrically conductive material 2502. An electrically conductive material 2502 (often copper (Cu), but silver (Ag), gold (Au), or aluminum (Al), as well as other suitable materials may be used instead) Application is by any process known in the art. The plating or filler melts with the component leads to form an electrical and mechanical bond. This plating or filler can form leads. Also, at this stage, traces such as trace 2504 can be formed, usually by plating.

  In the next step 2600 shown in FIG. 26, surface electrical insulation or dielectric material 2602 is applied to provide plated or filled vias (eg, filled via material 2502), traces (eg, trace 2504), and possible. A flexible substrate 2016 is overcoated. A lead or electrical connector that is a lead 2604a at one point and a lead 2604b at another point can extend beyond the surface insulating material 2602. Leads 2604a and 2604b allow connection to other electrical components or circuit boards. At this stage, the device 2208 is providing physical support. As an alternative to device 2208, an air cushion may provide support. At the end of step 2600, device 2208 is removed.

  FIG. 27 shows a completed assembly 2700 in a cross-sectional view of an exemplary RIP assembly showing discrete, analog, and LGA components mounted on a flexible substrate. Components 2102, 2002, and 2104 are insulated and attached to flexible substrate 2016 by materials 2004a and 2004. An insulating material 2032 supports the flexible substrate 2016.

  FIG. 28 is a cross-sectional view of a representative RIP assembly showing discrete, analog, and LGA components mounted on a flexible substrate and showing bending of the assembly, with bending points near 2802 and 2804. The assembly 2700 is shown in the having position. Bending the assembly 2700 allows the assembly 2700 to be placed in very expensive devices (e.g., mobile phones and handheld devices), and thus other miscellaneous device elements. Circuits can be inserted around.

<Trace density>
Referring to FIG. 10, the RIP subassembly includes a via, such as via 1002 (see FIG. 11 for a perspective view).

  FIG. 29 is a perspective view of a single layer RIP subassembly showing trace connections. Filled vias form leads (eg, leads 2904) and traces (eg, trace 2902) on the surface of substrate 2906 of RIP subassembly 2900.

  FIG. 30 is a top view of a single layer non-RIP subassembly showing a non-RIP subassembly 3000 using a soldered connection. On a printed circuit board (PCB) 3002, solder covers the leads (eg, 3004). Traces (eg, 3006) are formed between the leads, but the number is limited by reducing the space between the land edges. In general, a solder mask (not shown) is used to configure the solder termination.

  FIG. 31 is an illustration of a RIP subassembly showing an RIP subassembly 3100 in which an electrically insulating material 3102 wraps the component package 3104 and attaches the component package 3104 to the substrate 3112. A via is formed that extends through the substrate 3112 to a component lead (eg, lead 3106). Vias are filled or plated (eg, filled vias 3110) and traces (eg, traces 3108) are formed to connect the filled or plated vias and thus form appropriate electrical paths. Filled via 3110 covers only a small portion of the area of lead 3106, allowing more traces to be routed between lands as compared to FIG. Note also that it should be possible to reduce the size of the lands because no solder is required, thus increasing the possibility of routing on the package and thus potentially reducing the number and complexity of the package layers. .

  32 is a top view of a single layer RIP subassembly and is a top view of a RIP subassembly 3200 similar to the subassembly 3100 of FIG. The substrate 3202 covers a component package (not shown). In contrast to the non-RIP subassembly 3000 of FIG. 30, component package leads (eg, 3204) are partially covered by filled or plated vias (eg, filled vias 3206). Traces (eg, trace 3208a and trace 3208b) extend from filled or plated vias to form appropriate electrical paths. By covering only a portion of the area of the underlying lead, the RIP subassembly can place the traces more densely than the non-RIP subassembly. This is apparent by comparing the subassembly 3200 of FIG. 32 with the subassembly 3000 of FIG.

<Contains screen>
As described above with respect to FIG. 4, the material 404 can incorporate a metal screen, glass cloth, or other reinforcing material to improve strength and stability.

  FIG. 33 shows a photograph of the top surface of the RIP subassembly, where the assembly 3300 illustrates the step of including a screen 3304 within the electrically insulating material 3302. The electrically insulating material 3302 encloses a component package (eg, package 3306). Screen 3304 not only serves to increase strength and stability, but can also act as a heat spreader and provide EMI protection.

  FIG. 34 is a perspective view of the assembly 3300 showing a perspective view of the RIP subassembly and showing the steps of including the screen 3304. As shown in FIG. 33, the component package 3306 is wrapped with an electrically insulating material 3302 and the screen 3304 is embedded within the electrically insulating material 3302.

  While the particular systems, assemblies, and methods for solderless electronic assemblies shown and described in detail herein can fully achieve the aforementioned objectives of the present invention, this is presently preferred for the present invention. It is an embodiment, and thus represents a subject that is broadly contemplated by the present invention, the scope of the present invention fully encompasses other embodiments that may be apparent to those skilled in the art, and the present invention Accordingly, it is to be understood that the scope of the invention is not limited to anything other than the appended claims, and in this claim, references to a single element mean “at least one”. All structural and functional equivalents of the preferred embodiment elements known or later known to those skilled in the art are expressly incorporated herein by reference and are encompassed by the claims. Shall be. Moreover, a device or method need not address every problem sought to be solved by the present invention, as it is encompassed by the claims. Furthermore, an element, component, or method step within this disclosure is intended to be made available to the public regardless of whether that element, component, or method step is explicitly recited in the claims. is not.

Claims (32)

A flexible substrate 2016;
A component package 2002 having at least one lead 2012;
An electrically insulating material 2004 for attaching the component package 2002 to the flexible substrate 2016;
A circuit assembly 2000 comprising: at least one via 2020 extending through the flexible substrate 2016 to the at least one lead 2012. A flexible substrate 2016 having a first plane 2022 and a second plane 2024;
At least one component 2006 comprising a first set of one or more leads 2012 and having at least one surface;
A first electrically insulating material 2004 that attaches at least one surface of the component 2006 to the first plane 2022;
A circuit assembly 2000 comprising: at least one via 2020 extending from the second plane 2024 and exposing the first set of one or more leads 2012. A flexible substrate 2016 having a first plane 2022 and a second plane 2024;
At least one component package 2002 comprising a first set of one or more leads 2012 and having at least one surface;
A first electrically insulating material 2004 for attaching the at least one surface to the first plane 2022;
A circuit assembly 2000 comprising: at least one via 2020 extending from the second plane 2024 and exposing the first set of one or more leads 2012.   The circuit assembly of claim 3, wherein the flexible substrate 2016 is electrically insulating.   The circuit assembly of claim 3, wherein the first electrically insulating material 2004 encloses the component package 2002.   The circuit assembly of claim 3, wherein the first electrically insulating material 2004 has a tapered edge 2005.   The circuit assembly of claim 3, wherein the first electrically insulating material 2004 is thermally conductive.   The circuit assembly of claim 3, wherein the assembly further comprises a heat spreader.   The circuit assembly of claim 3, wherein the assembly further comprises a heat sink.   The circuit assembly of claim 3, further comprising the at least one via 2020 filled with an electrically conductive material that electrically connects to the first set of one or more leads 2012.   11. The conductive material is selected from the group consisting of copper, silver, aluminum, gold, tin, metal alloy, an electrically conductive film, an electrically conductive adhesive, and an electrically conductive ink. A circuit assembly according to claim 1.   The circuit assembly of claim 10, wherein the conductive material is plated on the flexible substrate 2016.   The circuit assembly of claim 10, wherein the conductive material is printed on the flexible substrate 2016.   The circuit assembly of claim 10, wherein the conductive material forms a second set of one or more leads on the flexible substrate 2016.   The circuit assembly of claim 10, wherein the conductive material forms a set of one or more traces 2028 on the flexible substrate 2016.   The circuit assembly of claim 10, further comprising a second electrically insulating material 2032 on the second plane 2024 that covers at least one of the at least one via 2020.   15. The circuit assembly of claim 14, further comprising a second electrically insulating material 2032 on the second plane 2024 that covers at least one of the second set of at least one lead. .   The circuit assembly of claim 15, further comprising a second electrically insulating material 2032 on the second plane 2024 that covers at least one of the at least one trace 2028. Placing 800 at least one component package 2002 on a flexible substrate 2016, the component package 2002 having at least one surface, the flexible substrate 2016 having a first plane 2022; And a second plane 2024 and the at least one component package 2002 is in contact with the first plane 2022;
Applying 2100 a first electrically insulating material 2004 that attaches at least one surface of the at least one component package 2002 to the first plane 2022, wherein the first electrically insulating material 2004 is the first electrically insulating material 2004. Forming a tapered edge 2005 on the first plane 2022 to expose at least one section of the first plane 2022; and
A first set of at least one via 2402 is formed through the second plane 2024 of the flexible substrate 2016 to expose a set of at least one lead 2012 of the at least one component package 2002. And a step 2400 for producing a circuit assembly. Disposing a flexible substrate 2016 having a first plane 2022 and a second plane 2024 on a temporary support, wherein the second plane 2024 contacts the temporary support. , Steps and
Placing 800 at least one component package 2002 having at least one surface in contact with the first plane 2022;
Applying 2100 a first electrically insulating material 2004 that attaches at least one surface of the at least one component package 2002 to the first plane 2022, wherein the first electrically insulating material 2004 is the first electrically insulating material 2004. Forming a tapered edge 2005 on the plane 2022 of step 2100;
Disposing one or more component supports 2208 on a first electrically insulating material 2004 and on the at least one component package, wherein the one or more component supports 2208 are Step 2300, temporarily supporting and electrically connecting the first electrically insulating material 2004 to the first plane 2022;
Removing the temporary support;
Forming a first set of at least one via 2402 through the second plane 2024 to expose a set of at least one lead 2012 of the at least one component package 2002; 2400;
Removing the one or more component supports 2208. A method of manufacturing a circuit assembly, comprising:   21. The method of claim 20, further comprising filling 2500 the electrically conductive material 2502 with the at least one via 2402.   The method of manufacturing a circuit assembly according to claim 21, further comprising a step 2600 of placing a second electrically insulating material 2032 covering the electrically conductive material 2502 on the second plane 2024.   21. The method of manufacturing a circuit assembly of claim 20, further comprising molding the first electrically insulating material 2004 using the one or more component supports 2208.   The method of manufacturing a circuit assembly according to claim 19, further comprising filling 2500 the electrically conductive material 2502 in the first set of at least one via 2402.   25. The conductive material is selected from the group consisting of copper, silver, aluminum, gold, tin, metal alloy, an electrically conductive film, an electrically conductive adhesive, and an electrically conductive ink. A method for manufacturing a circuit assembly according to claim 1.   The method of manufacturing a circuit assembly of claim 24, wherein the electrically conductive material forms a second set of at least one lead.   The method of manufacturing a circuit assembly of claim 26, wherein the electrically conductive material forms a set of at least one trace 2504.   The method of manufacturing a circuit assembly according to claim 24, further comprising a step 2600 of forming a layer of a second electrically insulating material 2602 overlying the electrically conductive material 2502 on the second plane 2024. .   An electronic product manufactured by the process according to claim 19.   The method of manufacturing a circuit assembly of claim 19, further comprising bending the circuit assembly at the at least one section of the first plane 2022.   A RIP subassembly comprising at least one via of at least one component package 3104 and at least one lead 3106, wherein the at least one via extends through a substrate 3112 and the at least one component package 3104 Exposing a portion of the at least one lead 3106 that is less than the entire area of the RIP subassembly.   An RIP subassembly, wherein the electrically insulating material 3302 for wrapping incorporates at least one metal screen 3304.

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