JP2012256629A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a crosstalk noise occurring between laminated wirings without accompanying complication and a big change in a wiring layout and a wiring structure.SOLUTION: A semiconductor device comprises: a wiring 103; a wiring 108 formed on the wiring 103 with sandwiching insulation films 104 and 106, and partially overlapping at least a part of the wiring 103 when viewed from above; and a conductive shield layer 105 formed in the insulation film at least on a part overlapping the wiring 103 and the wiring 108.

Description

  The technology described in this specification relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device and a manufacturing method thereof that can reduce crosstalk noise generated between stacked wirings.

  In recent years, with high integration, high functionality, and miniaturization of semiconductor devices, for example, a wiring structure in which wiring is embedded in a groove formed in an insulating film and copper is used as a wiring material has been adopted. It is coming. The method for forming this structure is as follows. First, after depositing an interlayer insulating film on a semiconductor substrate, a groove is formed in the interlayer insulating film using lithography, dry etching, or the like. Next, after depositing a copper film on the interlayer insulating film by, for example, plating, the copper film outside the groove is polished and removed by CMP (Chemical Mechanical Polishing), so that the copper is embedded in the groove. The wiring which becomes is formed. Hereinafter, a conventional method for forming a buried wiring will be described in detail with reference to FIGS. 12A and 12B (see, for example, Patent Document 1).

  As shown in FIG. 12A, first, after forming a wiring groove in the interlayer insulating film 702 deposited on the semiconductor substrate 701 using lithography and dry etching, the interlayer insulating film 702 including the wiring groove is formed. A copper film is deposited over the entire upper surface by, for example, plating. Next, the copper film outside the wiring groove is removed by CMP and the copper film embedded in the wiring groove is left, thereby forming the wiring 703. Next, a wiring 705 is formed in the same manner as the wiring 703 on the interlayer insulating film 704 deposited on the wiring 703 and the interlayer insulating film 702. Here, the wiring 705 includes a high-frequency wiring 705 </ b> A and a via portion electrically connected to the wiring 703. Next, a wiring 707 is formed in the interlayer insulating film 706 deposited on the wiring 705 and the interlayer insulating film 704 in the same manner as the wirings 703 and 705. The wiring 707 includes a high-frequency wiring 707A and a via portion electrically connected to the wiring 705.

  In the conventional semiconductor device shown in FIG. 12A, as shown in FIG. 12B, the high-frequency wirings 705A and 707A are orthogonal to reduce crosstalk noise generated between the high-frequency wirings 705A and 707A. The layout to be used is used.

JP 2001-244267 A

  By the way, as the semiconductor device is miniaturized, the clock frequency of the logic circuit and the number of wirings in the wiring layer increase, so that the power required for charging / discharging the capacitance of the wiring layer in the stacked wiring structure also greatly increases. On the other hand, as described above, in the conventional semiconductor device, the crosstalk noise generated between the stacked wirings is reduced by giving the layout a restriction that the upper layer wiring and the lower layer wiring are orthogonal to each other.

  However, when a layout in which the upper layer wiring and the lower layer wiring are orthogonal to each other is used to reduce crosstalk noise, there arises a problem that the routing of the wiring becomes complicated and the wiring structure needs to be significantly changed.

  In view of the foregoing, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can reduce crosstalk noise generated between stacked wirings without complicating or drastically changing the wiring layout or wiring structure. .

  In order to achieve the above object, a semiconductor device according to the present invention includes a first wiring, and a second wiring formed on the first wiring with an insulating film interposed therebetween, and the first wiring The wiring and the second wiring overlap at least partially in plan view, and a conductive shield layer is formed in the insulating film at least in the overlapping portion of the first wiring and the second wiring. Is formed.

  In the present application, the “wiring” means a signal wiring used for signal transmission of a circuit, a power supply wiring used for transmission of a power supply voltage, and the like, whereas the conductive shield layer is this It does not have such a transmission function.

  According to the semiconductor device of the present invention, the conductive shield layer is formed in the insulating film between the first wiring (lower layer wiring) and the second wiring (upper layer wiring). Therefore, crosstalk noise caused by capacitive coupling can be reduced. In addition, by forming a conductive shield layer, for example, between damascene wiring layers, it is possible to reduce crosstalk noise generated between stacked wirings without complicated or drastic changes in wiring layout or wiring structure. .

  In the semiconductor device according to the present invention, the first wiring includes, for example, a gate wiring formed on the substrate (a gate electrode formed on the active region, an element isolation region, and a gate electrode). It means both wiring to be connected).

  In the semiconductor device according to the present invention, the potential of the conductive shield layer may be fixed. Here, the potential of the conductive shield layer may be any of a power supply potential, a ground potential, or another potential different from those potentials. Alternatively, the potential of the conductive shield layer may be floated. A third wiring formed above or below the conductive shield layer; and a via formed in the insulating film to connect the third wiring and the conductive shield layer; May be further provided. Here, the third wiring may be provided in the same wiring layer as the first wiring or the second wiring, or may be provided in another wiring layer different from any of those wirings. .

  In the semiconductor device according to the present invention, the conductive shield layer may be formed over the entire overlap portion between the first wiring and the second wiring. In this way, crosstalk noise generated between the stacked wirings can be more reliably reduced.

  In the semiconductor device according to the present invention, there is a region where the conductive shield layer is not disposed in an overlap portion between the first wiring and the second wiring, and the dimension of the region is The width may be smaller than the width of the narrow wiring of the first wiring and the second wiring. In this case, crosstalk noise generated between the stacked wirings can be further reduced as compared with the conventional semiconductor device using a layout in which the upper layer wiring and the lower layer wiring are orthogonal to each other. Here, when the first wiring and the second wiring have the same wiring width, the dimension of the region where the conductive shield layer is not formed may be made smaller than the same wiring width.

  In the semiconductor device according to the present invention, the first wiring or the second wiring is formed in the same layer and at least partially overlaps the first wiring or the second wiring in a side view. A fourth wiring that is connected to the conductive shield layer, and overlaps the first wiring or the second wiring and the fourth wiring from the conductive shield layer through the insulating film And a conductive structure extending to the portion. In this way, crosstalk noise generated between the first wiring or the second wiring and the fourth wiring can be reduced by the conductive structure connected to the conductive shield layer.

  The semiconductor device according to the present invention further includes another conductive shield layer formed by sandwiching another insulating film under the first wiring, the conductive shield layer and the other conductive shield layer. Each extend to both sides of the first wiring, and other conductive structures connecting the conductive shield layer and the other conductive shield layer are provided on both sides of the first wiring. It may be done. In this case, the first wiring is surrounded by the conductive shield layer, the other conductive shield layer, and the other conductive structure that connects the two, so that other ones positioned on the top, bottom, left, and right of the first wiring Crosstalk noise generated in the first wiring due to the wiring and crosstalk noise generated in the other wiring due to the first wiring can be reliably reduced. Here, the other conductive structure may have a wall-like structure extending along the first wiring in a plan view.

  In the semiconductor device according to the present invention, the conductive shield layer may be composed of a metal film or a metal nitride film. Here, the conductive shield layer may be composed of a single layer structure of a metal nitride film, for example, TiN.

  In the semiconductor device according to the present invention, the conductive shield layer may have a thickness of 50 nm or less. In this way, it is possible to reduce crosstalk noise generated between the stacked wirings while miniaturizing the semiconductor device.

  In the semiconductor device according to the present invention, a distance between the first wiring and the second wiring may be 500 nm or less. In this way, the effect of reducing crosstalk noise generated between the stacked wirings can be remarkably obtained.

  In the semiconductor device according to the present invention, the insulating film includes a first insulating film and a second insulating film formed on the first insulating film, and the conductive shield layer includes It may be formed on the surface of the first insulating film, and the second insulating film may be formed so as to cover the conductive shield layer. Here, the second wiring may be embedded in the upper portion of the second insulating film.

  In the semiconductor device according to the present invention, a lower insulating film may be formed below the insulating film, and the first wiring may be embedded above the lower insulating film.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising a first wiring and a second wiring formed on the first wiring with an insulating film interposed therebetween, The first wiring and the second wiring overlap at least partially in plan view, and at least the conductive film is electrically conductive in the insulating film in the overlapping portion between the first wiring and the second wiring. A step of forming a shield layer;

  According to the semiconductor device manufacturing method of the present invention, the conductive shield layer is formed in the insulating film between the first wiring (lower layer wiring) and the second wiring (upper layer wiring). Since it can be shielded electrically, crosstalk noise caused by capacitive coupling can be reduced. In addition, by forming a conductive shield layer, for example, between damascene wiring layers, it is possible to reduce crosstalk noise generated between stacked wirings without complicated or drastic changes in wiring layout or wiring structure. .

  In the method of manufacturing a semiconductor device according to the present invention, the insulating film includes a first insulating film and a second insulating film formed on the first insulating film, and forms the conductive shield layer. Forming a first conductive film on a surface of the first insulating film, patterning the first conductive film to form the conductive shield layer, and then forming the conductive shield layer. The second insulating film may be formed so as to cover the surface. In this case, after the step of forming the conductive shield layer, a wiring groove is formed on the second insulating film, and then the second conductive film is embedded in the wiring groove by embedding the second conductive film. You may provide further the process to form.

  In the method of manufacturing a semiconductor device according to the present invention, after forming the lower insulating film below the insulating film before the step of forming the conductive shield layer, a wiring groove is formed above the lower insulating film. And forming a first wiring by embedding a third conductive film in the wiring trench and then forming the first wiring.

  According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can reduce crosstalk noise generated between stacked wirings without complicating or drastically changing the wiring layout or wiring structure.

FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, showing the semiconductor device according to the first embodiment. 2A to 2F are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 3A to 3E are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a plan view showing a semiconductor device according to a first modification of the first embodiment. FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to a second modification of the first embodiment. FIGS. 6A and 6B are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to a third modification of the first embodiment. 7A and 7B are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to the second embodiment. 8A to 8E are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the second embodiment. FIGS. 9A and 9B are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment. FIGS. 10A and 10B are cross-sectional views showing respective steps of the method for manufacturing the semiconductor device according to the second embodiment. FIGS. 11A and 11B are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the second embodiment. 12A and 12B are a cross-sectional view and a plan view showing a conventional semiconductor device, respectively.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

  FIGS. 1A and 1B are a plan view and a cross-sectional view, respectively, showing the semiconductor device according to the first embodiment. In FIG. 1A, wiring (including vias) and a conductive shield layer, which are main components, are shown. Moreover, FIG.1 (b) has shown the cross-sectional structure of the AA line of Fig.1 (a).

  As shown in FIGS. 1A and 1B, in the semiconductor device of this embodiment, an interlayer (not shown) such as a MOS (Metal-Oxide-Semiconductor) transistor is provided on a semiconductor substrate 101. An insulating film 102 is formed. In the upper part of the interlayer insulating film 102, for example, a wiring groove 102a having a depth of about 100 nm to 200 nm is formed, and the wiring 103 is formed in the wiring groove 102a. The wiring 103 includes a barrier film 103a that covers the wall surface and bottom surface of the wiring groove 102a and is made of, for example, Ta or TaN, and a conductive film 103b that is embedded in the wiring groove 102a with the barrier film 103a interposed therebetween and made of, for example, copper. Here, although illustration is omitted, the wiring 103 is electrically connected to an element formed on the semiconductor substrate 101. On the wiring 103 and the interlayer insulating film 102, an interlayer insulating film 104 having a thickness of about 60 nm to 100 nm and an interlayer insulating film 106 having a thickness of about 200 nm to 300 nm, for example, are sequentially formed. For example, wiring grooves 106b1 and 106b2 having a depth of about 100 nm to 200 nm are formed on the interlayer insulating film 106, and wirings 108 and 109 are formed in the wiring grooves 106b1 and 106b2, respectively. The wiring 108 includes a barrier film 108a that covers the wall surface and bottom surface of the wiring groove 106b1 and is made of, for example, Ta or TaN, and a conductive film 108b that is embedded in the wiring groove 106b1 with the barrier film 108a in between and is made of, for example, copper. The wiring 109 includes a barrier film 109a that covers the wall surface and bottom surface of the wiring groove 106b2, and is made of, for example, Ta or TaN, and a conductive film 109b that is embedded in the wiring groove 106b2 with the barrier film 109a interposed therebetween and made of, for example, copper. Here, as shown in FIG. 1A, the wiring 103 and the wiring 108 partially overlap in plan view.

  A feature of the present embodiment is that a conductive shield layer 105 made of, for example, TiN and having a thickness of about 10 nm to 50 nm is formed so as to cover the surface of the interlayer insulating film 104 including an overlapping portion (overlapping portion) between the wiring 103 and the wiring 108. It is formed. Here, the conductive shield layer 105 is covered with an interlayer insulating film 106. In other words, the conductive shield layer 105 is embedded in the laminated film of the interlayer insulating films 104 and 106.

  In this embodiment, the conductive shield layer 105 extends to the lower side of the wiring 109 on the surface of the interlayer insulating film 104, and the conductive shield layer 105 and the wiring 109 are connected to the interlayer insulation under the wiring groove 106. It is electrically connected via a via 107 formed in the film 106 and formed in a via hole 106a connected to the wiring groove 106b2. Thereby, the potential of the conductive shield layer 105 is fixed. Here, the potential of the conductive shield layer 105 may be any of a power supply potential, a ground potential, or another potential different from those potentials. The via 107 includes a barrier film 107a that covers the wall surface and bottom surface of the via hole 106a and is made of, for example, Ta or TaN, and a conductive film 107b that is embedded in the via hole 106a with the barrier film 107a interposed therebetween and is made of, for example, copper. The wiring 109 and the via 107 may have a dual damascene structure.

  In the present embodiment, the wirings 103 and 108 and the wiring 109 (that is, the conductive shield layer 105) are not electrically connected.

  According to the present embodiment described above, the conductive shield layer 105 is formed in the insulating film (laminated body of the interlayer insulating films 104 and 106) between the wiring (lower wiring) 103 and the wiring (upper wiring) 108. Therefore, the wirings 103 and 108 can be electrically shielded from each other, so that crosstalk noise caused by capacitive coupling can be reduced. Specifically, even when noise occurs in the wiring 108, crosstalk noise generated in the wiring 103 due to the noise can be reduced, and also when noise occurs in the wiring 103, the noise is caused. Thus, crosstalk noise generated in the wiring 108 can be reduced. In addition, since the conductive shield layer 105 is formed between the wiring layers of the damascene structure, it is possible to reduce crosstalk noise generated between the stacked wirings without complicating or drastically changing the wiring layout or the wiring structure. it can.

  A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings.

  FIGS. 2A to 2F and FIGS. 3A to 3E are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the first embodiment.

  First, as shown in FIG. 2A, after an element (not shown) such as a MOS transistor is formed on a semiconductor substrate 101, an interlayer insulating film 102 is formed on the semiconductor substrate 101 including the element.

  Next, as shown in FIG. 2B, a wiring trench 102a having a depth of, for example, about 100 nm to 200 nm is formed on the interlayer insulating film 102 by photolithography and dry etching. Thereafter, as shown in FIG. 2C, a barrier film 111 made of, for example, Ta or TaN is formed on the interlayer insulating film 102 so as to cover the wall surface and bottom surface of the wiring groove 102a, and then the barrier film 111 is formed. Then, a conductive film 112 made of, for example, copper is formed so as to fill the wiring trench 102a.

  Next, as shown in FIG. 2D, the barrier film 111 and the conductive film 112 outside the wiring trench 102a are removed by using, for example, a CMP method. Thereby, the wiring 103 composed of the barrier film 103a and the conductive film 103b is formed in the wiring groove 102a.

  Next, as shown in FIG. 2E, after an interlayer insulating film 104 having a thickness of, for example, about 60 nm to 100 nm is formed on the wiring 103 and the interlayer insulating film 102, the entire surface on the interlayer insulating film 104 is formed. For example, the conductive film 105A made of, for example, TiN and having a thickness of about 10 nm to 50 nm is formed by CVD.

  Next, as shown in FIG. 2F, dry etching is performed using a resist film 113 covering a predetermined region including an overlap portion between the wiring 103 and a wiring 108 (see FIG. 3E) described later as a mask. The conductive shield layer 105 is formed by patterning the conductive film 105A.

  Next, after removing the resist film 113, as shown in FIG. 3A, an interlayer insulating film 106 having a thickness of about 200 nm to 300 nm is formed on the conductive shield layer 105 and the interlayer insulating film 104, for example. .

  Next, as shown in FIG. 3B, a via hole 106a reaching the conductive shield layer 105 is formed in the interlayer insulating film 106 by photolithography and dry etching. Next, as shown in FIG. 3C, wiring trenches 106b1 and 106b2 having a depth of, for example, about 100 nm to 200 nm are formed on the interlayer insulating film 106 by photolithography and dry etching. Here, the wiring groove 106 b 1 is formed so as to partially overlap the wiring 103. The wiring trench 106b2 is formed so as to be connected to the via hole 106a.

  Next, as shown in FIG. 3D, a barrier film made of Ta or TaN, for example, is formed on the interlayer insulating film 106 so as to cover the wall surface and bottom surface of the via hole 106a and the wall surfaces and bottom surfaces of the wiring grooves 106b1 and 106b2. After forming 114, a conductive film 115 made of, for example, copper is formed on the barrier film 114 so that the via hole 106a and the wiring grooves 106b1 and 106b2 are filled.

  Next, as shown in FIG. 3E, the barrier film 114 and the conductive film 115 outside the via hole 106a and the wiring grooves 106b1 and 106b2 are removed by using, for example, a CMP method. As a result, a wiring 108 partially overlapping with the wiring 103 and formed of the barrier film 108a and the conductive film 108b is formed in the wiring groove 106b1, connected to the conductive shield layer 105, and connected to the barrier film 107a and the conductive film 107b. A via 107 made of is formed in the via hole 106a, and a wiring 109 connected to the via 107 and made of the barrier film 109a and the conductive film 109b is formed in the wiring groove 106b2.

  According to the manufacturing method of the present embodiment described above, the semiconductor device of the present embodiment shown in FIGS. 1A and 1B can be obtained, and thus the same as that described for the semiconductor device of the present embodiment. An effect can be obtained.

  In this embodiment, the material of the interlayer insulating films 102, 104, and 106 is not particularly limited. For example, a SiC film, a plasma TEOS (tetraethylorthosilicate) film, a SiOC film, a SiCO film, a SiCN film, or a laminate of these insulating films is used. A film or the like may be used.

  In this embodiment, a TiN film is used as the conductive shield layer 105. However, the present invention is not limited to this. For example, a metal film such as a W film, a Ta film, a Ti film, or an Al film, or a NiAlN film, TiSiN, or the like. A metal nitride film such as a film or a WN film may be used. Here, for miniaturization of the semiconductor device, a single layer film of a metal nitride film having a thickness of about 50 nm or less may be used as the conductive shield layer 105, for example.

  In the present embodiment, the potential of the conductive shield layer 105 is fixed, but instead, the potential of the conductive shield layer 105 may be made floating. However, from the viewpoint of the effect of this embodiment, it is more preferable to fix the potential of the conductive shield layer 105 than to make the potential of the conductive shield layer 105 floating. It is preferable to fix the power supply potential or the ground potential.

  In this embodiment, in order to fix the potential of the conductive shield layer 105, the wiring 109 provided in the same wiring layer as the wiring 108 and the conductive shield layer 105 are electrically connected. Thus, the conductive shield layer 105 may be electrically connected to another wiring provided in a wiring layer different from the wiring 108.

  In this embodiment, damascene wiring is formed as the wirings 103, 108, and 109, but the wiring structure is not particularly limited. The wiring 103 is a gate wiring formed on the semiconductor substrate 101 (meaning both a gate electrode formed on the active region and a wiring formed on the element isolation region and connected to the gate electrode). However, the same effect as this embodiment can be obtained.

  In the present embodiment, the conductive shield layer 105 is arranged at the boundary between the laminated films of the interlayer insulating films 104 and 106. However, the arrangement of the conductive shield layer 105 is particularly limited as long as it is in the insulating film between the laminated wirings. Not. In other words, the structure of the insulating film between the stacked wirings where the conductive shield layer 105 is disposed is not particularly limited.

  In the present embodiment, the distance between the wiring 103 and the conductive shield layer 105 (that is, the thickness of the interlayer insulating film 104) may be, for example, about 50 nm to 100 nm. Further, the interval between the wiring 108 and the conductive shield layer 105 may be about 80 nm to 150 nm, for example. Further, the distance between the wiring 103 and the wiring 108 between which the conductive shield layer 105 is disposed may be about 130 nm to 250 nm, for example. However, the numerical values such as the thickness of the interlayer insulating films 102, 104, and 106 and the thicknesses of the wirings 103, 108, and 109 in this embodiment are all examples, and are not limited to these values, and if these numerical values change. Needless to say, the distance between the above-mentioned wirings and conductive shield layers also changes. Also, depending on the wiring structure, interlayer insulating film material, etc., when the upper layer wiring and the lower layer wiring are at least partially overlapped, and the interval between the upper layer wiring and the lower layer wiring is 500 nm or less In addition, it is preferable to provide a conductive shield layer similar to that of the present embodiment at least in the overlapping portion of both wirings in the insulating film between the upper layer wiring and the lower layer wiring.

(First modification of the first embodiment)
Hereinafter, a semiconductor device according to a first modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 is a plan view showing a semiconductor device according to a first modification of the first embodiment. Note that FIG. 4 shows wiring (including vias) and a conductive shield layer as main components. In FIG. 4, the same components as those of the semiconductor device of the first embodiment shown in FIGS. 1A and 1B are denoted by the same reference numerals.

  The differences between the present modification and the first embodiment are as follows. In the first embodiment, as shown in FIG. 1A, the conductive shield layer 105 is formed over the entire overlapping portion (overlapping portion) between the wiring 103 and the wiring 108. On the other hand, in this modified example, as shown in FIG. 4, there is a region where the conductive shield layer 105 is not disposed in the overlap portion between the wiring 103 and the wiring 108. Here, the dimension L of the region is set smaller than the width W of the wiring 103.

  According to this modification, compared to a conventional semiconductor device using a layout in which upper layer wiring and lower layer wiring are orthogonal to each other, the area of a portion where the wiring 103 and the wiring 108 overlap without the conductive shield layer 105 interposed therebetween. Therefore, crosstalk noise generated between the stacked wirings can be further reduced.

  In this modification, it is assumed that the wiring widths of the wirings 103 and 108 are the same, and the size of the region is set smaller than the width W of the wiring 103. However, when the wiring widths of the wirings 103 and 108 are different, the region These dimensions may be set smaller than the width of the narrower wiring.

(Second modification of the first embodiment)
Hereinafter, a semiconductor device according to a second modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIGS. 5A and 5B are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to a second modification of the first embodiment. In FIG. 5A, wiring (including vias) and a conductive shield layer, which are main components, are shown. FIG. 5B shows a cross-sectional configuration taken along the line AA in FIG. 5A and 5B, the same reference numerals are given to the same components as those of the semiconductor device according to the first embodiment shown in FIGS. 1A and 1B.

  The differences between the present modification and the first embodiment are as follows. In the first embodiment, as shown in FIG. 1B, in order to fix the potential of the conductive shield layer 105, the wiring 109 provided in the same wiring layer as the wiring 108 and the conductive shield layer 105 are connected. Electrically connected. On the other hand, in this modified example, as shown in FIG. 5B, in order to fix the potential of the conductive shield layer 105, the wiring 109 and the conductive shield layer 105 provided in the same wiring layer as the wiring 103 are used. And are electrically connected.

  Specifically, in this modified example, as shown in FIG. 5B, wiring grooves 102a1 and 102a2 having a depth of, for example, about 100 nm to 200 nm are formed on the interlayer insulating film 102. Wirings 103 and 109 are formed in each of 102a1 and 102a2. The wiring 103 includes a barrier film 103a that covers the wall surface and bottom surface of the wiring groove 102a1 and is made of, for example, Ta or TaN, and a conductive film 103b that is embedded in the wiring groove 102a1 with the barrier film 103a interposed therebetween and made of, for example, copper. The wiring 109 includes a barrier film 109a that covers the wall surface and bottom surface of the wiring groove 102a2, and is made of, for example, Ta or TaN, and a conductive film 103b that is embedded in the wiring groove 102a2 with the barrier film 109a interposed therebetween and made of, for example, copper. The conductive shield layer 105 extends on the surface of the interlayer insulating film 104 to the upper side of the wiring 109, and the conductive shield layer 105 and the wiring 109 are formed in the interlayer insulating film 104 and connected to the wiring 109. It is electrically connected through a via 107 formed in the via hole 104a. Thereby, the potential of the conductive shield layer 105 is fixed. Here, the potential of the conductive shield layer 105 may be any of a power supply potential, a ground potential, or another potential different from those potentials. The via 107 includes a barrier film 107a that covers the wall surface and bottom surface of the via hole 104a and is made of, for example, Ta or TaN, and a conductive film 107b that is embedded in the via hole 104a with the barrier film 107a interposed therebetween and is made of, for example, copper.

  In this modification, the wirings 103 and 108 and the wiring 109 (that is, the conductive shield layer 105) are not electrically connected.

  According to this modification described above, the same effects as those of the first embodiment can be obtained.

(Third Modification of First Embodiment)
Hereinafter, a semiconductor device according to a third modification of the first embodiment of the present invention will be described with reference to the drawings.

  FIGS. 6A and 6B are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to a third modification of the first embodiment. In FIG. 6A, wiring (including vias) and a conductive shield layer (including a conductive structure described later), which are main components, are shown. FIG. 6B shows a cross-sectional configuration taken along line AA in FIG. 6A and 6B, the same components as those of the semiconductor device according to the first embodiment shown in FIGS. 1A and 1B are denoted by the same reference numerals.

  The first point that this modification differs from the first embodiment is that the wiring 121 is formed in the same wiring layer as the wiring 103 as shown in FIGS. 6A and 6B. . Here, the wiring 103 and the wiring 121 overlap at least partially in a side view. Specifically, as shown in FIG. 6B, wiring grooves 102a1 and 102a2 having a depth of, for example, about 100 nm to 200 nm are formed on the interlayer insulating film 102. The wiring grooves 102a1 and 102a2, respectively, are formed. Wirings 103 and 121 are formed in the inside. The wiring 103 includes a barrier film 103a that covers the wall surface and bottom surface of the wiring groove 102a1 and is made of, for example, Ta or TaN, and a conductive film 103b that is embedded in the wiring groove 102a1 with the barrier film 103a interposed therebetween and made of, for example, copper. The wiring 121 includes a barrier film 121a that covers the wall surface and bottom surface of the wiring groove 102a2, and is made of, for example, Ta or TaN, and a conductive film 121b that is embedded in the wiring groove 102a2 with the barrier film 121a interposed therebetween and is made of, for example, copper. In this modification, the conductive shield layer 105 extends to the upper side of the wiring 121 on the surface of the interlayer insulating film 104.

  A second difference of this modification from the first embodiment is that it is connected to the conductive shield layer 105 and is connected to the interlayer from the conductive shield layer 105 as shown in FIGS. 6 (a) and (b). A conductive structure (for example, a stacked body of wall-like vias 122 and 123) extending through the insulating film 104 to the interlayer insulating film 102 where the wiring 103 and the wiring 121 overlap is formed. Specifically, a via groove 102a3 is formed deeper than the wiring grooves 102a1 and 102a2 in the interlayer insulating film 102 where the wiring 103 and the wiring 121 overlap, and the wall-like via 122 is formed in the via groove 102a3. Is formed. The wall-shaped via 122 covers a wall surface and a bottom surface of the via groove 102a3 and includes a barrier film 122a made of, for example, Ta or TaN, and a conductive film 122b embedded in the via groove 102a3 with the barrier film 122a interposed therebetween and made of, for example, copper. Become. In the interlayer insulating film 104, a via groove 104a reaching the wall-like via 122 is formed, and a wall-like via 123 is formed in the via groove 104a. The wall-like via 123 includes a barrier film 123a that covers the wall surface and bottom surface of the via groove 104a and is made of, for example, Ta or TaN, and a conductive film 123b that is embedded in the via groove 104a with the barrier film 123a interposed therebetween and made of, for example, copper. Become. The conductive shield layer 105 is formed in contact with the wall-like via 123.

  According to the modification described above, the following effects can be obtained in addition to the same effects as those of the first embodiment. That is, crosstalk noise generated between the wiring 103 and the wiring 121 formed in the same wiring layer by a conductive structure (for example, a laminated body of the wall-like vias 122 and 123) connected to the conductive shield layer 105. Can be reduced.

  In this modification, the wiring 121 is formed in the same wiring layer as the wiring 103, and the conductive property extends from the conductive shield layer 105 to the interlayer insulating film 102 where the wiring 103 and the wiring 121 overlap. A structure (a laminated body of wall-like vias 122 and 123) was formed. However, instead of this, or in addition to this, another wiring is formed in the same wiring layer as the wiring 108, and the overlapping portion of the wiring 108 and the other wiring from the conductive shield layer 105. A conductive structure (for example, a wall-like via formed in the interlayer insulating film 106) may be formed extending to the interlayer insulating film 106.

(Second Embodiment)
Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

  7A and 7B are a plan view and a cross-sectional view, respectively, showing a semiconductor device according to the second embodiment. In FIG. 7A, wiring (including vias) and a conductive shield layer (conductive structure) which are main components are shown. Moreover, FIG.7 (b) has shown the cross-sectional structure of the AA line of Fig.7 (a).

  As shown in FIGS. 7A and 7B, in the semiconductor device of this embodiment, a gate wiring 250 is formed on a semiconductor substrate 201 provided with an element (not shown) such as a MOS transistor. . The gate wiring 250 includes both a gate electrode formed on the active region and a wiring formed on the element isolation region and connected to the gate electrode. An interlayer insulating film 202 is formed on the gate wiring 250 and the semiconductor substrate 201. A conductive shield layer 203 made of, for example, TiN and having a thickness of about 10 nm to 50 nm is formed so as to cover the surface of the interlayer insulating film 202 including an overlapping portion (overlapping portion) between the gate wiring 250 and a wiring 206 which is an upper layer wiring described later. Is formed. Here, the conductive shield layer 203 extends on both sides of the gate wiring 250.

  On the conductive shield layer 203 and the interlayer insulating film 202, for example, an interlayer insulating film 204 having a thickness of about 200 nm to 300 nm is formed. A via groove 204 a reaching the conductive shield layer 203 is formed in a portion of the interlayer insulating film 204 located on both sides of an overlap portion (overlapping portion) between the gate wiring 250 and a wiring 206 which is an upper layer wiring described later. ing. In addition, on the interlayer insulating film 204, a wiring groove 204b1 that at least partially overlaps the gate wiring 250 in a plan view, a wiring groove 204b2 connected to each via groove 204a, and a wiring groove 204b1 on both sides of the wiring groove 204b1. A wiring groove 204b3 is formed with the wiring groove 204b2 interposed therebetween. The depth of the wiring grooves 204b1, 204b2, and 204b3 is, for example, about 100 nm to 200 nm. A wall-like via 205 connected to the conductive shield layer 203 is formed in each via groove 204a. Each wall-shaped via 205 covers a wall surface and a bottom surface of the via groove 204a and is made of, for example, a barrier film 205a made of Ta or TaN, and a conductive film 205b buried in the via groove 204a with the barrier film 205a interposed therebetween and made of, for example, copper. Consists of. A wiring 206, a dummy wiring 207, and a wiring 216 are formed in each of the wiring grooves 204b1, 204b2, and 204b3. The wiring 206 includes a barrier film 206a that covers the wall surface and bottom surface of the wiring groove 204b1 and is made of, for example, Ta or TaN, and a conductive film 206b that is embedded in the wiring groove 204b1 with the barrier film 206a interposed therebetween and is made of, for example, copper. The dummy wiring 207 includes a barrier film 207a that covers the wall surface and bottom surface of the wiring groove 204b2, and is made of, for example, Ta or TaN, and a conductive film 207b that is embedded in the wiring groove 204b2 with the barrier film 207a interposed therebetween and is made of, for example, copper. . The dummy wiring 207 and the wall-like via 205 may have a dual damascene structure. The wiring 216 includes a barrier film 216a that covers the wall surface and bottom surface of the wiring groove 204b3 and is made of, for example, Ta or TaN, and a conductive film 216b that is embedded in the wiring groove 204b3 with the barrier film 216a interposed therebetween and made of, for example, copper.

  On each of the wiring 206, the dummy wiring 207 and the wiring 216 and on the interlayer insulating film 204, an interlayer insulating film 208 having a thickness of about 60 nm to 100 nm, for example, is formed. In the interlayer insulating film 208, via grooves 208a reaching the respective dummy wirings 207 are formed. In each via groove 208a, a wall-like via 209 connected to each dummy wiring 207 is formed. Each wall-shaped via 209 covers a wall surface and a bottom surface of the via groove 208a and is made of a barrier film 209a made of, for example, Ta or TaN, and a conductive film 209b buried in the via groove 208a with the barrier film 209a interposed therebetween and made of, for example, copper. Consists of. A conductive shield layer 210 made of, for example, TiN and having a thickness of about 10 nm to 50 nm is formed so as to cover the surface of the interlayer insulating film 208 including an overlapping portion (overlapping portion) between the wiring 206 and a wiring 213 which is an upper layer wiring described later. Has been. Here, the conductive shield layer 210 extends on both sides of the wiring 206 so as to be connected to each wall-like via 209.

  On the conductive shield layer 210 and the interlayer insulating film 208, for example, an interlayer insulating film 211 having a thickness of about 200 nm to 300 nm is formed. Via holes 217 reaching the respective wirings 216 are formed in the interlayer insulating films 208 and 211. A via hole 211a reaching the conductive shield layer 210 is formed in a portion of the interlayer insulating film 211 located on both sides of an overlap portion (overlap portion) between the wiring 206 and a wiring 213 which is an upper layer wiring described later. ing. In addition, on the interlayer insulating film 211, there are a wiring groove 211b1 that at least partially overlaps the wiring 206 in a plan view, a wiring groove 211b2 that is connected to each via hole 211a, and a wiring groove 211b3 that is connected to each via hole 217. Is formed. The depth of the wiring grooves 211b1, 211b2, and 211b3 is, for example, about 100 nm to 200 nm. In each via hole 217, a via 218 connected to each wiring 216 is formed. The via 218 includes a barrier film 218a that covers the wall surface and bottom surface of the via hole 217 and is made of, for example, Ta or TaN, and a conductive film 218b that is embedded in the via hole 217 with the barrier film 218a interposed therebetween and is made of, for example, copper. A via 212 connected to the conductive shield layer 210 is formed in each via hole 211a. Each via 212 includes a barrier film 212a that covers the wall surface and bottom surface of the via hole 211a and is made of, for example, Ta or TaN, and a conductive film 212b that is embedded in the via hole 211a with the barrier film 212a interposed therebetween and is made of, for example, copper. Wirings 213, 214, and 219 are formed in the wiring grooves 211b1, 211b2, and 211b3, respectively. The wiring 213 includes a barrier film 213a that covers the wall surface and bottom surface of the wiring groove 211b1, and is made of, for example, Ta or TaN, and a conductive film 213b that is embedded in the wiring groove 211b1 with the barrier film 213a interposed therebetween and made of, for example, copper. The wiring 214 includes a barrier film 214a that covers the wall surface and bottom surface of the wiring groove 211b2, and is made of, for example, Ta or TaN, and a conductive film 214b that is embedded in the wiring groove 211b2 with the barrier film 214a interposed therebetween and is made of, for example, copper. The wiring 214 and the via 212 may have a dual damascene structure. The wiring 219 includes a barrier film 219a that covers the wall surface and bottom surface of the wiring groove 211b3 and is made of, for example, Ta or TaN, and a conductive film 219b that is embedded in the wiring groove 211b3 with the barrier film 219a interposed therebetween and made of, for example, copper. The wiring 219 and the via 218 may have a dual damascene structure.

  In the present embodiment, the wirings 250, 206, and 213 and the wiring 214 (that is, the conductive shield layers 203 and 210) are not electrically connected.

  According to the present embodiment described above, the conductive shield layer 203 is formed in the insulating film (laminated body of the interlayer insulating films 202 and 204) between the gate wiring 250 and the wiring 206. And the wiring 206 can be electrically shielded from each other, so that crosstalk noise caused by capacitive coupling can be reduced. Specifically, even when noise occurs in the gate wiring 250, crosstalk noise generated in the wiring 206 due to the noise can be reduced, and also when noise occurs in the wiring 206, the noise is caused by the noise. Thus, crosstalk noise generated in the gate wiring 250 can be reduced.

  Further, according to the present embodiment, the conductive shield layer 210 is formed in the insulating film (laminated body of the interlayer insulating films 208 and 211) between the wiring (lower layer wiring) 206 and the wiring (upper layer wiring) 213. Therefore, the wirings 206 and 213 can be electrically shielded from each other, so that crosstalk noise caused by capacitive coupling can be reduced. Specifically, even when noise occurs in the wiring 206, crosstalk noise generated in the wiring 213 due to the noise can be reduced, and also when noise occurs in the wiring 213, the noise is caused by the noise. Thus, crosstalk noise generated in the wiring 206 can be reduced.

  In addition, according to the present embodiment, since the conductive shield layers 203 and 210 are formed between the wiring layers of the damascene structure, the wiring layout and the wiring structure are not complicated and drastically changed, without being changed between the stacked wirings. The generated crosstalk noise can be reduced.

  Further, according to the present embodiment, the wiring formed in the same wiring layer by the conductive structure (for example, the dummy wiring 207 and the wall-like vias 205 and 209) electrically connected to the conductive shield layers 203 and 210. Crosstalk noise generated between the wiring 206 and the wiring 216 can be reduced. That is, according to the present embodiment, the wiring 206 is surrounded by the conductive shield layers 203 and 210 and the conductive structure connecting the two (see the shield region 215 in FIG. 7B), whereby the wiring 206 is vertically and horizontally Crosstalk noise generated in the wiring 206 due to the other wiring located at the position and crosstalk noise generated in the other wiring due to the wiring 206 can be reliably reduced.

  In the present embodiment, the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) and the wiring 214 are electrically connected via the via 212. ing. Thereby, the potential of the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) is fixed. Here, the potential of the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) is any of a power supply potential, a ground potential, or another potential different from those potentials. There may be.

  A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIGS. 8A to 8E, FIGS. 9A and 9B, FIGS. 10A and 10B, and FIGS. 11A and 11B are semiconductors according to the second embodiment. It is sectional drawing which shows each process of the manufacturing method of an apparatus.

  First, as shown in FIG. 8A, after an element (not shown) such as a MOS transistor and a gate wiring 250 are formed on a semiconductor substrate 201, the semiconductor substrate 201 including the element and the gate wiring 250 is formed on the semiconductor substrate 201. An interlayer insulating film 202 is formed. The gate wiring 250 includes both a gate electrode formed on the active region and a wiring formed on the element isolation region and connected to the gate electrode. Next, a conductive film 203A made of, for example, TiN and having a thickness of about 10 nm to 50 nm is formed on the entire surface of the interlayer insulating film 202 by, eg, CVD.

  Next, as shown in FIG. 8B, the resist film 220 covering a predetermined region including an overlap portion between the gate wiring 250 and a wiring 206 (see FIG. 9A) which is an upper layer wiring described later is masked. As a result, the conductive shield layer 203 is formed by patterning the conductive film 203A by dry etching. Here, the conductive shield layer 203 extends on both sides of the gate wiring 250.

  Next, after removing the resist film 220, as shown in FIG. 8C, an interlayer insulating film 204 having a thickness of about 200 nm to 300 nm is formed on the conductive shield layer 203 and the interlayer insulating film 202, for example. . Next, via trenches 204 a reaching the conductive shield layer 203 are formed in the interlayer insulating film 204 at portions located on both sides of the gate wiring 250 by photolithography and dry etching. Next, as shown in FIG. 8D, by photolithography and dry etching, a wiring groove 204b1 at least partially overlapping the gate wiring 250 in plan view and the via grooves 204a are formed on the interlayer insulating film 204 in plan view. And the wiring groove 204b3 disposed on both sides of the wiring groove 204b1 with the wiring grooves 204b2 interposed therebetween. The depth of the wiring grooves 204b1, 204b2, and 204b3 is, for example, about 100 nm to 200 nm.

  Next, as shown in FIG. 8E, for example, Ta or TaN is formed on the interlayer insulating film 204 so as to cover the wall surface and bottom surface of the via groove 204a and the wall surfaces and bottom surface of the wiring grooves 204b1, 204b2, and 204b3. After forming the barrier film 221 to be formed, a conductive film 222 made of, for example, copper is formed on the barrier film 221 so that the via groove 204a and the wiring grooves 204b1, 204b2, and 204b3 are filled.

  Next, as shown in FIG. 9A, the barrier film 221 and the conductive film 222 outside the via groove 204a and the wiring grooves 204b1, 204b2, and 204b3 are removed by using, for example, a CMP method. As a result, a wiring 206 partially overlapping with the gate wiring 250 and made of the barrier film 206a and the conductive film 206b is formed in the wiring groove 204b1. A wall-like via 205 connected to the conductive shield layer 203 and made of the barrier film 205a and the conductive film 205b is formed in the via groove 204a, and connected to the wall-like via 205 and connected to the wall-like via 205 and the barrier film 207a and the conductive film 207b. Is formed in the wiring groove 204b2. Here, the dummy wiring 207 and the wall-like via 205 may have a dual damascene structure. Further, a wiring 216 which is disposed on both sides of the wiring 206 with the wirings 207 interposed therebetween and is composed of the barrier film 216a and the conductive film 216b is formed in the wiring groove 204b3.

  Next, as shown in FIG. 9B, an interlayer insulating film 208 having a thickness of, for example, about 60 nm to 100 nm is formed on each of the wiring 206, the dummy wiring 207, and the wiring 216 and on the interlayer insulating film 204. To do. Next, via grooves 208a reaching the dummy wirings 207 are formed in the interlayer insulating film 208 by photolithography and dry etching. Next, in the same manner as in the steps shown in FIGS. 8E and 9A, wall-shaped vias 209 connected to the dummy wirings 207 are formed in the via grooves 208a. That is, each wall-shaped via 209 covers the wall surface and bottom surface of the via groove 208a and is made of, for example, a barrier film 209a made of Ta or TaN, and a conductive film made of copper, for example, embedded in the via groove 208a with the barrier film 209a interposed therebetween. 209b. Next, in the same manner as the steps shown in FIGS. 8A and 8B, the interlayer insulating film 208 including an overlap portion between the wiring 206 and a wiring 213 (see FIG. 11B) which is an upper layer wiring described later. A conductive shield layer 210 made of, for example, TiN and having a thickness of about 10 nm to 50 nm is formed so as to cover the surface. Here, the conductive shield layer 210 is formed to extend on both sides of the wiring 206 so as to be connected to each wall-shaped via 209.

  Next, as illustrated in FIG. 10A, an interlayer insulating film 211 having a thickness of, for example, about 200 nm to 300 nm is formed on the conductive shield layer 210 and the interlayer insulating film 208. Next, via holes 217 reaching the respective wirings 216 are formed in the interlayer insulating films 208 and 211 by photolithography and dry etching, and the wirings 206 and wirings 213 which are upper layer wirings described later (see FIG. 11B). A via hole 211a reaching the conductive shield layer 210 is formed in a portion of the interlayer insulating film 211 located on both sides of the overlapping portion.

  Next, as shown in FIG. 10B, by photolithography and dry etching, connected to the upper part of the interlayer insulating film 211 with the wiring groove 211b1 at least partially overlapping with the wiring 206 in plan view and each via hole 211a. The wiring groove 211b2 to be connected and the wiring groove 211b3 connected to each via hole 217 are formed. Here, the depth of the wiring grooves 211b1, 211b2, and 211b3 is, for example, about 100 nm to 200 nm.

  Next, as shown in FIG. 11A, for example, Ta or TaN is formed on the interlayer insulating film 211 so as to cover the wall surfaces and bottom surfaces of the via holes 211a and 217 and the wall surfaces and bottom surfaces of the wiring grooves 211b1, 211b2, and 211b3. After the barrier film 223 made of is formed, a conductive film 224 made of, for example, copper is formed on the barrier film 223 so that the via holes 211a and 217, the bottom surface, and the wiring grooves 211b1, 211b2, and 211b3 are filled.

  Next, as illustrated in FIG. 11B, the via holes 211a and 217, the bottom surface, and the barrier film 223 and the conductive film 224 outside the wiring grooves 211b1, 211b2, and 211b3 are removed by using, for example, a CMP method. As a result, a wiring 213 partially overlapping with the wiring 206 and including the barrier film 213a and the conductive film 213b is formed in the wiring groove 211b1. A via 212 connected to the conductive shield layer 210 and formed of the barrier film 212a and the conductive film 212b is formed in the via hole 211a, and a wiring 214 connected to the via 212 and formed of the barrier film 214a and the conductive film 214b. Is formed in the wiring groove 211b2. Here, the wiring 214 and the via 212 may have a dual damascene structure. Furthermore, a via 218 connected to the wiring 216 and formed of the barrier film 218a and the conductive film 218b is formed in the via hole 217, and a wiring 219 connected to the via 218 and formed of the barrier film 219a and the conductive film 219b is formed in the wiring groove. 211b3. Here, the wiring 219 and the via 218 may have a dual damascene structure.

  According to the manufacturing method of the present embodiment described above, the semiconductor device of the present embodiment shown in FIGS. 7A and 7B can be obtained, and thus the same as that described for the semiconductor device of the present embodiment. An effect can be obtained.

  In the present embodiment, the material of the interlayer insulating films 202, 204, 208, and 211 is not particularly limited. For example, the SiC film, the plasma TEOS film, the SiOC film, the SiCO film, the SiCN film, or a laminated film of these insulating films is used. Etc. may be used.

  In this embodiment, TiN films are used as the conductive shield layers 203 and 210. However, the present invention is not limited to this. For example, a metal film such as a W film, a Ta film, a Ti film, or an Al film, or a NiAlN film, for example. Alternatively, a metal nitride film such as a TiSiN film or a WN film may be used. Here, for miniaturization of the semiconductor device, a single layer film of a metal nitride film having a thickness of about 50 nm or less may be used as the conductive shield layers 203 and 210, for example.

  Further, in this embodiment, the potential of the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) is fixed, but instead of this, the conductive shield layer 210 ( That is, the potentials of the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) may be floated. However, from the viewpoint of the effect of the present embodiment, the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) is made more conductive than the floating potential. 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) is preferably fixed. In particular, the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the It is preferable to fix the potential of the wall-like vias 205 and 209) to the power supply potential or the ground potential.

  In the present embodiment, the conductive shield layer 210 (that is, the conductive shield layer 203, the dummy wiring 207, and the wall-like vias 205 and 209) is provided in the same wiring layer as the wiring 213 in order to fix the potential. The wiring 214 and the conductive shield layer 210 are electrically connected, but instead of this, another wiring provided in a wiring layer different from the wiring 213 and the conductive shield layer 210 (or the conductive shield layer 203, dummy The wiring 207, the wall-shaped via 205, or the wall-shaped via 209) may be electrically connected.

  In this embodiment, damascene wiring is formed as the wirings 206, 213, 214, 216, and 219. However, the wiring structure is not particularly limited. Further, when the lower layer wiring of the wiring 206 is formed on the semiconductor substrate 201 with an insulating film interposed therebetween instead of the gate wiring 250, the same effect as in this embodiment can be obtained.

  Further, in this embodiment, instead of the laminated structure of the dummy wiring 207 and the wall-like via 205, a wall-like via that penetrates the interlayer insulating film 204 and connects the conductive shield layer 203 and the wall-like via 209 is formed. May be.

  In this embodiment, the conductive shield layer 203 is disposed at the boundary between the laminated films of the interlayer insulating films 202 and 204. However, the arrangement of the conductive shield layer 203 is particularly limited as long as it is in the insulating film between the laminated wirings. Not. In other words, the structure of the insulating film between the stacked wirings on which the conductive shield layer 203 is disposed is not particularly limited. Similarly, although the conductive shield layer 210 is arranged at the boundary between the laminated films of the interlayer insulating films 208 and 211, the arrangement of the conductive shield layer 210 is not particularly limited as long as it is in the insulating film between the laminated wirings. In other words, the structure of the insulating film between the stacked wirings on which the conductive shield layer 210 is disposed is not particularly limited.

  Further, in the present embodiment, the wiring 206 is surrounded by the conductive shield layers 203 and 210 and the conductive structure (for example, the dummy wiring 207 and the wall-like vias 205 and 209) that connect the conductive shield layers 203 and 210 (FIG. 7B). (See shielded area 215). However, a part of the conductive shield layer 203 or the conductive shield layer 210 may be removed, and a via or the like connected to the wiring 206 may be formed so as to pass through the region. Alternatively, a part of the dummy wiring 207 may be removed and a lead wiring connected to the wiring 206 may be formed so as to pass through the region.

  In this embodiment, the distance between the gate wiring 250 and the conductive shield layer 203 may be about 50 nm to 100 nm, for example. Further, the distance between the wiring 206 and the conductive shield layer 203 may be about 80 nm to 150 nm, for example. In addition, the distance between the gate wiring 250 and the wiring 206 between which the conductive shield layer 203 is disposed may be about 130 nm to 250 nm, for example. Further, the distance between the wiring 206 and the conductive shield layer 210 (that is, the thickness of the interlayer insulating film 208) may be, for example, about 50 nm to 100 nm. Further, the distance between the wiring 213 and the conductive shield layer 210 may be about 80 nm to 150 nm, for example. Further, the distance between the wiring 206 and the wiring 213 between which the conductive shield layer 210 is disposed may be, for example, about 130 nm to 250 nm. However, the numerical values such as the thicknesses of the interlayer insulating films 202, 204, 208, and 211 and the thicknesses of the wirings 206, 213, 214, 216, and 219 in the present embodiment are all examples, and are not limited thereto. Needless to say, if these numerical values change, the distance between the above-described wirings and conductive shield layers also changes. Also, depending on the wiring structure, interlayer insulating film material, etc., when the upper layer wiring and the lower layer wiring are at least partially overlapped, and the interval between the upper layer wiring and the lower layer wiring is 500 nm or less In addition, it is preferable to provide a conductive shield layer similar to that of the present embodiment at least in the overlapping portion of both wirings in the insulating film between the upper layer wiring and the lower layer wiring.

  The present invention relates to a semiconductor device and a manufacturing method thereof, and is suitable as a semiconductor device capable of reducing crosstalk noise generated between stacked wirings and a manufacturing method thereof.

101, 201 Semiconductor substrate 102, 104, 106, 202, 204, 208, 211 Interlayer insulating film 102a, 102a1, 102a2, 106b1, 106b2, 204b1, 204b2, 204b3, 211b1, 211b2, 211b3 Wiring groove 102a3, 204a, 208a Via Groove 103, 108, 109, 121, 206, 213, 214, 216, 219 Wiring 103a, 107a, 108a, 109a, 111, 114, 121a, 122a, 123a, 205a, 206a, 207a, 209a, 212a, 213a, 214a 216a, 218a, 219a, 221, 223 Barrier film 103b, 105A, 107b, 108b, 109b, 112, 115, 121b, 122b, 123b, 203A, 205b, 2 6b, 207b, 209b, 212b, 213b, 214b, 216b, 218b, 219b, 222,224 conductive film 104a via hole (via groove)
105, 203, 210 Conductive shield layer 106a, 211a, 217 Via hole 107, 212, 218 Via 113, 220 Resist film 122, 123, 205, 209 Wall-shaped via 207 Dummy wiring 215 Shield region 250 Gate wiring

Claims (20)

A first wiring;
A second wiring formed on the first wiring with an insulating film interposed therebetween,
The first wiring and the second wiring overlap at least partially in plan view,
A semiconductor device, wherein a conductive shield layer is formed at least in the insulating film in an overlapping portion between the first wiring and the second wiring. The semiconductor device according to claim 1,
A semiconductor device, wherein a potential of the conductive shield layer is fixed. The semiconductor device according to claim 2,
A third wiring formed above or below the conductive shield layer;
The semiconductor device further comprising a via formed in the insulating film so as to connect the third wiring and the conductive shield layer. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the conductive shield layer is formed over an entire overlap portion between the first wiring and the second wiring. The semiconductor device according to any one of claims 1 to 3,
There is a region where the conductive shield layer is not disposed in an overlap portion between the first wiring and the second wiring, and the dimensions of the region are the first wiring and the second wiring. A semiconductor device characterized by being smaller than the width of the narrow wiring. The semiconductor device according to any one of claims 1 to 5,
A fourth wiring formed in the same layer as the first wiring or the second wiring, and at least partially overlapping the first wiring or the second wiring in a side view;
A conductive structure connected to the conductive shield layer and extending from the conductive shield layer through the insulating film to an overlap portion between the first wiring or the second wiring and the fourth wiring And a semiconductor device. The semiconductor device according to any one of claims 1 to 6,
And further comprising another conductive shield layer formed under the first wiring with another insulating film interposed therebetween,
Each of the conductive shield layer and the other conductive shield layer extends to both sides of the first wiring,
2. A semiconductor device according to claim 1, wherein another conductive structure for connecting the conductive shield layer and the other conductive shield layer is provided on both sides of the first wiring. The semiconductor device according to claim 7,
The other conductive structure has a wall-like structure extending along the first wiring in a plan view. The semiconductor device according to any one of claims 1 to 8,
The semiconductor device according to claim 1, wherein the conductive shield layer is made of a metal film or a metal nitride film. The semiconductor device according to claim 9.
The semiconductor device according to claim 1, wherein the conductive shield layer has a single layer structure of a metal nitride film. The semiconductor device according to claim 10.
The semiconductor device, wherein the conductive shield layer is made of TiN. The semiconductor device according to claim 1,
The thickness of the said conductive shield layer is 50 nm or less, The semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of claims 1 to 12,
A distance between the first wiring and the second wiring is 500 nm or less. The semiconductor device according to claim 1,
The insulating film includes a first insulating film and a second insulating film formed on the first insulating film,
The conductive shield layer is formed on the surface of the first insulating film,
The semiconductor device, wherein the second insulating film is formed so as to cover the conductive shield layer. The semiconductor device according to claim 14.
The semiconductor device, wherein the second wiring is embedded in the upper portion of the second insulating film. The semiconductor device according to any one of claims 1 to 15,
A lower insulating film is formed below the insulating film,
The semiconductor device according to claim 1, wherein the first wiring is embedded in the upper portion of the lower insulating film. A method for manufacturing a semiconductor device, comprising: a first wiring; and a second wiring formed on the first wiring with an insulating film interposed therebetween,
The first wiring and the second wiring overlap at least partially in plan view,
A method of manufacturing a semiconductor device, comprising: forming a conductive shield layer in the insulating film at least in an overlap portion between the first wiring and the second wiring. In the manufacturing method of the semiconductor device according to claim 17,
The insulating film includes a first insulating film and a second insulating film formed on the first insulating film,
In the step of forming the conductive shield layer, after forming the first conductive film on the surface of the first insulating film, the first conductive film is patterned to form the conductive shield layer, Thereafter, the second insulating film is formed so as to cover the conductive shield layer. In the manufacturing method of the semiconductor device according to claim 18,
After the step of forming the conductive shield layer,
A step of forming a second wiring by forming a wiring groove on the second insulating film and then embedding a second conductive film in the wiring groove. Production method. In the manufacturing method of the semiconductor device of any one of Claims 17-19,
Prior to the step of forming the conductive shield layer,
After forming a lower insulating film below the insulating film, a wiring groove is formed above the lower insulating film, and then a third conductive film is embedded in the wiring groove to form the first wiring. A method of manufacturing a semiconductor device, further comprising a step.

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