JP2012252368A - Memory having information narrowing detection function, method for using the same, and memory and device including the memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a non-Neumann type information detection memory for making it unnecessary to perform successive comparison processing of a memory because of the fact that the largest problem of information detection such as pattern recognition is a search time.SOLUTION: Disclosed is a memory that has an information narrowing detection function, stores information for each memory address, and reads the information. The memory is characterized by including input means of input data, that is, both first data to be applied from the outside as data for comparing the stored data of the memory and second data as data for comparing the mutual addresses; means for determining doubly in parallel success/failure of the data of information and address stored in the both input data applied from the input means, and for further performing in parallel logical arithmetic operation of the success/failure determination result of the both data; and means for outputting the address of the memory which succeeds in the logical arithmetic operation. Thus, it is possible to widely use the memory for artificial intelligence or the like as well as intelligent information search.

Description

The present invention relates to a memory having an information narrowing detection function, a method of using the memory, a device using the memory, and artificial intelligence.

In the era when information is converted into data and can be used easily, various problems remain to detect and use appropriate information from the enormous information data.
In particular, technologies common to information detection typified by image recognition, voice recognition, OCR character recognition, full-text search, biometric authentication such as fingerprints, etc., detect matching or similar information (pattern) from information or It is a pattern recognition technology to analyze and is indispensable for advanced information processing because it is used in various fields such as social infrastructure equipment, industrial equipment, factory equipment, digital cameras and home appliances, and the latest robots and artificial intelligence. is there.

However, the biggest problem in the technology of information detection using pattern recognition as an example is the number of comparison combinations (number of searches) at the time of comparing information. Depending on the content of the target information, a high-speed arithmetic processing machine such as a supercomputer may be used to find the answer, and in some cases, the detection accuracy must be sacrificed.

The present invention realizes a memory capable of guaranteeing the accuracy of information detection, which is a long-standing problem of pattern recognition and information detection techniques as described above, and reducing the number of comparison combinations (number of searches, search time) to the limit. Application method, same applicant, same inventor filed on Feb. 18, 2010, Japanese Patent Application No. 2010-33376, information processing device information common management method, information detection method, data and address relative relationship lump All the items related to the parallel comparison associative memory, the information processing apparatus having the function of managing information in common, and the software program, the relative relation of data and address, and the parallel comparison associative memory, all of which claim priority to the present application It is.

Similarly, Japanese Patent Application No. 2010-47215 filed on March 4, 2010, a semiconductor integrated circuit having an information narrowing detection function, its use, and an apparatus using this semiconductor integrated circuit are independent of the aforementioned Japanese Patent Application No. 2010-33376. Changed the expression of the name of the semiconductor integrated circuit with the information refinement detection function and the invention, and clarified the concept of the logical operation of the double parallel pass / fail judgment result, which is the greatest feature of the present invention In addition, the range of information to be detected is expanded not only to two-dimensional images but also to information from one dimension to multi-dimension, and this entire application is claimed with priority over the present application.

The present application clarifies the expression of the name of the invention with a memory having an information narrowing detection function, integrates the above two previous applications, and mainly reduces the number of information narrowing circuits in the above Japanese Patent Application 2010-47215. Added a method of using this memory, for example, a means for doing this, a means for multiplexing double parallel logic operations, and an application to artificial intelligence, etc. It is.

As described above, information detection technology using pattern recognition and pattern matching as an example is extremely wide, and there are a large number of inventions related to shortening the search time, but the detection time is shortened as in the present invention. Therefore, there are no techniques or examples of the memory for essentially avoiding the sequential processing of individual memories, which is the fate of Neumann computers.
For reference, Japanese Patent Laid-Open No. 7-114577, data search device, data compression device and method show a method for repeatedly searching for information by comparing adjacent information, but the invention of the present application is In addition to comparing adjacent information, the data contents and the positional relationship between the addresses are compared in double parallel for all memory information.

JP-A-7-114577

The problem to be solved by the present invention is:
Targeting information that can be arranged in one-dimensional to multi-dimensional addresses or information that can be arranged, information that is detected (unknown information) and information that serves as a reference for detection (known information) Pattern recognition and knowledge processing that determine the same or similar information as the known information from the unknown information when the relationship between the data and the addresses of the multiple addresses passes the condition In the detection of information, etc., to ensure the accuracy of detection, reduce the number of data comparisons to the limit, and establish a non-Neumann-type information detection memory that allows the memory itself to detect the above information and establish its usage It is.

In order to solve the above problems,
Claim 1 is a memory capable of storing information and reading the information for each memory address,
The first data supplied from the outside is data for comparing the stored data of this memory, the second data is the data for comparing the addresses of this memory, input means for both input data,
(1) means for comparing the data stored in the memory with the first data in parallel and determining pass / fail; (2) means for comparing the address of the memory with the second data in parallel and determining pass / fail; and (3) or more ( 1) and (2) further comprising data for logically calculating both the pass / fail judgment results in parallel and an address double parallel logical operation means.
In claim 2, the pass / fail judgment means of (1) and the double parallel logic operation means of (3) are obtained by calculating the logical product of the pass / fail judgment of (1) and the pass / fail judgment of (2) ( It is characterized by comprising equivalent double parallel logical product (AND) operation means equivalent to AND).
In claim 3, the memory is
Counter means for measuring the result of each equivalent double parallel AND (AND) operation means for each memory address;
The first comparison is a means for counting up the counter of the memory address that has passed and passed the memory in parallel by the first data to 1 to make it a primary breakthrough address,
The subsequent comparison is based on the first data, and the positional relationship between the addresses of the memory address that has passed the pass / fail judgment of the memory in parallel and the primary breakthrough address is determined by the second data. Means for calculating by an equivalent double parallel logical product (AND) calculation means, and counting up the counter of the primary breakthrough address that broke through this calculation to be an N (an integer greater than or equal to 2) next breakthrough address;
Means for outputting the address of the Nth breakthrough address;
It is characterized by comprising.
According to a fourth aspect of the present invention, the equivalent double parallel logical product (AND) operation means is repeatedly performed by an address swap (exchange) means based on data for comparing addresses as the second data.
In claim 5, the data for comparing the address which is the second data is based on the primary breakthrough address,
(1) Comparison data indicating whether the comparison target address matches the relative address (2) Comparison data indicating whether the comparison target address exists inside or outside the range to be compared More than (1) (2) Or both.
In claim 6, the memory (1) information stored or storable as one-dimensional information taking voice information as an example (2) information stored or storable as two-dimensional information taking image information as an example ( 3) Information stored or storable as three-dimensional information taking 3D information as an example (4) Information stored or storable as multidimensional information taking spatio-temporal information as an example (5) Clustering information as an example The information is stored in each address group or is storable information. The memory configuration is intended to detect at least one of the information (1) to (5).
The data for comparing stored memory data as the first data is (1) coincidence of memory data, and (2) magnitude of memory data.
(3) Comparison including Don't Care for each memory bit It is characterized in that it is at least one of (1) to (3) above.
In the present invention, the first data and the second data may be input by one or both of (1) a data bus, (2) dedicated input, and (1) and (2).
According to a ninth aspect of the present invention, the means for outputting the address of the Nth breakthrough address is output by one or both of (1) a data bus (2) dedicated output and (1) and (2).
According to a tenth aspect of the present invention, the means for storing the primary breakthrough address is added to the counter means, whereby the circuit quantity of the counter means is reduced to a circuit quantity corresponding to the quantity of the primary breakthrough addresses that appear probabilistically. To do.
The present invention is characterized in that a processor is used as the address swapping means.
According to a twelfth aspect of the present invention, the double parallel logic operation is switched for each bank of memory.
In claim 13, a plurality of the first data and second data input means,
And a plurality of the double parallel logic operation means.
According to a fourteenth aspect of the present invention, the memory is used by being incorporated in a semiconductor for another purpose such as a CPU.
In claim 15, both the data and the address of the plurality of addresses of the information to be detected (unknown information) and the information to be detected (known information) are required. By passing the comparison condition of the number of times, by detecting information that is the same as or similar to the known information from the unknown information, the known information is used for the purpose of detecting the information and the position of the information. By comparing the unknown information stored in the memory according to claim 1 with the data of 1 and the second data, information that is the same as or similar to the known information from the unknown information and its address are: It is detected by reading the Nth order break-through address.
According to a sixteenth aspect, a plurality of samples necessary and sufficient for determining the same information or similar information are extracted from information (known information) serving as a reference for the detection based on a statistical probability, and this is extracted as the first information. And the second data are used as comparison conditions, so that the number of comparisons necessary for determining the same information or similar information is within the number of samples.
According to claim 17, when extracting the sample, an absolute value of a difference in data between adjacent samples is obtained, and information detection is performed with a sample feature amount obtained by summing the absolute values as a reference value or more. It is characterized by.
In claim 18, the positional relationship of the addresses according to claim 3 is (1) positional relationship on the address array stored as the one-dimensional information (2) positional relationship on the address array stored as the two-dimensional information (3) Positional relationship on the address array stored as the three-dimensional information (4) Positional relationship on the address array stored as the multidimensional information At least one positional relationship of (1) to (4) The pattern recognition is performed using the positional relationship of the addresses.
According to a nineteenth aspect of the present invention, the first comparison sample serving as the primary breakthrough address is a plurality of types of samples, or detection is performed with a certain range.
The present invention is characterized in that a CPU capable of reading and writing data by accessing a memory having the information narrowing detection function is used in combination.
The knowledge processing may be performed by storing knowledge information in a memory having the information narrowing detection function.
In claim 22
An apparatus using a memory having the information narrowing-down detection function.
The artificial intelligence according to claim 23, wherein a memory having the information narrowing detection function is used.
It is said.

It can be used as a memory with intelligent knowledge, and it can be used not only for reliable and high-speed detection or analysis of the identity and similarity of all information, but also in a wide range of information prediction fields and advanced knowledge processing. It can be used and a new flow of information processing by full-fledged non-Neumann information processing can be expected.

FIG. 1 shows an example of sampling points (Example 1). FIG. 2 shows an information detection example using sampling points (Example 2). FIG. 3 shows an example of sampling point evaluation method (Example 3). FIG. 4 is a conceptual example of a double parallel logic operation of data and address. FIG. 5 shows an example of a memory having an information narrowing detection function (Example 4). FIG. 6 shows an example of the address swap means A (Embodiment 5). FIG. 7 is an image A of address swap. FIG. 8 is an image B of address swap. FIG. 9 is an image C of address swap. FIG. 10 shows the concept of deformation image detection (Example 6). FIG. 11 shows an example of the address swap means B (Embodiment 7). FIG. 12 shows an example of the address swap means C (Embodiment 8). FIG. 13 shows a reduction example of the information narrowing detection circuit (Embodiment 9). FIG. 14 is a conceptual example of a double parallel logical operation of multiplexed data and address. FIG. 15 shows an example of information detection of an address one-dimensional array (Example 10). FIG. 16 shows an example of information detection of an address three-dimensional array (Example 11). FIG. 17 shows an example of advanced knowledge processing using the memory of the present invention (Embodiment 12).

First, the concept of information detection according to the present invention will be described using an image that is two-dimensional information as an example.

Normally, when detecting the identity of an image to be detected (unknown information 2) and a detection reference image (known information 1), it is collected from the detection reference image (known information 1). Based on some kind of image information, an image of an unknown detection target is basically searched by a brute force method. When the accuracy is obtained, it is necessary for each image coordinate.

As an example of the time required for searching, when searching for specific data on a displayed image for a specific pixel of a television screen by a personal computer or a digital television signal, about 2 million pixels are the target.
Once this full-screen bitmap data is expanded from the graphic memory to the search memory, the entire range of the expanded data is simply searched by the CPU searching for specific data at an average of 50 ns per pixel. In this case, the first search of the entire graphic range (full screen range) is 2 million × 50 nsec = 100 msec. Usually, the search target is narrowed down after the second time, but the target image is specified although the search time is shortened. However, if it is necessary to search a large number of images on one screen, the search time cannot be ignored no matter how fast processing is performed.

Furthermore, the above explanation is for the case of completely the same image. However, if there is a change in size or rotation of the image, it is necessary to repeatedly perform coordinate transformation operations, so the processing time starts from several hundred times the above. Such a search is difficult to implement because it may be several thousand times more.
The above is the fate of information detection by a Neumann computer that requires sequential CPU retrieval for each memory address.

Due to the technical background of the search time as described above, the mainstream of current search is a search for similarity between images by clustering of feature data obtained by extracting image features, and recent digital camera face recognition It is widely used for speech recognition and smile recognition.
However, the search capability, such as detection accuracy, search time, and detectable information, depends greatly on these feature extraction methods and clustering methods.
Also, in the field of image search, there are many cases where the misperception rate is fatal, and there are many needs for searching for images that require identity rather than similarity.

As described above, the reliability of the image search is pursued and the theme of time reduction is contradictory to each other. First, the reliable detection of the same image in the image search will be described.

As described above, the present invention seeks certainty and detects information in principle for one coordinate (address). Information that cannot be separated for realizing this will be described below. Explain the types and their resolution.

There are various types of image information. Here, two types of image information data will be described as an example.

The first is the case where the data from the frame buffer (graphic memory) of the displayed image is used as the image information. In the case of color, the information is usually stored in the data depth of R, G, B, 16 bits to 32 bits. .
Although it is possible to use the R, G, B, and color signals as they are, as an example of effective image detection, R, G, By collecting G, B, and 4 bits (3 sets of 16 combinations) into one pixel data, it is possible to detect an image with any color with high accuracy.
In this case, this color combination is 12 bits, 4096 combinations. When colors on the screen vary, the probability that one color exists on the screen is 2 million / 4096≈488 pixels (address). .

Second, for example, JPEG (Joint Photographic Experts Group), MPEG (Moving Picture Experts Group), and many other compressed image data blocks (for example, 8 × 8 pixels) as one coordinate, and the luminance of the block It is also possible to use the DC (direct current) component data of DTC (discrete cosine transform) of the color difference signal as it is as the data of the coordinates, or to use other information such as vector information.
In the case of this DCT, since it is a block unit, the number of coordinates (address) can be reduced significantly (for example, 1/64) as compared with pixels.

Needless to say, in either case, the resolution has never been high, but since the memory capacity becomes large, if the number of bits required from the LSB side of the quantized data 15 as described above is selected and used as image information data. Good.
In the following, an example will be described in which the pixel described above is targeted, and image data based on combination data of 12 bits and 4096 combinations of R, G, B with 2 million pixels (address) is used as image information.

FIG. 1 (example of sampling points) shows a sampling point 13 of an image (known information 1) serving as a detection reference.
The detection reference image A is an image of a relatively small size, and a total of 25 coordinates are arranged at equal intervals in the vertical and horizontal directions with the coordinates y0 and x0 as the center on the region of the image (known information 1) that becomes the detection reference. This is a case where the sampling points 13 are automatically arranged. In this case, 33 pixels 11 each on the XY axes and a total of 1089 pixels 11 are targeted.
There is no problem in increasing the size of the detection reference image.

The numbers 1 to 25 shown in the figure indicate the comparison order 14. In this example, the sampling points 13 that are far from the center and close to the sampling points 13 are set to be detected in diagonal order. The details are not limited to this and will be described later.

The detection reference image B is an example in which the sampling points 13 from 1 to 22 are manually set in correspondence with the detection reference image without being arranged at equal intervals as described above. The method of setting and detecting 13 uses the high feature recognition ability of human beings, and is effective in differentiating from other pixels by specifying a characteristic point or characteristic range. .

In this way, sample points can be set for each coordinate by using a detection method in which one coordinate is a detection unit in order to obtain the certainty of image detection. In many cases, a certain region is collectively used as a feature sample. This is one of the features of this method that cannot be realized by other search and detection methods.

FIG. 2 (an example of information detection using sampling points) is an explanation of the case where an image is detected using the detection reference image A shown in FIG. 1 described above as a detection reference image.
An image that serves as a reference for detection (known information 1) and an image that serves as a detection target (unknown information 2) are represented on the same image. The same screen is used for explanation purposes.
The group A shown in the figure corresponds to the case where the primary comparison is matched but the secondary comparison is NG. The group B is NG in the 11th comparison, the group C is NG in the 22nd comparison, and the group D is all sampling points. These detections in the case where the numbers 13 coincide with each other may be performed by reading the coordinate data 12 described above for each address and comparing them with each other.
In this figure, group A to group E are described as image areas that are completely separated in position, but in the case of an image, the coordinates that are usually the same data are adjacent or concentrated, and the tendency is more pronounced as the resolution is lower. However, there is no problem if the relative positional relationship is compared correctly.

In this case, it is possible to determine that the region of the group D is the same image as the reference screen in terms of probability. However, in addition to the sampling point 13, it is confirmed that all the pixels in each other's images match. By doing so, it is possible to exclude similar images and guarantee that they are completely the same image. This method is optimal for detection when the size of the target image is relatively small.

  By utilizing the verification method as described above, when the sampling points 13 such as the group E are partially concentrated and become inconsistent, the matching image portion is changed to a part of the image. It can be determined that the image has been added, and in the case of group C, it can also be determined as a similar image, which will be described later.

  As described above, a method for determining a relative position with respect to the data of the subsequent coordinates with reference to one coordinate of the sampling point 13 as a reference and leaving coordinates having no contradiction in the relative position as a candidate coordinate is a method of information retrieval such as pattern recognition. A method and a device which are conventional means and efficiently perform a combinational search and detect an image (information) at an extremely high speed are the gist of the present invention, and details thereof will be described later.

What is particularly important in the image detection method described above is the method of selecting the sampling point 13, one of which is a certain range of image data and the other is the degree of change in the image data.
For example, when a black image portion without change, a white image portion, an image with little change, or an image with few features such as an image with only character information is designated, it becomes difficult to detect the image.

The concept of the sampling point 13 that is closely related to the effectiveness and reliability of image detection will be described below.
When one coordinate on the image is used as a reference, the probability that the coordinate adjacent to this coordinate becomes the quantized data 15 that is the same as or close to the reference coordinate, that is, the correlation increases, and the correlation decreases as the coordinates move away. Accordingly, as shown in the sample of FIG. 1, it is more probable that confirmation is performed sequentially from the farther sampling point 13 each time, and the detection is quicker and the detection is efficient.

Accordingly, the existence probability of the same coordinate group by the plurality of sampling points completely dispersed is an index obtained by adding the number of sampling points 13 to the number of bits of data of these sampling points 13.

For example, if one coordinate described above is R, G, B and each 4 bit configuration, the number of combinations is 2 12 (4K ways), but if there are 10 sampling points 13, 2 120 power It is a probability combination corresponding to infinity in the number of combinations and actual operation, and if all of these sampling points 13 match if they are not monotonous images with few features, they may be determined as the same image.

However, since the target is an image in a limited narrow range or a monochrome image such as a character, the sampling points 13 that are completely dispersed as described above cannot be taken.

Accordingly, the discrimination ability evaluation of the sampling point 13 described below is performed, and an appropriate measure may be taken, such as raising an alarm, enlarging the image area, or adding the sampling point 13.

FIG. 3 (example of sampling point evaluation method) is an example of evaluating the discrimination ability of the sampling point 13 in the case of the detection reference image A of FIG. 1, and a total of 25 up to the coordinate 25 is finally set with the coordinate 1 as the detection reference coordinate. This shows a total of 16 sets of adjacent sampling points from A to P with four sampling points 13 adjacent to one sampling point 13 as one set.

As an example, group A includes four sampling points 13, 2, 10, 14, and 18, group B includes four sampling points 13, 10, 18, and 22, and so on.
At this time, each of the four sampling points 13 from the A group to the P group has a feature size, i.e., a sample size, in that there is a difference in the coordinate data 12 in each of the luminance information and the color information. Since it leads to the size of the feature quantity, the data is obtained by 6 combinations 2-10, 2-14, 2-18, 10-14, 10-18, and 14-18 of the two samples. The total value of the six combinations and the total (16 groups) are totaled, and the reference value of the feature value of the group can be obtained.
In the case of combined data of R, G, and B as in this example, each may be evaluated independently.
In the case of grasping the discrimination ability in the case of the same number of samples, the average feature amount obtained by adding the respective feature amounts of the A group to the P group and dividing by the 16 groups is used as a measure (reference value) of the feature amount. It can be used.

Needless to say, if the feature amount of this sample is small, the discrimination ability as the sampling point 13 will be affected. It is sufficient to adjust the number of sampling points 13 by increasing the number of sampling points 13 or by increasing the area of the image. Of course, the opposite case is also possible. It is important to make a reasonable number of search processes (time) suitable for.
The above is also effective when manually determining the sampling point 13.
This example is an example in which the discrimination ability is evaluated for two-dimensional information, but the feature amount can be determined based on the idea of taking the difference between the sample adjacent to one dimension to multidimension and its data.
Furthermore, depending on the type of information to be targeted, if a sample reference is uniquely determined and determined from the characteristics of the information, it is possible to detect information more reliably.

Up to now, the detection of information pursuing the certainty that is indispensable in realizing the present invention has been explained for the image of two-dimensional information, but the basic content of this idea is different from information of other dimensions Is also common.

Here, the arrangement of information stored in the memory for realizing the present invention will be described.
The information of the one-dimensional array is information stored continuously on the memory address, and the two-dimensional information has the maximum number of coordinates of each dimension as the array basic condition like the address 3 from 1 to n in FIG. It is information that is converted into a table and stored continuously as a one-dimensional memory address array, or information that can be stored, and the data size and memory capacity of the memory have a memory configuration suitable for each purpose.
Similarly, when storing three-dimensional or even multi-dimensional information on a memory address, the information is the same information as described above, which is converted into a table using the maximum number of coordinates of each dimension as an array basic condition. Is the same.

Therefore, if the coordinate data corresponding to each dimension is given for this information, the address corresponding to the given coordinate data can be specified based on the maximum number of coordinates of each dimension which is the basic array condition. The relative position of coordinates and the range of coordinates can be specified in the same manner.
Of course, if the target address is directly known even in high-dimensional information, it can be directly specified by the address or relative address.
The above has been described for the sake of confirmation. This address arrangement method is a general information arrangement method that is usually performed, and this general arrangement method of information for memory realizes the present invention. Since it is the basic information array above, it is extremely easy to use.

Hereinafter, a case where the memory 21 having the information narrowing-down detection function of the present invention is applied to an associative memory based on the conventional thinking will be described.

The associative memory is used for a memory that is particularly important in an information processing apparatus and requires high-speed processing, such as a cache memory and communication data processing.
In addition, for image data and the like, it has been actively studied as a search device for the purpose of a shortest distance search (similarity distance search) for detecting a similar image by a clustering method.

The outline of the associative memory will be described below.
The associative memory used for high-speed data processing, in addition to the normal memory function, gives data to be compared from the outside simultaneously (in parallel), and searches for information that can read the address of the memory that passes It is a very convenient device.
An example of this parallel processing 53 image is that seats (addresses) are prepared and seated at a venue where a large number of people gather, so that these people can freely select a color card (data) of their choice. For example, when examining people with red cards (data), in the case of a normal memory, it is necessary to examine all people by sequential comparison such as the order of seats, while in the case of an associative memory, for example, red The cards can be judged very quickly because they only have to raise their hands all at once (parallel comparison) and confirm (output processing) their seats (addresses).
As described above, the associative memory is a convenient device for comparing a large amount of information in parallel and searching for only necessary data.

Although it is an associative memory with various merits, as one of the weak points in the configuration, in the case of a memory device that reads and writes data by the data bus and the address bus, the comparison data (in this case red) given from the outside is Even if the pass determination is possible, if there are a plurality of addresses that pass, the addresses cannot be output all at once.

In order to solve this, it is sufficient to provide a priority function for the output, and output the address of the memory that passes sequentially for the memory that passes. However, if the number of addresses is not sufficiently narrowed down, it takes time to read. is necessary.
In a normal case, this address is read out, and the next comparison condition is given to the read address, and thereafter, narrowing down by sequential processing is performed based on this condition.
In the case of 12 bits and 4096 combination data of 2 million pixels (addresses) in the previous example, it is necessary to repeat the subsequent condition comparison for an average of 488 addresses, and most of them are not targeted (normally not left) This is the same for the third and subsequent pixels, which are wasteful processing.

Accordingly, in order to completely eliminate such sequential processing, the memory 21 having the information narrowing down detection function of the present invention can further reduce the relationship between the seats (addresses of people) who raised their hands with a red card. (Relationships) (except those next to each other and people with red cards in front, back, left, right) ) For both the pass of the stored data (card color) and the pass of the address (relative relationship of the seat) by giving comparison conditions (card color and seat relative relationship) Double parallel pass / fail judgment with the function to narrow down and detect addresses that pass the AND operation 55 based on the parallel pass / fail judgment result (adjacent or people with red cards in front, back, left and right) 54 results Memory is to be realized more different double parallel logical operations 60 which can be a memory.

FIG. 4 (concept of double parallel logical operation of data and address) is a concept of logical product (AND) operation of the memory data described above and the double parallel pass / fail judgment result of the address.
Comparing the contents of the data of each address and comparing each address in parallel (double parallel), respectively, a pass / fail judgment 54, and a logical product (AND) operation 55 for narrowing down information based on the pass / fail judgment result Are further performed in parallel.
This calculation result may be used in any form.

As described above, an extremely large narrowing effect can be obtained even by narrowing down once, but ideal information narrowing down detection can be performed if these double parallel logic operations 60 can be continuously repeated.

In order to realize the above idea, the address pass / fail judgment circuit in the lower part of FIG. 4 is easy to express as a concept, but in the normal way of thinking, how to compare addresses and which address Since it is not determined whether to do this, it is not easy to actually make this concept a logic circuit.

For example, an address that has survived compared to the first time described so far, which can be considered as a primary breakthrough address 56 and compared with each address on the basis of this, is also the primary method as described above If the breakthrough address 56 is 488 addresses, a combined parallel address comparison circuit must be configured by combining all addresses and the 488 addresses, so that the configuration becomes extremely large.

If the number of memory addresses is small, it is possible to realize address comparison with the above configuration, but in this embodiment, even with a large-scale memory, the logic configuration of FIG. 4 is as simple as possible. To achieve this, by defining the primary breakthrough address 56 as the address of the reference origin for each (every) comparison, the addresses (coordinates) to be compared each time are the same as the respective primary breakthrough addresses 56. Focusing on the fact that the relative address (coordinate) is relatively the same position (address) in each comparison, the optimal solution of this logic circuit is obtained.

Specifically, the primary breakthrough address 56 is set as a reference origin coordinate for each sampling point shown in FIG. 1 described above, and a fixed relative bias or range is set for the addresses to be compared, and each primary breakthrough is set. It may be configured to check whether the data of the address of the other party of the address 56 passes this, and if it passes, this is used as the breakthrough address.

Further, by providing a counter for recording the number of breakthroughs at each address and allowing the number of breakthroughs to be accumulated and counted up at the primary breakthrough address 56 which is the reference origin, the number of breakthroughs within the primary breakthrough address 56 is the highest. By determining the address of the memory (N times) as the Nth order breakthrough address 57, a continuous narrowing down logic circuit becomes possible, and even with a very simple logic circuit configuration, the configuration satisfies all the original purposes. A device that overcomes one of the above problems can be realized.

As will be described later, the double parallel logical operation 60 of FIG. 4 is not limited to the logical product (AND) operation 55 alone, and the use of the operation result is also free.

FIG. 5 (an example of a memory having an information refinement detection function) shows an outline of the function of the memory 21 of the present invention related to the above contents based on an associative memory, and details such as timing of data processing are omitted. Only the concepts relevant to the present invention will be described.

An address bus 22 and a data bus 23 are connected to a memory 21 (hereinafter also referred to as a memory of the present invention) having the information narrowing detection function, and is configured to be able to exchange data with the outside.
Accordingly, the addresses of the memories 1 to n 32 are selected by the address decoder 31 of the address bus 22, and data can be written and read from the data bus 23.

The input data 25 gives data for detecting information to the memory 21 of the present invention. The memory comparison data 26 as the first data is data for comparing data in the memory from the outside. The data comparison circuit 33 determines whether or not the memory 32 from 1 to n and the data pass or fail, and if the result is a pass, the result is output as a pass output 41 before the address swap.
The address comparison data 27 and the address swap circuit 34 as the second input data 25 will be described later.

The breakthrough counter 35 is a counter that stores and adds the pass count of the data comparison circuit 33 as the breakthrough count by the pass output 42 after the address swap. The breakthrough counter 35 is a comparison count counter 29 that counts the number of comparisons between pieces of information. The number of times of breakthrough counter 35 has a function of outputting a match with the comparison number signal 43, and the output is connected to the OR gate 36 and the inhibit gate 37, and the cascade 44 is sequentially connected from the youngest address. An output priority (priority) process is performed in which the counter of the youngest address is prioritized and only one address is output.

The breakthrough address output processing circuit 38 performs a process of placing the priority output address on the output bus 24 and a process of clearing the breakthrough number counter 35 of the address for which the output process has been completed. If there is 35, that address is set as the next priority output, and the address of the Nth breakthrough can be sent out to the outside by the output bus 24 sequentially.
The dedicated output form of the dedicated bus output of this example is an example, and the output result can be directly put on the data bus 23.
Therefore, according to this configuration, the address (coordinates) of the number of breakthrough counter 35 having the largest number of breakthroughs (N times) is Winner (Nth breakthrough address 57), and the addresses are output in order of younger addresses. It is a configuration.

FIG. 6 (an example of the address swap circuit A) shows the basic concept of the address swap circuit 34 which is a means for realizing the present invention with a very simple logic circuit configuration.
The address swap circuit 34 is provided between the data comparison circuit 33 and the breakthrough number counter 35. The address swap circuit 34 outputs the breakthrough output to the target primary breakthrough address 56 at the time of each sample comparison. Provided for cumulative addition as a calculation result, and in the case of this example, the pass comparison output 41 before address swap by the relative address comparison data 51 of the address comparison data 27 which is the second data of the input data 25 described above, 6 are converted into XY-axis coordinate data, the converted pass output is shifted by the relative address, and the pass count counter 35 of the corresponding address as the pass output 42 after the address swap (the primary break address 56). ) Can be input as a breakthrough output.
That is, the pass output after address swap 42 is input to the primary breakthrough address 56 as a breakthrough output when the relative address condition of the address of the primary breakthrough address 56 is passed.
Of course, it is also possible to specify relative address comparison data 51 instead of coordinate data directly as a relative address and shift the relative address.

The input of the first and second data described above can be given from the data bus 23 or from a dedicated input.
An example in which the pixel data of the image described above or information data corresponding thereto is stored in the memory 21 of the present invention having this configuration and the image is detected from the unknown information 2 will be described.

The pixel data of the image is written in the addresses 32 corresponding to the respective coordinates in the memories 32 from memory 1 to n in FIG. 5 described above, and the comparison number counter 29 and all the breakthrough number counters 35 are all cleared. After that, the comparison number counter 29 is incremented for each comparison.
First, the pixel data of sample 1 is given as input data 25 to the memory comparison data 26 as the primary comparison, and the pass judgment of all the memories is performed in parallel and the pre-address swap pass output 41 of the data comparison circuit 33 is output as the primary pass output. The primary pass output is not subjected to address swap, but is passed as the pass output 42 after the address swap, in addition to the input of the breakthrough counter 35, and the counter value of the breakthrough address is set to 1. This is the primary breakthrough address 56. As described above, the second data is not necessary for the primary comparison.
As described above, the average number of occurrences of the primary breakthrough address 56 is 488 (i, j, k in FIG. 6). The same applies hereinafter.
In the case of FIG. 2, at this time, the memory address where the value of the breakthrough number counter 35 is 1 is five addresses of group A, group B 1, group C 1, group D 1, and group E 1. The coordinates are Winner candidates (primary breakthrough address 56), and this is the address (coordinates) that will be the point of explanation in the future.

Next, by specifying the pixel data of the sample 2 as the memory comparison data 26 as the secondary comparison, another address is newly selected as an average of 488 secondary secondary pass outputs.
Further, by designating the difference between the addresses of sample 1 and sample 2 as relative address comparison data 51 of address comparison data 27, among the newly selected 488 addresses, the primary breakthrough address 56 described above is used. The address (coordinates) corresponding to this difference is shifted and converted by the address swap circuit 34 shown in FIG. The post-address swap pass output 42 is added to the counter 35 (primary breakthrough address 56) as a breakthrough output.

That is, when the breakthrough counter 35 of the coordinates (addresses) 2 of groups A to E in FIG. 2 is counted up, the breakthrough counter 35 (primary breakthrough address 56 of the candidate coordinates that survived the determination of sample 1). ), A breakthrough input is given to the primary breakthrough address 56 as a secondary breakthrough output by biasing the relative address so that the count can be continuously increased.

In the case of FIG. 2 described above, at this time, the primary breakthrough address 56 in which the value of the breakthrough counter 35 is 2, is 1 for group B, 1 for group C, 1 for group D, 4 for 1 for group E. The location is a coordinate maintained as a candidate, and 1 in group A cannot be counted up and is dropped from the candidate.
The above contents determine whether or not the target memory address position (address position corresponding to the secondary sample) exists at the target position (relative address comparison data 51) with reference to the primary breakthrough address 56. This is equivalent to the logical product (AND) operation 55 being performed in parallel with the pass address by the secondary data comparison and the result being input as the breakthrough output to the breakthrough number counter 35 of the primary breakthrough address 56.

In the same manner, the data comparison in the memory 32 and the relative address with respect to the other samples based on the sample 1 of the primary comparison are read as a pair of input data 25, and the memory that breaks through each address group is primary. By collecting and counting up to the breakthrough address 56, it is possible to continuously narrow down the primary breakthrough addresses 56 (Winner candidates).

Accordingly, the primary breakthrough address 56 that breaks through to the last sample 25 (N is 25) in FIG. 2 is only the 1 coordinate (25th Winner) of group D, and the breakthrough counter 35 of this coordinate (address) The value is 25, and the breakthrough counter 35 coincides with the comparison signal 43 of the comparison counter 29 and its output is input to the subsequent OR gate 36 and the inhibit gate 37.

FIG. 7 (image A of address swap) explains as an image the pass of both the data explained so far and the relative relationship of the addresses, that is, the contents of breakthrough by the double parallel AND operation.
As shown in the figure, a total of six primary breakthrough addresses 56 from A to F are shown in the coordinates of the screen by the first primary comparison.
This address swap is performed relative to all addresses, but the primary breakthrough address 56 is the relative coordinate position of the secondary comparison to be compared next in each address group to be compared. Look through the telescope, and if there is a pass output of the secondary pass address (black circle in this figure), it will be taken as a breakthrough output, which is just an image of swap.
Similarly, in the tertiary comparison, the relative coordinate position to be compared is looked into with a telescope, and the pass output of the tertiary pass address (black triangle mark in this figure) is taken as the breakthrough output, and so on.
In this example, the E counter is updated to 2, and the B counter is updated to 3.

FIG. 8 (image B of address swap) explains the image on the coordinates of A and B and the two primary breakthrough addresses 56 shown in FIG. 7 as an image on the address.
As shown in FIG. 8, the primary breakthrough address 56 is an image in which the data comparison circuit from sample 2 to sample 25 is looked into with a telescope, and if the looked-in data comparison circuit passes, it is taken as a breakthrough output. .
Needless to say, switching of the telescope is set every time by relative address comparison data 51 which is data for comparing the relative positional relationship of addresses.

Actually, the pass output by the secondary, tertiary, and Nth order comparisons that are not relative to the address of the primary breakthrough address 56 is also counted up to a relatively shifted address, but the sample is appropriate and intentional. Otherwise, it will be sporadic every time and pass output will not be concentrated on a specific address.
This is because a special relationship (pattern) that the specific part of the sample image (information) and the unknown image (information) are the same is not established.
The primary breakthrough address 56 always retains the counting advantage (initially 1) and has the right to collect the pass output as breakthrough output on behalf of the group of sample addresses associated with the relative address of the primary breakthrough address 56. It is the image of the ruler.

FIG. 9 (address swap image C) shows an example of address swap at an actual two-dimensional array address.
Tables A and B show addresses (coordinates) 1 to 100 before the address swap, and four addresses (coordinates) 24, 50, 67, and 72 are the primary breakthrough addresses 56.
Table A shows the case where the secondary comparison address is the data comparison address where the relative address is −22. At this time, the address 72 is not subject to the coordinates of the other party.
Table B shows a case where the tertiary comparison address is an address having a relative address of +31 and the data comparison address. At this time, the addresses 50 and 72 are excluded from the coordinates of the other party.
Table C is obtained by shifting the address of Table A by -22. The primary breakthrough address 56 of 24, 50, and 67 can normally obtain the pass / fail result of each partner's data. It can be counted up (swap count) as a breakthrough output.
Table D is obtained by shifting Table B by +31 addresses, and the primary breakthrough address 56 of 24 and 67 can normally obtain the pass / fail result of each partner's data. You can count up (swap count).
The above process is repeated a predetermined number of times, and the primary breakthrough address 56 in which the coordinate position of the address of the other party to be compared is normal can survive to the end.

As described above based on various examples, the content up to now is the same as the sampling point 13 (data of the data) that is compared each time after that by performing address swapping (exchange) with reference to the primary breakthrough address 56. Pass) and further whether or not it exists at the target position (relative address comparison data 51) is continuously double-parallelized, and a pass / fail judgment 54 is performed, and a logical product (AND) operation 55 is performed in parallel. This is equivalent to outputting the result to the breakthrough counter 35 of the primary breakthrough address 56 every time. The address swap circuit 34 integrates the parallel address pass / fail judgment and the parallel AND operation in the lower part of FIG. It is a highly efficient logic circuit that plays a role, that is, an equivalent double parallel AND (AND) operation 61 means.
The final result is that the N-th breakthrough address 57, which is the number of comparisons, is read by the break-through address output processing circuit 38 and the output bus 24, and the address of the group of information including the N-th breakthrough address 57 is specified, that is, the pattern is recognized. Become.
By specifying the comparison number signal 43 using the comparison number counter 29 as a presettable counter, it is possible to read the address of the counter (Nth order breakthrough address 57) having an arbitrary count value and its progress.

An example of the address swap circuit 34 is provided with a register for address conversion as shown in FIG. 6, and the pre-address swap pass output 41 from the data comparison circuit 33 is relatively transferred by the coordinate data of the relative address comparison data 51. Since this register operation is a relative shift of all addresses, the data output means by addition / subtraction operation, or the simplest one can be easily realized by a shift register of the data length for the address. It is.

The address swap method using the above registers is an example for explanation, and other methods such as swapping (exchange) using an address decoder directly may be used.
Similarly, the address swap circuit 34 and the breakthrough number counter 35 are indispensable means for realizing the information narrowing detection of the present invention. However, the present invention is not limited to this configuration, and the address swap circuit 34 and the breakthrough number counter 35 are individually implemented for each address by other methods. It is also possible.

This method of determining pass / fail of the relative relationship between data and its addresses collectively is a pass / fail determination in which both the data comparison conditions of all the memories 32 shown in FIG. 54, which is equivalent to the logical product operation 55 performed in parallel. In principle, the address sequential processing of Neumann type information processing for individual addresses is unnecessary.

Therefore, when the unknown image of 2 million pixels described so far has a resolution of 12 bits and the number of data groups is 4096 groups, the number of comparisons of data necessary to detect the same image from the unknown images is as follows. Usually, the image is converged in 2 to 3 times, and the target image can be surely found by the number of data comparisons of the maximum number of samples (25 times in this example).

Furthermore, as shown in FIG. 7, this method is a repetition of all coordinate pattern matching using input data with the primary breakthrough address 56 as a reference origin (comparison for all memories each time), so that part of the image is partially displayed. It is also possible to detect an approximate image (hereinafter referred to as an approximate image) when it is missing.

For example, in the case of FIG. 2, after completing the comparison 25 times, the counter of the coordinate 1 of group A is 1, the counter of the coordinate of group B is 10, the value of the counter of the coordinate of 1 of group C is 21, The value of the coordinate of 1 is 25, and the value of the coordinate of 1 of the group E is 22.
That is, the address of the coordinate with a high counter value is highly likely to be an image with a partial image missing or an approximate image.
Coordinates whose counter value is equal to or greater than a certain value (for example, 20 times) are read out, and after completion of a predetermined (in this case, 25 times) comparison, peripheral coordinates may be determined in detail if necessary.
Therefore, this method is effective not only for detecting the same image at a high speed but also for an approximate image based on a certain definition.

Further, by further developing the concept of this address wap (exchange), it is also possible to detect an image whose image is enlarged or reduced or rotated, hereinafter referred to as a deformed image, with a minimum number of detections.

FIG. 10 (concept of detecting a deformed image) explains an effective method in the case where detection is performed on the premise of a deformed image in which the image to be compared is enlarged or reduced or rotated, and in some cases, the data is changed.

In FIG. 10, the sampling point 13 of the known image is superimposed on the primary breakthrough address 56 of the unknown image that has passed the comparison of the primary sample.
This example shows a case where the size of an unknown image is likely to be doubled (4 times as a screen) on the XY axes with the reference origin of coordinate 1 as the center.
If the deformed image to be searched exists in this, all the coordinates 2 to 25 of the sample corresponding to the deformed image should be present inside the circle shown in the figure, and therefore the coordinates including the circle The range may be the image detection range of this coordinate 1.

Therefore, the conventional concept of address (coordinate) shift conversion is expanded, and whether or not there is a coordinate having the same data value as the sample in the coordinate range specified from the reference origin of coordinate 1, in this case, the number is It is possible to detect a deformed image by determining whether the coordinates are equivalent to the number of samples to be specified (25 in this example) within this range by determining whether there is simply no relation. Become.

Also in this case, the certainty of the sample is determined, and the certainty is high by setting the number of samples and the discrimination ability as a fixed reference and setting the target range within a fixed range.

In this case as well, a means for concentrating and storing the output of both data and addresses (breakthrough) at the target primary breakthrough address 56 every hour, which is stored and added, in this example, the decision result is accumulated in the breakthrough number counter 35 of one coordinate. If a method is possible, even for such a deformed image, the image can be detected with the minimum number of data comparisons that maximizes the number of samples.

In FIG. 11 (example of address swap means B), the address conversion described in FIG. 6 is regarded as a range of addresses from one-to-one address shift conversion to realize the above concept, and this is converted into address comparison data 27 from the outside. , By inputting as address range comparison data 52, the pre-address swap pass output 41 of i, j, k that passed in this address range is taken in as an address range corresponding to the comparison condition. In this configuration, a pass output 42 after address swapping is input to the breakthrough counter 35 of the primary breakthrough address 56 in the address group.
This is an image in which the telescope described in FIG. 7 is changed to a parabolic astronomical telescope and the breakthrough output is taken to the primary breakthrough address 56.

For example, when one coordinate of an image having an image range of about 1000 pixels shown in FIG. 1 as described above is used as a reference, if the coordinate range of XY axis slightly over 7000 pixels with the one coordinate as the center is 2 Even in a deformed image with rotation expanded to double, the image can be detected with the minimum number of data comparisons that maximizes the number of samples.

In the case of an image when the coordinate conversion or the image is reduced, the coordinates corresponding to the sample coordinates may be lost.
Although this method is less reliable than the method of completely matching relative coordinates described in FIG. 6, it is possible to detect an image at a very high speed by making the identification ability and the number of samples appropriate.

Further, if the data comparison circuit 33 of the memory 32 determines the pass / fail as a size comparison having a range of luminance and color levels from the comparison of pass / fail of data matching, it depends not only on the deformed image but also on the definition method. However, similar images can be detected.
In such a case, it is more effective to make a pass / fail determination using a ternary memory that can be compared by Don't Care for each memory bit other than the pass / fail determination by magnitude or match.

Normally, detection of an image with a change in size or rotation of the image requires an extremely large number of search processing operations such as coordinate conversion. However, according to this method, the target deformed image (by comparing the number of samples only) (Including approximate images) can be detected.
In many cases, it is sufficient to be able to detect the center position and the center of gravity position of a deformed image or a similar image as described above, but how many times it is necessary to detect the enlargement / reduction or rotation angle of the image. This can be handled by adding a data comparison.

When it is necessary as described above, after detecting the range where the image exists once, as shown in FIG. 10, where the coordinates of the four diagonals 2, 4, 3, 5 exist, What is necessary is to divide the detection range A into 4 divisions and the division detection range B into 16 divisions so that the range can be limited and detected. If you compare the data, you can grasp the deformation of the image.
Usually, when detecting a deformed image for which the degree of deformation cannot be estimated, it is necessary to estimate the deformation situation of the possible image, perform a number of coordinate transformations, and perform pattern matching. Compared to detection, pattern matching that is too fast for comparison is possible.
If the range to be divided is subdivided, more accurate detection is possible.
Although the above is an example, a complex image can be detected by adding the minimum number of data comparisons in this way.

In this example, an explanation was given of an example in which a large range was set for all sampling points on the assumption that the image could be scaled or rotated, but for each sampling point It is also possible to perform detection by specifying a specific range individually. This method is also important in the case where the same or similar data exists continuously in order to complement the uncertainty of the data and its address (position). If a similar image is defined based on the position of sampling point 13 and its data, it is possible to detect a wide range of images including the same image, approximate image, modified image, and similar image.

The memory 21 of the present invention compares, for example, two detection methods other than the two detection methods described above, ie, the coordinate shift method (matches the relative address to be compared with the address) and the coordinate range method (exists within the range of the coordinates with which the address is compared). The application of address swap is possible even outside the coordinate range, etc., both of which can be realized only by the data setting of the address comparison data 27 of the address swap circuit 34, so that these can be integrated. By combining these image detection methods, more various images can be detected.
In this example, in order to simplify the explanation, the method of combining the R, G, B color data into one address data has been described, but it is also easy to compare each of the R, G, B addresses independently. Is feasible.

The memory 21 of the present invention has a basic structure capable of comparing memory data in parallel, such as an associative memory, a means for performing address swapping, a counter for storing the number of passes, and a general Since it is a very simple structure that can be configured with a priority encoder, it is easy to increase the capacity.

Needless to say, the memory 21 of the present invention fundamentally solves the number of search (comparison) of the combination problem based on the correlation between the data and the address of the data, and if the sample is properly selected, the number of samples is limited to the upper limit. The device guarantees the minimum number of data comparisons, and can be applied to image detection by coordinate correlation of clustered similar features and various other information.

In the description so far, the case where information is repeatedly narrowed down has been described, but it is needless to say that single information detection can be performed by narrowing down only the primary comparison and the secondary comparison.

As described above, if the memory 21 of the present invention having the intelligence knowledge capable of detecting information by itself can be used, the CPU or GPU only gives input data and reads the result at the time of information retrieval. Can be reduced.
Since extremely high-speed information detection is possible, if the memory size is insufficient, information detection may be performed by dividing the information.

Even if the data comparison processing time of each time of the memory 21 of the present invention is a conservative processing time and averages 1 μsec each time, even if it is an image of any size, it may be several hundreds of times even if it is several μsec to long. Since it is possible to reliably detect target information within a microsecond, it is possible to detect information on one frame (frame) for a moving image as well as known information 1 to be detected continuously. Wide application is possible even when there is a large amount.
Needless to say, further advanced information detection is possible by collaboration (combination use) with a normal CPU that sequentially processes by accessing the memory 32 of the memory 21 of the present invention.

Although the outline of the present invention has been described above centering on image information, the information detection method and the memory 21 of the present invention are also effective for detecting one-dimensional information (such as speech) and information arranged as a multidimensional space. It is.

FIG. 12 (an example of the address swap means C) expands the two-dimensional information of FIG. 6 to three axes of X, Y, and Z so that the same arrangement or similar arrangement of information arranged in the three-dimensional space can be detected. An example of information detection, which is an example and can be an N-dimensional space, will be described later.

  The memory 21 having the information narrowing detection function described so far has made it possible to count the number of breakthroughs for all the memories, and continuously detect the same information and similar information by the number of breakthroughs. When the number of memories is large or for the purpose of further simplifying the circuit configuration, the number of circuits of the breakthrough number counter 35, the OR gate 36, and the inhibit gate 37 can be reduced.

  FIG. 13 (reduction example of the information narrowing detection circuit) is a reduction in the number of circuits based on the basic concept of the memory 21 of the present invention shown in FIGS. 4 and 5, and is used as described above. Note that the number of circuits after the number counter 35 is the number of primary breakthrough addresses 56 that appear in the primary comparison in the normal case (in the above description, the resolution is 4096 with 2 million addresses and an average of 488 addresses). The number corresponding to this, for example, the number of circuits after the breakthrough counter 35 is reduced to, for example, 1/1000 or 1/2000 of the number of addresses in the memory 32, and the output is reduced from A to X in the figure. .

In this case, the counter stores one breakthrough address 56 of each address group described with reference to FIG. 7 and can be read as a group breakthrough counter 58 configured to be able to read this address. What is necessary is just composition.
In such a configuration, the address swap may be performed by mounting a simple address arithmetic processor in the address swap circuit 34. In this way, the degree of freedom of address swap (exchange) using the arithmetic processor By narrowing down, it can be expected to narrow down information by various methods.

If the number of primary breakthrough addresses 56 overflows, an alarm may be raised to change the primary comparison sample.

Further, as a method for reducing the number of circuits, a circuit configuration in which the double parallel logical operation 60 is performed by switching for each bank of the memory is also possible.

The method that can count the number of passes for all memories is ideal because there is no limit on the number of appearances of the primary breakthrough address 56, but the information refinement detection function that simplifies the circuit configuration of the information refinement function in this way. Even with the memory 21 provided, it is possible to reliably detect target information by the information detection methods described so far.

With the configuration as described above, the degree of freedom regarding the number of addresses and the number of bits of the memory 21 of the present invention, that is, the memory capacity can be increased, and a ternary memory can also be used as described above. It is.

FIG. 14 (conceptual example of the double parallel logical operation of multiplexed data and address) is an example in which the double parallel logical operation described in FIG. 4 is multiplexed.
As shown in the figure, the memory 21 of the present invention comprises two sets of comparison data for comparing memory data and two sets of data for comparing addresses, two sets of double parallel pass / fail judgment circuits, and a double parallel logical product. Two sets of arithmetic circuits are provided, respectively, and a logical sum (OR) operation 59 is further performed in parallel to output the logical product operation results.

Such a configuration is also possible by applying the circuit configuration of the memory 21 shown in FIG.
With this configuration, two patterns can be detected simultaneously.
This example is an example of multiplexing, and a number of combinations other than two sets can be used, and the operation can be exclusive logic or any other logical operation other than logical product (AND) or logical sum (OR).
By multiplexing in this way according to the type and purpose of the information to be detected and using the double parallel logical operation 60 of various logical operations, it becomes possible to detect more advanced information.

The configuration of the memory 21 of the present invention is summarized by combining FIGS.
A memory that stores information for each memory address and can read the information.
The first data supplied from the outside is data for comparing the stored data of this memory, the second data is the data for comparing the addresses of this memory, input means for both input data,
(1) means for comparing the data stored in the memory with the first data in parallel and determining pass / fail; (2) means for comparing the address of the memory with the second data in parallel and determining pass / fail; and (3) or more ( 1) and (2) a memory having an information narrowing detection function, characterized by further comprising: data for logically operating both pass / fail determination results in parallel and address double-parallel logical operation 60 means.

Furthermore, as an example to narrow down the memory information to a simple circuit configuration,
The calculation result of the (1) pass / fail judgment means and the (3) double parallel logic operation means 60 is obtained by calculating a logical product (AND) of the (1) pass / fail judgment and the (2) pass / fail judgment. 2. The memory having an information narrowing down detection function according to claim 1, wherein said memory is constituted by equivalent double parallel logical product (AND) operation 61 means.

Further, as shown in FIG. 5, FIG. 13, etc., the result of the equivalent double parallel logical product (AND) operation means 61 is measured for each memory address in order to perform continuous double parallel logical operation 60 on this memory. Counter 35 means;
The first comparison is a means for counting up the counter of the memory address that has passed and passed the memory in parallel by the first data to 1 and setting it as the primary breakthrough address 56;
The subsequent comparison is based on the first data, and the positional relationship between the addresses of the memory address that has passed the pass / fail judgment of the memory in parallel and the primary breakthrough address is determined by the second data. An equivalent double parallel logical product (AND) operation means 61 means, and a means for counting up the counter of the primary breakthrough address that broke through this operation to become an N (an integer greater than or equal to 2) next breakthrough address;
Means for outputting the address of the Nth breakthrough address;
It is a memory characterized by comprising.

Further, the equivalent double parallel logical product (AND) operation means 61 is a memory which is repeatedly executed by address swap (exchange) means based on data for comparing addresses as the second data. .

Furthermore, the data for comparing the address which is the second data is based on the primary breakthrough address,
(1) Comparison data indicating whether the comparison target address matches the relative address (2) Comparison data indicating whether the comparison target address exists inside or outside the range to be compared Or a memory characterized by being both.

In addition, this memory reduces the number of circuits for narrowing down and multiplexes double parallel logic operations 60. In addition to logical products and logical sums, logical operations are not limited to logical products and logical sums. This is a memory capable of performing the calculation 60.

The description of the memory 21 itself of the present invention has been completed, and an example of information detection in a one-dimensional and multi-dimensional space will be described below.

FIG. 15 (information detection example of one-dimensional address array) shows, for example, data such as economic trends, stock prices, and temperatures on the vertical axis corresponding to addresses with the horizontal axis as the time axis, and is given as a sample. The information detection is based on the data of the information, and the information is detected from a huge database in the past. Such information detection is arranged and stored so as to associate the memory address with the time axis. It can be done very easily with the data.

As another example of information detection for the time axis, in the case of speech, based on sampling time before compression, speech data corresponding to this time, and speech data for each AAU (audio decoding unit) of the compressed speech data. Information detection is possible.
As an example of the memory 21 of the present invention capable of comparing ternary data, a spectrum band such as a human voice is classified into data by class, and it is very simply time-series if it is data for one time and one address. An array can be created.
Based on this, similar pattern recognition with a template sound source or the like is sufficient, and extremely high speed speech recognition is possible, which can be used in various fields of speech recognition.

Such detection of one-dimensional sequence information is extremely effective in performing a combination analysis of a DNA sequence requiring a large amount of information processing and four base sequences of a genome at high speed.
Similarly, the analysis based on the arrangement of character strings is the same.

FIG. 16 (information detection example of an address three-dimensional array) shows an example of detecting information arranged in a three-dimensional space.
As shown in the figure, it is an image obtained by detecting a specific pattern arranged in a three-dimensional space by the same method as described above.

  Needless to say, 3D space can represent the real space in which we exist, so it can be applied to all 3D information that can quantify the position of the 3D space and its data. It is also possible to develop into multidimensional information such as information.

  Such information detection in a three-dimensional space can be used for analysis of all arrangement relationships in outer space from the atomic or molecular level.

Especially for robots that require real-time processing because they can be detected at high speed, for example, 3D pattern recognition, 3D object recognition, object movement tracking, etc. that compare with many template screens for fast moving objects etc. Applications are endless.

In either case, it can be easily realized by storing data in an address array so that the memory address is associated with X, Y, Z, and 3 axes. It goes without saying that information can also be detected.

  In the above description, pattern recognition has been performed on information that has already been arranged for addresses or information that can be arranged in an address in a one-dimensional to multi-dimensional space. As an example, addresses are classified into clustered information groups. By devising the address and data arrangement, such as detecting this information, it is also possible to use information detection that makes full use of conventional algorithms.

The above is an outline of the case where information from one dimension to multi-dimension is detected. The features of the memory 21 of the present invention are summarized as follows.

The detection of information using the memory 21 of the present invention uses a single address and its data as a unit of detection, and the input data setting method can be used for a wide range of information such as approximate information, deformation information, and similar information, particularly from strict and accurate detection of the same information. Information can be detected reliably at high speed.

The number of samplings for information detection and how to select sampling points can be evaluated using statistical methods, and sampling can be automated, eliminating waste of the number of samplings and making the detection time reasonably reasonable. Another feature is that sample points can be set for each address (coordinate).

It can also be noted that detection censoring when there is no target information on unknown information is extremely fast.

This detection method is applicable to any information because there is no restriction on the size (size) of each other's information as long as a certain condition is satisfied, and the information is divided according to the size of the memory 21 of the present invention. Is also possible.

It is also possible to recognize a target pattern even from a memory in which one-dimensional information, multidimensional information, and other information are mixed and stored.

Also, in this method, if unknown information is appropriately arranged and stored in the memory 21 of the present invention, data other than sample points such as information processing, feature extraction, classification, etc. performed by other pattern recognition Another major feature is that no pre-processing is required.

Furthermore, this method has a great feature that time before performing information detection such as algorithm development is unnecessary, and the detection method (setting of comparison conditions) has a very simple configuration.
Therefore, it is not necessary to make cut-and-trial adjustments during system testing, and it will reliably detect the information you expect with the detection method you set. This method can be widely used for various information detection applications.

In the description so far, the description has been made centering on detection of information by collecting a sample on the assumption that there is known information 1. However, the input data 25 is set and information analysis is performed based on human judgment and estimation. It is also important.

In such a case, the primary comparison data, which is the first input data 25, affects the detection result. Therefore, detection is performed by setting a plurality of comparison data or by making the input data have a range. The analysis may be performed by a method that gradually limits the range depending on the result.
Such analysis greatly reduces the time and labor of data analysis such as information prediction in all fields such as astronomy, weather, physics, chemistry, and economy.

The memory 21 having the information narrowing function of the present invention eliminates the sequential processing of the memory, which is the fate of the Neumann computer, and the memory itself has intelligence knowledge to detect information. It will greatly break the common sense.
Therefore, it is not only used for image recognition, voice recognition, OCR character recognition, full-text search, fingerprint authentication, iris authentication, and robot artificial intelligence pattern recognition that have been studied and used in the past, but also weather, economic conditions, In addition to analysis of stock prices, molecular structures, DNA, genomes, character sequences, etc., discovery of new information (information prediction), social infrastructure, industrial equipment, industrial equipment, home equipment, and so on It can be widely used to detect information in unknown fields that have never been done.

The memory 21 having the information narrowing function of the present invention can also be used for knowledge processing as an artificial intelligence engine that requires detection of various types of information.
For example, the memory 21 of the present invention is applied to the cerebrum and cerebellum of the human brain, and further to the right brain and the left brain, and a plurality of parallel and hierarchical arrangements are used, and as templates, object recognition information, person recognition information, Various types of information, such as character recognition information, voice recognition information, taste information, and tactile information, are stored and compared with surrounding images and sounds given in real time, and information from various sensors. By doing so, it is possible to identify various information at the same time as human recognition ability, and to use it for extremely advanced knowledge processing such as selecting and executing the optimum action in the information. The way is endless.
FIG. 17 (an example of advanced knowledge processing using the memory of the present invention) is an embodiment in which the knowledge information described above is stored in the memory 21 of the present invention and knowledge processing is performed. The learning effect can be easily realized by updating the memory 21.

The memory 21 of the present invention transcends the conventional memory concept, has a very wide range of uses, and creates a new flow of information processing.

The memory 21 of the present invention is an ASIC (Application) other than the associative memory.
It can be realized as a memory having a general RAM or ROM configuration by using a specific integrated circuit (FPGA) or a field programmable gate array (FPGA). Can be configured with a memory structure with a unique dedicated structure, with a new type of semiconductor, or with other functions.

In the future, in addition to the semiconductor memory as described above, the memory of the present invention using a new element such as an optical element, a magnetic element, or a Josephson element currently under study can be expected.

1. Known information2. 2. Unknown information Address 4. Address data 11. Pixel 12. Coordinate data 13. Sampling point 14. Comparison order 15. Quantized data 21. 21. Memory with information narrowing detection function Address bus 23. Data bus 24. Output bus 25. Input data 26. Memory comparison data 27. Address comparison data 28. Reset signal 29. Comparison counter 31. Address decoder 32. Memory 33. Data comparison circuit 34. Address swap circuit 35. Breakthrough counter 36. OR gate 37. Inhibit gate 38. Breakthrough address output processing circuit 41. Pass output before address swap 42. Pass output after address swap 43. Comparison number signal 44. Cascade connection 51. Relative address comparison data 52. Address range comparison data 53. Parallel processing 54. Double parallel pass / fail judgment 55. AND operation 56.1 primary breakthrough address 57. Nth breakthrough address 58. Breakthrough counter by group 59. OR operation 60. Double parallel logic operation 61. Equivalent double parallel conjunction (AND) operation

The present invention relates to a memory having an information narrowing detection function, a method of using the same, and an apparatus including the memory.

In order to solve the above problems, in claim 1, a memory is provided that can store information for each memory address and can read the information.
(1) externally applied, the first comparison data for comparing the data stored in the memory in parallel, a second comparison data for comparing the addresses between the address of the memory in parallel, Means for inputting each comparison data
(2) first comparison data acceptance determining unit compares the data stored in the memory in parallel
(3) Means for comparing the addresses of this memory in parallel with the second comparison data to determine pass / fail.
(4) Data for logically calculating the result of both pass / fail judgments in the above (2) and (3) in parallel for each address and the logical operation means for each pass / fail result of the address
(1) to (4) are provided.
In claim 2, the logical operation of the memory having the information refinement detection function is a logical product (AND) operation,
(1 ) Means for determining whether or not the memory data is accepted or rejected in parallel by the first comparison data at the time of detecting information for the first time, and storing at least one passed memory address as a primary breakthrough address
(2) At the time of detecting information after the next time, the memory address which passed the pass / fail judgment of the memory data in parallel with the new first comparison data was replaced by the address replacement means based on the second comparison data. address
(3) Means for outputting an address that broke the logical product (AND) operation of the addresses (1) and (2) above
The above (1) to (3) are provided.
In a third aspect of the present invention, a memory having the information narrowing down detection function is:
(1) Counter means for measuring a comparison pass / fail judgment result based on each comparison data repeatedly given a predetermined number of times for each memory address
(2) A means for counting up the counter of the passed memory address to 1 at the time of detecting the information for the first time and setting this as the primary breakthrough address
(3) At the time of detection of the next and subsequent information repeatedly given, the address replacement means cumulatively counts up the logical product (AND) operation result to the primary breakthrough address counter and compares N ( 2 or more comparisons). Number of times ) Means for the next breakthrough
(4) Means for outputting the address of the Nth breakthrough address in (3) above
(1) to (4) are provided.
In claim 4
The address replacement means performs address replacement in parallel with the entire address range based on the second comparison data .
In claim 5, the data for comparing the addresses of the memory addresses as the second comparison data in parallel is:
The primary break-through address is used as a reference address, and when the information is detected after the next time, the memory address that has passed the pass / fail judgment of the memory data in parallel with the first comparison data, and the reference address, The relative position of
(1) match whether comparison data (2) for determining the comparison data or for determining whether present in the range (1) (2) in one of the information detection comparison data It is characterized by being.
The memory having the information narrowing down detection function according to claim 6,
(1) Information stored or storable as one-dimensional information taking voice information as an example (2) Information stored or storable as two-dimensional information taking image information as an example (3) Three-dimensional information as an example Information stored or storable as three-dimensional information (4) information stored or storable as multidimensional information as an example of spatiotemporal information (5) information as an example of clustering information by address group The memory configuration is intended for detection of at least one piece of information (1) to (5) above the stored or storable information.
In Claim 7, The data for comparing the data memorize | stored in the memory which is said 1st comparison data in parallel are:
(1) Memory data match detection (2) Memory data size detection
(3) Memory data range detection
(4) Comparison detection of individual memory bits
(5) Comparison detection of ternary memory data Above, it is at least one information detection comparison data (1) to (5).
In claim 8, the first comparison data and the second comparison data are:
(1) Data bus (2) Dedicated input It is characterized by being input by either or both of the input means (1) and (2).
In claim 9
The means for outputting the logical AND (AND) operation breakthrough according to claim 2 or the Nth breakthrough address according to claim 3 ,
(1) Data bus (2) Dedicated output or higher (1) (2) Output by either or both output means
According to a tenth aspect of the present invention, means for storing the address of the primary breakthrough address when the initial information is detected is added to the counter means to reduce the number of counter means for individually measuring memory addresses ( counter means = address number / n, n: natural number ).
In claim 11
A processor is mounted on a memory having the information narrowing detection function, and the address replacement means is realized by the processor .
In claim 12
(2) to (4) according to claim 1, further comprising a memory bank division comparison means for dividing and implementing the memory range .
A thirteenth aspect is characterized in that a plurality of means (1) to (4) according to the first aspect are provided in parallel .
According to a fourteenth aspect of the present invention, the memory having the information narrowing-down detection function is used by being incorporated in a semiconductor for another purpose such as a CPU.
In claim 15
In the memory having the information refinement detection function according to claim 2,
At the time of the first information detection and the information detection after the next time, each comparison data is given to this memory based on the known information, and the logical product (AND) operation breakthrough address is read and stored in this memory. It is characterized in that information detection is performed on information that is the same as or similar to the known information.
In claim 16
In the memory having the information refinement detection function according to claim 3,
The comparison data, which are a plurality of comparison samples necessary and sufficient to detect the same information or the similar information, are repeatedly given to the memory, and the counter value of the Nth order break-out counter is read out to be stored in the memory. It is characterized in that information detection is performed on information that is the same as or similar to the known information.
According to another aspect of the present invention, when the comparison sample is extracted, an absolute value of a difference between data of adjacent samples is obtained, and information is detected with a sample feature amount obtained by summing the absolute values as a predetermined value or more. It is characterized by that.
In claim 18
The information that is the same as or similar to the known information is pattern information .
In claim 19
Wherein Upon providing said first comparison data when the first information detection to determine the primary break address, the detection of the select optimal first of the comparative sample of a plurality of kinds of sample data, or the first comparison One or both of detection of information is performed by giving a certain data range to the data .
The present invention is characterized in that information is detected using a CPU capable of reading and writing data by accessing a memory having the information narrowing detection function .
According to a twenty-first aspect, the pattern information is stored as knowledge information in a memory having the information narrowing detection function, and knowledge processing is performed by detecting the pattern information .
In claim 22
An apparatus including a memory having the information narrowing-down detection function according to claim 1 .
It is said.

As described above, the present invention seeks certainty, and in principle detects information for each coordinate (address) as a comparative detection target, and can be separated for realizing this below. Explain the types of information and their resolution.

As described above, a method for determining a relative position with respect to the data of the subsequent coordinates with reference to one coordinate of the sampling point 13 as a reference and leaving coordinates having no contradiction in the relative position as a candidate coordinate is a method of information retrieval such as pattern recognition. a conventional manner, these combinatorial search efficiently performed, a spirit of method and device the present invention for detecting an image (information) at ultra high speed, will be described later this detailed.

As an example, group A includes four sampling points 13, 2, 10, 14, and 18, group B includes four sampling points 13, 10, 18, and 22, and so on.
At this time, each of the four sampling points 13 from the A group to the P group has a feature size, i.e., a sample size, in that there is a difference in the coordinate data 12 in each of the luminance information and the color information in each group. Since it leads to the size of the feature quantity, the data is obtained by 6 combinations 2-10, 2-14, 2-18, 10-14, 10-18, and 14-18 of the two samples. The total value of the six combinations and the total (16 groups) are summed up to obtain a predetermined value of the feature amount of the group.
In the case of combined data of R, G, and B as in this example, each may be evaluated independently.
Also, in the case of grasping the discrimination ability in the case of the same number of samples, the average feature amount obtained by adding the respective feature amounts of the A group to the P group and dividing by the 16 groups is used as a scale ( predetermined value ) of the feature amount. It can be used.

The associative memory is used for a memory that is particularly important in an information processing apparatus and requires high-speed processing, such as a cache memory and communication data processing.
In addition, for image data and the like, it has been actively studied as a search device for the purpose of a shortest distance search (similarity distance search) for detecting a similar image by a clustering technique.

The outline of the associative memory will be described below.
The associative memory used for high-speed data processing is the information that can give the data to be compared from the outside in addition to the normal memory function all at the same time (in parallel) and read the address of the passing memory It is a very convenient device for searching for.
An example of this parallel processing 53 image is that seats (addresses) are prepared and seated at a venue where a large number of people gather, so that these people can freely select a color card (data) of their choice. For example, when examining people with red cards (data), in the case of a normal memory, it is necessary to examine all people by sequential comparison such as the order of seats, while in the case of an associative memory, for example, red The cards can be judged very quickly because they only have to raise their hands all at once (parallel comparison) and confirm (output processing) their seats (addresses).
As described above, the associative memory is a convenient device for comparing a large amount of information in parallel and searching for only the necessary data.

Although it is an associative memory with various merits, as one of the weak points in the configuration, in the case of a memory device that reads and writes data by the data bus and the address bus, the comparison data (in this case red) given from the outside at the same time Even if the pass determination is possible, when there are a plurality of pass addresses, the addresses cannot be output all at once.

Accordingly, in order to completely eliminate such sequential processing, the memory 21 having the information narrowing down detection function of the present invention can further reduce the relationship between the seats (addresses of people) who raised their hands with a red card. (Relationships) (except those next to each other and people with red cards in front, back, left, right) ) and compared to the target condition (card colors, by providing relative relationship) of the seat, and passing the stored data (color card), and passing the positional relationship between the address between (relative relationship of the seat), Double parallel with the function of narrowing down and detecting addresses that pass the AND operation 55 based on the parallel pass / fail judgment result of both of them (people with seats with red cards next to each other, front, back, left and right) Pass / fail judgment 5 The possible memory is to be realized more different double parallel logical operations 60 which can be a memory.

If the number of memory addresses is small, it is possible to realize address comparison with the above configuration, but in this embodiment, even with a large-scale memory, the logic configuration of FIG. 4 is as simple as possible. To achieve this, by defining the primary breakthrough address 56 as the address of the reference origin for each (every) comparison, the addresses (coordinates) to be compared each time are the same as the respective primary breakthrough addresses 56. Note that the relative address (coordinates) is relatively the same position (address) in each comparison, that is, by comparing the relative relationship between the primary breakthrough address 56 and each other's addresses to be compared each time thereafter. The optimal solution of logic circuit is being sought.

Further, by providing a counter for recording the number of breakthroughs at each address and allowing the number of breakthroughs to be accumulated and counted up at the primary breakthrough address 56 which is the reference origin, the number of breakthroughs within the primary breakthrough address 56 is the highest. By determining the address of the memory (N times) as the Nth order breakthrough address 57, a continuous narrowing down logic circuit becomes possible, and even with a very simple logic circuit configuration, the configuration satisfies all the original purposes. A device that overcomes one of the above problems can be realized.

As described above based on various examples, the contents up to now are the same data (sampling point 13) that is compared each time after the address break ( address replacement ) with reference to the primary breakthrough address 56. Data pass) and whether or not it exists at the target position (relative address comparison data 51). 55, which is equivalent to outputting the result to the breakthrough number counter 35 of the primary breakthrough address 56 every time. The address swap circuit 34 integrates the parallel address pass / fail judgment and the parallel AND operation in the lower part of FIG. It is a highly efficient logic circuit that plays a role of one person, that is, an equivalent double parallel AND (AND) operation 61 means.
The final result is that the N-th breakthrough address 57, which is the number of comparisons, is read by the break-through address output processing circuit 38 and the output bus 24, and the address of the group of information including the N-th breakthrough address 57 is specified, that is, the pattern is recognized. Become.
By specifying the comparison number signal 43 using the comparison number counter 29 as a presettable counter, it is possible to read the address of the counter (Nth order breakthrough address 57) having an arbitrary count value and its progress.

The address swap method using the above registers is an example for explanation, and may be implemented by other methods such as swapping ( address replacement ) by directly using an address decoder.
Similarly, the address swap circuit 34 and the breakthrough number counter 35 are indispensable means for realizing the information narrowing detection of the present invention. However, the present invention is not limited to this configuration, and the address swap circuit 34 and the breakthrough number counter 35 are individually implemented for each address by other methods. It is also possible.

For example, in the case of FIG. 2, after completing the comparison 25 times, the counter of the coordinate 1 of group A is 1, the counter of the coordinate of group B is 10, the value of the counter of the coordinate of 1 of group C is 21, The value of the coordinate of 1 is 25, and the value of the coordinate of 1 of the group E is 22.
That is, the address of the coordinate with a high counter value is highly likely to be an image with a partial image missing or an approximate image.
Coordinates whose counter value is equal to or greater than a certain value (for example, 20 times) are read out, and after completion of a predetermined (in this case, 25 times) comparison, peripheral coordinates may be determined in detail if necessary.
Supporting this scheme I is is also effective approximation image based on certain defined not such only possible to detect the same image at a high speed.

Further, by further developing the concept of address wap ( address replacement ), it is possible to detect an image whose image is enlarged or reduced or rotated, and hereinafter referred to as a deformed image, with a minimum number of detections.

Further, if the data comparison circuit 33 of the memory 32 determines the pass / fail as a size comparison having a range of luminance and color levels from the comparison of pass / fail of data matching, it depends not only on the deformed image but also on the definition method. However, similar images can be detected.
Except acceptance determination by exact match as described above, magnitude comparison, range comparison, memory bit individual comparison, more Do not Care 3 value memory that can be compared by, etc. utilizing more effective information when the acceptance determination of Detection is possible .

The memory 21 of the present invention has a basic structure capable of comparing memory data in parallel, such as an associative memory, a means for performing address swapping ( address replacement ), a counter for storing the number of passes, Since it has a very simple structure that can be configured with a conventional priority encoder, it is easy to increase the capacity.

Needless to say, the memory 21 of the present invention fundamentally solves the number of search (comparison) of the combination problem based on the correlation between the data and the address of the data, and if the sample is properly selected, the number of samples is limited to the upper limit. The device guarantees the minimum number of data comparisons, and can be applied to image detection by coordinate correlation of clustered similar features and various other information.

In this case, the counter stores one breakthrough address 56 of each address group described with reference to FIG. 7 and can be read as a group breakthrough counter 58 configured to be able to read this address. What is necessary is just composition.
In such a configuration, address swap may be performed by mounting a simple address arithmetic processor in the address swap circuit 34. In this way, address swap ( address replacement ) is performed using the arithmetic processor. By increasing the degree of freedom, it can be expected to narrow down information by various methods.

The configuration of the memory 21 of the present invention is summarized by combining FIGS.
A memory that stores information for each memory address and can read the information.
(1) externally applied, the first comparison data for comparing the data stored in the memory in parallel, a second comparison data for comparing the addresses between the address of the memory in parallel, Means for inputting each comparison data
(2) first comparison data acceptance determining unit compares the data stored in the memory in parallel
(3) Means for comparing the addresses of this memory in parallel with the second comparison data to determine pass / fail.
(4) Data for logically calculating the result of both pass / fail judgments in the above (2) and (3) in parallel for each address and the logical operation means for each pass / fail result of the address
A memory with information narrowing detecting function, characterized by comprising (4) from above (1).

Furthermore, as an example to narrow down the memory information to a simple circuit configuration,
The logical operation of the memory having the information refinement detection function is a logical product (AND) operation,
(1 ) Means for determining whether or not the memory data is accepted or rejected in parallel by the first comparison data at the time of detecting information for the first time, and storing at least one passed memory address as a primary breakthrough address
(2) At the time of detecting information after the next time, the memory address which passed the pass / fail judgment of the memory data in parallel with the new first comparison data was replaced by the address replacement means based on the second comparison data. address
(3) Means for outputting an address that broke the logical product (AND) operation of the addresses (1) and (2) above
A memory with information narrowing detecting function according to claim 1, characterized in that it comprises more than (1) to (3).

Further, as shown in FIG. 5, FIG. 13, etc., the memory having the information narrowing down detection function in order to perform continuous repetitive double parallel logical operation 60 on this memory is as follows:
(1) Counter means for measuring a comparison pass / fail judgment result based on each comparison data repeatedly given a predetermined number of times for each memory address
(2) A means for counting up the counter of the passed memory address to 1 at the time of detecting the information for the first time and setting this as the primary breakthrough address
(3) At the time of detection of the next and subsequent information repeatedly given, the address replacement means cumulatively counts up the logical product (AND) operation result to the primary breakthrough address counter and compares N ( 2 or more comparisons). Number of times ) Means for the next breakthrough
(4) Means for outputting the address of the Nth breakthrough address in (3) above
A memory with information narrowing detection according to claim 2, characterized by including the above (1) to (4).

3. The memory having an information narrowing-down detection function according to claim 2, wherein said address replacement means replaces addresses in parallel in the entire address range based on said second comparison data .

Furthermore, the data for comparing the addresses of the memory addresses which are the second comparison data in parallel,
The primary break-through address is used as a reference address, and when the information is detected after the next time, the memory address that has passed the pass / fail judgment of the memory data in parallel with the first comparison data, and the reference address, The relative position of
(1) match whether comparison data (2) for determining the comparison data or for determining whether present in the range (1) (2) in one of the information detection comparison data 3. A memory having an information refinement detection function according to claim 2 .

Claims (23)

A memory that stores information for each memory address and can read the information.
The first data supplied from the outside is data for comparing the stored data of this memory, the second data is the data for comparing the addresses of this memory, input means for both input data,
(1) means for comparing the data stored in the memory with the first data in parallel and determining pass / fail; (2) means for comparing the address of the memory with the second data in parallel and determining pass / fail; and (3) or more ( 1), (2) A memory having an information narrowing detection function, characterized by further comprising: data for logically computing both pass / fail judgment results in parallel and address double parallel logic computing means. The calculation result of the (1) pass / fail judgment means and the (3) double parallel logic operation means is equivalent to the logical product (AND) of the (1) pass / fail judgment and the (2) pass / fail judgment. The memory having the information narrowing-down detection function according to claim 1, wherein the memory comprises an equivalent double parallel logical product (AND) operation means. The memory is
Counter means for measuring the result of each equivalent double parallel AND (AND) operation means for each memory address;
The first comparison is a means for counting up the counter of the memory address that has passed and passed the memory in parallel by the first data to 1 to make it a primary breakthrough address,
The subsequent comparison is based on the first data, and the positional relationship between the addresses of the memory address that has passed the pass / fail judgment of the memory in parallel and the primary breakthrough address is determined by the second data. Means for calculating by an equivalent double parallel logical product (AND) calculation means, and counting up the counter of the primary breakthrough address that broke through this calculation to be an N (an integer greater than or equal to 2) next breakthrough address;
Means for outputting the address of the Nth breakthrough address;
The memory having the information narrowing-down detection function according to claim 2. 4. The equivalent double parallel logical product (AND) operation means is repeatedly performed by address swap (exchange) means based on data for comparing addresses as the second data. A memory equipped with an information refinement detection function. The data for comparing the address which is the second data is based on the primary breakthrough address,
(1) Comparison data indicating whether the comparison target address matches the relative address (2) Comparison data indicating whether the comparison target address exists inside or outside the range to be compared More than (1) (2) 4. The memory having an information narrowing-down detection function according to claim 3, wherein the memory is a combination of both. The memory is (1) information stored or storable as one-dimensional information taking voice information as an example (2) information stored or storable as two-dimensional information taking image information as an example (3) three-dimensional information Information stored or memorable as three-dimensional information, for example (4) information memorized or memorable as multidimensional information, for example, spatio-temporal information (5) address information, for example, clustering information 4. The information narrowing detection function according to claim 3, wherein the memory configuration is intended for detection of at least one piece of information (1) to (5) that is greater than or equal to the information stored or storable by group. Memory. The data for comparing the memory data stored as the first data is (1) memory data match (2) memory data size
(3) The memory having the information narrowing detection function according to claim 3, wherein the memory includes at least one of the comparisons (1) to (3) including Don't Care for each individual memory bit. 4. The information narrowing-down detection according to claim 3, wherein the first data and the second data are input by one or both of (1) a data bus, (2) dedicated input, and (1) and (2). Functional memory. 4. The information narrowing down according to claim 3, wherein the means for outputting the address of the Nth breakthrough address is output by one or both of (1) data bus (2) dedicated output and (1) (2). Memory with detection function. 4. The circuit means of the counter means is reduced to a circuit quantity commensurate with the quantity of primary breakthrough addresses that appear probabilistically by adding means for storing the primary breakthrough address to the counter means. A memory with the described information refinement detection function. 4. The memory having an information narrowing-down detection function according to claim 3, wherein a processor is used as said address swapping (exchange) means. 2. The memory having an information narrowing-down detection function according to claim 1, wherein the double parallel logic operation is switched for each bank of the memory. A plurality of the first data and second data input means;
The memory having an information narrowing-down detection function according to claim 1, further comprising a plurality of the double parallel logic operation means. 2. The memory having an information narrowing-down detection function according to claim 1, wherein the memory is used by being incorporated in a semiconductor for another purpose such as a CPU. Comparison conditions of the required number of times for both the data and the addresses of the multiple addresses of the information to be detected (unknown information) and the information to be detected (known information). If the information is the same as or similar to the known information from the unknown information, the known information is used as the first data for the purpose of detecting the information and the position of the information. The second data is used to compare the unknown information stored in the memory according to claim 1, and from among the unknown information, the same or similar information as the known information and its address are used for the Nth order breakthrough. A method of using a memory having an information narrowing detection function, wherein the detection is performed by reading an address. Extracting a plurality of samples necessary and sufficient to determine the same information or similar information based on a statistical probability from information (known information) that serves as a reference for detection, the first data, 16. The information narrowing-down detection function according to claim 15, wherein the comparison number necessary for determining the same information or similar information is set within the number of samples by using a comparison condition as the second data. How to use memory with When extracting the sample, an absolute value of a difference between data of adjacent samples is obtained, and information is detected with a sample feature amount obtained by summing the absolute values as a reference value or more. The use method of the memory provided with the information narrowing-down detection function according to claim 15. The positional relationship of addresses according to claim 3 is: (1) positional relationship on the address array stored as the one-dimensional information (2) positional relationship on the address array stored as the two-dimensional information (3) Positional relationship on the address array stored as three-dimensional information (4) Positional relationship on the address array stored as the multidimensional information More than (1) to (4), 16. The method of using a memory having an information refinement detection function according to claim 15, wherein pattern recognition is performed using the positional relationship of addresses. 16. The method of using a memory having an information refinement detection function according to claim 15, wherein the first comparison sample serving as the primary breakthrough address is a plurality of types of samples, or detection is performed with a certain range. . A method of using a memory having an information narrowing detection function, wherein a CPU capable of accessing and reading and writing data is used in combination with a memory having the information narrowing detection function. A method of using a memory having an information narrowing detection function, wherein knowledge processing is performed by storing knowledge information in a memory having the information narrowing detection function. An apparatus using a memory having the information narrowing-down detection function. Artificial intelligence using a memory having the information narrowing detection function.

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