JP2012247747A - Data processing apparatus and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing apparatus and method capable of reducing the power consumption.SOLUTION: On the basis of information on the processing time required for processing preliminarily provided data and processing time limit information showing the time limit for termination of processing on a plurality of pieces of data as processing objects supplied from the outside, processing start timings of the plurality of pieces of data are controlled respectively so that a processor continuously executes processing on the plurality of pieces of data while satisfying the time limit for termination of processing. Alternatively, the number of pieces of data stored in a storage buffer is counted, and in response to detecting that a preliminarily set prescribed number of pieces of data have been stored in the storage buffer, the processor is caused to continuously execute processing on the prescribed number of pieces of data stored in the storage buffer.

Description

  The present invention relates to a data processing apparatus and method for executing predetermined processing on data using a processor.

  In recent years, digitalization of recording media and transmission systems has progressed, and electronic devices that reproduce images and sounds synchronously based on image signals and audio signals recorded or transmitted with time information added are increasing. In general, in such an electronic device, in order to ensure real-time processing necessary for recording or reproduction, an image signal and an audio signal are divided into predetermined sections (frames), and image data and audio in units of the frames. Encoding and decoding processing necessary for recording and reproduction is executed on the data.

  For example, when image data or audio data is encoded or decoded by a DSP (Digital Signal Processor), the DSP performs subsequent input of image data and audio data according to an instruction from a CPU (Central Processing Unit) or the like. While the image data and audio data of the next frame are input, encoding or decoding is sequentially performed. Note that image data and audio data for each frame are input to the DSP at independent timings.

  Meanwhile, in portable electronic devices such as mobile phones, portable game machines, notebook and tablet personal computers, it is important to reduce power consumption of the entire device. When the battery capacity of the storage battery to be mounted increases due to the large power consumption, the storage battery becomes large and the weight increases, and the portability of the electronic device is reduced. On the other hand, if the battery capacity is reduced in order to avoid an increase in the size of the storage battery, inconvenience such as frequent charging of the storage battery occurs.

  An electronic device including a processor such as a DSP consumes a large amount of power when the processor executes a required process. Therefore, in order to reduce the power consumption of the entire electronic device, the consumption of the processor included in the electronic device It is also necessary to reduce power.

  As a method for reducing the power consumption of a processor, for example, a method of stopping power supply to the processor when the processor is not executing processing is known. That is, in order to reduce the power consumption of the processor, a method of frequently turning on / off the power supply of the processor according to the operation state is effective.

  However, the processor normally consumes a lot of power in transition with the required state transition when the power is turned on, so if the power is turned on and off frequently, the chance of turning the power from OFF to ON increases. Power increases.

  For example, in an electronic device that decodes image data and audio data described above with a DSP, if the DSP is turned on / off in response to decoding / stopping of image data and decoding / stopping of audio data, power is supplied for each frame. The power consumption of the DSP may increase as compared to the case where the power ON / OFF is not controlled.

  Note that reducing power consumption of the entire device by stopping power supply to a circuit or electronic device (including a processor) that is not operating is also described in Patent Document 1, for example.

Japanese Patent Laid-Open No. 05-233088

  As described above, in an electronic device including a processor, the power consumption of the processor can be reduced by frequently turning on / off the power according to the operating state of the processor. On the other hand, if the power of the processor is frequently turned on / off, the power consumption may increase compared to the case where the power on / off is not controlled.

  The present invention has been made to solve the problems of the background art as described above, and provides a data processing apparatus and method capable of reducing power consumption while turning on / off a power supply of a processor according to an operating state. The purpose is to provide.

In order to achieve the above object, a data processing apparatus of the present invention includes a processor that executes predetermined processing on a plurality of data input at predetermined intervals;
A control unit that causes the processor to continuously execute the processing on the plurality of data to be processed;
Have

On the other hand, the data processing method of the present invention is a data processing method for executing predetermined processing on a plurality of data input at predetermined intervals using a processor,
Computer
In this method, the processor continuously executes the processing for a plurality of data to be processed.

  According to the present invention, the power consumption of the data processing apparatus can be reduced while turning on / off the power supply of the processor according to the operation state.

It is a block diagram which shows the example of 1 structure of the data processor of 1st Embodiment. It is a block diagram which shows the example of 1 structure of the data processor of 1st Embodiment. It is a flowchart which shows the process sequence of the data processor shown in FIG. It is a figure which shows operation | movement of a data processor, The figure (a) is a timing chart which shows an example of operation | movement of background art, The figure (b) is a timing chart which shows an example of operation | movement of the data processor shown in FIG. It is. It is a figure which shows operation | movement of a data processor, The figure (a) is a timing chart which shows the other example of operation | movement of background art, The figure (b) is another example of operation | movement of the data processor shown in FIG. It is a timing chart which shows. It is a block diagram which shows the example of 1 structure of the data processor of 2nd Embodiment. It is a flowchart which shows the process sequence of the data processor shown in FIG.

  Next, the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of the data processing apparatus of the present invention.

As shown in FIG. 1, the data processing apparatus of the present invention performs the above-described processing for a plurality of data to be processed, and a processor 1 that executes predetermined processing on a plurality of data input at predetermined intervals. And a control unit 2 that causes the processor 1 to execute continuously.
(First embodiment)
FIG. 2 is a block diagram illustrating a configuration example of the data processing apparatus according to the first embodiment.

  As shown in FIG. 2, the data processing apparatus according to the first embodiment includes a start timing adjustment unit 302, an image processing start instruction unit 112, an audio processing start instruction unit 212, and a DSP 400. The DSP 400 includes an image decoding unit 102 that decodes encoded image data, and an audio decoding unit 202 that decodes encoded audio data. In the data processing apparatus according to the first embodiment, the processor 1 shown in FIG. 1 is realized by a DSP 400 shown in FIG. 2, for example.

  The image decoding unit 102 decodes image data input from the outside via the image data input terminal 101, and outputs the decoded image data from the image output terminal 103. The audio decoding unit 202 decodes audio data input from the outside via the audio data input terminal 201, and outputs the decoded audio data from the audio output terminal 203. The DSP 400 realizes the functions of the image decoding unit 102 and the audio decoding unit 202 by executing processing according to a program provided in advance. In the present embodiment, it is assumed that the DSP 400 sequentially performs decoding processing without decoding image data and audio data in parallel.

  The start timing adjustment unit 302 includes an image processing start signal input from the outside via the image start signal input terminal 111, a sound processing start signal input from the outside via the sound start signal input terminal 211, and a processing time limit information input terminal. Based on the processing time limit information input from the outside via 301, the decoding start timings of the image data and the audio data are respectively determined. The start timing adjustment unit 302 also determines an image decoding start instruction signal for instructing start of decoding of image data and an audio decoding start instruction signal for instructing start of decoding of audio data in accordance with the determined decoding start timing of image data and audio data. Is output.

  The image processing start signal and the audio processing start signal are generated by, for example, an external CPU and are input to the start timing adjustment unit 302. The image processing start signal is input to the start timing adjustment unit 302 when the image data to be decoded is supplied to the image decoding unit 102 and the image decoding unit 102 can decode the image data. Similarly, the audio processing start signal is input to the start timing adjusting unit 302 when the audio data to be decoded is supplied to the audio decoding unit 202 and the audio decoding unit 202 can decode the audio data.

  The processing time limit information is information indicating the end time limit of the decoding process of the image data and the sound data, and is generated by, for example, an external CPU or the like and input to the start timing adjustment unit 302. The processing time limit information is updated for each frame. For example, when the reference time is set to 0 ms and the section length of one frame is set to 60 ms, the decoding process for the image data and audio data from time 0 to 60 ms must be completed after another 60 ms, that is, by time 120 ms. Therefore, for example, a time of 120 ms is set in the processing time limit information corresponding to the image data and the audio data at the time of 0 to 60 ms. Similarly, the processing time limit information corresponding to the image data and the audio data at the time 60 to 120 ms is set to the time 180 ms, and the processing time limit information corresponding to the image data and the sound data at the time 120 to 180 ms is set to the time 240 ms.

  When receiving the image decoding start instruction signal from the start timing adjustment unit 302, the image processing start instruction unit 112 activates the image decoding unit 102 included in the DSP 400 and causes the image decoding unit 102 to execute decoding of image data.

  When receiving the audio processing start instruction signal from the start timing adjustment unit 302, the audio processing start instruction unit 212 activates the audio decoding unit 202 included in the DSP 400 and causes the audio decoding unit 202 to perform decoding of audio data.

  In the data processing apparatus according to the first embodiment, the control unit 2 illustrated in FIG. 1 can be realized by the start timing adjustment unit 302, the image processing start instruction unit 112, and the audio processing start instruction unit 212 illustrated in FIG. The start timing adjusting unit 302, the image processing start instructing unit 112, and the audio processing start instructing unit 212 shown in FIG. 2 are, for example, an information processing apparatus including a well-known logic circuit, memory, CPU that executes a required process according to a program, and the like. (Computer). In this case, the memory provided in the control unit 2 stores various control programs executed by the CPU and various data used in the processing. The CPU implements the function as the control unit 2 of the present embodiment by executing processing (software processing) according to the control program stored in the memory.

  2 is controlled by a CPU (not shown) or the like included in an electronic device or the like including the data processing apparatus of the present invention. The DSP power supply is turned on / off by, for example, an instruction from the image processing start instruction unit 112 or the sound processing start instruction unit 212 to a power supply unit (not shown) or a DSP that supplies power to the DSP 400. A specific method for turning on / off the DSP power source may be selected in accordance with the device specification of the DSP 400.

  FIG. 3 is a flowchart showing a processing procedure of the data processing apparatus shown in FIG.

  As shown in FIG. 3, when an image processing start signal, an audio processing start signal, and processing time limit information are input to the start timing adjustment unit 302 (step A1), image data and audio data are based on these signals and information. The start timing of the decoding process is determined (step A2).

  Subsequently, the start timing adjustment unit 302 outputs an image decoding start instruction signal indicating the determined decoding processing start timing to the image processing start instruction unit 112, and outputs an audio decoding start instruction signal to the audio processing start instruction unit 212. (Step A3).

  When the image processing start instruction unit 112 receives the image decoding start instruction signal, the image processing start instruction unit 112 activates the image decoding unit 102 of the DSP 400 and causes the image decoding unit 102 to execute the decoding process of the input image data. In addition, when receiving the audio decoding start instruction signal, the audio processing start instruction unit 212 activates the audio decoding unit 202 of the DSP 400 and causes the audio decoding unit 202 to decode the input audio data (step A4).

  The image decoding unit 102 outputs the decoded image data from the image output terminal 103, and the audio decoding unit 202 outputs the decoded audio data from the audio output terminal 203 (step A5).

  Next, a method for determining the decoding start timing of image data and audio data by the start timing adjustment unit 302 shown in FIG. 2 will be specifically described using FIG. 4 and FIG. 5 in comparison with the background art.

  4A and 4B are diagrams showing the operation of the data processing apparatus. FIG. 4A is a timing chart showing an example of the operation of the background art, and FIG. 4B is an example of the operation of the data processing apparatus shown in FIG. It is a timing chart which shows.

  FIG. 5 is a diagram showing the operation of the data processing device, where FIG. 5A is a timing chart showing another example of the operation of the background art, and FIG. 5B is the data processing device shown in FIG. 12 is a timing chart showing another example of the operation.

  FIG. 4 shows an operation example of the first case in which an image processing start signal is input to the start timing adjustment unit 302 at a time of 200 ms and an audio processing start signal is input at a time of 185 ms, and FIG. 5 illustrates the start timing adjustment unit. An operation example of the second case is shown in which an image processing start signal is input to 302 at time 205 ms and an audio processing start signal is input at time 185 ms.

  In the following description, the time required for the image decoding unit 102 to decode one frame of image data is 30 ms, and the time required for the audio decoding unit 202 to decode one frame of audio data is 10 ms. And It is assumed that the processing time required for decoding audio data and image data is registered in advance in the start timing processing unit 302 for a certain time or maximum time determined according to the performance of the DSP 400.

  4 and 5 show an example of the operation of the data processing apparatus when image data and audio data input at a time of 120 ms to 180 ms are decoded at a time of 180 ms to 240 ms, respectively. In this case, it is assumed that information indicating the time 240 ms is input to the start timing adjustment unit 302 as the processing time limit information corresponding to the image data and the audio data input at the time 120 ms to 180 ms.

  First, the operation of the first case in which an image processing start signal is input to the start timing adjustment unit 302 at a time of 200 ms and an audio processing start signal is input at a time of 185 ms will be described with reference to FIG.

  In the case of the first case, since the data processing apparatus of the background art does not adjust the decoding start timing of the image data and the audio data, when the audio processing start signal is input at time 185 ms as shown in FIG. Audio data is decoded at 185 to 195 ms, and when an image processing start signal is input at time 200 ms, the image data is decoded at time 200 to 230 ms. Here, when control is performed to turn off the DSP power when the DSP 400 is not executing processing, ON / OFF of the DSP power is controlled as shown in FIG.

  Specifically, the DSP power supply is OFF until time 185 ms, and is turned ON to start the audio data decoding process at time 185 ms. Subsequently, when the time 195 ms is reached, the decoding of the audio data is finished and turned off, and when the time 200 ms is reached, the image data is turned on again to start the decoding process of the image data. Then, when the time reaches 230 ms, the decoding of the image data ends and is turned OFF. That is, the DSP power supply is turned on twice and turned off twice during a period of 180 to 240 ms.

  On the other hand, in the data processing apparatus according to the present embodiment, the start timing adjusting unit 302 adjusts the decoding start timing of the image data and the audio data.

  When the start timing adjustment unit 302 receives either the image processing start signal or the audio processing start signal, the start timing adjustment unit 302 determines whether the other processing start signal is also received, and does not receive the other processing start signal. In this case, the decoding start instruction signal for the image data and the audio data is output after receiving the processing start signal. That is, the start timing adjustment unit 302 adjusts the processing start timing of each data so that a plurality of data (here, image data and audio data) can be processed continuously.

  Specifically, as illustrated in FIG. 4B, when the start timing adjustment unit 302 receives the audio processing start signal at time 185 ms, the start timing adjustment unit 302 has not received the image processing start signal yet. Do not start decryption. That is, a speech decoding start instruction signal is not output to the speech processing start instruction unit 212. Therefore, the audio data decoding process is not started, and the DSP power supply remains off.

  In the case of the first case, the start timing adjustment unit 302 receives the image processing start signal at a time of 200 ms. At this time, the DSP 400 starts the decoding process of the audio data and the image data. That is, an audio decoding start instruction signal is output to the audio processing start instruction unit 212, and an image decoding start instruction signal is output to the image processing start instruction unit 112. In this case, the decoding process of the audio data and the image data is started from the time 200 ms, and each decoding process is completed after 30 ms + 10 ms = 40 ms from the time 200 ms, that is, at the time 240 ms, so that the processing time limit information is not violated. Further, the DSP power source is switched from OFF to ON at a time of 200 ms, and switched from ON to OFF at a time of 240 ms.

  Therefore, in the first case, when the DSP power ON / OFF control according to the present embodiment is employed, the DSP power is only turned ON / OFF once every 60 ms from 180 to 240 ms. Therefore, an increase in power consumption due to an increase in the number of on / off times of the DSP power supply is suppressed.

  Next, the operation of the second case in which an image processing start signal is input to the start timing adjustment unit 302 at time 205 ms and an audio processing start signal is input at time 185 ms will be described with reference to FIG.

  In the case of the second case, since the data processing apparatus of the background art does not adjust the decoding start timing of the image data and the audio data, when the audio processing start signal is input at time 185 ms as shown in FIG. Audio data is decoded at 185 to 195 ms, and when an image processing start signal is input at time 205 ms, the image data is decoded at time 205 to 235 ms. Here, when control is performed to turn off the DSP power when the DSP 400 is not executing processing, ON / OFF of the DSP power is controlled as shown in FIG.

  Specifically, the DSP power supply is OFF until time 185 ms, and is turned ON to start the audio data decoding process at time 185 ms. Subsequently, when the time 195 ms is reached, the decoding of the audio data is completed and turned off, and when the time 205 ms is reached, the image data is turned on again to start the decoding process of the image data. At time 235 ms, the decoding of the image data is completed and turned off. That is, the DSP power supply is turned on twice and turned off twice during a period of 180 to 240 ms.

  On the other hand, in the data processing apparatus of the present embodiment, as in the first case, the start timing adjustment unit 302 does not receive an image processing start signal even when an audio processing start signal is input at time 185 ms. Do not start decrypting data. That is, a speech decoding start instruction signal is not output to the speech processing start instruction unit 212. Therefore, the audio data decoding process is not started, and the DSP power supply remains off.

  Here, as described above, the time required for decoding the image data and the sound data is 40 ms, and the processing time limit information corresponding to the image data and the sound data input at the time 120 to 180 ms is the time 240 ms. When the decoding of the audio data and the image data is started at the time 205 ms when the start signal is received, the respective decoding ends at 30 ms + 10 ms = 40 ms after the time 205 ms, that is, at the time 245 ms. Accordingly, the decoding of the image data and the audio data is not completed by the time 240 ms which is the process end time specified by the process time limit information.

  Therefore, the start timing adjustment unit 302 determines the decoding start timing so that the decoding process of the image data and the audio data is completed by the end time of the processing based on the processing time limit information.

  Specifically, as shown in FIG. 5B, the processing time necessary for decoding the image data and the audio data from the time 240 ms of the processing time limit information, that is, the time of 200 ms before the processing end time 40 ms. Even if the image processing start signal is not received, decoding of the audio data is started. By controlling in this way, the decoding of the image data and the audio data is finished by the time of 240 ms, which is the process deadline.

  In the second case, as in the first case, the DSP power supply can be turned on and off only once in the period of 180 to 240 ms. Therefore, an increase in power consumption due to an increase in the number of times the DSP power supply is turned on and off is suppressed. Is done. Further, since the decoding of the image data and the audio data can be completed by the end date of the processing specified by the processing time limit information, the real time property of the processing is not impaired.

According to the present embodiment, by adjusting the processing start timing of each data so that the DSP 400 processes a plurality of data continuously, the processor power is turned off during the period when the processing is not performed, and the ON / OFF is performed. Since the number of times can be suppressed, the power consumption of the data processing apparatus can be reduced.
(Second Embodiment)
FIG. 6 is a block diagram illustrating a configuration example of the data processing apparatus according to the second embodiment.

  As shown in FIG. 6, the data processing apparatus according to the second embodiment includes a counter unit 303, a start timing instruction unit 304, an image data storage buffer 104, a switch 105, an audio data storage buffer 204, a switch 205, and image processing start. It has an instruction unit 112, an audio processing start instruction unit 212, and a DSP 400. The DSP 400 includes an image decoding unit 102 that decodes encoded image data, and an audio decoding unit 202 that decodes encoded audio data.

  As in the first embodiment, the image decoding unit 102 decodes image data input from the outside via the image data input terminal 101 and outputs the decoded image data from the image output terminal 103. The audio decoding unit 202 decodes audio data input from the outside via the audio data input terminal 201, and outputs the decoded audio data from the audio output terminal 203. The DSP 400 realizes the functions of the image decoding unit 102 and the audio decoding unit 202 by executing processing according to a program provided in advance. In the present embodiment, it is assumed that the DSP 400 sequentially performs decoding processing without decoding image data and audio data in parallel. In the data processing apparatus according to the second embodiment, the processor 1 shown in FIG. 1 is realized by a DSP 400 shown in FIG. 6, for example.

  The image data storage buffer 104 stores a predetermined number of image data input from the outside via the image data input terminal 101.

  The audio data accumulation buffer 204 accumulates a predetermined number of audio data input from the outside via the audio data input terminal 201.

  The counter unit 303 counts the number of input image processing start signals and audio processing start signals, and outputs a count end signal indicating the end of counting to the start timing instruction unit 304 when the count value reaches a predetermined value. To do. For example, when the predetermined value is set to “5”, the counter unit 303 counts the number of input of the image processing start signal and the sound processing start signal, respectively, and the number of inputs of the image processing start signal and the sound processing start signal is When each becomes “5”, that is, when 5 frames of image data are accumulated in the image data accumulation buffer 104 and 5 frames of audio data are accumulated in the audio data accumulation buffer 204, the start timing instruction unit 304 counts them. Output an end signal.

  When receiving the count end signal from the counter unit 303, the start timing instruction unit 304 outputs an image decoding start instruction signal to the image processing start instruction unit 112 and outputs an audio decoding start instruction signal to the audio processing start instruction unit 212.

  When receiving the image decoding start instruction signal, the image processing start instruction unit 112 turns on the switch 105 and activates the image decoding unit 102 of the DSP 400, and the image decoding unit 102 stores the image stored in the image data storage buffer 104. Decrypt data.

  When the audio processing start instruction unit 212 receives the audio decoding start instruction signal, the audio processing start instruction unit 212 turns on the switch 205 and activates the audio decoding unit 202 of the DSP 400, and the audio decoding unit 202 stores the audio stored in the audio data storage buffer 204. Decrypt data.

  In the data processing apparatus according to the second embodiment, the control unit 4 illustrated in FIG. 1 includes the image data storage buffer 104, the audio data storage buffer 204, the counter unit 303, the start timing instruction unit 304, and the switch 105 illustrated in FIG. , The switch 205, the image processing start instruction unit 112, and the sound processing start instruction unit 212.

  An image data storage buffer 104, an audio data storage buffer 204, a counter unit 303, a start timing instruction unit 304, a switch 105, a switch 205, an image processing start instruction unit 112, and an audio processing start instruction unit 212 illustrated in FIG. It can be realized by an information processing apparatus (computer) including a CPU or the like that executes a required process according to a logic circuit, a memory, and a program. In that case, the memory included in the control unit 4 stores various control programs executed by the CPU and various data used in the processing. The CPU implements the function as the control unit 4 of the present embodiment by executing processing (software processing) according to the control program stored in the memory.

  6 is controlled by a CPU (not shown) included in an electronic device or the like including the data processing apparatus of the present invention, as in the first embodiment. . The DSP power supply is turned on / off by, for example, an instruction from the image processing start instruction unit 112 or the sound processing start instruction unit 212 to a power supply unit (not shown) or a DSP that supplies power to the DSP 400. A specific method for turning on / off the DSP power source may be selected in accordance with the device specification of the DSP 400.

  FIG. 7 is a flowchart showing a processing procedure of the data processing apparatus shown in FIG.

  As shown in FIG. 7, when the image processing start signal and the audio processing start signal are received, the start timing adjustment unit 302 counts the number of inputs (step B1), and inputs the image processing start signal and the audio processing start signal. When the numbers reach predetermined values, a count end signal is output to the start timing instruction unit 304 (step B2).

  When receiving the count end signal, the start timing instruction unit 304 outputs an image decoding start instruction signal to the image processing start instruction unit 112, and outputs an audio decoding start instruction signal to the audio processing start instruction unit 212 (step B3).

  When receiving the image decoding start instruction signal, the image processing start instruction unit 112 turns on the switch 105 and activates the image decoding unit 102 of the DSP 400, and the image decoding unit 102 stores the image stored in the image data storage buffer 104. Decrypt data.

  When the audio processing start instruction unit 212 receives the audio decoding start instruction signal, the audio processing start instruction unit 212 turns on the switch 205 and activates the audio decoding unit 202 of the DSP 400, and the audio decoding unit 202 stores the audio stored in the audio data storage buffer 204. Data decryption is executed (step B4).

  The image decoding unit 102 outputs the decoded image data from the image output terminal 103, and the audio decoding unit 202 outputs the decoded audio data from the audio output terminal 203 (step B5).

  In the data processing apparatus according to the present embodiment, for example, when “5” is set as the predetermined value in the counter unit 303 in advance, when the count end signal is output from the counter unit 303, 5 frames are stored in the image data storage buffer 104. Image data for 5 frames is stored, and the audio data storage buffer 204 stores 5 frames of audio data. Therefore, the image decoding unit 102 and the audio decoding unit 202 can continuously process the accumulated data for five frames.

  For example, when data of time 0 to 60 ms, data of time 60 to 120 ms, data of time 120 to 180 ms, data of time 180 to 240 ms, and data of time 240 to 300 ms are accumulated, the decoding process of these data is performed. Start from time 300ms.

  Here, as in the first embodiment, the time required for the image decoding unit 102 to decode one frame of image data is 30 ms, and the audio decoding unit 202 decodes one frame of audio data. If the time required for this is 10 ms, the time required for the process is (30 + 10) × 5 = 200 ms, and the decoding process started from time 300 ms ends at time 500 ms. Therefore, the DSP power supply may be turned on at time 300 ms and turned off at time 500 ms.

  In the data processing apparatus according to the first embodiment, the DSP power supply is turned on and off once for each frame. Therefore, the DSP power supply is turned on and off five times each from 300 to 600 ms. The

  On the other hand, in the data processing apparatus of the second embodiment, the DSP power supply is only turned on / off once every 300 ms, and the DSP power supply is turned on / off further than in the first embodiment. The number of times is suppressed, and the power consumption of the data processing apparatus can be reduced.

  In the data processing apparatus according to the second embodiment, the start timing of the first decoding process is delayed by a predetermined section (frame) length that is a predetermined value × processing unit preset in the counter unit 303. The image data and audio data for each frame are sequentially decoded without interruption. Therefore, the real time property of the process is not impaired.

  Therefore, according to the second embodiment, it is possible to reduce power consumption as compared with the data processing device of the first embodiment while ensuring real-time processing of images, sounds, and the like.

  In the second embodiment, an example in which image data and audio data correspond one-to-one is shown. However, in the data processing apparatus, image data and audio data are separated by different periods (sampling rate). ). In that case, the number of input image processing start signals from which the counter unit 303 outputs a count end signal may be different from the number of input audio processing start signals.

  In the first embodiment and the second embodiment described above, the configuration example of the data processing apparatus that decodes the image data and the sound data using the DSP 400 has been shown. However, the present invention is directed to the image data and the sound data. The present invention can also be applied to a configuration that encodes.

  Further, in the first embodiment and the second embodiment described above, an example in which the DSP power supply is turned on / off in accordance with the operation state of the DSP 400 has been shown. However, for example, the DSP 400 has a low power consumption mode. In this case, the DSP operation mode (low power consumption mode / normal operation mode) may be switched in place of the DSP power ON / OFF.

  When the DSP is in the low power consumption mode, the DSP consumes a little more power than turning off the DSP power supply. However, in general, the time until the DSP starts processing is shorter when the DSP is shifted from the low power consumption mode to the normal operation mode than when the DSP power source is turned on. Therefore, the processing time by the DSP can be shortened compared to turning on / off the DSP power supply. Furthermore, depending on the frequency of the DSP power supply ON / OFF, switching the DSP operation mode may reduce the total power consumption of the DSP.

DESCRIPTION OF SYMBOLS 1 Processor 2, 4 Control part 3 Accumulation buffer 101 Image data input terminal 102 Image decoding part 103 Image output terminal 104 Image data accumulation buffer 105, 205 Switch 111 Image start signal input terminal 112 Image processing start instruction part 201 Audio | voice data input terminal 202 Audio decoding unit 203 Audio output terminal 204 Audio data storage buffer 211 Audio start signal input terminal 212 Audio processing start instruction unit 301 Processing time limit information input terminal 302 Start timing adjustment unit 303 Counter unit 304 Start timing instruction unit 400 DSP

Claims (9)

A processor that executes a predetermined process on a plurality of data input at predetermined intervals;
A control unit that causes the processor to continuously execute the processing on the plurality of data to be processed;
A data processing apparatus. The controller is
Based on information on processing time required for the processing on the data, which is prepared in advance, and processing time limit information indicating an end time limit of the processing on the plurality of data to be processed, supplied from the outside, the processor performs the processing The data processing apparatus according to claim 1, wherein the start timing of the processing for the plurality of data is controlled so as to continuously execute the processing for the plurality of data while satisfying the end deadline. The controller is
A storage buffer for storing the data;
When the number of data stored in the storage buffer is counted and it is detected that a predetermined number of data stored in the storage buffer is stored, the processing for the predetermined number of data stored in the storage buffer is performed. The data processing apparatus according to claim 1, wherein the processor is continuously executed. The processor is
The required power is supplied when the processing is being performed on the data, and the power supply is stopped when the processing is not being performed on the data. The data processing apparatus described. A data processing method for executing a predetermined process on a plurality of data input at predetermined intervals using a processor,
Computer
A data processing method for causing the processor to continuously execute the processing on a plurality of data to be processed. The computer is
Based on information on processing time required for the processing on the data, which is prepared in advance, and processing time limit information indicating an end time limit of the processing on the plurality of data to be processed, supplied from the outside, the processor performs the processing 6. The data processing method according to claim 5, wherein start timings of the processes for the plurality of data are respectively controlled so as to continuously execute the processes for the plurality of data while satisfying an end deadline. The computer is
The number of data accumulated in the accumulation buffer for accumulating the data is counted, and when it is detected that a predetermined number of data set in advance is accumulated in the accumulation buffer, the predetermined number of data accumulated in the accumulation buffer The data processing method according to claim 5, wherein the processing is continuously executed by the processor.   When the processor is executing the processing on the data, it supplies the processor with the required power, and when the processor is not executing the processing on the data, the power is supplied to the processor. The data processing method of any one of Claim 5 to 7 which stops. A program for causing a computer to execute data processing for executing predetermined processing on a plurality of data input at predetermined intervals using a processor,
A program for causing the processor to continuously execute the processing on a plurality of data to be processed.

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