JP2012244088A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an FET composed of a nano-wire serving as a channel and a gate electrode formed around the nano-wire to be manufactured easily with high accuracy.SOLUTION: In a gate electrode formation region of a substrate 121 having a sheathed nano-wire 103 disposed thereon, an upper gate electrode 124 overlying with a lower gate electrode 122 is formed across the sheathed nano-wire 103. Formation of the upper gate electrode 124 may be carried out by using known lithography technology and lift-off. For example, this can be achieved by forming, on the substrate 121 with the sheathed nano-wire 103 disposed thereon across the lower gate electrode 122, a resist pattern having an opening in an electrode formation part by an electron beam exposure and then depositing an electrode material on top of that. Then, by removing the resist pattern formed earlier, it is possible to form the upper gate electrode 124.

Description

  The present invention relates to a field effect transistor using a semiconductor nanowire and a manufacturing method thereof.

  A field effect transistor (FET) using a high-quality semiconductor nanowire obtained as a bottom-up by crystal growth as a one-dimensional conduction channel is considered promising as a next-generation device. In the case of a lateral FET in which the substrate and the nanowire are parallel, an FET having the entire conductive substrate covered with the insulating film as the gate electrode and an FET having the gate electrode disposed on the nanowire through the insulating film are manufactured. . However, it is difficult to optimize the gate characteristics because the gate electric field mainly acts from only one side.

  On the other hand, there has been proposed an FET using a gate provided around the nanowire through an insulating film covering the nanowire (see Non-Patent Document 1 and Non-Patent Document 2). This FET is called “wrap-around gate”, “surround gate”, “gate-all-around”, etc., and is a vertical FET device (see Non-Patent Document 1) and a lateral FET device (Non-Patent Document). 2). According to these devices, the short channel effect is suppressed, and characteristics such as S value (subthreshold slope) and ON / OFF ratio can be improved.

T. Tanaka et al., "Vertical Surrounding Gate Transistors Using Single InAs Nanowires Grown on Si Substrates", Applied Physics Express, vol.3, 025003, 2010. L. Zhang et al., "Parallel Core-Shell Metal-Dielectric-Semiconductor Germanium Nanowires for High-Current Surround-Gate Field-Effect Transistors", NANO LETTERS, vol.6, no.12, pp.2785-2789, 2006 . S.A.Dayeh et al., "III-V Nanowire Growth Mechanism: V / III Ratio and Temperature Effects", NANO LETTERS, vol.7, no.8, pp.2486-2490, 2007. S.Dhara et al., "Magnetotransport properties of individual InAs nanowires", PHYSICAL REVIEW B, vol.79, 121311R, 2009. A. Bringer et al., "Spin precession and modulation in ballistic cylindrical nanowires due to the Rashba effect", PHYSICAL REVIEW B, vol.83, 115305, 2011. A. E. Hansen et al., "Spin relaxation in InAs nanowires studied by tunable weak antilocalization", PHYSICAL REVIEW B, vol.71, 205328, 2005.

  However, the above-described FET has a problem that it is not easy to manufacture. First, in a vertical GAA (gate-all-around) FET used in a state in which nanowires are set up as shown in Non-Patent Document 1, first, a gate electrode is formed, and then the entire nanowire is embedded in the entire substrate with an insulating film. Next, by etching, only the upper part of the nanowire is exposed without exposing the gate electrode, and a metal is deposited on the exposed part by vapor deposition or the like to form a drain electrode. As described above, the process for manufacturing the element is complicated.

  In addition, when a plurality of gate electrodes required to form quantum dots in a nanowire are formed on a single nanowire, the above process is repeated a plurality of times while maintaining insulation between the upper and lower gate electrodes. In particular, the wiring is taken out in the horizontal direction. Such a process is not easy.

In the manufacture of the lateral GAAFET shown in Non-Patent Document 2, first, the entire nanowire is covered with an insulating film (Al ₂ O ₃ ) and a single gate electrode (Al), and this is transferred to another substrate. Next, in a state of being transferred to another substrate, a part of the gate electrode is removed by wet etching from the upper surface, and the width (gate length) of the gate electrode is set to a predetermined dimension. In addition, while being transferred to the substrate, wet etching from the top surface is used to remove the portion of Al and Al ₂ O ₃ that will become the source / drain regions, and deposit a metal such as Ti on the portion of the nanowire exposed by the removal. Source / drain electrodes are formed.

  In this method, since the amount of wet etching differs between the upper and lower surfaces of the nanowire as viewed from the substrate, it is impossible to realize a uniform gate length with an error of about 10 nm over the entire circumference of the nanowire, which is necessary for quantum dot formation. It is difficult to accurately form a plurality of gate electrodes having a width of several tens of nanometers.

  The present invention has been made to solve the above-described problems, so that an FET formed by surrounding a nanowire serving as a channel around a gate electrode can be more easily manufactured with high accuracy. The purpose is to do.

  The method of manufacturing a field effect transistor according to the present invention includes a step of forming a semiconductor nanowire, a step of forming an insulating layer covering a side surface of the semiconductor nanowire and forming a coated nanowire covered with the insulating layer, A step of forming a lower gate electrode on the gate electrode formation region; a step of disposing a covering nanowire on the lower gate electrode; and a covering nanowire on the gate electrode formation region of the substrate on which the covering nanowire is disposed. Forming an upper gate electrode that intersects with the lower gate electrode, removing an insulating layer at both ends of the coated nanowire, and removing a source electrode and both ends of the semiconductor nanowire exposed by removing the insulating layer And a step of connecting and forming the drain electrode.

  In the field effect transistor manufacturing method, the upper gate electrode may be formed so as to cover the side peripheral surface of the coated nanowire on the region intersecting the lower gate electrode. In addition, a plurality of gate electrode formation regions extending in the same direction are provided, a lower gate electrode is formed in each of the plurality of gate electrode formation regions, and a covered nanowire is disposed so as to cross the plurality of lower gate electrodes. A plurality of upper gate electrodes that intersect with each of the plurality of lower gate electrodes may be formed.

  Further, the field effect transistor according to the present invention is disposed so as to intersect the lower gate electrode formed on the gate electrode formation region on the substrate and the lower gate electrode, and at the intersection of the lower gate electrode. A semiconductor nanowire whose side surface is covered with an insulating layer, and an upper gate formed on the gate electrode formation region of the substrate on which the semiconductor nanowire is arranged so as to intersect the semiconductor nanowire via the insulating layer and overlap the lower gate electrode And at least a source electrode and a drain electrode connected to both ends of the semiconductor nanowire.

  In the field effect transistor, the upper gate electrode may be formed so as to cover the side peripheral surface of the semiconductor nanowire on the region intersecting with the lower gate electrode through an insulating layer. In addition, a plurality of gate electrode formation regions extending in the same direction, a plurality of lower gate electrodes formed in each of the plurality of gate electrode formation regions and intersecting the coated nanowires, and a plurality of lower portions intersecting the coated nanowires A plurality of upper gate electrodes formed to overlap each of the gate electrodes may be provided.

  As described above, according to the present invention, since the upper gate electrode is formed so as to intersect the covered nanowire and overlap the lower gate electrode, the gate electrode is formed around the nanowire serving as the channel. An excellent effect is obtained that the FET can be more easily manufactured with high accuracy.

FIG. 1A is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor according to an embodiment of the present invention. FIG. 1B is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor in the embodiment of the present invention. FIG. 1C is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor in the embodiment of the present invention. FIG. 1D is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor in the embodiment of the present invention. FIG. 1E is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor in the embodiment of the present invention. FIG. 1F is a configuration diagram showing a state in each step for explaining a method of manufacturing the field effect transistor in the embodiment of the present invention. FIG. 1G is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor in the embodiment of the present invention. FIG. 1H is a configuration diagram showing a state in each step for explaining a method of manufacturing a field effect transistor in the embodiment of the present invention. FIG. 2 is a photograph showing the results of observation of the field effect transistor according to the embodiment of the present invention with a scanning electron microscope. FIG. 3 is a perspective view showing the configuration of another field effect transistor according to the embodiment of the present invention. FIG. 4 is a photograph showing a result of observing another field effect transistor in the embodiment of the present invention with a scanning electron microscope. FIG. 5 is a perspective view showing the state of the band gap energy of the quantum well structure. FIG. 6 is a configuration diagram showing the configuration of a “diffusive” system in which a plurality of impurities 601 as scatterers exist and are subjected to many scatterings during conduction, while the phase coherence is maintained. FIG. 7 is a characteristic diagram showing characteristics of an FET using a semiconductor nanowire made of InAs. FIG. 8 is an explanatory diagram for explaining the operation principle of an FET using a semiconductor nanowire made of InAs. FIG. 9 is a perspective view showing a configuration of an FET using a semiconductor nanowire made of InAs. FIG. 10 shows the relationship (a) between the magnetic field and the source-drain conductance when the gate voltage is changed, and the change in the spin orbit length (vertical axis) with respect to the electric field E _ind induced by the application of the gate voltage (b). FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1H are configuration diagrams showing states in respective steps for explaining a method of manufacturing a field effect transistor according to an embodiment of the present invention. 1A, 1C, 1D, 1E, 1G, and 1H are perspective views, and FIGS. 1B and 1F are partial cross-sectional views.

First, as shown in FIG. 1A, a semiconductor nanowire 101 is formed. For example, a metal fine particle catalyst (not shown) such as Au having a diameter of several tens of nanometers is placed on a growth substrate 151 made of InAs, and trimethylindium (TMIn) and arsine (AsH ₃ ) are supplied to the VLS. By using the (Vapor-liquid-solid) method or the like, the semiconductor nanowire 101 made of InAs can be formed (see Non-Patent Document 3). Alternatively, the semiconductor nanowire may be formed using another method such as selective growth using a patterned oxide film without using a metal fine particle catalyst (see Non-Patent Document 1).

Next, as shown in FIG. 1B, an insulating layer 102 that covers the side surface (peripheral surface) of the semiconductor nanowire 101 is formed to form a covered nanowire 103 that is covered with the insulating layer 102. For example, as described above, in a state where the semiconductor nanowire 101 made of InAs is formed on the growth substrate 151, an atomic layer deposition (ALD) method is used, and a high dielectric constant suitable for improving gate characteristics is obtained. An insulating layer 102 such as Al ₂ O ₃ or HfO ₂ may be formed so as to cover the semiconductor nanowire 101.

  As is well known, the ALD method is a film formation method in which a single molecular layer of an organic compound as a raw material is adsorbed on a surface to be formed, and a layer having a uniform thickness is formed on a three-dimensional surface. It is possible to form. According to this ALD method, it is easy to form the insulating layer 102 on all side surfaces of the semiconductor nanowire 101. Note that the insulating layer 102 can be formed so as to cover the side surface of the semiconductor nanowire 101 by using a sputtering method without being limited to the ALD method.

  Next, as shown in FIG. 1C, the lower gate electrode 122 is formed on the gate electrode formation region on the substrate 121. The lower gate electrode 122 may be formed in a strip shape extending in one direction. FIG. 1C shows a state in which a terminal 123 connected to the lower gate electrode 122 is formed simultaneously with the lower gate electrode 122. As the substrate 121, for example, a silicon substrate having a surface formed with an insulating film such as silicon oxide may be used. The substrate 121 does not necessarily have conductivity.

  The lower gate electrode 122 may be formed by a known lithography technique and lift-off. For example, a resist pattern having an opening in the electrode formation portion is formed on the substrate 121 by electron beam exposure, and a Ti layer and an Au layer are deposited on the resist pattern to a thickness of about 10 nm. Thereafter, the lower gate electrode 122 and the terminal 123 can be formed by removing the previously formed resist pattern. Here, an alignment mark (not shown) having a known relative positional relationship with the gate electrode formation region is formed on the substrate 121, and a location designed on the plane of the substrate 121 with the alignment mark as a reference. The resist pattern described above may be formed in the (gate electrode formation region). Thus, the lower gate electrode 122 can be formed in accordance with the gate electrode formation region. This is a method generally used in lithography exposure.

  Next, as shown in FIG. 1D, the covered nanowires 103 are arranged on the lower gate electrode 122 so as to cross each other. For example, the coated nanowire 103 on the growth substrate 151 is transferred to the substrate 121 by pressing the growth substrate 151 on which the coated nanowire 103 is formed against the substrate 121 on which the lower gate electrode 122 is formed. The nanowire 103 may be disposed on the substrate 121. Further, a plurality of coated nanowires 103 are separated from the growth substrate 151, and these are put in a solvent such as alcohol, and a dispersion is prepared by applying ultrasonic waves thereto, and this dispersion is applied to the substrate 121. The coated nanowire 103 may be disposed on the substrate 121 by dropping and evaporating the solvent. Thus, any one of the plurality of coated nanowires 103 arranged on the substrate 121 is arranged so as to cross the lower gate electrode 122. In FIG. 1D, nanowires arranged in other regions on the substrate 121 are not shown in the drawing.

  Next, as shown in FIG. 1E, an upper gate electrode 124 is formed on the gate electrode formation region of the substrate 121 on which the coated nanowire 103 is arranged, and intersects the coated nanowire 103 and overlaps the lower gate electrode 122. In the intersecting region where the covering nanowire 103 intersects with the lower gate electrode 122 and the upper gate electrode 124, the side peripheral surface of the semiconductor nanowire 101 is covered with the insulating layer 102. Therefore, the lower gate electrode 122 and the upper gate electrode 124 intersect the semiconductor nanowire 101 through the insulating layer 102.

  The upper gate electrode 124 may be formed by a known lithography technique and lift-off. For example, a resist pattern having an opening in an electrode forming portion is formed by electron beam exposure on a substrate 121 in which the coated nanowire 103 is arranged to intersect with the lower gate electrode 122, and an electrode material is deposited thereon. . Thereafter, the upper gate electrode 124 can be formed by removing the previously formed resist pattern.

  Also in the formation of the upper gate electrode 124 described above, the resist pattern described above is formed at a location (gate electrode formation region) designed on the plane of the substrate 121 with the alignment mark formed on the substrate 121 as a reference. do it. By doing in this way, the upper gate electrode 124 can be formed according to the lower gate electrode 122 already formed in the gate electrode formation region. In general, alignment using such an alignment mark can be performed with high accuracy with a shift amount of 10 nm or less.

  Here, by depositing the electrode material described above from a plurality of directions, as shown in the cross-sectional view of FIG. 1F, the side peripheral surface of the coated nanowire 103 on the intersecting region with the lower gate electrode 122 is It can be formed so as to be covered with the upper gate electrode 124. Here, “the state in which the upper gate electrode 124 covers the side peripheral surface of the coated nanowire 103 on the intersection region with the lower gate electrode 122” means that the region other than the contact region with the lower gate electrode 122 in the intersection region. The side peripheral surface of the coated nanowire 103 is covered with the upper gate electrode 124. For example, in the vapor deposition of the electrode material, the electrode material may be vapor-deposited obliquely with respect to the plane of the substrate 121 from two directions in the side surface direction of the coated nanowire 103 to the same thickness as the diameter of the coated nanowire 103. Note that the above electrode forming step can be easily performed on a plurality of gate electrodes simultaneously.

Next, as shown in FIG. 1G, the insulating layers 102 at both ends of the coated nanowire 103 are removed, and the semiconductor nanowire 101 is exposed. A resist pattern that covers a region other than the exposed region is formed on the substrate 121, and in this state, the insulating layers 102 at both ends of the coated nanowire 103 may be removed by etching. For example, the insulating layer 102 made of Al ₂ O ₃ can be selectively etched by using an alkaline etching solution. Alternatively, the insulating layer 102 may be removed by dry etching such as argon ion sputtering.

  Next, as shown in FIG. 1H, a source electrode 125 and a drain electrode 126 are connected (ohmic contact) to both ends of the semiconductor nanowire 101 exposed by removing the insulating layer 102. For example, without removing the resist pattern used to remove some of the insulating layers 102 described above, a metal material is deposited on the resist pattern, and then the resist pattern is lifted off. Can be formed.

  Through the above manufacturing process, as shown in FIG. 1H, a lateral FET in which a single gate electrode composed of a lower gate electrode 122 and an upper gate electrode 124 has a GAA structure with respect to the semiconductor nanowire 101 is obtained. FIG. 2 is a photograph showing the result of observing the FET with a scanning electron microscope.

  This FET is disposed so as to intersect the lower gate electrode 122 formed on the gate electrode formation region on the substrate 121 and the lower gate electrode 122, and the side surface of the intersection with the lower gate electrode 122 is insulated. The semiconductor nanowire 101 covered with the layer 102 and the gate electrode formation region of the substrate 121 on which the semiconductor nanowire 101 is arranged are formed so as to intersect the semiconductor nanowire 101 via the insulating layer 102 and overlap the lower gate electrode 122. And the source electrode 125 and the drain electrode 126 connected to both ends of the semiconductor nanowire 101, respectively. In the present embodiment, the upper gate electrode 124 is formed so as to cover the side peripheral surface of the semiconductor nanowire 101 on the region intersecting with the lower gate electrode 122 with the insulating layer 102 interposed therebetween.

  In this FET, a constant drain voltage is applied between the source and drain electrodes to cause a drain current to flow, and a gate voltage is applied to the gate electrode, thereby enabling an FET operation to modulate the drain current. Since the gate electrode has a GAA structure, the drain current changes steeply with respect to the change of the gate voltage in the vicinity of the pinch-off region where the drain current approaches zero.

  According to the above-described embodiment, since the lower gate electrode 122 and the upper gate electrode 124 are overlapped to form one gate electrode, for example, the upper gate electrode 124 is covered with the coated nanowire 103 on the intersection region with the lower gate electrode 122. It is easy to make the gate electrode have a GAA structure if it is formed so as to cover the peripheral surface of the gate. Further, the lower gate electrode 122 and the upper gate electrode 124 can be easily manufactured with alignment accuracy and dimensional accuracy of several nm by a well-known patterning technique such as a lithography technique. Thus, according to the present embodiment, an FET formed by surrounding a gate electrode around a nanowire can be more easily manufactured with high accuracy.

  Note that the number of gate electrodes is not limited to one, and a set of a plurality of lower gate electrodes and upper gate electrodes may be formed for the coated nanowire, and a plurality of gate electrodes may be provided. For example, as shown in FIG. 3, a lower gate electrode 122a, a lower gate electrode 122b, an upper gate electrode 124a, and an upper gate electrode 124b that intersect with the coated nanowire 103 may be formed.

  By doing so, the gate electrode composed of the lower gate electrode 122 a and the upper gate electrode 124 a and the gate electrode composed of the lower gate electrode 122 b and the upper gate electrode 124 b can be formed so as to intersect the covered nanowire 103. In this case, a quantum dot can be formed in the semiconductor nanowire in the region sandwiched between the two gate electrodes by biasing the two gate electrodes.

  The number of gate electrodes is not limited to two, and five gate electrodes may be provided as shown in FIG. FIG. 4 is a photograph showing a result of observing a FET having a GAA structure in which five gate electrodes intersect with a coated nanowire (semiconductor nanowire) with a scanning electron microscope. In FIG. 4, the pattern width (gate length) of each gate electrode is 40 nm, and the interval between the gate electrodes is 80 nm. By using a plurality of gate electrodes, a multi-functional device using a plurality of quantum dots can be realized.

  As described above, according to the present invention, a lateral nanowire FET having a GAA structure with excellent gate characteristics can be realized. In addition, since there is no upper limit to the number of gate electrodes, a more sophisticated device using quantum dots can be realized.

  Hereinafter, spintronic devices such as FETs using nanowires will be described. In this spintronic device, the conductance between the source and the drain is controlled by modulating the spin-orbit interaction in the solid by the electric field (electric field) of the gate electrode. The spin-orbit interaction in solids is a relativistic effect derived from crystal structure asymmetry (bulk inversion asymmetry) and asymmetry in artificial structures such as quantum wells, and the latter is called the Rashba effect. The spin orbit interaction has a large value in a narrow band gap semiconductor such as InAs.

  The Rashba effect generates an effective magnetic field perpendicular to the direction of motion of the electrons and the electric field, and rotates the spin of the electrons. This magnitude can be modulated from the outside by a gate voltage or the like. For example, in the case of the quantum well structure showing the state of the band gap energy in the perspective view of FIG. 5, the state of the electron spin of the two-dimensional electron gas 505 formed in the well layer 503 sandwiched between the two barrier layers 502 and 504 is shown. , And can be modulated by the gate voltage applied to the gate electrode 501. Therefore, the rush bar effect is expected to be applied to spintronic devices such as spin transistors.

  Here, the spin-orbit interaction appearing as weak antilocalization will be briefly described. As shown in FIG. 6, phase coherence is maintained, but in a “diffusive” system in which a plurality of impurities 601 as scatterers are present and electrons are scattered many times during conduction, A clockwise orbit (dotted line) and a counterclockwise orbit (solid line) having inversion symmetry interfere with each other at the origin. In FIG. 6, thick arrows indicate the state of electron spin. For this reason, in general, the magnetic conductivity takes a minimum value at zero magnetic field (weak localization). However, in a system with strong spin-orbit interaction, the magnetic conductivity has a local maximum value (weak antilocalization).

  When the Rashba effect is modulated by the gate voltage, the Rashba effect shifts between the two, and the weakly delocalized peak becomes stronger. For example, in an FET using a semiconductor nanowire made of InAs, as shown in FIGS. 7A and 7B, the relationship between the conductance (vertical axis) and the magnetic field (horizontal axis) varies depending on the gate voltage. (Refer nonpatent literature 4).

  For example, in InAs, the conduction band is bent downward near the surface, and electrons are accumulated. When the state of the conduction band edge (internal electric field E) is changed by the gate voltage (FIG. 8), the Rashba effect is modulated. The modulation of the rush bar effect described above can be performed more efficiently by adopting the GAA structure. For example, as shown in FIG. 9A, when a flat gate electrode 802 is provided on one side of a semiconductor nanowire 801 made of InAs, the lower surface of the semiconductor nanowire 801 on the gate electrode 802 side and The internal electric field is modulated in the opposite direction with the top surface away. On the other hand, as shown in FIG. 9B, by providing the gate electrode 812 so as to surround the side surface of the semiconductor nanowire 811, the internal charge increases in the entire side surface of the semiconductor nanowire 811, and the efficiency is increased. (See Non-Patent Document 5).

In the field effect transistor according to the present embodiment described with reference to FIG. 1H described above, the relationship between the magnetic field and the source-drain conductance when the gate voltage is changed changes as shown in FIG. To do. Further, as indicated by a circle in FIG. 10B, the spin orbit length (vertical axis) changes with respect to the electric field E _ind induced by application of the gate voltage. The dotted line in (b) of FIG. 10 shows the case of the FET having the form described with reference to (a) of FIG. 9 (see Non-Patent Document 6), whereas in the case of the FET having a GAA structure indicated by a circle, It can be seen that the spin-orbit length becomes shorter and the spin-orbit interaction becomes stronger more rapidly than the induced electric field. As described above, by using the GAA structure, a more efficient rush bar effect can be realized, and application to a spintronic device can be expected.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, the formation of the gate electrode is not limited to the evaporation method, and the electrode material may be deposited by a sputtering method. Further, the lower gate electrode and the upper gate electrode may be made of the same material or different materials. In the above-described embodiment, InAs is used as the semiconductor nanowire. However, the present invention is not limited to this. The above-described modulation by the high-efficiency rush bar effect is caused by the shape of the nanowire and the GAA structure, and the same applies even when other semiconductors are used.

  DESCRIPTION OF SYMBOLS 101 ... Semiconductor nanowire, 102 ... Insulating layer, 103 ... Covering nanowire, 121 ... Substrate, 122 ... Lower gate electrode, 123 ... Terminal, 124 ... Upper gate electrode, 125 ... Source electrode, 126 ... Drain electrode, 151 ... Growth substrate.

Claims (6)

Forming a semiconductor nanowire;
Forming an insulating layer covering a side surface of the semiconductor nanowire to form a coated nanowire covered with the insulating layer;
Forming a lower gate electrode on the gate electrode formation region on the substrate;
Placing the coated nanowires crossing over the lower gate electrode;
Forming an upper gate electrode on the gate electrode formation region of the substrate on which the coated nanowires are disposed, intersecting the coated nanowire and overlapping the lower gate electrode;
Removing the insulating layer at both ends of the coated nanowire;
And a step of connecting and forming a source electrode and a drain electrode at both ends of the semiconductor nanowire exposed by removing the insulating layer. In the manufacturing method of the field effect transistor of Claim 1,
The method of manufacturing a field effect transistor, wherein the upper gate electrode is formed so as to cover a side peripheral surface of the coated nanowire on a region intersecting with the lower gate electrode. In the manufacturing method of the field effect transistor of Claim 1 or 2,
A plurality of the gate electrode formation regions extending in the same direction;
Forming the lower gate electrode in each of the plurality of gate electrode formation regions;
Arranging the coated nanowires across the plurality of lower gate electrodes;
A method of manufacturing a field effect transistor, comprising: forming a plurality of upper gate electrodes that intersect with each of the plurality of lower gate electrodes so as to intersect the coated nanowires. A lower gate electrode formed on the gate electrode formation region on the substrate;
A semiconductor nanowire that is arranged to cross over the lower gate electrode and the side surface of the crossing with the lower gate electrode is covered with an insulating layer;
An upper gate electrode formed on the gate electrode formation region of the substrate on which the semiconductor nanowire is disposed, and intersecting the semiconductor nanowire via the insulating layer and overlapping the lower gate electrode;
A field effect transistor comprising at least a source electrode and a drain electrode respectively connected to both ends of the semiconductor nanowire. The field effect transistor according to claim 4.
The field effect transistor according to claim 1, wherein the upper gate electrode is formed so as to cover a side peripheral surface of the semiconductor nanowire on a region intersecting with the lower gate electrode through the insulating layer. The field effect transistor according to claim 4 or 5,
A plurality of the gate electrode formation regions extending in the same direction;
A plurality of the lower gate electrodes formed in each of the plurality of gate electrode formation regions and intersecting the coated nanowires;
And a plurality of the upper gate electrodes formed to overlap each of the plurality of lower gate electrodes so as to intersect the coated nanowires.