JP2012244083A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of leakage current due to a crystal defect, in a semiconductor device having a plurality of second-conductivity-type regions that are selectively formed in a surface portion of a first-conductivity-type semiconductor layer.SOLUTION: A MOSFET is formed using a silicon carbide substrate 10 in which an n-type silicon carbide drift layer 20 is formed on its primary surface. In a top-surface portion of the silicon carbide drift layer 20, a plurality of p-type first well regions 30 are selectively formed. In the region of the silicon carbide drift layer 20 where a basal plane defect exists, an integral p-type second well region 31 is formed in the top-surface portion of the silicon carbide drift layer 20 so as to overlap the first well regions 30.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for reducing leakage current caused by crystal defects.

  Semiconductor elements using silicon carbide (SiC) are promising as next-generation switching elements that can achieve high breakdown voltage, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. However, many problems to be solved remain in the silicon carbide semiconductor device.

  It is known that silicon carbide has many basal plane defects such as stacking faults, that is, crystal defects formed in the basal plane. For example, basal plane dislocations in the drift layer of a semiconductor device may become a leak path when a reverse bias is applied to a pn junction formed in the drift layer. Therefore, if the semiconductor device has crystal defects, it may be a defective product that cannot cut off current even in the off state, which causes a decrease in yield.

  Therefore, various techniques for improving the yield of the semiconductor device by applying a certain treatment to the region including the crystal defect of the silicon carbide semiconductor device have been proposed (for example, Patent Documents 1 and 2 below).

JP 2002-134760 A JP 2000-003946 A

  Since the basal plane defect is a crystal defect formed two-dimensionally within the basal plane, the direction in which the leakage current due to the basal plane defect flows is along the basal plane. On the other hand, electrons and holes that cause leakage current are accelerated more strongly as the applied electric field is larger. Therefore, if the electric field parallel to the leakage current path can be suppressed, the leakage current becomes smaller. Therefore, in order to reduce the leakage current due to the basal plane defect, it is effective to reduce the electric field strength in the direction along the basal plane.

  In the above Patent Document 1, in the Schottky barrier diode that is a silicon carbide semiconductor device, in order to suppress the influence of the micropipe that is one of crystal defects, selective ion implantation is performed in the vicinity of the micropipe on the substrate surface, The micropipe is inactivated. This method cannot be expected to suppress the electric field in the direction along the basal plane defect.

  Further, the technique of Patent Document 2 detects a crystal defect that causes a leakage current in a silicon carbide semiconductor substrate, and if a desired yield cannot be obtained, does not flow it into a MOS device manufacturing process, or detects a detected crystal By not forming the gate oxide film formation region on the defect, the yield is improved, and the leakage current of the crystal defect is not actively suppressed.

  The present invention has been made to solve the above-described problems, and in a semiconductor device including a plurality of second conductivity type regions selectively formed on a surface portion of a first conductivity type semiconductor layer, The object is to suppress the occurrence of leakage current due to crystal defects.

  The semiconductor device according to the present invention includes a semiconductor substrate, a first conductivity type drift layer formed on a main surface of the semiconductor substrate, and a second selectively formed on the upper surface of the drift layer. A plurality of first well regions of the conductivity type and a region where crystal defects of the drift layer exist are formed integrally with the crystal defects including the crystal defects in plan view without being separated from the upper surface portion of the drift layer. And a second well region of two conductivity types.

  According to the present invention, since the generation of leakage current due to crystal defects such as basal plane defects can be suppressed, it is possible to improve the yield in manufacturing the silicon carbide semiconductor device and reduce the cost.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment. It is a figure which shows typically the cross-sectional structure of a semiconductor device. It is a schematic diagram of the electric field distribution in a semiconductor device. It is a figure which shows the simulation result of the electric potential distribution in a semiconductor device. It is a figure which shows the simulation result showing the relationship between the angle of the basal plane with respect to the surface of a semiconductor substrate, and the electric field strength of a basal plane direction. It is a figure which shows the simulation result showing the relationship between the depth of a 2nd well area | region, and the electric field strength of a basal plane direction. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a process diagram illustrating the method for manufacturing the semiconductor device according to the second embodiment.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a vertical MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) which is a silicon carbide semiconductor device according to the first embodiment. In the following, it is assumed that the first conductivity type is n-type and the second conductivity type is p-type, but conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes an n-type low-resistance silicon carbide semiconductor substrate (silicon carbide substrate) 10 having a 4H polytype and an upper surface (first main surface) thereof. An epitaxial substrate including an n-type silicon carbide drift layer 20 grown epitaxially is used. Silicon carbide substrate 10 has a (0001) plane as the first principal surface and is inclined 4 ° with respect to the c-axis direction.

  A plurality of p-type first well regions 30 are periodically formed on the upper surface portion of silicon carbide drift layer 20 apart from each other (with a predetermined interval). First well region 30 includes aluminum (Al) as a p-type impurity, and is formed shallower than the bottom surface of silicon carbide drift layer 20. An n-type source region 40 is selectively formed on the surface portion in each first well region 30. The source region 40 contains nitrogen (N) as an n-type impurity and is formed shallower than the first well region 30.

  In silicon carbide drift layer 20, a portion of an n-type region (region sandwiched between adjacent first well regions 30) adjacent to first well region 30 is called a JFET (Junction Field Effect Transistor) region. Current path during on-operation.

  On the silicon carbide drift layer 20, a gate electrode 60 extends through a gate insulating film 50 of silicon oxide so as to straddle the source region 40 and the JFET region in the first well region 30. As shown in FIG. 1, the gate insulating film 50 and the gate electrode 60 are formed across the source regions 40 of the adjacent first well regions 30. Therefore, the gate insulating film 50 and the gate electrode 60 also extend over the JFET region.

  In the first well region 30, a region between the source region 40 located below the gate electrode 60 and the JFET region becomes a channel region where an inversion layer (inversion channel) is formed when the MOSFET is turned on.

  An opening exposing the upper surface of the source region 40 is provided in the gate insulating film 50, and a source electrode 70 electrically connected to the source region 40 (and a part of the first well region 30) is formed therein. Is done. A drain electrode 80 is provided on the lower surface (second main surface) of silicon carbide substrate 10.

  Although illustration is omitted, an area where no on-current flows in the outer peripheral portion surrounding a region where the plurality of first well regions 30 are periodically arranged for the purpose of securing a wiring region and improving the breakdown voltage of the element termination portion ( Outer peripheral region) is formed. A region where a plurality of first well regions 30 inside the outer peripheral region are arranged side by side is referred to as an active region.

  In FIG. 1, basal plane defects (including stacking faults) existing in silicon carbide drift layer 20 are shown. As shown in the figure, in the semiconductor device of the present embodiment, the p-type second well region 31 is formed in the entire region including the region where the basal plane defect exists in a plan view on the upper surface portion of the silicon carbide drift layer 20. Overlaid on the first well region 30 and the source region 40. In other words, the p-type second well region 31 includes the basal plane defect in an upper portion of the region where the basal plane defect exists in the silicon carbide drift layer 20 in a plan view, and continuously (integrally) without being separated. )It is formed. The second well region 31 contains aluminum (Al) as a p-type impurity, and is desirably deeper than the first well region 30 as will be described later.

  Here, the operation of the MOSFET of FIG. 1 will be briefly described. When a positive voltage equal to or higher than the threshold voltage is applied to gate electrode 60, an inverted channel is formed in the channel region, and a path through which electrons serving as carriers flow between source region 40 and silicon carbide drift layer 20 (JFET region). Can do. Electrons flowing from the source region 40 to the JFET region reach the drain electrode 80 via the silicon carbide drift layer 20 and the silicon carbide substrate 10 according to an electric field formed by a positive voltage applied to the drain electrode 80.

  That is, the MOSFET can pass a current from the drain electrode 80 to the source electrode 70 when a positive voltage higher than the threshold is applied to the gate electrode 60. This state is the on state, and the current flowing at that time is the on current. However, in the MOSFET of the present embodiment, no on-current flows through the portion where the second well region 31 is formed.

  On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 60, an inversion channel is not formed in the channel region, and no current flows from the drain electrode 80 to the source electrode 70. This state is an off state. At this time, a positive voltage applied to drain electrode 80 acts, and a depletion layer extends from the pn junction between silicon carbide drift layer 20 and first well region 30. In the portion where second well region 31 is formed, the depletion layer extends from the pn junction between first well region 30 and second well region 31 and silicon carbide drift layer 20.

  Next, a method for manufacturing the MOSFET of FIG. 1 will be described. 2 to 9 are schematic sectional views showing the process.

First, an n-type low-resistance silicon carbide substrate 10 having a plane direction of the first main surface of (0001) plane and a 4H polytype is prepared. Then, n-type silicon carbide drift layer 20 is epitaxially grown on the upper surface by chemical vapor deposition (CVD) (FIG. 2). The silicon carbide drift layer 20 has an n-type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ and a thickness of about 5 to 50 μm.

  Next, in order to identify the position of the basal plane defect existing in the silicon carbide drift layer 20 in the wafer, a crystal defect inspection is performed. As a method for inspecting crystal defects, for example, an optical microscope including a differential interference microscope, a confocal microscope inspection, a laser microscope, a photoluminescence measurement, an FT-IR (Fourier Transform Infrared Spectrophotometer) measurement, an X-ray diffraction and the like are widely known. Any of these may be employed in the present invention.

  Thereafter, the first implantation mask 100 having an opening on the formation region of the first well region 30 is formed on the silicon carbide drift layer 20 by using a photolithography technique. That is, a positive photoresist is applied to the upper surface of the silicon carbide drift layer 20, and the first well mask 30 is exposed by using a photomask having a pattern in which the formation region of the first well region 30 is opened, and then subjected to a development process, thereby performing the first implantation mask. 100 is formed.

Then, using the first implantation mask 100 as a mask, Al, which is a p-type impurity, is selectively ion implanted into the silicon carbide drift layer 20 to form the first well region 30 (FIG. 3). At this time, the depth of ion implantation of Al is about 0.5 to 3 μm within a range not exceeding the thickness of the silicon carbide drift layer 20. Further, the concentration of Al as the ion-implanted impurity is higher than the concentration of the n-type impurity of the silicon carbide drift layer 20 in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

  After the removal of the first implantation mask 100, a second implantation mask 101 having an opening in the formation region of the second well region 31, that is, the region where the basal plane defect is detected by the defect inspection is formed. The second implantation mask 101 is formed by applying a positive photoresist on the upper surface of the silicon carbide drift layer 20 and selectively irradiating the position where the basal plane defect exists in a plan view with a part of the photoresist. The film can be formed by performing a development process after exposing the film.

Then, using second implantation mask 101 as a mask, Al, which is a p-type impurity, is selectively ion implanted into silicon carbide drift layer 20 to form second well region 31 (FIG. 4). At this time, the depth of ion implantation of Al is desirably 0.1 μm or more and 3 times or less deeper than that of Al implanted at the time of forming the first well region 30. The impurity concentration of the ion-implanted Al is in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ and higher than the n-type impurity concentration of the silicon carbide drift layer 20, more preferably The concentration is the same as that of Al ion-implanted to form the 1-well region 30.

  Except for the case where the basal plane direction (the direction along the basal plane) is completely perpendicular to the main surface of silicon carbide drift layer 20, the basal plane defects have a finite extent in silicon carbide drift layer 20. . The formation region of the second well region 31 preferably completely includes the basal plane defect in plan view. As can be seen from the process of FIG. 4, the width of the second well region 31 is determined by the size of the opening in which the second implantation mask 101 is provided. Therefore, in order to compensate for the deviation of the exposure position due to a mechanical error, an opening of the second implantation mask 101 is formed with a margin of 0.1 μm or more outside the basal plane defect at the stage of irradiating the photoresist with ultraviolet rays. It is preferable to do.

After removing the second implantation mask 101, a third implantation mask 102 having an opening in the formation region of the source region 40 is formed on the silicon carbide drift layer 20 using photolithography. Then, using the third implantation mask 102 as a mask, nitrogen (N) which is an n-type impurity is ion-implanted to form the source region 40 (FIG. 5). At this time, the N ion implantation depth is made shallower than the thickness of the first well region 30. The impurity concentration of the ion-implanted N is in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ and exceeds the p-type impurity concentration of the first well region 30.

  After removing the third implantation mask 102 (FIG. 6), annealing is performed in an inert gas atmosphere such as argon (Ar) gas at 1300 to 1900 ° C. for 30 seconds to 1 hour using a heat treatment apparatus. By this annealing, ion-implanted N and Al are activated.

  Thereafter, the upper surface of silicon carbide drift layer 20 is thermally oxidized to form gate insulating film 50 having a predetermined thickness (FIG. 7). A conductive polycrystalline silicon film is formed on the gate insulating film 50 by a low pressure CVD method and patterned to form a gate electrode 60 (FIG. 8). Then, an opening reaching the source region 40 is formed in the gate insulating film 50, and a source electrode 70 connected to a part of the source region 40 is formed therein (FIG. 9). Further, by forming drain electrode 80 on the lower surface of silicon carbide substrate 10, the structure of the MOSFET of FIG. 1 is completed. Examples of the material for the source electrode 70 and the drain electrode 80 include an Al alloy.

  In the above description, the first well region 30, the second well region 31, and the source region 40 are formed in this order by various ion implantations into the silicon carbide drift layer 20, but the formation order thereof may be arbitrary.

  The effect of the present invention will be described. As described above, since the basal plane defect is a crystal defect formed two-dimensionally in the basal plane, the direction in which the leakage current flows in the off state is also the direction in the basal plane. On the other hand, electrons and holes that cause leakage current are accelerated more strongly as the applied electric field is larger. Therefore, if the electric field parallel to the leakage current path can be suppressed, the leakage current becomes smaller. Therefore, in order to reduce the leakage current caused by the basal plane defect, it is effective to reduce the electric field strength in the direction along the basal plane (base plane direction). The inventors of the present invention have made the present invention paying attention to this characteristic.

  10A and 10B are diagrams schematically showing a cross-sectional structure of the MOSFET. Since the effect of the present invention (reduction of leakage current) is obtained mainly when the MOSFET is in the off state, elements that do not affect the off-state electric field distribution such as the source region 40 are omitted here, and the off-state MOSFET is omitted. The structure of is simplified and reproduced.

  Structure A shown in FIG. 10A corresponds to a MOSFET having a conventional structure in which only the first well region 30 is formed in the silicon carbide drift layer 20 on the silicon carbide substrate 10. In the structure B shown in FIG. 10B, the silicon carbide drift layer 20 on the silicon carbide substrate 10 is formed with a plurality of first well regions 30 and an integral second well region 31 straddling them. This corresponds to the MOSFET of the form.

  Here, similarly to FIG. 1, silicon carbide substrate 10 and silicon carbide drift layer 20 are n-type, and first well region 30 and second well region 31 are p-type. In the following description, a direction perpendicular to the upper surface (first main surface) of silicon carbide substrate 10 is “upward”, and a direction perpendicular to the lower surface (second main surface) is “downward”. The direction from 30 to the other first well region 30 adjacent thereto is referred to as a “lateral direction”.

  FIGS. 11A and 11B are diagrams showing directions of electric fields generated in the first well region 30 in the silicon carbide drift layer 20 and its periphery in the OFF state of the MOSFETs having the structures A and B, respectively. .

  In the OFF state of the MOSFET of structure A, silicon carbide drift layer 20 (including the JFET region) is depleted, and positive space charges corresponding to donor ions are generated in that portion. On the other hand, since first well region 30 has a higher impurity concentration than silicon carbide drift layer 20, only the outer peripheral portion close to silicon carbide drift layer 20 is depleted in first well region 30, and a negative electrode corresponding to acceptor ions is present in that portion. The space charge is generated. Electric lines of force are formed so as to connect these positive space charges and negative space charges, and an electric field corresponding to the density is generated in the direction of the arrow in FIG.

  In silicon carbide drift layer 20, the lines of electric force generated from donor ions generated in the region below first well region 30 are terminated by acceptor ions generated in first well region 30 immediately above, so that the first well region The direction of most electric fields generated under 30 is upward. On the other hand, the first well region 30 does not exist immediately above the JFET region and the region below it in the silicon carbide drift layer 20, and therefore the electric lines of force generated from donor ions in the portion are close to the first well region 30. Terminate with acceptor ions generated inside. For this reason, in the structure A, as shown in FIG.

  In the MOSFET having the structure B, since the second well region 31 is formed between the adjacent first well regions 30, there is no JFET region in that portion. In structure B, since second well region 31 is formed uniformly, the electric lines of force generated from the donor ions generated in silicon carbide drift layer 20 are the acceptors in second well region 31 immediately above it. Terminate with ions. Accordingly, in the silicon carbide drift layer 20 having the structure B, only an upward electric field is generated as shown in FIG. That is, in the structure B, no horizontal electric field component is generated.

The inventors calculated the internal electric field distribution for each of the structures A and B using a two-dimensional device simulation by the finite element method. In the simulation, the silicon carbide drift layer 20 is assumed to have a donor concentration of 1 × 10 ¹⁶ cm ⁻³ and a film thickness of 10 μm in both structures A and B. In both structures A and B, the first well region 30 has an acceptor concentration of 1 × 10 ¹⁸ cm ⁻³ and a depth of 0.8 μm, and two first well regions 30 are formed at an interval of 4 μm above the silicon carbide drift layer 20. It was assumed that it was placed.

Further, the second well region 31 provided in the structure B includes two first well regions 30 (that is, the second well region 31 is thicker than the first well region 30), and the acceptor concentration is 1 × 10 ¹⁸ cm ^{−. 3. The} depth was assumed to be 1.0 μm. It is assumed that the impurity concentration of the region where the first well region 30 and the second well region 31 overlap is the sum of the single impurity concentrations. Further, assuming that the MOSFET is in an off state, it is assumed that a reverse bias of 1000 V is applied to each of the structures A and B.

  FIGS. 12A and 12B show the simulation results, and show the calculation results of the potential distribution when a reverse bias of 1000 V is applied to the structures A and B, respectively. In the figure, the potential distribution is indicated by equipotential lines in increments of 50V. As shown in FIG. 12A, in the structure A, it can be seen that equipotential lines are bent around the first well region 30 and have electric fields in various directions. Further, as shown in FIG. 12B, it can be seen that in the structure B, the equipotential lines are almost horizontal over the entire region, and no electric field in the lateral direction is generated.

  Here, it is assumed that the basal plane in silicon carbide drift layer 20 in structures A and B is perpendicular to the cross section of FIG. 10 and forms an angle θ with respect to the upper surface of silicon carbide substrate 10. That is, it is assumed that the upper surface of silicon carbide substrate 10 is a surface inclined by θ from the c-plane of silicon carbide. FIG. 13 shows the maximum value of the electric field strength in the basal plane direction in the entire silicon carbide drift layer 20 of each of the structures A and B (including the first well region 30 and the second well region 31) under this assumption. The relationship between the maximum electric field strength) and the ratio thereof and the angle θ is shown. In FIG. 13, it is assumed that a reverse bias of 1000 V is applied to each of the structures A and B.

  As can be seen from FIG. 13, regardless of the value of θ, the maximum electric field strength in the basal plane direction is smaller in the structure B than in the structure A. Further, as can be seen from the graph of their ratio, it can be seen that the maximum electric field strength in the basal plane direction decreases dramatically in the structure B especially when θ is 8 ° or less. This result means that the leakage current is suppressed in the structure B compared to the structure A when the basal plane defect exists.

  FIG. 14 shows the change in the maximum electric field strength in the basal plane direction when only the depth of the second well region 31 is changed between 0.2 μm and 1.2 μm in the above two-dimensional simulation for the structure B. Show. A plot in which the depth of the second well region 31 corresponds to 0.0 μm corresponds to the structure A in which the second well region 31 does not exist. It can be seen that the maximum value of the electric field strength in the basal plane direction is reduced as compared with the case where the second well region 31 does not exist, regardless of the value of the depth of the second well region 31.

  It can also be seen that when the depth of the second well region 31 is deeper than the depth of the first well region 30 (0.8 μm), the electric field strength in the basal plane direction is most reduced. This is because the bottom position of the second well region 31 is made deeper than the bottom position of the first well region 30, so that the second well region is separated from the pn junction between the silicon carbide drift layer 20 and the second well region 31. This is because the depletion layer extending to the inside of 31 does not reach the first well region 30 and the electric field component in the lateral direction is completely eliminated. Therefore, it is desirable that the depth of the second well region 31 is deeper than that of the first well region 30.

This depth relationship will be examined in more detail. The depth d at which the electric field enters the second well region 31 from the pn junction surface formed between the second well region 31 and the silicon carbide drift layer 20 is expressed by the following equation (1).
d = {2ε ₀ ε _s (V _D + φ _bi )} / qN _A Formula (1)
In this equation, ε ₀ is the dielectric constant of vacuum, ε _s is the relative dielectric constant of silicon carbide, V _D is the drain voltage, φ _bi is the diffusion potential of the pn junction, q is the elementary charge, and N _A is the second well region. An acceptor concentration of 31.

That is, if the depth of the second well region 31 is made deeper than the depth of the first well region 30 by d or more determined by the equation (1), the depletion layer does not reach the first well region 30, and the second well region 31. The electric field component in the lateral direction below can be minimized. For example, if N _A is 1 × 10 ¹⁸ cm ⁻³ and V _D is 600 V, d is 0.08 μm.

  In the structure B shown in FIG. 10B, the second well region 31 is formed on the entire upper surface portion of the silicon carbide drift layer 20 for the convenience of simulation. Actually, as shown in FIG. 1, the second well region 31 is locally formed in a region where a basal plane defect exists. In the region where the second well region 31 is formed, the JFET region serving as an on-current path disappears and the on-resistance does not flow. Therefore, when the second well region 31 is formed on the entire surface of the silicon carbide drift layer 20, the switching element It will not function as.

  Further, from the viewpoint of reducing the on-resistance, it is desirable that the area of the current path is wide, so that the area of the formation region of the second well region 31 is preferably as small as possible. Therefore, it is desirable that the second well region 31 is formed only in a region where a basal plane defect exists. This is why the crystal defect inspection is performed on the silicon carbide drift layer 20 and the position of the basal plane defect is specified prior to the formation of the second well region 31 in the practice of the present invention.

  As described above, according to the present embodiment, the second well region 31 is formed in the region of the silicon carbide drift layer 20 where the basal plane defect exists, thereby generating an electric field component in the direction along the basal plane defect. Is suppressed. Therefore, the occurrence of leakage current due to the basal plane defects can be suppressed, and the yield in the manufacture of the silicon carbide semiconductor device can be improved and the cost can be reduced accordingly.

<Embodiment 2>
As described with reference to FIGS. 3 and 4, in the first embodiment, the p-type impurity region (second well region 31) formed in the entire upper surface portion of the region where the basal plane defect exists in silicon carbide drift layer 20 Was formed in a process separate from the first well region 30. In this embodiment, a method for forming them simultaneously will be described.

  FIG. 15 is a cross sectional view showing a configuration of a vertical MOSFET which is a silicon carbide semiconductor device according to the second embodiment. In the figure, elements having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  In the MOSFET of FIG. 15, the third well region 32 formed by the same ion implantation as the formation of the first well region 30 is formed in the entire upper surface portion of the region where the basal plane defect exists in the silicon carbide drift layer 20. This is different from the configuration of FIG. That is, the third well region 32 is not formed over the first well region 30 but is formed simultaneously with the first well region 30. Therefore, the depth (thickness), impurity concentration, etc. of the third well region 32 are the same as those of the first well region 30.

  A method for manufacturing the MOSFET according to the present embodiment will be described. First, silicon carbide drift layer 20 is formed on silicon carbide substrate 10 by the same procedure as in the first embodiment, and the position of the basal plane defect existing in silicon carbide drift layer 20 in the wafer is specified by crystal defect inspection. .

  Subsequently, a positive type photoresist is applied to the upper surface of the silicon carbide drift layer 20 and exposed using a photomask having a pattern in which the formation region of the first well region 30 is opened. As in the first embodiment, this photomask uses a pattern in which the pattern of the first well region 30 is periodically formed over the entire region including the region where the basal plane defects exist.

  In the first embodiment, the development process is performed here. However, in this embodiment, before the development process, the region where the basal plane defect exists is selectively irradiated with ultraviolet rays, and the photoresist in that portion is exposed. Let Then, when the development process is performed, as shown in FIG. 16, the fourth implantation mask 103 in which both the formation region of the first well region 30 and the formation region of the third well region 32 (region where the basal plane defect exists) is opened. Is formed. That is, the opening pattern of the fourth implantation mask 103 is the logical sum of the formation region of the first well region 30 and the formation region of the third well region 32. Moreover, you may perform the resist baking with respect to the 4th implantation mask 103 as needed.

  Then, using the fourth implantation mask 103 as a mask, Al, which is a p-type impurity, is selectively ion implanted into the silicon carbide drift layer 20 to form the first well region 30 and the third well region 32 simultaneously ( FIG. 16). The ion implantation conditions (dose amount, implantation depth, etc.) may be the same as those in forming the first well region 30 of the first embodiment.

  Also in the present embodiment, a p-type impurity region (third well region 32) having a constant thickness is formed in the entire upper region of the region where the basal plane defect of silicon carbide drift layer 20 exists, as in the first embodiment. Therefore, only an upward electric field component is generated in that region. Therefore, the electric field component in the direction along the basal plane defect can be reduced, and the leakage current caused by the basal plane defect can be suppressed. Further, in the present embodiment, since the implantation mask forming process and the ion implantation process can be reduced by one time as compared with the first embodiment, the process cost can be reduced.

  In the above description, silicon carbide substrate 10 has a (0001) plane of the first main surface, a 4H polytype, and the first main surface is inclined by 4 ° with respect to the c-axis direction. However, the application of the present invention is not limited to this. For example, the plane orientation of silicon carbide substrate 10 may be a (000-1) plane. Further, the inclination angle of the first main surface with respect to the c-axis may be 60 ° or less, preferably 8 ° or less, and the direction of the inclination is not limited. The first main surface may not be inclined with respect to the c-axis.

  In addition, the application of the present invention is not limited to MOSFETs, and the active region has a configuration in which regions that are depleted during reverse bias (the first well region 30 in the above example) are arranged apart from each other. The present invention can be widely applied to semiconductor devices. Examples of such a semiconductor device include an IGBT (Insulated Gate Bipolar Transistor), a JBS (junction barrier Schottky) diode, and a JFET.

  Further, the present invention is not limited to application to silicon carbide semiconductor devices, but can be widely applied to semiconductor devices formed using other compound semiconductors that can generate basal plane defects (including stacking faults). It is. In particular, since the present invention is expected to be applied to a power semiconductor device that controls a high voltage, it can be applied to a device using a wide band gap semiconductor capable of realizing a high breakdown voltage and a low loss. Examples of the wide band gap semiconductor include gallium nitride and aluminum nitride in addition to silicon carbide.

  10 silicon carbide substrate, 20 silicon carbide drift layer, 30 first well region, 31 second well region, 32 third well region, 40 source region, 50 gate insulating film, 60 gate electrode, 70 source electrode, 80 drain electrode, 100-103 implantation mask.

Claims (17)

A semiconductor substrate;
A drift layer of a first conductivity type formed on the main surface of the semiconductor substrate;
A plurality of first well regions of a second conductivity type that are selectively spaced apart from each other on the upper surface of the drift layer;
A region of the drift layer where crystal defects are present; and a second well region of a second conductivity type which is formed integrally with the upper surface of the drift layer so as to include the crystal defects in a plan view. A semiconductor device. The semiconductor device according to claim 1, wherein the second well region is formed so as to overlap one or more of the plurality of first well regions. 3. The semiconductor device according to claim 2, wherein a bottom of the second well region is located deeper from a surface of the drift layer than a bottom of the plurality of first well regions. 4. The semiconductor device according to claim 2, wherein the second well region extends over two or more of the plurality of first well regions. 5. The semiconductor device according to claim 1, wherein the second well region has the same thickness and impurity concentration as the plurality of first well regions. The semiconductor device according to claim 1, wherein the crystal defect is a basal plane defect. The semiconductor device according to claim 6, wherein the basal plane defect is a stacking fault. The semiconductor device according to claim 1, wherein the semiconductor substrate and the drift layer are compound semiconductors. The semiconductor device according to claim 1, wherein the compound semiconductor is silicon carbide. The semiconductor device according to claim 1, wherein the main surface of the semiconductor substrate is inclined within 8 ° from the c-plane. The semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device is any one of a MOSFET, an IGBT, a JBS, and a JFET. (A) preparing a semiconductor substrate having a first conductivity type drift layer on the main surface; (b) performing a crystal defect inspection for detecting a crystal defect in the drift layer and specifying its position;
(C) forming a plurality of second-conductivity-type first well regions on the top surface of the drift layer apart from each other;
(D) A second well region of the second conductivity type is formed on the upper surface portion of the drift layer in the region including the position of the identified crystal defect so as to include the crystal defect in a plan view without being separated. A method of manufacturing a semiconductor device. The step (c) is performed by first ion implantation using an implantation mask in which a formation region of the first well region is opened.
The method of manufacturing a semiconductor device according to claim 12, wherein the step (d) is performed by second ion implantation using an implantation mask in which a formation region of the second well region is opened. 14. The method of manufacturing a semiconductor device according to claim 13, wherein in the second ion implantation, an impurity of a second conductivity type is implanted deeper than in the first ion implantation. 13. The steps (c) and (d) are simultaneously performed by ion implantation using an implantation mask in which both the formation region of the first well region and the formation region of the second well region are opened. A method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device according to claim 12, wherein the crystal defect detected in the step (b) is a basal plane defect. The method of manufacturing a semiconductor device according to claim 16, wherein the basal plane defect is a stacking fault.

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