JP2012243778A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method obtained by devising a processing method for a channel formation region of a semiconductor layer, in which a channel formation region is to be formed and a region on the opposite side and neighborhood.SOLUTION: A semiconductor device manufacturing method comprises performing at least a first etching and a second etching on a part of a laminated semiconductor films in which an amorphous semiconductor film is provided at least on a crystalline semiconductor film. The first etching is performed with remaining a part of the amorphous semiconductor film. The second etching is performed to expose, after removing a coating film on the amorphous semiconductor film, a part of the crystalline semiconductor film provided on the laminated semiconductor films under a condition that an etching rate for the amorphous semiconductor film is high and an etching rate for the crystalline semiconductor film is low.

Description

  The present invention relates to a method for manufacturing a semiconductor device. Note that in this specification, a semiconductor device refers to a semiconductor element itself or a device including a semiconductor element, and examples of such a semiconductor element include a transistor (such as a thin film transistor). A display device such as a liquid crystal display device is also included in the semiconductor device.

  In recent years, semiconductor devices have become indispensable for human life. A thin film transistor included in such a semiconductor device is manufactured by forming a thin film on a substrate and processing the thin film into a desired shape by etching or the like. Such a method for manufacturing a thin film element is applied to, for example, a liquid crystal display device (for example, a liquid crystal television).

  A thin film transistor of a conventional liquid crystal television often uses an amorphous silicon film as a semiconductor film. This is because a thin film transistor formed of an amorphous silicon film has a relatively easy structure.

  However, due to recent movie situations (for example, watching 3D movies, watching 3D sports, etc.), it is difficult to express the clarity of a movie on a liquid crystal television using an amorphous silicon film, and a thin film transistor that responds at high speed. Development is underway. Therefore, development of a microcrystalline silicon film with high carrier mobility has been advanced. As a prior art document in which a thin film transistor using a microcrystalline silicon film is disclosed, for example, Patent Document 1 is cited.

  The electrical characteristics of the thin film transistor are greatly affected by the state in the vicinity of the side opposite to the channel formation region of the layer in which the channel formation region is formed (a portion called a back channel; hereinafter referred to as a “back channel portion”). For example, in Patent Document 1, by forming a back channel portion of a channel etch type thin film transistor in which an amorphous silicon film is provided over a microcrystalline silicon film, the resist mask is removed, and then the back channel portion is further etched. A method for manufacturing a thin film transistor in which off-state current is reduced is disclosed.

JP 2009-084222 A

  However, it is difficult to perform processing so that the microcrystalline silicon film is exposed and the amorphous silicon film is removed in the channel etch type thin film transistor in which the amorphous silicon film is provided over the microcrystalline silicon film. This is because the microcrystalline silicon film and the amorphous silicon film have different crystal structures but have the same main component.

  An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device in which electrical characteristics are improved (particularly, off-state current is reduced) by devising formation of a back channel portion.

  An object of one embodiment of the present invention is to provide a semiconductor device with improved electrical characteristics (particularly with reduced off-state current).

  One embodiment of the present invention is a semiconductor device in which a back channel portion is provided so that the second semiconductor layer does not remain over the first semiconductor layer in a state where the first semiconductor layer and the second semiconductor layer are stacked. In the manufacturing process, the first etching is performed in a state where the resist mask remains under a condition with a high etching rate with respect to the first semiconductor layer and the second semiconductor layer, and then the second etching is performed after removing the resist mask. A method for manufacturing a semiconductor device. Here, the second etching is a step of removing the coating film formed during the first etching (or formed when the resist mask is removed or exposed to the atmosphere), And the step of performing under the condition that the etching rate for the semiconductor layer is low is performed in this order.

  Here, for example, the first etching is performed with a chlorine-based gas, the step of removing the coating film of the second etching is performed with a fluorine-based gas, and the etching rate of the second etching with respect to the first semiconductor layer is low. The process performed according to conditions is performed with hydrogen gas. The gas used in the step of removing the coating film may be a gas that can be introduced into the film forming apparatus, and a gas used for cleaning the inside of the chamber is preferably used. This is because they can be used together.

  Note that in this specification, “film” refers to a film formed over the entire surface by a CVD method (including a plasma CVD method) or a sputtering method. On the other hand, the “layer” refers to a “film” that has been processed or a film that has not been processed in a state where it is formed on the entire surface of the formation surface. However, “film” and “layer” may be used without particular distinction.

  Note that in this specification, an “etching mask” refers to a mask layer formed to prevent a film formed under the etching mask from being etched. Examples of the etching mask include a resist mask.

  According to one embodiment of the present invention, electrical characteristics of a semiconductor device can be improved. In particular, it is possible to improve a decrease in electrical characteristics due to the shape of the back channel portion and impurities.

10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device (electronic device) which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device (electronic device) which is one embodiment of the present invention. 6A and 6B illustrate a semiconductor device (electronic device) which is one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

(Embodiment 1)
In this embodiment, a semiconductor device which is one embodiment of the present invention and a manufacturing method thereof will be described.

  A first conductive film 102 is formed over the substrate 100, and a first etching mask 104 is formed over the first conductive film 102 (FIG. 1A). The gate electrode 106 is formed by processing the first conductive film 102 using the first etching mask 104.

  The substrate 100 is an insulating substrate. As the substrate 100, for example, a glass substrate, a quartz substrate, a ceramic substrate, or a plastic substrate having heat resistance enough to withstand the processing temperature of the manufacturing process can be used. Note that the substrate 100 is not necessarily a light-transmitting substrate.

  The first conductive film 102 is formed using a conductive material (eg, a metal material or a semiconductor material to which an impurity element of one conductivity type is added), for example, by a sputtering method. Note that the first conductive film 102 may be formed as a single layer or a stack of a plurality of films.

  For example, a resist mask may be formed as the first etching mask 104, but is not limited to a specific one as long as it can be used as a mask in an etching process.

  The gate electrode 106 also constitutes a scanning line.

  Note that the formation of the gate electrode 106 is not limited to the structure illustrated in the drawing, and the gate electrode 106 may be selectively formed using a droplet discharge method (for example, an inkjet method) or the like. It is preferable to use a droplet discharge method (for example, an ink jet method) or the like for forming the gate electrode 106 because the first etching mask 104 is not formed and removed, and the number of masks is reduced by one.

  Next, the first etching mask 104 is removed, and a gate insulating layer 108 is formed over the gate electrode 106 (FIG. 1B).

  For the gate insulating layer 108, an insulating material (eg, silicon nitride, silicon nitride oxide, silicon oxynitride, or silicon oxide film) may be formed using a plasma CVD method, for example. Note that the gate insulating layer 108 may be a single layer or a stack of a plurality of layers. Here, for example, a two-layer structure in which a silicon oxynitride layer is stacked over a silicon nitride layer is preferable.

  Note that “silicon nitride oxide” has a nitrogen content higher than that of oxygen, and is preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). When measured using Hydrogen Forward Scattering Spectrometry), the composition range is 5 to 30 atomic% for oxygen, 20 to 55 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 10 to 30 atomic% for hydrogen. It means what is included.

  Note that “silicon oxynitride” has a composition containing more oxygen than nitrogen, and preferably has a composition range of 50 to 70 oxygen when measured using RBS and HFS. The term “atom percent” includes nitrogen in the range of 0.5 to 15 atom%, silicon in the range of 25 to 35 atom%, and hydrogen in the range of 0.1 to 10 atom%.

  However, when the total of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

Note that in the case where a crystalline semiconductor film is formed over the gate insulating layer 108, plasma treatment is preferably performed on the gate insulating layer 108 with a gas containing oxygen. Here, examples of the gas containing oxygen include N ₂ O gas. By performing plasma treatment on the gate insulating layer 108 with a gas containing oxygen, the crystallinity of the crystalline semiconductor film formed over the gate insulating layer 108 can be improved.

  Next, a first semiconductor film 110, a second semiconductor film 112, and an impurity semiconductor film 114 are stacked in this order over the gate insulating layer 108, and a second etching mask 116 is formed over the impurity semiconductor film 114. (FIG. 1C).

  The first semiconductor film 110 is a semiconductor film that is mostly crystalline. An example of the crystalline semiconductor is a microcrystalline semiconductor. Here, a microcrystalline semiconductor refers to a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). A microcrystalline semiconductor is a semiconductor having a third state which is stable in terms of free energy, is a crystalline semiconductor having a short-range order and lattice distortion, and has a crystal grain size of 2 nm to 200 nm, preferably 10 nm. A semiconductor in which columnar or needle-like crystal grains having a size of 80 nm or more and more preferably 20 nm or more and 50 nm or less are grown in a normal direction with respect to the substrate surface. For this reason, a grain boundary may be formed at the interface between columnar or needle-like crystal grains. Here, the crystal grain size is the maximum diameter of crystal grains in a plane parallel to the substrate surface. In addition, the crystal grain includes an amorphous semiconductor region and a crystallite which is a microcrystal that can be regarded as a single crystal. Note that the crystal grains may have twins.

As the microcrystalline semiconductor, microcrystalline silicon may be used. In microcrystalline silicon which is one of microcrystalline semiconductors, the peak of its Raman spectrum is shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as He, Ar, Kr, or Ne to further promote lattice distortion, stability is improved and a favorable microcrystalline semiconductor film can be obtained.

Note that when the concentrations of oxygen and nitrogen (measured by secondary ion mass spectrometry) contained in the crystalline semiconductor film are lowered and preferably these concentrations are less than 1 × 10 ¹⁸ cm ⁻³ , the crystallinity is increased. be able to.

  Note that the crystalline semiconductor film is preferably formed by a two-stage film formation process. In the two-stage film formation process, for example, in the first stage, a microcrystalline silicon film having a thickness of about 5 nm under a pressure of about 500 Pa. In the second stage, a microcrystalline silicon film having a desired thickness may be formed under a pressure of about 5000 Pa. In the second stage, the flow rate ratio of silane is preferably smaller than that in the first stage so that the conditions are highly diluted.

  The second semiconductor film 112 is a semiconductor film that functions as a buffer layer and is mostly amorphous. Preferably, it has an amorphous semiconductor and a small semiconductor crystal grain, and has an Urbach edge measured by a constant photocurrent method (CPM) or photoluminescence spectroscopy as compared with a conventional amorphous semiconductor. It is a semiconductor film with low energy and a small amount of defect absorption spectrum. Such a semiconductor film has fewer defects than a conventional amorphous semiconductor film, and has an orderly structure in which the level tail at the band edge (mobility edge) of the valence band is steep. It is a high semiconductor film.

The second semiconductor film 112 may contain halogen or nitrogen. When nitrogen is contained, it may be contained as an NH group or NH ₂ group.

  Note that here, the interface region between the first semiconductor film 110 and the second semiconductor film 112 includes a microcrystalline semiconductor region and an amorphous semiconductor region filled between the microcrystalline semiconductor regions. Specifically, a microcrystalline semiconductor region extending in a conical shape from the first semiconductor film 110 and a “film containing an amorphous semiconductor” similar to the second semiconductor film 112 are formed.

  In addition, since the buffer layer is provided by the second semiconductor film 112, the off-state current of the transistor can be reduced. Since the interface region has a microcrystalline semiconductor region extending in a conical shape, resistance in the vertical direction (thickness direction), that is, a source region including the second semiconductor film 112 and the impurity semiconductor film 114 Alternatively, resistance between the drain region and the drain region can be reduced, and the on-state current of the transistor can be increased. That is, as compared with the case where a conventional amorphous semiconductor is applied, a decrease in on-state current can be suppressed while sufficiently reducing off-state current, and switching characteristics of the transistor can be improved.

  The microcrystalline semiconductor region is preferably mainly constituted by cone-shaped crystal grains whose tips are narrowed from the first semiconductor film 110 toward the second semiconductor film 112. Alternatively, most of the crystal grains may have a width that increases from the first semiconductor film 110 toward the second semiconductor film 112.

  In addition, in the interface region, when the microcrystalline semiconductor region is a crystal grain extending in a cone shape whose tip is narrowed from the first semiconductor film 110 toward the second semiconductor film 112, the first semiconductor film The proportion of the microcrystalline semiconductor region is higher on the 110 side than on the second semiconductor film 112 side. The microcrystalline semiconductor region grows in the thickness direction from the surface of the first semiconductor film 110, but the flow rate of hydrogen with respect to the deposition gas (eg, silane) in the source gas is small (that is, the dilution rate is low), or When the concentration of the source gas containing nitrogen is high, crystal growth in the microcrystalline semiconductor region is suppressed, the crystal grains have a cone shape, and the deposited semiconductor is mostly an amorphous semiconductor.

Incidentally, the interface region, nitrogen, it is particularly preferable to contain an NH group or an NH ₂ group. This is because defects at the interface of the crystal included in the microcrystalline semiconductor region, the interface between the microcrystalline semiconductor region and the amorphous semiconductor region, and nitrogen, particularly NH groups or NH ₂ groups, are bonded to dangling bonds of silicon atoms. This is because the number of carriers is reduced and the carrier flows easily. Therefore, when nitrogen, preferably NH group or NH ₂ group, is contained at a concentration of 1 × 10 ²⁰ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ , dangling bonds of silicon atoms are nitrogen, preferably NH groups or easily cross-linked with an NH ₂ group, the carrier is more easily flow. As a result, bonds that promote the movement of carriers at the grain boundaries and defects can be formed, and the carrier mobility in the interface region can be improved. Therefore, the field effect mobility of the transistor is improved.

  Note that by reducing the oxygen concentration in the interface region, the defect density at the interface between the microcrystalline semiconductor region and the amorphous semiconductor region or the interface between crystal grains can be reduced, and bonds that inhibit carrier movement can be reduced. Can do.

  The impurity semiconductor film 114 is formed using a semiconductor to which an impurity element imparting one conductivity type is added. In the case where the transistor is n-type, a semiconductor to which an impurity element imparting one conductivity type is added includes, for example, silicon to which P or As is added. Alternatively, in the case where the transistor is a p-type, for example, B can be added as an impurity element imparting one conductivity type. However, the transistor is preferably n-type. Therefore, here, silicon added with P is used as an example. Note that the impurity semiconductor film 114 may be formed using an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.

  The second etching mask 116 can be formed using a material and a method similar to those of the first etching mask 104.

  Next, the first semiconductor film 110, the second semiconductor film 112, and the impurity semiconductor film 114 are processed using the second etching mask 116 to form the semiconductor stacked body 118, and then the second etching mask 116 is formed. Is removed (FIG. 1D).

  Here, it is preferable to perform an insulating process on the sidewall of the semiconductor stacked body 118. This is because when the first semiconductor layer 138 of the completed transistor is in contact with the source electrode and the drain electrode formed by the stacked conductive film 126 to be formed next, off-state current often increases. Here, as the insulating treatment, an insulating film is formed in a state in which the side wall of the semiconductor stacked body 118 is exposed to oxygen plasma or nitrogen plasma, or the side wall of the semiconductor stacked body 118 is exposed, and the insulating film is made anisotropic. A process of forming a sidewall insulating layer in contact with the sidewall of the semiconductor stacked body 118 by performing etching in a direction perpendicular to the surface of the substrate 100 by a high etching method can be given.

  Next, a second conductive film 120, a third conductive film 122, and a fourth conductive film 124 are stacked in this order so as to cover the semiconductor stacked body 118 over the gate insulating layer 108, thereby forming a stacked conductive film 126. A third etching mask 128 is formed over the fourth conductive film 124 (FIG. 2A).

  The second conductive film 120, the third conductive film 122, and the fourth conductive film 124 are formed using a conductive material (eg, a metal material or a semiconductor material to which an impurity element of one conductivity type is added), for example, And formed by sputtering. For example, a titanium film may be formed as the second conductive film 120, an aluminum film may be formed as the third conductive film 122, and a titanium film may be formed as the fourth conductive film 124. Note that each of the second conductive film 120, the third conductive film 122, and the fourth conductive film 124 may be formed as a single layer or a stack of a plurality of films.

  Here, the laminated conductive film 126 may be a single-layer conductive film, or is not limited to the illustrated three layers, and may be two layers.

  The third etching mask 128 can be formed using a material and a method similar to those of the first etching mask 104 and the second etching mask 116.

  Next, the stacked conductive film 126 is processed using the third etching mask 128 to form the source electrode 130A and the drain electrode 130B, and the semiconductor stacked body 118 is processed (referred to as a first etching step). ) To form an etched semiconductor stacked body 132 (FIG. 2B).

  The first etching step may be performed by a method capable of etching the stacked conductive film 126 and the semiconductor stacked body 118. Here, for example, the first etching step may be performed using a chlorine-based gas. For example, it is preferable to use a mixed gas of boron trichloride gas and chlorine gas. However, the present invention is not limited to this, and only chlorine gas may be used. Alternatively, another gas that can etch the stacked conductive film 126 may be used.

  Note that the source electrode 130A and the drain electrode 130B constitute at least a signal line, a source electrode, or a drain electrode.

  Note that since the source and the drain are switched depending on each potential, the source electrode 130A and the drain electrode 130B may be reversed.

  Note that in the etched semiconductor stacked body 132, the second semiconductor film 112 remains in the etched portion, and the first semiconductor layer 138 is not exposed.

  Next, the third etching mask 128 is removed (FIG. 2C).

  Here, in the case where the third etching mask 128 is a resist mask, the third etching mask 128 is removed by using one or both of ashing using oxygen gas and peeling using a resist stripping solution. . In order to remove the third etching mask 128 in a state where the etched semiconductor stacked body 132 is exposed, a coating film 134 is formed in a portion where the etched semiconductor stacked body 132 is exposed.

  Here, since the coating film 134 is formed at the time of the first etching or at the time of ashing using an oxygen gas and stripping with a resist stripping solution, silicon oxide is often the main component.

  Next, the semiconductor stacked body 132 etched using the source electrode 130A and the drain electrode 130B as a mask is further processed (referred to as a second etching step), whereby the stacked semiconductor layer 136 is formed. In the stacked semiconductor layer 136, the first semiconductor layer 138 is exposed in a portion that does not overlap with the source electrode 130A and the drain electrode 130B. In addition to the first semiconductor layer 138, the stacked semiconductor layer 136 includes a second semiconductor layer 140A, a second semiconductor layer 140B, a source region 142A, and a drain region 142B (FIG. 3A).

  The stacked semiconductor layer 136 includes a first semiconductor layer 138 exposed in the channel formation region.

  When the first semiconductor layer 138 is exposed, the back channel portion is exposed, and the electric field from the back gate electrode provided to overlap with the channel forming region with the insulating layer interposed therebetween may be sufficient. it can.

  The second semiconductor layer 140A and the second semiconductor layer 140B function as a buffer layer. By providing the buffer layer in this manner, off current can be reduced.

  The source region 142A and the drain region 142B are connected to each other with favorable electrical characteristics at the interfaces of the second semiconductor layer 140A and the second semiconductor layer 140B and the source electrode 130A and the drain electrode 130B, respectively. Preferably, the interface is in ohmic contact.

  In the second etching step, the coating film 134 is removed, and the second semiconductor film portion is removed while the portions of the first semiconductor film that do not overlap with the source electrode 130A and the drain electrode 130B remain. And a process. In the second etching step, a method is employed in which the steps up to the step of forming the insulating film to be the passivation layer 144 can be performed in the same chamber without being exposed to the atmosphere.

  The step of removing the coating film 134 may be performed using a fluorine-based gas, for example, sulfur hexafluoride gas, fluorine gas, or carbonyl fluoride gas. Here, preferably, nitrogen trifluoride gas is used. This is because the nitrogen trifluoride gas is a gas used for cleaning the inside of the chamber and can also be used as this.

  The step of removing the second semiconductor film while leaving the portion of the first semiconductor film that does not overlap with the source electrode 130A and the drain electrode 130B may be performed with hydrogen gas. By etching using hydrogen gas, the portion of the second semiconductor film can be removed while the portion of the first semiconductor film that does not overlap with the source electrode 130A and the drain electrode 130B remains.

  As described above, the step of removing the coating film 134 in which the second etching step is performed with the fluorine-based gas, and the portion of the first semiconductor film that is performed with the fluorine-based gas and the hydrogen gas are left while the second semiconductor film is formed. By the step of removing the portion, the portion of the first semiconductor film can be sufficiently left and the portion of the second semiconductor film can be sufficiently removed.

  Here, for example, when the coating film 134 is a silicon oxide film, if the process of removing the coating film 134 is not performed, etching with hydrogen gas is difficult, but the process of removing the coating film 134 is performed. By performing the step, a part of the first semiconductor film can be sufficiently left and a part of the second semiconductor film can be sufficiently removed.

  Note that the gas used here may contain a rare gas such as an argon gas. The concentration of hydrogen can be adjusted with a rare gas such as argon gas, and the etching rate can be adjusted.

  In this manner, the second semiconductor film portion can be removed while the first semiconductor film portion remains.

  Here, it is preferable that the first semiconductor layer 138 is exposed to water plasma in a state where the first semiconductor layer 138 is exposed. Alternatively, plasma generated by a mixed gas of hydrogen gas and oxygen gas may be used instead of water plasma. Here, in this step, the portion of the second semiconductor film is not left in the portion where the first semiconductor layer 138 is exposed, so that the electrical characteristics of the transistor can be improved.

  Next, an insulating film (not shown) is formed on the gate insulating layer 108 so as to cover the stacked semiconductor layer 136, the source electrode 130A, and the drain electrode 130B in the same chamber without being exposed to the atmosphere. Then, a fourth etching mask 146 is formed, and the insulating film is processed using the fourth etching mask 146, whereby a passivation layer 144 having an opening 148 is formed (FIG. 3B).

  The passivation layer 144 prevents at least the back channel portion where the first semiconductor layer 138 is exposed from being contaminated. The insulating film to be the passivation layer 144 may be formed using the same material and method as the gate insulating layer 108, for example.

  The fourth etching mask 146 can be formed using a material and a method similar to those of the first etching mask 104, the second etching mask 116, and the third etching mask 128.

  The opening 148 is provided in a portion overlapping with either the source electrode 130A or the drain electrode 130B.

  Next, the fourth etching mask 146 is removed, a fifth conductive film (not shown) is formed, a fifth etching mask 152 is formed over the fifth conductive film, and the fifth etching mask 152 is formed. A back gate electrode 150A and a pixel electrode 150B are formed by processing the fifth conductive film using (FIG. 3C).

  The fifth conductive film can be formed using a conductive composition including a light-transmitting conductive polymer (also referred to as a conductive polymer). The fifth conductive film formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less. Note that a so-called π-electron conjugated conductive polymer can be used as the conductive polymer. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

  Alternatively, the fifth conductive film is formed using, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, It can be formed using indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

  Although not illustrated, an organic resin layer formed by a spin coating method or the like may be provided between the passivation layer 144 and the fifth conductive film.

  The back gate electrode 150A constitutes a back gate provided in the pixel transistor.

  Since the pixel electrode 150B forms a pixel electrode connected to the pixel transistor, the pixel electrode 150B is preferably formed using a light-transmitting material.

  As described above, it is preferable to form the back gate electrode 150A and the pixel electrode 150B as the same layer by the same process because the process is simplified, but the invention is not limited thereto, and the back gate electrode 150A and the pixel electrode 150B may be formed by different processes as different layers.

  The fifth etching mask 152 can be formed using a material and a method similar to those of the first etching mask 104, the second etching mask 116, the third etching mask 128, and the fourth etching mask 146.

  Note that the back gate electrode 150A and the pixel electrode 150B may be selectively formed using a droplet discharge method (for example, an inkjet method) or the like. When a droplet discharge method (for example, an ink jet method) or the like is used for forming the back gate electrode 150A and the pixel electrode 150B, the formation process and the removal process of the fifth etching mask 152 are unnecessary, and the number of masks is one. Reduced and preferred.

  Thereafter, the fifth etching mask 152 is removed. In this way, a pixel transistor can be manufactured.

  According to one embodiment of the present invention, the first semiconductor layer to be a channel formation region is left in a necessary thickness, and the second semiconductor film portion is not left in the portion to be a channel formation region. Can do.

  FIG. 4 illustrates a semiconductor device which is one embodiment of the present invention. 4 includes a gate electrode 106 provided over a substrate 100, a gate insulating layer 108 provided so as to cover the gate electrode 106, and a first channel formation region portion provided over the gate insulating layer 108. The semiconductor device illustrated in FIG. The stacked semiconductor layer 136 from which the semiconductor layer 138 is exposed, the source electrode 130A and the drain electrode 130B provided on the gate insulating layer 108 and the stacked semiconductor layer 136, and the stacked semiconductor layer 136 and the source on the gate insulating layer 108 A passivation layer 144 provided so as to cover the electrode 130A and the drain electrode 130B and having an opening 148, and a back gate electrode 150A provided on the passivation layer 144 so as to overlap with a portion where the first semiconductor layer 138 is exposed. And a drain electrode in the opening 148 Having a pixel electrode 150B which is connected to 30B.

  According to one embodiment of the present invention, contamination of the interface between the first semiconductor layer 138 and the passivation layer 144 included in the stacked semiconductor layer 136 is suppressed, and the thickness of the first semiconductor layer 138 is sufficient. Therefore, the on-current can be sufficient while suppressing the off-current. Further, since the back gate electrode 150A is provided so as to overlap with the exposed portion of the first semiconductor layer 138, the on-state current can be further increased by the electric field of the back gate electrode.

  As described above, the semiconductor device which is one embodiment of the present invention can be manufactured.

(Embodiment 2)
As a semiconductor device to which the thin film transistor manufactured as described in Embodiment 1 is applied, electronic paper can be given. Electronic paper can be used for electronic devices in various fields as long as they display information. For example, it can be applied to electronic books (electronic books), posters, digital signage, PID (Public Information Display), advertisements in vehicles such as trains, displays on various cards such as credit cards, etc. using electronic paper. . An example of the electronic device is illustrated in FIG.

  FIG. 5 illustrates an example of an electronic book. For example, the electronic book 200 includes two housings, a housing 202 and a housing 204. The housing 202 and the housing 204 are integrated by a shaft portion 214 and can be opened and closed with the shaft portion 214 as an axis. With this configuration, it can be handled in the same way as a paper book.

  A display portion 206 and a photoelectric conversion device 208 are incorporated in the housing 202, and a display portion 210 and a photoelectric conversion device 212 are incorporated in the housing 204. The display unit 206 and the display unit 210 may be configured to display a continuation screen or may be configured to display different screens. By adopting a configuration that displays different screens, for example, a sentence can be displayed on the right display unit (display unit 206 in FIG. 5) and an image can be displayed on the left display unit (display unit 210 in FIG. 5). .

  FIG. 5 shows an example in which the housing 202 includes an operation unit and the like. For example, the housing 202 includes a power source 216, operation keys 218, a speaker 220, and the like. The page can be turned with the operation key 218. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the electronic book 200 may have a configuration having a function as an electronic dictionary.

  In addition, the electronic book 200 may be configured to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

(Embodiment 3)
As a semiconductor device to which the thin film transistor manufactured as described in Embodiment 1 is applied, various electronic devices (including game machines) can be used in addition to electronic paper. Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines.

  FIG. 6A illustrates an example of a television device. In the television device 222, a display portion 226 is incorporated in a housing 224. The display unit 226 can display an image. Here, a configuration in which the housing 224 is supported by the stand 228 is shown.

  The television device 222 can be operated with an operation switch provided in the housing 224 or a separate remote controller 234. Channels and volume can be operated with operation keys 232 provided on the remote controller 234, and an image displayed on the display unit 226 can be operated. The remote controller 234 may be provided with a display unit 230 that displays information output from the remote controller 234.

  Note that the television set 222 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

  FIG. 6B illustrates an example of a digital photo frame. For example, the digital photo frame 236 includes a display portion 240 incorporated in a housing 238. The display unit 240 can display various images. For example, by displaying image data captured by a digital camera or the like, the display unit 240 can function in the same manner as a normal photo frame.

  Note that the digital photo frame 236 includes an operation unit, an external connection terminal (a terminal that can be connected to various cables such as a USB terminal and a USB cable), a recording medium insertion unit, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory storing image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 240.

The digital photo frame 236 may be configured to transmit and receive information wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

  FIG. 7 is a perspective view illustrating an example of a portable computer.

  The portable computer in FIG. 7 overlaps an upper housing 242 having a display portion 246 with a hinge unit connecting the upper housing 242 and the lower housing 244 closed and a lower housing 244 having a keyboard 248. When the user performs keyboard input, the hinge unit can be opened and an input operation can be performed while viewing the display unit 246.

  In addition to the keyboard 248, the lower housing 244 has a pointing device 252 that performs an input operation. When the display portion 246 is a touch input panel, an input operation can be performed by touching part of the display portion. Further, the lower housing 244 has a calculation function unit such as a CPU and a hard disk. The lower housing 244 has an external connection port 250 into which another device, for example, a communication cable compliant with the USB communication standard is inserted.

  The upper housing 242 further includes a display portion 254 that can be slid and housed inside the upper housing 242 so that a wide display screen can be realized. Further, the user can adjust the orientation of the screen of the display unit 254 that can be stored. Further, when the storable display unit 254 is a touch input panel, an input operation can be performed by touching a part of the storable display unit.

  The display portion 246 or the storable display portion 254 uses a video display device such as a liquid crystal display panel, a light emitting display panel such as an organic light emitting element or an inorganic light emitting element.

  In addition, the portable computer in FIG. 7 includes a receiver and the like, and can receive a television broadcast and display an image on a display portion. In addition, with the hinge unit connecting the upper housing 242 and the lower housing 244 closed, the display unit 254 is slid to expose the entire screen, and the screen angle is adjusted to allow the user to watch TV broadcasting. You can also. In this case, since the hinge unit is closed and the display unit 246 is not displayed, and only the circuit that only displays the television broadcast is activated, the power consumption can be minimized, and the battery capacity can be limited. It is useful in portable computers that are used.

  In this embodiment, even if the coating film 134 is removed, it is clear that etching by hydrogen gas plasma is difficult to proceed if exposed to the atmosphere between the removal of the coating film 134 and the hydrogen gas plasma treatment. To.

  First, the gate electrode 106 was formed over the substrate 100 as illustrated in FIG. 1B, and the gate insulating layer 108 was formed to cover the gate electrode 106.

Here, the gate insulating layer 108 is formed of silicon nitride. The detailed conditions of the plasma CVD method for forming silicon nitride are as follows.
Monosilane (SiH ₄ ) gas flow rate = 15 sccm
Ammonia (NH ₃ ) gas flow rate = 500 sccm
Nitrogen (N ₂ ) gas flow rate = 180 sccm
Hydrogen (H ₂ ) gas flow rate = 200 sccm
Reaction chamber pressure = 100 Pa
Distance between upper electrode and lower electrode = 26 mm
High frequency power frequency = 13.56 MHz
High frequency power = 200W
Upper electrode temperature = 200 ° C.
Lower electrode temperature = 300 ° C.

Next, plasma treatment was performed on the surface of the gate insulating layer 108. The detailed conditions of the plasma treatment are as follows.
Nitrous oxide (N ₂ O) gas flow rate = 400 sccm
Reaction chamber pressure = 60 Pa
Distance between upper electrode and lower electrode = 30 mm
High frequency power frequency = 13.56 MHz
High frequency power = 900W
Upper electrode temperature = 200 ° C.
Lower electrode temperature = 300 ° C.

  Next, a first semiconductor film 110, a second semiconductor film 112, and an impurity semiconductor film 114 were formed over the gate insulating layer 108 whose surface was subjected to plasma treatment.

The first semiconductor film 110 was formed by a two-step formation process. In the two-stage formation process, a microcrystalline silicon film having a thickness of 5 nm was formed in the first stage, and a microcrystalline silicon film having a thickness of 65 nm was formed in the second stage. Here, the detailed conditions of the plasma CVD method are as follows.
<First stage>
Monosilane (SiH ₄ ) gas flow rate = 2.7 sccm
Argon (Ar) gas flow rate = 3000 sccm
Hydrogen (H ₂ ) gas flow rate = 3000 sccm
Reaction chamber pressure = 10 kPa
Distance between upper electrode and lower electrode = 7 mm
High frequency power frequency = 13.56 MHz
High frequency power = 200W
Lower electrode temperature = 300 ° C.
<Second stage>
Monosilane (SiH ₄ ) gas flow rate = 2 sccm
Hydrogen (H ₂ ) gas flow rate = 3000 sccm
Reaction chamber pressure = 10 kPa
Distance between upper electrode and lower electrode = 7 mm
High frequency power frequency = 13.56 MHz
High frequency power = 700W
Lower electrode temperature = 300 ° C.

Next, a second semiconductor film 112 was formed over the first semiconductor film 110 so as to have a thickness of 80 nm. Here, the detailed conditions of the plasma CVD method are as follows.
Monosilane (SiH ₄ ) gas flow rate = 25 sccm
Hydrogen diluted ammonia gas flow rate = 100 sccm
Argon (Ar) gas flow rate = 750 sccm
Hydrogen (H ₂ ) gas flow rate = 650 sccm
Reaction chamber pressure = 1250 Pa
Distance between upper electrode and lower electrode = 15 mm
High frequency power frequency = 13.56 MHz
High frequency power = 150W
Upper electrode temperature = 200 ° C.
Lower electrode temperature = 300 ° C.

  Here, the hydrogen-diluted ammonia gas refers to a gas obtained by diluting ammonia gas to 1000 ppm by volume with hydrogen gas.

Next, the impurity semiconductor film 114 was formed to a thickness of 50 nm over the second semiconductor film 112. Here, the detailed conditions of the plasma CVD method are as follows.
Monosilane (SiH ₄ ) gas flow rate = 90 sccm
Monosilane diluted phosphine gas flow rate = 10 sccm
Hydrogen (H ₂ ) gas flow rate = 500 sccm
Reaction chamber pressure = 170 Pa
Spacing between upper electrode and lower electrode = 25 mm
High frequency power frequency = 13.56 MHz
High frequency power = 30W
Upper electrode temperature = 200 ° C.
Lower electrode temperature = 300 ° C.

  Here, the monosilane diluted phosphine gas refers to a gas obtained by diluting phosphine gas with monosilane gas to 5 percent by volume.

  Next, a resist mask having an arbitrary pattern is formed over the first semiconductor film 110, the second semiconductor film 112, and the impurity semiconductor film 114, and the first semiconductor film 110, the second semiconductor film 112, and the impurity semiconductor are formed. The semiconductor layer 118 was formed by etching the film 114.

Thereafter, the resist mask was removed, and a single layer titanium film was formed with a thickness of 300 nm on the semiconductor stacked body 118 by a sputtering method instead of the stacked conductive film 126. Here, the detailed conditions of the sputtering method are as follows.
Argon (Ar) gas flow rate = 30 sccm
Reaction chamber pressure = 0.4 Pa
Distance between titanium target and substrate = 185mm
Power = 2000W

After the single-layer titanium film is formed in this way, a resist mask having an arbitrary pattern (at least partly overlaps with the semiconductor stacked body 118) is formed on the titanium film, and the titanium film is formed using the resist mask. The semiconductor stacked body 118 was etched. Here, the etching was performed by ICP. The detailed etching conditions are as follows.
Boron trichloride (BCl ₃ ) gas flow rate = 60 sccm
Chlorine (Cl ₂ ) gas flow rate = 20 sccm
Reaction chamber pressure = 1.9 Pa
Distance between upper electrode and lower electrode = 122 mm
High frequency power frequency = 13.56 MHz
High frequency power = 450W
Bias power between upper electrode and lower electrode = 100 W
Upper electrode temperature = 100 ° C.
Lower electrode temperature = 70 ° C.

  Then, after etching, ashing with oxygen plasma is performed, and further the resist mask is stripped using a resist stripping solution.

  Here, when the total thickness of the remaining film in the portion that did not overlap with the resist mask during etching was measured with a spectroscopic ellipsometer, it was 80 nm. Therefore, part of the second semiconductor film 112 and the impurity semiconductor film 114 are removed by the etching, and the film remaining in the sample is part of the second semiconductor film 112 and the first semiconductor film 110. In the portion where the first semiconductor film 110 is not exposed and does not overlap with the resist mask at the time of etching, it can be said that the uppermost layer of the remaining film is a part of the second semiconductor film 112.

Next, the sample was subjected to plasma treatment with nitrogen trifluoride gas under the following conditions. The detailed conditions of the plasma treatment are as follows.
Nitrogen trifluoride (NF ₃ ) gas flow rate = 20 sccm
Argon (Ar) gas flow rate = 300 sccm
Reaction chamber pressure = 10 Pa
Distance between upper electrode and lower electrode = 46mm
High frequency power frequency = 13.56 MHz
High frequency power = 30W
Upper electrode temperature = 200 ° C.
Lower electrode temperature = 300 ° C.
Processing time = 120 seconds

Next, the substrate was exposed to the atmosphere, and a plasma treatment was performed on the exposed sample with hydrogen gas. The detailed conditions of the plasma treatment are as follows.
Hydrogen (H ₂ ) gas flow rate = 1000 sccm
Reaction chamber pressure = 1000 Pa
Distance between upper electrode and lower electrode = 7 mm
High frequency power frequency = 13.56 MHz
High frequency power = 100W
Upper electrode temperature = 200 ° C.
Lower electrode temperature = 300 ° C.
Processing time = 300 seconds

  Thus, when the total thickness of the sample subjected to the plasma treatment with hydrogen gas was measured with a spectroscopic ellipsometer, it was 80 nm.

  Therefore, even if the coating film 134 is removed, it can be said that etching by hydrogen gas plasma does not proceed easily when exposed to the atmosphere between the removal of the coating film 134 and the hydrogen gas plasma treatment.

100 substrate 102 first conductive film 104 first etching mask 106 gate electrode 108 gate insulating layer 110 first semiconductor film 112 second semiconductor film 114 impurity semiconductor film 116 second etching mask 118 semiconductor stacked body 120 second Conductive film 122 third conductive film 124 fourth conductive film 126 laminated conductive film 128 third etching mask 130A source electrode 130B drain electrode 132 etched semiconductor laminated body 134 coating film 136 laminated semiconductor layer 138 first Semiconductor layer 140A Second semiconductor layer 140B Second semiconductor layer 142A Source region 142B Drain region 144 Passivation layer 146 Fourth etching mask 148 Opening 150A Back gate electrode 150B Pixel electrode 152 Fifth etching mask 200 Electronic book 02 Case 204 Case 206 Display unit 208 Photoelectric conversion device 210 Display unit 212 Photoelectric conversion device 214 Shaft unit 216 Power supply 218 Operation key 220 Speaker 222 Television device 224 Case 226 Display unit 228 Stand 230 Display unit 232 Operation key 234 Remote control Controller 236 Digital photo frame 238 Case 240 Display unit 242 Upper case 244 Lower case 246 Display unit 248 Keyboard 250 External connection port 252 Pointing device 254 Display unit

Claims (7)

For at least a part of a stacked semiconductor film in which an amorphous semiconductor film is provided over a crystalline semiconductor film,
Performing at least a first etch and a second etch,
The first etching is performed while leaving a part of the amorphous semiconductor film,
The second etching has a high etching rate with respect to the amorphous semiconductor film after removing the coating film formed during the first etching on the amorphous semiconductor film, and the crystalline semiconductor film Performed under conditions with low etching rate for
A method for manufacturing a semiconductor device, comprising exposing a part of the crystalline semiconductor film provided in the stacked semiconductor film. Forming an etching mask over at least a first region of the stacked semiconductor film in which the amorphous semiconductor film is provided over the crystalline semiconductor film;
Exposing the crystalline semiconductor film in the second region by at least the first etching and the second etching;
The first etching is performed while leaving a part of the amorphous semiconductor film,
The second etching has a high etching rate with respect to the amorphous semiconductor film after removing the coating film formed during the first etching on the amorphous semiconductor film, and the crystalline semiconductor film A method for manufacturing a semiconductor device, which is performed under a condition where an etching rate with respect to is low. In claim 1 or claim 2,
The first etching is performed with a chlorine-based gas,
The method for manufacturing a semiconductor device, wherein the second etching is performed using a fluorine-based gas and then a gas containing hydrogen. In claim 3,
The chlorine gas is a mixed gas of boron trichloride gas and chlorine gas,
The method for manufacturing a semiconductor device, wherein the fluorine-based gas is nitrogen trifluoride. In claim 3 or claim 4,
A method for manufacturing a semiconductor device, wherein the gas containing hydrogen contains an argon gas. In any one of Claims 1 thru | or 5,
The method for manufacturing a semiconductor device, wherein the crystalline semiconductor film is a microcrystalline semiconductor film. In claim 6,
The microcrystalline semiconductor film is microcrystalline silicon;
A method for manufacturing a semiconductor device, wherein the amorphous semiconductor film is amorphous silicon.

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