JP2012243141A - Information processing device, control method of information processing device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute an error correction of an error occurring caused by a secular change.SOLUTION: An information processing device according to the present invention includes: a storage section comprising a plurality of blocks for storing data and allowing to rewrite data of each of the plurality of blocks; and a processing section periodically executing, for each of the plurality of blocks, an error detection of data stored in the block, when detecting an error, executing the error correction of the detected error, and rewriting for the block of the data after the error correction.

Description

  The present invention relates to an information processing apparatus that stores data, a control method for the information processing apparatus, and a program.

  Information processing apparatuses such as mobile phones and smartphones generally include a CPU (Central Processing Unit) that executes a program and a memory that stores data such as a program executed by the CPU (hereinafter referred to as program data).

  In recent years, information processing apparatuses in which the above-described memory is composed of a RAM (Random Access Memory) and a NAND flash memory are becoming mainstream. In such an information processing apparatus, the CPU is connected to the RAM and the NAND flash memory, reads the program data stored in the NAND flash memory, transfers the read program data to the RAM, and executes the program.

  In general, in NAND flash memory, an error may occur when program data is repeatedly read due to the structure of a memory cell. A phenomenon in which an error occurs due to repeated reading of program data is called a read disturb phenomenon. If there is an error in the program data, the CPU may not be able to execute the program correctly.

  Therefore, generally, in a NAND flash memory, program data and ECC (Error Check and Correction) data for performing error correction of the program data are stored in association with each other.

  FIG. 9 is a diagram showing a general data configuration of the NAND flash memory.

  As shown in FIG. 9, the NAND flash memory has a plurality of blocks in which m pages each composed of an area P for storing program data and an area E for storing ECC data for performing error correction of the program data are collected. . With such a data structure, if there is an error of several bits, error correction can be performed using ECC data stored on the same page as the program data. In the NAND flash memory, data is written in units of pages and stored data is erased in units of blocks. Note that there is an upper limit on the number of bits that can be corrected using ECC data.

  Japanese Patent Laid-Open No. 2008-198310 discloses a program after error correction in which program data is read to execute a program, error of the program data is detected, and error correction is performed when there is an error. An information processing apparatus that rewrites data to a block in which program data is stored is disclosed. Note that rewriting means that program data stored in a block is temporarily saved in another unused block, and the original program data (data after error correction) is deleted after the data stored in the block is erased. Is written to the block. According to this information processing apparatus, it is possible to perform error correction of an error in program data caused by the above-described read disturb phenomenon, and to store refreshed program data having no error in a block.

JP 2008-198310 A

  In the NAND flash memory, in addition to the error due to the read disturb phenomenon described above, an error due to secular change also occurs. In the information processing apparatus disclosed in Patent Document 1, error correction is performed in response to reading of program data. For this reason, program data that is frequently read is also frequently corrected, whereas program data that is not frequently read may not be corrected for a long period of time. If error correction is not performed over a long period of time, errors due to secular change accumulate, exceeding the upper limit of the number of bits that can be corrected using ECC data, and error correction may be performed. There is a risk that it will not be possible.

  An object of the present invention is to provide an information processing apparatus, an information processing apparatus control method, and a program capable of correcting an error caused by aging.

In order to achieve the above object, the information processing apparatus of the present invention provides:
A plurality of blocks for storing data, and a storage unit capable of rewriting data for each of the plurality of blocks;
For each of the plurality of blocks, error detection of the data stored in the block is periodically performed. When an error is detected, error detection of the detected error is performed, and the error-corrected data is re-executed with respect to the block. And a processing unit that performs writing.

In order to achieve the above object, a method for controlling an information processing apparatus of the present invention includes:
A method for controlling an information processing apparatus,
Store data in each of multiple blocks,
For each of the plurality of blocks, error detection of the data stored in the block is periodically performed. When an error is detected, error detection of the detected error is performed, and the error-corrected data is re-executed with respect to the block. Write.

In order to achieve the above object, the program of the present invention
In the information processing device,
A process of storing data in each of a plurality of blocks;
For each of the plurality of blocks, error detection of the data stored in the block is periodically performed. When an error is detected, error detection of the detected error is performed, and the error-corrected data is re-executed with respect to the block. And a process for performing writing.

  According to the present invention, it is possible to perform error correction of errors caused by aging.

It is a block diagram which shows the structure of the information processing apparatus of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the control part shown in FIG. It is a flowchart which shows the operation | movement at the time of the checksum calculation of the control part shown in FIG. FIG. 3 is a diagram showing an example of a configuration of a management table stored in the NAND flash memory shown in FIG. 2. FIG. 3 is a diagram showing an example of a state of a management table stored in the NAND flash memory shown in FIG. 2. It is a flowchart which shows the operation | movement at the time of rewriting of the control part shown in FIG. FIG. 3 is a diagram showing another example of the state of the management table stored in the NAND flash memory shown in FIG. 2. It is a block diagram which shows the structure of the information processing apparatus of the 2nd Embodiment of this invention. It is a figure which shows the data structure of NAND flash memory.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the information processing apparatus 100 according to the first embodiment of this invention. In FIG. 1, a case where the information processing apparatus 100 is a mobile phone will be described as an example. However, the present invention is not limited to this, and the information processing apparatus 100 may be a smartphone, a PDA (Personal Digital Assistants). There are various types such as portable music players, electronic notebooks, personal computers, transceivers, and portable game machines.

  An information processing apparatus 100 illustrated in FIG. 1 includes an antenna 101, a transmission / reception unit 102, a speaker 103, a microphone 104, a display unit 105, an operation unit 106, a control unit 107, and a power supply unit 108.

  The transmission / reception unit 102 transmits / receives radio waves via the antenna 101 under the control of the control unit 107.

  The speaker 103 outputs sound under the control of the control unit 107.

  The microphone 104 collects peripheral sounds and outputs sound data to the control unit 107 under the control of the control unit 107.

  The display unit 105 displays various videos under the control of the control unit 107.

  The operation unit 106 outputs a signal corresponding to a user operation input to the control unit 107. A specific example of the operation unit 106 is a touch panel.

  The control unit 107 executes various programs in accordance with signals output from the operation unit 106, and controls the transmission / reception unit 102, the speaker 103, the microphone 104, the display unit 105, and the like.

  The power supply unit 108 supplies power to each unit described above.

  Next, the internal configuration of the control unit 107 will be described.

  FIG. 2 is a block diagram illustrating a configuration of the control unit 107.

  The control unit 107 illustrated in FIG. 2 includes a NAND flash memory 201, a CPU 202, and a RAM 203. The CPU 202 is an example of a processing unit.

  As shown in FIG. 9, the NAND flash memory 201 is a block in which m pages each composed of an area P for storing program data and an area E for storing ECC data for error correction of the program data are collected. A plurality. The ECC data is calculated when the program data is written, and is written in the area E of the same page as the program data. In general, the capacity of one page is 2112 bytes including the area P and the area E. As an example of a method for performing error correction using ECC data, a method for performing error correction of 1 bit by adding 16-bit ECC data to 512 bytes of program data, or a method of performing error correction of 4 bits. and so on. Program data is written in units of pages, and stored program data is erased in units of blocks. Program data can be rewritten in each block.

  Further, the NAND flash memory 201 stores, for each of a plurality of blocks, a management table in which the block number of the block is associated with the number of error bits of program data stored in the block.

  The CPU 202 reads the program data stored in the NAND flash memory 201, transfers it to the RAM 203, and executes the program.

  Further, the CPU 202 periodically detects an error by calculating a checksum of program data stored in each page included in the block for each of a plurality of blocks constituting the NAND flash memory 201. When an error is detected, error correction is performed using ECC data stored in the same page as the program data, and the data after error correction is rewritten.

  The RAM 203 temporarily stores program data transferred from the CPUP 202.

  Next, the operation of the control unit 107 of this embodiment will be described.

  FIG. 3 is a flowchart showing the operation of the control unit 107 when calculating the checksum.

  In the following, it is assumed that the error correction capability of program data using ECC data is 4 bits.

  The CPU 202 periodically calculates the checksum of the program data stored in the page for each page included in the block for each of the plurality of blocks constituting the NAND flash memory 201 (step S101). In accordance with the calculation result, the number of error bits of the program data is detected, and the detected number of error bits is temporarily stored in the RAM 203.

  When the detection of the number of error bits of the program data stored in all pages included in each block is completed for all the blocks, the CPU 202 calculates the total number of error bits of the program data in each block. The number is stored in the management table in correspondence with the number (step S102).

  FIG. 4 is a diagram illustrating an example of the configuration of the management table 401.

  As shown in FIG. 4, the NAND flash memory 201 stores a management table 401 in which the block number of each block is associated with the number of error bits of program data stored in the block.

  As described above, the CPU 202 periodically calculates the checksum of the program data stored in each block and detects the number of error bits. In the management table 401, in addition to the detection result (latest) of the most recent error bit number, the detection results (+1 to +4) of the past four error bit numbers are stored.

  In FIG. 4, for example, the latest error bit number (when the last checksum is calculated) is 0 for the block with block number M = 0, and the chuck is 1 to 4 times before. It indicates that the number of error bits when the sum is calculated is also zero. Also, for example, the block with the block number M = 100 has the latest number of error bits (when the last checksum is calculated) of 3, and the calculation of the checksum four times before one time. Indicates that the number of error bits is 2.

  Referring to FIG. 3 again, the CPU 202 sets the block number M = 0 (step S103), and the number of error bits stored corresponding to the block number M in the management table 401 shown in FIG. It is then determined whether or not it is 4 bits or more (step S104). Note that the above criterion is an example, and for example, whether or not the latest number of error bits is 4 bits or more may be used as the criterion. In the present embodiment, since the determination criterion is whether or not the number of error bits is 4 or more consecutively 5 times, the management table stores the number of error bits for the past 4 times. The number of error bits stored in the management table may be changed according to the determination criterion.

  When the number of error bits stored corresponding to the block number M is 4 bits or more for 5 consecutive times (step S104: Yes), the CPU 202 sets the block number M to group 1 (step S105). ).

  When the number of error bits stored corresponding to the block number M is not 4 bits or more in succession 5 times (step S104: No), the CPU 202 updates the latest stored bit number corresponding to the block number M. It is determined whether or not the number of error bits is 3 bits or more (step S106).

  When the latest number of error bits stored corresponding to the block number M is 3 bits or more (step S106: Yes), the CPU 202 sets the block number M to group 2 (step S107).

  When the latest error bit number stored corresponding to the block number M is not 3 bits or more (step S106: No), the CPU 202 determines the latest error bit number stored corresponding to the block number M. Is determined to be 2 bits or more (step S108).

  When the latest number of error bits stored corresponding to the block number M is 2 bits or more (step S108: Yes), the CPU 202 sets the block number M to group 3 (step S109).

  When the latest error bit number stored corresponding to the block number M is not 2 bits or more (step S108: No), the CPU 202 determines the latest error bit number stored corresponding to the block number M. Is 1 bit or more (step S110).

  When the latest number of error bits stored corresponding to the block number M is 1 bit or more (step S110: Yes), the CPU 202 sets the block M to group 4 (step S111).

  When the latest number of error bits stored corresponding to the block number M is not 1 bit or more (step S110: No), the CPU 202 does not perform grouping of the block number M, and sets the group number M = M + 1. (Step S112), it is determined whether or not the group number M is larger than the final block number (Step S113).

  If the group number M is not greater than the final block number (step S113: No), the CPU 202 returns to the process of step S104.

  When the group number M is larger than the final block number (step S113: Yes), the CPU 202 stores the group set for each block in the management table 401 in association with each block.

  As described above, in this embodiment, it is assumed that the error correction capability of program data using ECC data is 4 bits. Therefore, if the number of error bits in the program data is 5 bits or more, there is a possibility that error correction cannot be performed. Therefore, the CPU 202 constantly monitors the number of error bits in each block, and performs grouping of the blocks shown in FIG. 3 when a block whose error bit number is 4 bits or more in succession is detected five times. .

  FIG. 5 is a diagram showing the state of the management table 401 after grouping.

  As shown in FIG. 5, the NAND flash memory 201 stores a block number of each block in association with information indicating a group set for the block number. Here, for example, block 1 and block 3 are classified into group 4 according to the flow shown in FIG. Further, since the latest number of bit errors is 2, the block 100 is classified into the group 3 according to the flow shown in FIG. Further, since the number of error bits in the block 101 is 5 or more consecutively 4 bits or more, the block 101 is classified into the group 1 according to the flow shown in FIG. Further, since the latest number of bit errors is 2, the block 102 is classified into the group 3 according to the flow shown in FIG. Further, since the latest number of error bits is 0, block 0 and block 2 are not classified into any group.

  FIG. 6 is a flowchart showing the operation of the control unit 107 during rewriting.

  After the process of step S114 shown in FIG. 3 is completed, the CPU 202 reads the block number and information indicating the group set for the block number stored in the management table 401 (step S201).

  Next, the CPU 202 rearranges the block numbers according to information indicating the set group (step S202). As a result, the CPU 202 assigns each group to the group, for example, group 1 = block number 101, group 2 = block number 100, group 3 = block number 102, group 4 = block number 1, and block number 3. Manage the block number to which it belongs.

  Next, the CPU 202 performs error correction on the program data in which an error is detected for the block to which the block number belongs to group 1, and rewrites the block (step S203). Here, as described above, since a 4-bit bit error is detected in the blocks belonging to group 1, if an error further occurs, the error correction capability using ECC data is exceeded and error correction cannot be performed. . Thus, by rewriting preferentially from the block to which the block number belongs to group 1, it is possible to reduce the possibility that error correction capability using ECC data will be exceeded and error correction cannot be performed.

  When the rewriting for one block is completed, the CPU 202 determines whether or not the rewriting for all the blocks to which the block number belongs to group 1 is completed (step S204).

  If rewriting to all blocks to which the block number belongs to group 1 has not been completed (step S204: No), the processing returns to step S203, and rewriting is performed on the blocks for which rewriting has not ended.

  When rewriting to all blocks to which block numbers belong to group 1 is completed (step S204: Yes), the CPU 202 clears block information stored corresponding to all block numbers belonging to group 1. (Step S205). Note that clearing the block information stored corresponding to the block number indicates that the latest number of error bits stored corresponding to the block number is set to zero. By clearing the block information corresponding to the block number of the block that has been rewritten, for example, when rewriting is resumed after interruption of rewriting described later, the rewriting is performed with reference to the management table 401. No blocks can be identified.

  Next, the CPU 202 determines whether or not there is a rewrite interruption request and it is necessary to interrupt the rewrite (step S206). The rewrite interruption request includes, for example, a request to execute a predetermined program having a high priority via the operation unit 106.

  When it is necessary to interrupt rewriting (step S206: Yes), the CPU 202 ends the process.

  When it is not necessary to interrupt the rewrite (step S206: No), the CPU 202 performs error correction on the program data in which an error is detected for the block to which the block number belongs to group 2, and rewrites the block. This is performed (step S207). Here, as described above, the block to which the block number belongs to group 2 has a larger number of error bits than the block to which the block number belongs to group 3 and group 4, and therefore the block to which the block number belongs to group 3 and group 4 is larger. Needs to be rewritten preferentially.

  When the rewriting for one block is completed, the CPU 202 determines whether or not the rewriting for all the blocks to which the block number belongs to group 2 is completed (step S208).

  If rewriting for all blocks to which the block number belongs to group 2 has not been completed (step S208: No), the process returns to step S207, and rewriting is performed for the block for which rewriting has not been completed.

  When rewriting to all blocks to which the block number belongs to group 2 is completed (step S208: Yes), the CPU 202 clears the block information stored corresponding to all block numbers belonging to group 2. (Step S209).

  Next, the CPU 202 determines whether or not rewriting needs to be interrupted (step S210).

  When it is necessary to interrupt rewriting (step S210: Yes), the CPU 202 ends the process.

  When it is not necessary to interrupt the rewrite (step S210: No), the CPU 202 performs error correction on the program data in which an error is detected for the block to which the block number belongs to group 3, and rewrites the block. This is performed (step S211). Here, as described above, the block whose block number belongs to group 3 has a larger number of error bits than the block whose group number belongs to group 4, and therefore rewrites preferentially over the block whose block number belongs to group 4. Need to do.

  When the rewriting for one block is completed, the CPU 202 determines whether or not the rewriting for all the blocks to which the block number belongs to the group 3 is completed (step S212).

  If rewriting for all blocks to which the block number belongs to group 3 has not been completed (step S212: No), the process returns to step S211 to rewrite the block for which rewriting has not been completed.

  When rewriting to all blocks to which the block number belongs to group 3 is completed (step S212: Yes), the CPU 202 clears the block information stored corresponding to all block numbers belonging to group 3. (Step S213).

  Next, the CPU 202 determines whether or not rewriting needs to be interrupted (step S214).

  When the rewriting needs to be interrupted (step S214: Yes), the CPU 202 ends the process.

  When it is not necessary to interrupt the rewrite (step S214: No), the CPU 202 performs error correction on the program data in which an error is detected for the block to which the block number belongs to group 4, and rewrites the block. This is performed (step S215). Here, as described above, since the block to which the block number belongs to group 4 has a smaller number of error bits than the block to which the block number belongs to group 1 to group 3, and the need for rewriting is low, Rewriting is performed at the end of the blocks to which the block numbers belong to group 4.

  When the rewriting for one block is completed, the CPU 202 determines whether or not the rewriting for all the blocks to which the block number belongs to the group 4 is completed (step S216).

  When rewriting to all blocks to which the block number belongs to group 4 has not been completed (step S216: No), the process returns to step S215, and rewriting is performed on the blocks for which rewriting has not been completed.

  When rewriting to all the blocks to which the block number belongs to group 4 is completed (step S216: Yes), the CPU 202 clears the block information stored corresponding to all the block numbers belonging to group 4. (Step S217), and the process ends.

  FIG. 7 is a diagram showing the state of the management table 401 when the checksum is calculated after rewriting to all the blocks to which the block numbers belonging to the group 4 belong is completed.

  As shown in FIG. 7, the error is not detected in the program data stored in each block by rewriting the block in which the error is detected.

  As described above, according to the information processing apparatus 100 of the present embodiment, for each of a plurality of blocks constituting the NAND flash memory 201, error detection is periodically performed on program data stored in the block, and an error is detected. Error correction is performed, and the program data after error correction is rewritten to the block.

  Since each of a plurality of blocks constituting the NAND flash memory 201 periodically detects and corrects errors in the data stored therein, it is possible to detect and correct errors caused by secular changes.

  Further, according to the information processing apparatus 100 of the present embodiment, the number of error bits is detected for each of a plurality of blocks, and rewriting is performed in order from the block with the largest number of detected error bits. The possibility that an error will occur in program data exceeding the number of bits that can be corrected using ECC data can be reduced.

(Second Embodiment)
FIG. 8 is a block diagram showing the configuration of the information processing apparatus 800 according to the second embodiment of this invention. Note that the present invention relates to how to properly perform error correction of data stored in the information processing apparatus, and therefore, description of configurations not directly related to the present invention is omitted.

  An information processing apparatus 800 illustrated in FIG. 8 includes a storage unit 801 and a processing unit 802.

  The storage unit 801 is a memory capable of storing data and rewriting data. A specific example of the storage unit 801 is a NAND flash memory. The storage unit 801 is composed of a plurality of blocks having a predetermined capacity for storing data, similarly to the general data configuration of the NAND flash memory shown in FIG.

  The processing unit 802 periodically performs error detection on the data stored in each of the plurality of blocks constituting the storage unit 801, performs error correction on the detected error, and performs error correction on the data after error correction. Rewrite the block.

  As described above, according to the present embodiment, the information processing apparatus 800 periodically performs error detection on the data stored in the block for each of the plurality of blocks constituting the storage unit 801, and detects the error of the detected error. Correction is performed, and the data after error correction is rewritten to the block.

  For each of the plurality of blocks, the error of the data stored periodically is detected, so that the error caused by the secular change can be detected and corrected.

  In addition, you may apply the method performed in the information processing apparatus of this invention to the program for making a computer perform. In addition, the program can be stored in a storage medium and can be provided to the outside via a network.

DESCRIPTION OF SYMBOLS 100,800 Information processing apparatus 101 Antenna 102 Transmission / reception part 103 Speaker 104 Microphone 105 Display part 106 Operation part 107 Control part 108 Power supply part 201 NAND flash memory 202 CPU
203 RAM
401 management table 801 storage unit 802 processing unit

Claims (9)

A plurality of blocks for storing data, and a storage unit capable of rewriting data for each of the plurality of blocks;
For each of the plurality of blocks, error detection of the data stored in the block is periodically performed. When an error is detected, error detection of the detected error is performed, and the error-corrected data is re-executed with respect to the block. An information processing apparatus comprising: a processing unit that performs writing. The information processing apparatus according to claim 1,
The processing unit periodically detects the number of errors in data stored in each of the plurality of blocks, and rewrites the blocks in descending order of the detected number of errors. Information processing device. The information processing apparatus according to claim 2,
The processing unit divides the plurality of blocks according to the detected number of errors, and rewrites the blocks belonging to the group in order from the group to which the detected block having the highest number of errors belongs. Information processing apparatus. The information processing apparatus according to claim 3,
When a rewrite interruption request is input when rewriting to the block is performed, the process is interrupted after rewriting is performed on all blocks belonging to the group to which the block belongs. Information processing device. A method for controlling an information processing apparatus,
Store data in each of multiple blocks,
For each of the plurality of blocks, error detection of the data stored in the block is periodically performed. When an error is detected, error detection of the detected error is performed, and the error-corrected data is re-executed with respect to the block. A method for controlling an information processing apparatus, wherein writing is performed. The control method of the information processing apparatus according to claim 5,
Control of the information processing apparatus, wherein for each of the plurality of blocks, the number of errors in data stored in the block is periodically detected, and rewriting is performed in order from the block with the largest number of detected errors Method. The control method of the information processing apparatus according to claim 6,
An information processing apparatus comprising: grouping the plurality of blocks according to the detected number of errors; and rewriting the blocks belonging to the group in order from the group to which the block with the large number of detected errors belongs. Control method. In the control method of the information processing apparatus according to claim 7,
When a rewrite interruption request is input when rewriting to the block is performed, the process is interrupted after rewriting is performed on all blocks belonging to the group to which the block belongs. A method for controlling an information processing apparatus. In the information processing device,
A process of storing data in each of a plurality of blocks;
For each of the plurality of blocks, error detection of the data stored in the block is periodically performed. When an error is detected, error detection of the detected error is performed, and the error-corrected data is re-executed with respect to the block. A program that executes a process of performing writing.

Images