JP2012237930A - Method for manufacturing semiconductor device and method for forming mask pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which is capable of improving exposure characteristics and improving characteristics of the semiconductor device.SOLUTION: A resist line width for correction which is a resist line width having less line width roughness (LWR) is selected in accordance with a correlation between resist line widths (transfer pattern dimensions) of a plurality of photoresist patterns obtained by trial exposure and development processing and the line width roughness, and a mask pattern where a reference mask line width has been corrected on the basis of a difference between a target dimension and the resist line width for correction is formed. The mask pattern is used to perform exposure and development, therefore a semiconductor is manufactured. Thus the line width roughness (LWR) can be reduced and characteristics of the semiconductor device can be improved.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a method for forming a mask pattern, and more particularly to a method for manufacturing a semiconductor device and a method for forming a mask pattern having a data correction step in designing a mask pattern.

  LSI (Large Scale Integration) is photolithography (exposure / exposure) that irradiates a reticle (mask), which is an original plate on which a circuit pattern is drawn, with exposure light, and transfers the circuit pattern onto the surface of a semiconductor wafer (hereinafter referred to as a wafer). Developed) technology.

  In recent years, with the high integration and high speed of LSI, pattern miniaturization is rapidly progressing. As the circuit pattern dimensions become smaller, the mask design becomes more complex. Specifically, when designing a mask, optical proximity effect correction (OPC) or process proximity effect correction (PPC) is performed, and the shape of the circuit pattern to be transferred is desired. It is devised to be a shape.

  Furthermore, as the dimensions of circuit patterns become smaller, strict requirements have been made for photoresist materials to which circuit patterns are transferred. Specifically, improvement in sensitivity characteristics, resolution characteristics, line variation characteristics (LER or LWR), and the like is expected for the photoresist material.

  For example, the following Patent Document 1 describes an OPC processing step for performing optical proximity effect correction assuming a single-layer phase shift mask, a step for determining transmittance after optical proximity effect correction, and a transmittance after determining transmittance. And a mask pattern forming method using an optical proximity effect correction technique for a mask pattern having a plurality of phase shift regions of transmittance, including a step of applying a corresponding mask bias. Thereby, even if the number of correction parameters increases, the time required for the OPC process can be shortened.

JP 2004-85923 A

  The present inventor is engaged in research and development on exposure technology. In particular, improvement of exposure characteristics using EUV light is being studied.

  Specifically, investigations are being made on photoresist materials that can improve sensitivity characteristics, resolution characteristics, line variation characteristics (LER or LWR), and improve these characteristics.

  In particular, among the above characteristics, line variation, that is, line edge variation is an important factor affecting the characteristics of the semiconductor device, and the line variation causes deterioration of the semiconductor device characteristics.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of improving the exposure characteristics and improving the characteristics of the semiconductor device. In particular, an object of the present invention is to provide a semiconductor device manufacturing method capable of improving the characteristics of a semiconductor device by reducing line variations.

  Another object of the present invention is to provide a method for forming a good mask pattern. By using a mask formed by this mask pattern forming method, the characteristics of the semiconductor device can be improved. In particular, a resist pattern with reduced line variation can be formed.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in this application, a method for manufacturing a semiconductor device shown in a typical embodiment includes the following steps (a) and (b). The step (a) is a mask pattern forming step and includes the following steps (a1) to (a6). Step (a1) is a step of preparing a reference design mask having a pattern having a reference mask line width. Step (a2) is a step of performing test exposure and development processing on the test photoresist on the test substrate using the reference design mask. The step (a3) is a step of examining the correlation between the resist line width and the line variation of the plurality of photoresist patterns obtained in the step (a2). Step (a4) is a step of selecting a resist line width for correction, which is a resist line width having a smaller line variation, from the correlation between the resist line width and the line variation. Step (a5) is a step of correcting the reference mask line width based on the difference between the reference resist line width corresponding to the reference mask line width and the correction resist line width. The step (a6) is a step of forming a mask pattern based on the corrected mask line width after the correction in the step (a5). Step (b) is a step of exposing and developing the photoresist formed on the first film on the semiconductor substrate using the mask pattern.

  Among the inventions disclosed in the present application, the mask pattern forming method shown in the representative embodiment includes the following steps (a1) to (a6). Step (a1) is a step of preparing a reference design mask having a pattern having a reference mask line width. Step (a2) is a step of performing test exposure and development processing on the test photoresist on the test substrate using the reference design mask. The step (a3) is a step of examining the correlation between the resist line width and the line variation of the plurality of photoresist patterns obtained in the step (a2). Step (a4) is a step of selecting a resist line width for correction, which is a resist line width having a smaller line variation, from the correlation between the resist line width and the line variation. Step (a5) is a step of correcting the reference mask line width based on the difference between the reference resist line width corresponding to the reference mask line width and the correction resist line width. The step (a6) is a step of forming a mask pattern based on the corrected mask line width after the correction in the step (a5).

  Among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, the characteristics of the semiconductor device can be improved.

  Among the inventions disclosed in the present application, according to the mask pattern forming method shown in the following representative embodiments, a good mask pattern can be formed.

It is a schematic block diagram which shows the scanning EUV exposure apparatus of this Embodiment. It is sectional drawing which shows typically the relationship between the reticle pattern of this Embodiment, and a resist pattern. It is a top view of a reticle pattern. It is a top view of the resist pattern after exposure and development processing. It is a top view for demonstrating LWR. It is a top view for demonstrating LER. It is a graph which shows the relationship between a transfer pattern dimension (nm) and LWR (nm). It is a flowchart of the process of forming a circuit pattern on a semiconductor substrate using the reticle creation process of this Embodiment, and the reticle. It is principal part sectional drawing of the board | substrate which shows the manufacturing process of the semiconductor device of this Embodiment. FIG. 10 is a main-portion cross-sectional view of the substrate, illustrating the manufacturing process of the semiconductor device of the present embodiment, which is subsequent to FIG. 9; FIG. 11 is a main-portion cross-sectional view of the substrate, illustrating the manufacturing process of the semiconductor device of the present embodiment, and is a main-portion cross-sectional view of the substrate illustrating the manufacturing process of the semiconductor device following FIG. 10; FIG. 12 is a main-portion cross-sectional view of the substrate, illustrating the manufacturing process of the semiconductor device according to the present embodiment, which is subsequent to FIG. 11; It is another flowchart of the process of forming a circuit pattern on a semiconductor substrate using the reticle creation process and the reticle of the present embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment and a method for forming a reticle used therefor will be described with reference to the drawings.

  FIG. 1 is a schematic block diagram showing a scanning EUV exposure apparatus of the present embodiment. The EUV exposure apparatus 10A includes an EUV light source 11 that generates an EUV exposure light beam 12, an illumination optical system 13 that includes illumination mirrors 14, 15, and 16, and a projection optical system 37 that includes projection mirrors 31, 32, 33, 34, 35, and 36. , A folding mirror 17, a reticle stage 22 on which a reflective reticle 21 is mounted, a wafer stage 24 on which a semiconductor substrate (wafer) 1 as an object to be exposed is mounted, a chamber 25 which is a space for storing these, and an exhaust in the chamber 25. It comprises a plurality of pumps 26A, 26B, 26C, 26D and the like.

  A multilayer film (not shown) for specularly reflecting the EUV exposure light beam 12 is formed on each surface of the folding mirror 17, reticle 21 and projection mirrors 31 to 36. Although not shown, an EUV resist is applied to the surface of the semiconductor substrate (wafer) 1. The reticle stage 22 and the wafer stage 24 have a mechanism for scanning in synchronization with a speed ratio proportional to the reduction magnification. In the following, the scanning direction in the plane of reticle 21 or semiconductor substrate (wafer) 1 is the Y-axis direction, the direction perpendicular thereto is the X-axis direction, and the direction perpendicular to the plane of reticle 21 or semiconductor substrate (wafer) 1 is Z. Axial direction.

  In general, in a scanning exposure apparatus, a reticle and a wafer are moved in synchronization according to a reduction ratio to perform one-shot exposure (referred to as scan exposure). For example, in the case of 1/4 reduction projection, the reticle is synchronized at a speed four times that of the wafer. As described above, the exposure light beam emitted from the light source is irradiated while scanning on the wafer, and after one shot of exposure is performed, when the exposure light beam stops or does not reach the wafer surface by a shutter or the like, one shot ( This is also called “one scan”. Next, the wafer moves to the initial position of the next exposure shot called a step. Thereafter, exposure (second scan) is performed again by scanning the reticle and wafer. As described above, in the scanning exposure apparatus, almost the entire surface of the wafer is exposed while alternately repeating scanning and steps.

  FIG. 2 is a cross-sectional view schematically showing the relationship between the reticle pattern of this embodiment and a resist pattern (transfer pattern). In general, reduced projection exposure is performed. Here, for ease of explanation, an explanation will be given with an example of equal magnification (1: 1) exposure. Although there is no limitation on the shape of the reticle pattern, a line-shaped reticle pattern will be described as an example here. FIG. 3 is a plan view of a reticle pattern, and FIG. 4 is a plan view of a resist pattern after exposure and development processing. FIG. 5 is a plan view for explaining the LWR, and FIG. 6 is a plan view for explaining the LER.

  As shown in FIG. 2, by irradiating the reticle 21 with EUV light Ea and irradiating the reflected EUV light Ea onto the photoresist film 5 formed on the film (etched film) 3 on the semiconductor substrate 1, A reticle pattern (here, a line pattern arranged with a space) L drawn on the reticle 21 is transferred onto the photoresist film 5. Here, a positive type photoresist is used. In this case, the reflected EUV light Ea is irradiated corresponding to the shape of the space (LS), the photoresist film 5 is denatured and can be melted by the developer. Next, the altered portion 5a in the photoresist film 5 is removed by development processing. Through the above process, the photoresist film 5 remains at a position corresponding to the reticle pattern (line pattern) L. Hereinafter, the remaining photoresist film 5 may be referred to as a resist pattern (transfer pattern).

  As shown in FIGS. 2 and 3, a plurality of line patterns (light absorption portions) L, which are reticle patterns (drawing patterns) drawn on the reticle, have a predetermined space (light reflection portion) LS on the reticle 21. It is placed and placed. The width of the line pattern L is LL, and the sum (pitch) of the line pattern and the space is LP = LL + LS. In general, LL = LS.

  Also, as shown in FIG. 4, the width of the resist pattern 5 is RL, and the width of the space is RS. In the case of the same magnification (1: 1) exposure, it is ideal that LL = RL and LS = RS. However, various corrections are performed in consideration of the exposure characteristics and the photoresist material, and the desired RL and The shapes of the LL and LS of the reticle 21 are designed and corrected so as to be RS.

  Further, in FIG. 4, the resist pattern 5 is schematically shown by a rectangle and the long side thereof is shown by a straight line. However, the resist pattern 5 is uneven at the end (side surface). That is, as shown in FIGS. 5 and 6, the end portion of the resist pattern 5 is not linear but wavy.

  Such variations in the end portions of the resist pattern (transfer pattern) 5 are referred to as “line variations”. Examples of the index indicating the variation include LER and LWR.

  As shown in FIG. 5, LWR (line width roughness) indicates line width variation caused by unevenness, and LER (line edge roughness) indicates unevenness generated on the wall surface of the line pattern as shown in FIG. Indicates the size.

  If the value of such line variations (LER, LWR) is large, the characteristics of the semiconductor device deteriorate. For example, if the LWR of a gate electrode constituting a MISFET (metal insulator semiconductor field effect transistor) is large, the gate length varies. In this case, the on / off ratio of the MISFET is deteriorated, and there is a problem that the threshold voltage varies.

  Next, the considerations (experimental example) of the inventors will be described. FIG. 7 is a graph showing the relationship between the transfer pattern dimension (nm) and LWR (nm). The transfer pattern dimension and LWR are measured by performing exposure using a reticle (first design reticle, test reticle) designed so that the width (RL) of the transfer pattern 5 becomes a predetermined dimension (target dimension). It is a thing. A circle (graph a) indicates a case where the predetermined dimension is 45 nm, and a square mark (graph b) indicates a case where the predetermined dimension (target dimension) is 32 nm.

As described above, when transferring using the reticle (first design reticle, test reticle) designed to have the predetermined dimension (target dimension), if the exposure is performed while increasing the exposure amount as needed, The average width dimension (nm) decreases. This is because the intensity of the reflected EUV light Ea increases and the width of the altered portion 5a increases (see FIG. 2). The exposure amount can be expressed by, for example, exposure intensity × exposure time, and the exposure amount can be changed by changing the exposure time. When the LWR was measured for each transfer pattern having a different width, the transfer pattern (target dimension; the horizontal axis in graph a was less than 45 nm) having a narrower width than a predetermined dimension (45 nm for graph a, 32 nm for graph b). In graph b, a decrease in LWR was confirmed in the region below the horizontal axis of 32 nm. In particular, the minimum value of LWR is shown at point Pa in graph a and at point Pb in graph b. The exposure amount is in the range of 8 J / cm ² of 12 mJ / cm ^2, in increments of 0.5 mJ / cm ^2. As the photoresist material, a PHS (polyhydroxystyrene) -based photoresist, which is a chemically amplified positive resist, was used. The exposure dose at Pa is 10 mJ / cm ² and the exposure dose at Pb is 11.5 mJ / cm ² .

  Thus, it was found that the LWR is reduced in a transfer pattern that is formed with a slightly larger exposure amount than the design exposure amount determined corresponding to the target size and has a size smaller than the target size. In addition to the above PHS photoresists, these tendencies tend to include acrylate material photoresists that are chemically amplified positive resists, fullerene material photoresists that are chemically amplified positive resists, and chemical amplification systems. This was also confirmed when a Noria material type photoresist, which is a positive resist, and a PHS-acrylate hybrid material type photoresist, which is a chemical amplification type positive resist, were used.

[Line variation correction processing]
Therefore, when designing a reticle for device manufacture (correction, fine adjustment), the relationship between the transfer pattern dimension and the LWR is previously investigated for the target photoresist. That is, a test photoresist is applied on a film to be etched on a test semiconductor substrate, and test exposure and development are performed at the same magnification using a reference design reticle having a reticle pattern width (reference mask line width) of LL. Do. Thereby, the relationship between the line width (average line width) of the transfer pattern and the line variation (LER, LWR) is examined. Next, a smaller LWR, preferably a minimum LWR (correction resist line width) is determined from the relationship between the line width of this transfer pattern and the line variation (LER, LWR). Next, a difference α = RL0−RL1 between the target dimension RL0 and the transfer pattern dimension (correction resist line width) RL1 having the minimum LWR is obtained, α is set as a correction value, and the correction value α is set for the reticle pattern. Design the pattern in consideration.

  For example, in the case of the same size (1: 1) exposure, the width of the reticle pattern (line pattern) L of the reticle 21 (reference mask line width, LL) is reduced by α / 2 from both sides to obtain “LL-α”. The width should be Of course, with respect to the width of the reticle pattern (line pattern) L of the reticle 21, other correction values β are considered from various correction data, and for example, the width of the line pattern L may be “LL−α + β”.

  In the case of 1/4 reduction projection exposure, (LL−α) × 4 [nm] is used. In the case of 1 / N reduction projection exposure, (LL−α) × N [nm]. And it is sufficient. Also, the reduction magnification may be set to LL × N− (α + β) × Nc [nm] in consideration of various corrections, flare effects, and MEEF (Mask Error Enhancement Factor). Thus, it goes without saying that other corrections (β, Nc, etc.) other than the correction of the width (LL) are considered separately.

  For example, in the graph a shown in FIG. 7, since RL0 = 45 and RL1 = 37 nm, α = 45−37 = 8 nm. Therefore, in the case of the same magnification (1: 1) exposure, the width of the line pattern L of the reticle 21 may be reduced by 4 nm from both sides to a width of 37 nm. In the case of 1/4 reduction projection exposure, it may be 37 × 4 (nm). Of course, other correction factors such as the correction magnification Nc and the correction value β may be considered. For example, in the case of 1/4 reduction projection exposure, for example, when β = 2 as the correction for reducing the dimension due to the flare effect and Nc = 3.5 as the correction by MEEF, the line width at the reticle is 45 × 4. − (8-2) × 3.5 = 159 nm.

  For example, in the graph b shown in FIG. 7, since RL0 = 32 and RL1 = 29.5 nm, α = 32-29.5 = 2.5 nm. Therefore, in the case of the same magnification (1: 1) exposure, the width of the line pattern L of the reticle 21 may be reduced by 1.25 nm from both sides to be 29.5 nm. In the case of 1/4 reduction projection exposure, it may be 29.5 × 4 (nm). Of course, other correction factors such as the correction magnification Nc and the correction value β may be considered.

  Thus, according to the present embodiment, line variations such as LWR can be reduced. Thereby, the controllability of the transfer pattern shape and the pattern shape of the film to be etched is improved. As a result, the characteristics of the semiconductor device are improved.

  In FIG. 7, LWR is used for the vertical axis, but LER may be used.

[Explanation of flow including reticle design (correction) process]
FIG. 8 is a flowchart of the reticle forming process of the present embodiment and the process of forming a circuit pattern on a semiconductor substrate using the reticle.

  As shown in FIG. 8, design data (CAD data) is prepared in step ST1. For example, necessary data such as a target dimension (for example, 45 nm) is prepared based on a device (semiconductor device) to be manufactured.

  Next, in step ST2, various existing correction processes are performed on the reticle pattern dimension (reference mask line width, eg, LL0) corresponding to the target dimension (reference resist line width, eg, 45 nm) to obtain a correction unit. (Correction grid) is defined. Examples of correction processing include OPC, PPC, flare correction, oblique incidence correction, and azimuth correction. By such OPC or PPC, the line width controllability of a gate electrode (pattern to be etched) G described later can be improved. In particular, in exposure processing using EUV light, flare correction is important in order to reduce the influence of fog exposure called flare. In the exposure processing using EUV light, the difference (oblique incidence correction) between the scanning direction (Y direction) and the arc direction (X direction) when the EUV light is irradiated through the arc-shaped slit, and the arc direction It is necessary to perform correction in consideration of position dependency (azimuth correction). As described above, the controllability of the pattern shape such as the line width of the gate electrode G can be improved by predetermining the correction value depending on the pattern and forming the reticle for manufacturing the device in consideration of the correction.

  Next, in step ST3, line variation correction processing, specifically, the LWR correction processing is performed. That is, the relationship between the transfer pattern dimension and the LWR described above (see FIG. 7) is examined, and the line width (pattern dimension) of the transfer pattern that makes the LWR better, preferably the minimum, and the exposure amount at that time are determined.

  Next, the correction value α is obtained from the difference (RL0−RL1) between the target dimension RL0 and the transfer pattern dimension RL1.

  Next, in step ST4, a reticle (mask) is formed. Specifically, the dimension of the reticle pattern is corrected in consideration of the correction data (for example, Nc, β, α) in steps ST2 and ST3 (for example, LL0 is corrected to LL1). Next, a reticle for device manufacture is formed using the corrected reticle pattern dimension (LL1). That is, a circuit pattern is formed on the reticle using a pattern having the corrected reticle pattern dimension (correction mask line width, LL1). The dimension of the corrected reticle pattern (corrected mask line width, LL1) is smaller than the original reticle pattern dimension (reference mask line width, eg, LL0) (LL1 <LL0).

  The reticle can be formed using, for example, a drawing device (image device). Hereinafter, an example of the reticle forming process will be described. For example, a low thermal expansion glass (LTME) substrate is used as a base material (substrate), and a multilayer film made of a Mo / Si multilayer film is formed thereon. Next, for example, a TaN film is deposited as a light shielding film on the multilayer film. Next, a photoresist film is formed on the TaN film. Note that after a hard mask is formed on the TaN film, a photoresist film may be formed thereon.

  Next, the substrate is transported into the drawing apparatus, and a desired circuit pattern is drawn on the photoresist film while scanning the electron beam. After the electron beam irradiation (exposure), the photoresist film is developed. A reticle is formed by etching the underlying TaN film using this transfer pattern as a mask. When a hard mask is used, the hard mask is etched using the resist pattern as a mask, and further, the underlying TaN film is etched using the hard mask as a mask.

  Next, a semiconductor device is fabricated using the reticle fabricated in step ST4 (hereinafter, this reticle is denoted by 21c). 9 to 12 are cross-sectional views of the main part of the substrate showing the manufacturing steps of the semiconductor device of the present embodiment. Here, a case where a MISFET is manufactured as a semiconductor device will be described as an example.

  As shown in step ST5 of FIG. 8 and FIG. 9, a semiconductor substrate (substrate, wafer) 301 having a conductive film (first film) 305 deposited via a gate insulating film 303 is prepared. A photoresist film (photosensitive insulating film) R is formed on the entire surface of the semiconductor substrate 301. Note that the photoresist film R may be formed after the organic base film is formed over the conductive film 305. Furthermore, a multilayer structure film in which a silicon-based oxide hard mask / spin-on-carbon film (SOC) / SiN-based hard mask is stacked between the conductive film 305 and the organic base film may be formed.

  Next, as shown in FIG. 10, the photoresist film R is exposed using the reticle 21c manufactured in step ST4, that is, the reticle 21c drawn with the corrected line width. Specifically, the reticle 21c is irradiated with EUV light Ea, and the circuit pattern Lc drawn on the reticle 21c is transferred to the photoresist film R by the reflected EUV light. At this time, the exposure amount (exposure condition) by the EUV light Ea is the exposure amount when the pattern dimension of the point where the selected LWR becomes better, preferably the smallest, is formed in step ST3. For example, in FIG. 7 described above, when the target size is 45 nm, the exposure amount at the point Pa is used, and when the target size is 32 nm, the exposure amount at the point Pb.

  Next, as shown in FIG. 11, the altered portion Ra in the photoresist film R is removed by development processing, thereby forming a resist pattern (R). At this time, as shown in step ST6 of FIG. 8, the line width and other dimensions and LWR of the resist pattern (R) may be measured. If the measurement result is out of the allowable range based on the measurement result, the process returns to step ST3 via the route R11. In other words, the measurement result may be fed back to step ST3. Thus, further correction such as fine adjustment of the line width of the reticle pattern is performed. Although not shown, the measurement result may be fed back to step ST2 for further correction.

  When the measurement result is within an allowable range, as shown in step ST7 and FIG. 12, the lower conductive film is etched using the resist pattern (R) as a mask, for example, a gate electrode (Pattern) G is formed. Thereafter, the resist pattern (R) is removed by ashing or the like. Thereafter, impurity ions are implanted into the semiconductor substrate on both sides of the gate electrode G, thereby forming source and drain regions 307.

  Next, as shown in step ST8 of FIG. 8, dimensions such as the line width of the gate electrode (pattern) G may be measured. If this measurement result is out of the allowable range, it is fed back to step ST2 via route R12. As a result, the reticle pattern is further corrected to form a corrected reticle for device manufacture. Although not shown, the measurement result may be fed back to step ST3. Whether or not it is within the allowable range is verified as follows, for example. The average of the line width of the gate electrode (pattern) G is taken, and the determination is made based on whether the average is within ± “twice the correction grid”. The reason why the line is doubled is that the line has both ends and the line width changes by twice the correction grid.

  Although the so-called MISFET formation process has been described above as an example, it goes without saying that the flow shown in FIG. 8 can be applied when forming various circuit patterns constituting the semiconductor device.

  In the above flow, the circuit pattern is drawn on the reticle 21c. However, the reticle 21c may be a test reticle in the same manner as the reticle 21, and a simple line pattern may be drawn. In this case, all the corrections are considered after the desired resist pattern dimension or the dimension of the film to be etched (pattern) is within the allowable range due to the feedback by the flow routes R11 and R12 shown in FIG. A circuit pattern may be formed as a correction reticle for device manufacture.

  In FIG. 8, after performing various correction processes (step ST2), the line variation correction process (step ST3) is performed. However, the order may be reversed. FIG. 13 is a flowchart showing another reticle creation process of the present embodiment.

  As shown in FIG. 13, after preparing design data in step ST1, line variation correction processing is performed in step ST3. That is, the relationship between the line width of the transfer pattern and the LWR (see FIG. 7) described above is examined, and the line width (pattern dimension) of the transfer pattern that makes the LWR better, preferably the minimum, and the exposure amount at that time are determined. To do. Next, in step ST2, various correction processes such as OPC, flare correction, oblique incidence correction, and azimuth correction are performed.

  The subsequent steps ST4 to ST8 and the feedback route (R11, R12, etc.) are the same as the flow shown in FIG.

  As described above, according to the flow in FIG. 13, various corrections in step ST2 can be performed based on the exposure amount determined in step ST3. In addition to the effects of the flow in FIG. be able to.

  As described above in detail, according to the flow shown in FIG. 8, line variations such as LWR can be reduced. In addition, a reticle can be formed based on various corrections. Thereby, the controllability of the resist pattern shape corresponding to the circuit pattern and the pattern shape of the film to be etched is improved, and the characteristics of the semiconductor device are improved. For example, the LWR of the gate electrode constituting the MISFET is reduced, and the variation in gate length is reduced. As a result, the on / off characteristics of the MISFET are improved. In addition, the controllability of the threshold voltage of the MISFET is improved. Thus, the characteristics and reliability of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved. In addition, the throughput of the semiconductor device can be shortened and the manufacturing cost can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In particular, in the present embodiment, exposure is performed using EUV light. However, KrF excimer laser (248 nm), ArF excimer laser (193 nm) is used for ultraviolet rays such as g-line (436 nm) and i-line (365 nm). An exposure technique using as an exposure source may be used. An exposure technique using an electron beam (EB) as an exposure source may be used. However, EUV light is 1/10 or less of the wavelength of ArF, and a very fine pattern forming method is possible. For example, among the photoresists used in the above embodiments, a PHS-based photoresist and a PHS-acrylate hybrid material-based photoresist can be applied to an exposure process using a KrF excimer laser as an exposure source. The acrylate material-based photoresist can be applied to an exposure process using an ArF excimer laser as an exposure source. The fullerene material-based photoresist and the noria material-based photoresist can be applied to an exposure process using an electron beam as an exposure source.

  The present invention relates to a method for manufacturing a semiconductor device and a method for forming a mask pattern, and more particularly to a method for manufacturing a semiconductor device and a method for forming a mask pattern having a data correction step in designing a mask pattern.

1 Semiconductor substrate 5 Photoresist film (resist pattern, transfer pattern)
5a Altered part 10A EUV exposure apparatus 11 EUV light source 12 EUV exposure beam 13 Illumination optical system 14 Illumination mirror 17 Folding mirror 21 Reticle 21c Reticle 22 Reticle stage 24 Wafer stage 25 Chamber 26A Pump 31-36 Projection mirror 37 Projection optical system 301 Semiconductor substrate 303 Gate insulating film 305 Conductive film 307 Source / drain region Ea EUV light (reflected EUV light)
G Gate electrode L Reticle pattern (line pattern)
Lc Circuit pattern R Photoresist film R11 Route R12 Route Ra Altered portions ST1 to ST8 Step

Claims (20)

(A) a mask pattern forming step,
(A1) preparing a reference design mask having a pattern of a reference mask line width;
(A2) performing a test exposure and a development process on the test photoresist on the test substrate using the reference design mask;
(A3) examining the correlation between the resist line width and line variation of the plurality of photoresist patterns obtained by the step (a2);
(A4) selecting a correction resist line width that is a resist line width having a smaller line variation from the correlation between the resist line width and the line variation;
(A5) correcting the reference mask line width based on a difference between a reference resist line width corresponding to the reference mask line width and the correction resist line width;
(A6) forming a mask pattern based on the corrected mask line width after the correction in the step (a5), and a mask pattern forming step having
(B) exposing and developing a photoresist formed on the first film on the semiconductor substrate using the mask pattern;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the line variation is LWR or LER.   In the step (a2), the plurality of regions of the test photoresist are exposed to a plurality of times while changing the exposure amount using the reference design mask, and then developed, whereby the plurality of photo resists are developed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is a step of forming a resist pattern.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the correction resist line width is a minimum value of a graph showing a correlation between the resist line width and line variation. The first photoresist pattern of the plurality of photoresist patterns is exposed with a first exposure amount,
The second photoresist pattern of the plurality of photoresist patterns is exposed at a second exposure amount larger than the first exposure amount,
The resist line width of the second photoresist pattern is smaller than the resist line width of the first photoresist pattern,
The resist line width of the second photoresist pattern is the correction resist line width,
4. The method of manufacturing a semiconductor device according to claim 3, wherein the correction mask line width is smaller than the reference mask line width.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the exposure in the step (b) is performed with the second exposure amount.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the test photoresist and the photoresist in the step (b) are made of a positive photoresist material.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the test exposure in the step (a2) and the exposure in the step (b) are exposures for irradiating EUV light.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the test exposure in the step (a2) and the exposure in the step (b) are exposures by irradiating ultraviolet rays, a KrF laser, or an ArF laser.   2. The method of manufacturing a semiconductor device according to claim 1, wherein correction data obtained by correction processing other than the correction in the step (a5) is added to the reference mask line width.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the correction processing is OPC correction, flare correction, oblique incidence correction, or azimuth correction.   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step (a5), the reference mask line width is corrected based on a correction value of another correction process in addition to the correction based on the difference. .   13. The method of manufacturing a semiconductor device according to claim 12, wherein the other correction processing is OPC correction, flare correction, oblique incidence correction, or azimuth correction. After the step (b),
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching the first film using the photoresist developed in the step (b) as a mask. (A) a mask pattern forming step,
(A1) preparing a reference design mask having a pattern of a reference mask line width;
(A2) performing a test exposure and a development process on the test photoresist on the test substrate using the reference design mask;
(A3) examining the correlation between the resist line width and line variation of the plurality of photoresist patterns obtained by the step (a2);
(A4) selecting a correction resist line width that is a resist line width having a smaller line variation from the correlation between the resist line width and the line variation;
(A5) correcting the reference mask line width based on a difference between a reference resist line width corresponding to the reference mask line width and the correction resist line width;
(A6) forming a mask pattern based on the corrected mask line width after the correction in the step (a5), and a mask pattern forming step having
A mask pattern forming method characterized by comprising:   16. The method of forming a mask pattern according to claim 15, wherein the line variation is LWR or LER.   In the step (a2), the plurality of regions of the test photoresist are exposed to a plurality of times while changing the exposure amount using the reference design mask, and then developed, whereby the plurality of photo resists are developed. 16. The method of forming a mask pattern according to claim 15, which is a step of forming a resist pattern.   16. The mask pattern forming method according to claim 15, wherein the correction resist line width is a minimum value of a graph showing a correlation between the resist line width and line variation. The first photoresist pattern of the plurality of photoresist patterns is exposed with a first exposure amount,
The second photoresist pattern of the plurality of photoresist patterns is exposed at a second exposure amount larger than the first exposure amount,
The resist line width of the second photoresist pattern is smaller than the resist line width of the first photoresist pattern,
The resist line width of the second photoresist pattern is the correction resist line width,
18. The mask pattern forming method according to claim 17, wherein the correction mask line width is smaller than the reference mask line width.   16. The mask pattern forming method according to claim 15, wherein the mask pattern has a region where lines and spaces are repeatedly arranged, and the width of the lines is smaller than the width of the spaces.

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