JP2012230488A - Information processing device, scheduling method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To normally operate software which operates under a one-CPU environment and includes a sequence dependent on task priority in a multi-processor type information processing device.SOLUTION: An information processing device comprises: plural processors; and a scheduler that, when a specific task comes into an execution state in any of the plural processors, brings all the other tasks having priority lower than that of the specific task into an execution standby state until completion of processing of the specific task.

Description

  The present invention relates to an information processing apparatus, a scheduling method, and a program.

  In recent years, some software that operates in a real-time OS (Operating System) includes a sequence that operates in a 1 CPU (Central Processing Unit) environment and that depends on task priority.

  Here, with reference to FIG. 4, an operation when a single processor type information processing apparatus equipped with one CPU executes software including a sequence depending on task priority, which operates in a 1 CPU environment. explain.

  In FIG. 4, it is assumed that the program includes two tasks, task A and task B. Here, it is assumed that task A is a task that is executed by sharing time with other tasks and has a low priority, and task B is a task that is executed in real time and has a high priority.

  As shown in FIG. 4, it is assumed that task A having a low priority is in an execution state on the CPU (step C1), and task A wakes up task B having a high priority in this state (step C1). C2).

  In this case, the CPU is assigned to the task B having a higher priority, and the task B enters an execution state on the CPU (step C3). As a result, task A enters an execution waiting state.

  Thereafter, when the processing of task B is completed and task B enters the execution waiting state (step C4), the CPU is assigned to task A that has been in the execution waiting state, and task A enters the execution state on the CPU (step C5). ).

  In this way, in a single processor type information processing apparatus, when executing software having a structure depending on the priority of a task that operates in a 1 CPU environment, while task B having a high priority is in an execution state, The CPU is not assigned to the task A having a low priority, and the task A is always in an execution waiting state.

  However, in the case of an information processing apparatus that downloads and uses software, the usage environment of the information processing apparatus assumed by the software developer does not necessarily match the actual usage environment of the information processing apparatus.

  For this reason, in a multiprocessor type information processing apparatus equipped with a plurality of CPUs, there is a case where software including a sequence depending on the priority of a task that operates in a 1 CPU environment is executed. The operation in this case will be described with reference to FIG.

  In FIG. 5, the program includes two tasks, task A and task B, similar to those in FIG. 4, and the information processing apparatus is provided with two CPUs, CPU # 1 and CPU # 2. It shall be.

  As shown in FIG. 5, it is assumed that task A having a low priority is in an execution state on CPU # 1 (step D1), and task A wakes up task B having a high priority in this state (step D2). ).

  In this case, since CPU # 2 different from CPU # 1 is in an empty state, that CPU # 2 is assigned to task B having a higher priority, and task B enters an execution state on CPU # 2 (step D3). . Therefore, task A remains in the running state on CPU # 1.

  As described above, in the multiprocessor type information processing apparatus, when the software including the sequence depending on the priority of the task that operates in the 1 CPU environment is executed, the task B having a high priority is in the execution state. However, the CPU may be assigned to task A having a low priority, and task A may be executed.

  Then, the sequence depending on the task priority described above does not become the expected sequence, and the software cannot be operated normally.

  Other examples of the multiprocessor type information processing apparatus that executes software including a sequence depending on the priority of a task (or process) are described in Patent Documents 1 and 2.

  In the multiprocessor type information processing apparatus described in Patent Document 1, if the CPU is a LAST CPU, the CPU has a lower priority than the process in the execution waiting state on the CPU. If it is, the process is switched to a process waiting for execution. Therefore, a process with a low priority that is in an execution state on a CPU that is not a LAST CPU may be executed while a process with a high priority is in the execution state.

  Further, in the multiprocessor type information processing apparatus described in Patent Document 2, a task that is in the execution waiting state has a priority of a task that has the lowest priority and is in the execution waiting state among a plurality of CPUs. CPUs performing tasks equivalent to or less than are assigned. Therefore, tasks other than the task with the lowest priority among the tasks with the lower priority in the execution state on the CPU may be executed while the task with the higher priority is in the execution state.

Japanese Patent Laid-Open No. 62-115567 Japanese Patent Laid-Open No. 3-087935

  As described above, in a related multiprocessor type information processing apparatus, when executing software including a sequence that depends on the priority of a task that operates in a 1 CPU environment, a task with a high priority is in an execution state. For some time, tasks with low priority were executed, and there was a problem that software could not operate normally.

  Therefore, an object of the present invention is to provide an information processing apparatus, a scheduling method, and a program that can solve the above-described problems.

The first information processing apparatus of the present invention
Multiple processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task are in an execution wait state until the processing of the specific task ends. And a scheduler.

The second information processing apparatus of the present invention
Multiple processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task among tasks belonging to the same task group as the specific task, And a scheduler that waits for execution until the processing of the specific task is completed.

The first scheduling method of the present invention includes:
A scheduling method performed by an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task are in an execution wait state until the processing of the specific task ends. To.

The second scheduling method of the present invention includes:
A scheduling method performed by an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task among tasks belonging to the same task group as the specific task, Until the processing of the specific task is completed, it is put in a waiting state.

The first program of the present invention is:
In an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task are in an execution wait state until the processing of the specific task ends. To execute the procedure.

The second program of the present invention is:
In an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task among tasks belonging to the same task group as the specific task, The process of waiting for execution is executed until the processing of the specific task is completed.

  According to the present invention, even in a multiprocessor type information processing apparatus, it is possible to normally operate software including a sequence depending on task priority, which operates under a 1 CPU environment.

It is a block diagram which shows the structure of the information processing apparatus of the 1st and 2nd embodiment of this invention. It is a sequence diagram explaining operation | movement of the information processing apparatus of the 1st Embodiment of this invention. It is a sequence diagram explaining operation | movement of the information processing apparatus of the 2nd Embodiment of this invention. FIG. 11 is a sequence diagram illustrating an operation of a related single processor type information processing apparatus. FIG. 11 is a sequence diagram illustrating an operation of a related multiprocessor type information processing apparatus.

EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.
(1) 1st Embodiment First, the structure of the information processing apparatus of this embodiment is demonstrated with reference to FIG.

  As shown in FIG. 1, the information processing apparatus of this embodiment is a multiprocessor type information processing apparatus having a plurality of CPUs (# 1 to #n) 10-1 to 10-n and a processor control unit 20. It is.

  The CPUs (# 1 to #n) 10-1 to 10-n are processors that execute tasks.

  The processor control unit 20 executes the OS 30 and the scheduler 40 on the OS 30.

  The scheduler 40 performs scheduling for assigning tasks to the CPUs (# 1 to #n) 10-1 to 10-n.

  At this time, when a specific task is in an execution state in any of the CPUs (# 1 to #n) 10-1 to 10-n, the scheduler 40 has all other lower priority than the specific task. The task is forcibly put into a waiting state until the processing of the specific task is completed.

  Here, the specific task refers to a task having a high priority, such as a task executed in real time.

  Hereinafter, the operation of the information processing apparatus of the present embodiment will be described with reference to FIG.

  In FIG. 2, the program includes two tasks, task A and task B, similar to those in FIG. 4, and the information processing apparatus includes CPU (# 1) 10-1 and CPU (# 2) 10. It is assumed that two CPUs -2 are provided.

  As shown in FIG. 2, task A having a low priority is in an execution state on CPU # 1 (10-1) (step A1). In this state, task A wakes up task B having a high priority. Assume that an instruction is issued (step A2).

  In this case, since the CPU # 2 (10-2) is in an empty state, the scheduler 40 assigns the CPU # 2 (10-2) to the task B and wakes up the task B on the CPU # 2 (10-2). (Step A3). As a result, the task B enters an execution state on the CPU # 2 (10-2) (step A4).

  Further, since the task B is a task with high priority, the scheduler 40 forcibly places the task A in the execution state on the CPU # 1 (10-1) into the execution waiting state (step A5).

  Thereafter, when the processing of task B is completed and task B enters the execution waiting state (step A6), scheduler 40 assigns CPU # 1 (10-1) to task A that has been forcibly waiting for execution, and CPU Task A is woken up on # 1 (10-1) (step A7). As a result, task A enters the execution state on CPU # 1 (10-1) (step A8).

  As described above, in the present embodiment, the scheduler 40 identifies the specific task having a high priority in any one of the CPUs (# 1 to #n) 10-1 to 10-n. All other tasks having a lower priority than the current task are forcibly placed in a waiting state until the processing of the specific task is completed.

  Therefore, for example, in the example of FIG. 2, when the task B having a higher priority enters the execution state, the scheduler 40 changes the task A having a lower priority than the task B until the processing of the task B ends. Force to wait for execution.

  Therefore, since a task with a low priority is not executed while a task with a high priority is in an execution state, the software includes a sequence depending on the priority of the task that operates in a 1 CPU environment. However, the effect of being able to operate normally is obtained.

In the example of FIG. 2, when a task B having a high priority is woken up, there is a free CPU, but depending on the number of CPUs and the number of tasks, there is no free CPU. There is also. In that case, task A, which has a lower priority than task B, is forcibly placed in a waiting state, a free CPU is created, the free CPU is assigned to task B, and task B is woken up. It ’s fine.
(2) Second Embodiment In the above-described first embodiment, when a specific task having a high priority is in an execution state, all other tasks are forcibly placed in an execution wait state.

  However, the tasks are classified into task sets (hereinafter referred to as task groups) according to the task type and the like, and while a specific task is in an execution state, it is assigned to a task group different from the specific task. There are cases where there is no problem even if the task to which it belongs is executed.

  Therefore, in the present embodiment, the scheduler 40 has the same task as the specific task when the specific task is in the execution state in any of the CPUs (# 1 to #n) 10-1 to 10-n. Of the tasks belonging to the group, all other tasks having a lower priority than the specific task are forcibly put into an execution waiting state until the processing of the specific task is completed.

  The present embodiment differs from the first embodiment in the above-described operation of the scheduler 40, and the configuration itself is the same as that of the first embodiment.

  Hereinafter, the operation of the information processing apparatus of the present embodiment will be described with reference to FIG.

  In FIG. 3, the program includes three tasks, task A, task B, and task C. Tasks A and B belong to task group α, and task C belongs to task group β. Here, it is assumed that the tasks A and C are tasks that are executed by time sharing with other tasks and have a low priority, and the task B is a task that is executed in real time and has a high priority. Further, it is assumed that the information processing apparatus includes two CPUs, CPU (# 1) 10-1 and CPU (# 2) 10-2.

  As shown in FIG. 3, task C belonging to task group β and having a low priority is in an execution state on CPU # 1 (10-1) (step B1). In this state, task C is assigned to task group α. It is assumed that an instruction to wake up task A having a low belonging priority is issued (step B2).

  In this case, since the CPU # 2 (10-2) is in an empty state, the scheduler 40 assigns the CPU # 2 (10-2) to the task A and wakes up the task A on the CPU # 2 (10-2). (Step B3). As a result, the task A enters the execution state on the CPU # 2 (10-2) (step B4). At this time, the task C remains in the execution state on the CPU # 1 (10-1).

  Here, it is assumed that the task A in the execution state on the CPU # 2 (10-2) issues an instruction to wake up the task B having a high priority (step B5).

  In this case, task B is a task with a high priority, and tasks A and B belong to the same task group α. Therefore, when task B enters an execution state, task A must be forcibly put into an execution wait state. . However, there is no free CPU at this time.

  Therefore, the scheduler 40 forcibly places the task A in the execution state on the CPU # 2 (10-2) into the execution waiting state (step B6), and then assigns the CPU # 2 (10-2) to the task B. Allocate and wake up task B on CPU # 2 (10-2) (step B7). As a result, task B enters the execution state on CPU # 2 (10-2) (step B8). At this time, the task C remains in the execution state on the CPU # 1 (10-1).

  Thereafter, when the processing of task B is completed and task B enters a state of waiting for execution (step B9), scheduler 40 assigns CPU # 2 (10-2) to task A forcibly waiting for execution, and CPU Task A is woken up on # 2 (10-2) (step B10). As a result, task A enters the execution state on CPU # 2 (10-2) (step B11).

  As described above, in the present embodiment, the scheduler 40 identifies the specific task having a high priority in any one of the CPUs (# 1 to #n) 10-1 to 10-n. All other tasks having a lower priority than the specific task among the tasks belonging to the same task group as the current task are forcibly placed in a waiting state until the processing of the specific task is completed.

  Therefore, for example, in the example of FIG. 3, when the task B having a higher priority is in an execution state, the scheduler 40 belongs only to the task A that belongs to the same task group as the task B and has a lower priority than the task B. Until the processing of task B is completed, the task is forcibly put in a waiting state.

  Therefore, while a task with a high priority is in an execution state, a task with a low priority belonging to the same task group as that task is not executed. Even software including a dependent sequence can be operated normally.

  In the example of FIG. 3, when a task B having a high priority is woken up, there is no free CPU, but there is a free CPU depending on the number of CPUs and the number of tasks. In some cases. In this case, task B may be woken up on a free CPU, and then task A having a lower priority than task B may be forcibly placed in an execution wait state.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  For example, in the above embodiment, the processor control unit 20 executes the OS 30 and the scheduler 40. However, the OS 30 and the scheduler 40 are executed by any of the CPUs (# 1 to #n) 10-1 to 10-n. May be executed.

  Moreover, although the example in the case where the number of CPUs is two was given in the said embodiment, the number of CPUs is not limited to this.

  The present invention is also applicable to multiprocessor information processing apparatuses such as mobile phones, smartphones, game machines, tablet PCs (Personal Computers), and notebook PCs.

  The method performed by the information processing apparatus of the present invention may be applied to a program for causing a computer to execute. In addition, the program can be stored in a storage medium and can be provided to the outside via a network.

10-1 to 10-n CPU
20 processor control unit 30 OS
40 scheduler

Claims (8)

Multiple processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task are in an execution wait state until the processing of the specific task ends. An information processing apparatus. Multiple processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task among tasks belonging to the same task group as the specific task, An information processing apparatus comprising: a scheduler that waits for execution until the processing of the specific task is completed.   The information processing apparatus according to claim 1, wherein the specific task is a task executed in real time. A scheduling method performed by an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task are in an execution wait state until the processing of the specific task ends. A scheduling method. A scheduling method performed by an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task among tasks belonging to the same task group as the specific task, A scheduling method for waiting for execution until the processing of the specific task is completed.   The scheduling method according to claim 4, wherein the specific task is a task executed in real time. In an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task are in an execution wait state until the processing of the specific task ends. Program to execute the procedure to make. In an information processing apparatus having a plurality of processors,
When a specific task is in an execution state in any of the plurality of processors, all other tasks having a lower priority than the specific task among tasks belonging to the same task group as the specific task, A program for executing a procedure of waiting for execution until the processing of the specific task is completed.

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