JP2012226558A - Semiconductor integrated circuit device and load current stabilization circuit - Google Patents

Abstract

Power supply voltage fluctuation is suppressed and a power supply voltage fluctuation margin necessary for circuit operation is compressed.
A load current stabilization circuit (115/215) includes a dummy load circuit (142/242), a dummy clock generation circuit (120/220), and a dummy driver circuit (152/252). The dummy load circuit (142/242) simulates the load circuit (141/241) driven by the load driver circuit (151/251) based on the variable frequency first clock signal (TCLK). The dummy clock generation circuit (120/220) generates a dummy clock signal (DCLK) for driving the dummy load circuit (142/242). The dummy driver circuit (152/252) is supplied with power from a regulator (110/210) that supplies power to the load driver circuit (151/251). Based on the dummy clock signal (DCLK), the dummy driver circuit (142/252) is supplied. 242) is driven.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device incorporating a regulator and a load current stabilizing circuit.

  A regulator used in a circuit that is sensitive to fluctuations in power supply voltage, such as a flash macro circuit, needs to set a power supply voltage fluctuation margin in consideration of the influence on the output voltage that appears when the operating frequency fluctuates. By suppressing fluctuations in the regulator output voltage when the operating frequency fluctuates, there are significant effects in reducing circuit area and improving performance and reliability.

  For example, Japanese Patent Application Laid-Open No. 2006-343935 discloses a voltage stabilization circuit for a power supply wiring that stabilizes the voltage of a power supply wiring connected to a circuit whose current consumption is not constant over time. The voltage stabilization circuit for the power supply wiring includes a current compensation circuit having a current consumption capability equivalent to that of the original circuit, and a control circuit for enabling the current compensation circuit during a period in which the original circuit is in a stopped state. When the original circuit connected to the power supply wiring transitions between the stopped state and the operating state, the current compensation circuit is connected to the power supply wiring in parallel with the original circuit. During the period when the original circuit is in the stopped state, the current compensation circuit receives power from the power supply wiring and consumes the same current as the original circuit in place of the original circuit. The amount of current flowing through the power supply wiring in a certain period is made the same as the amount of current in the period in which the original circuit is in an operating state. That is, while the original circuit is in a stopped state, the current compensation circuit consumes the same power supply current as the original circuit instead of the original circuit, thereby stabilizing the voltage of the power supply wiring. However, this voltage stabilization circuit can suppress fluctuations in the output voltage only when transitioning between two states of a stopped state and an operating state.

JP 2006-343935 A

  The present invention provides a load current stabilization circuit that suppresses fluctuations in power supply voltage and compresses a power supply voltage fluctuation margin necessary for circuit operation.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the “DETAILED DESCRIPTION”. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In view of the present invention, the load current stabilization circuit (115/215) includes a dummy load circuit (142/242), a dummy clock generation circuit (120/220), and a dummy driver circuit (152/252). To do. The dummy load circuit (142/242) simulates the load circuit (141/241) driven by the load driver circuit (151/251) based on the variable frequency first clock signal (TCLK). The dummy clock generation circuit (120/220) generates a dummy clock signal (DCLK) for driving the dummy load circuit (142/242). The dummy driver circuit (152/252) is supplied with power from a regulator (110/210) that supplies power to the load driver circuit (151/251). Based on the dummy clock signal (DCLK), the dummy driver circuit (142/252) is supplied. 242) is driven.

  In another aspect of the present invention, a semiconductor integrated circuit device includes the load current stabilization circuit (115/215) and a regulator (110/210). The regulator (110/210) supplies power to the dummy driver circuit (152/252) and the load driver circuit (151/251) of the load current stabilization circuit (115/215).

  According to the present invention, it is possible to provide a load current stabilization circuit that suppresses fluctuations in power supply voltage and compresses a power supply voltage fluctuation margin necessary for circuit operation.

FIG. 1 is a diagram showing a configuration of the semiconductor integrated circuit device according to the first embodiment. FIG. 2 is a block diagram showing a configuration of a peripheral portion of the regulator according to the first embodiment. FIG. 3 is a block diagram showing a configuration of the dummy clock generation circuit according to the first embodiment. FIG. 4 is a timing chart for explaining the operation of the load current stabilization circuit according to the first embodiment. FIG. 5 is a diagram for explaining the relationship between the load current and the output voltage. FIG. 6 is a diagram showing a configuration of the semiconductor integrated circuit device according to the second embodiment. FIG. 7 is a block diagram showing a configuration of a peripheral portion of the regulator according to the second embodiment. FIG. 8 is a block diagram showing a configuration of a dummy clock generation circuit according to the second embodiment. FIG. 9 is a timing chart for explaining the operation of the load current stabilization circuit according to the second embodiment.

  DESCRIPTION OF EMBODIMENTS Embodiments for carrying out the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 shows the configuration of a semiconductor integrated circuit device according to the first embodiment of the present invention. The semiconductor integrated circuit device includes a CPU 190, a flash memory unit 100, and an oscillator 170. The flash memory unit 100 includes a regulator 110 that generates a power supply voltage used internally, and operates based on a clock signal TCLK supplied from an oscillator 170. The CPU 190 executes a program based on the clock signal TCLK supplied from the oscillator 170 and accesses the flash memory unit 100. The oscillator 170 supplies a clock signal TCLK to the CPU 190 and the flash memory unit 100. In addition, the CPU 190 changes the oscillation frequency of the oscillator 170 according to the operation status.

  FIG. 2 is a block diagram showing a peripheral configuration of the regulator 110 built in the flash memory unit 100. The flash memory unit 100 includes a load circuit 141, a driver circuit 151, and a load current stabilization circuit 115 around the regulator 110. The load current stabilization circuit 115 includes a dummy clock generation circuit 120, a dummy load circuit 142, a driver circuit 152, and an oscillator 130.

  The oscillator 130 outputs a clock signal CLKH having a frequency equal to or higher than the highest frequency of the clock signal TCLK that drives the load circuit 141. The dummy clock generation circuit 120 generates and outputs a clock signal DCLK that drives the dummy load circuit 142 based on the clock signal TCLK and the clock signal CLKH output from the oscillator 130. The regulator 110 supplies power to the driver circuits 151 and 152. The driver circuit 151 receives the clock signal TCLK and drives the load circuit 141. The driver circuit 152 inputs the clock signal DCLK and drives the dummy load circuit 142.

  The load circuit 141 is an original load in the flash memory unit 100 and is exemplified by a word line of the flash memory cell. That is, the driver circuit 151 charges and discharges the load circuit 141 such as a word line of the flash memory cell based on the clock signal TCLK. The dummy load circuit 142 is a circuit that simulates the load circuit 141. If the load circuit 141 is a capacitive load, the dummy load circuit 142 is similarly a capacitive circuit, and the capacitance value is set to the same value. Therefore, the driver circuit 152 charges and discharges the load circuit 142 based on the clock signal DCLK.

  As shown in FIG. 3, the dummy clock generation circuit 120 includes D-type flip-flops 121, 122, 123, and 124 having an asynchronous reset input, an OR circuit 125, a NOT circuit 126, and an AND circuit 128.

  The flip-flop 122 is connected to the data input node D at the H level (power supply voltage VDD), takes in the H level in synchronization with the rising edge of the clock signal TCLK, and outputs it from the output node Q. The flip-flop 123 takes in the output of the flip-flop 122 in synchronization with the rising edge of the clock signal CLKH, and outputs it from the output node Q. The flip-flop 124 takes in the output of the flip-flop 123 in synchronization with the rising edge of the clock signal CLKH, and outputs it from the output node Q. The flip-flop 121 takes in the output of the flip-flop 123 in synchronization with the rising edge of the clock signal TCLK, and outputs it from the output node Q. When the flip-flop 121 becomes H level, the flip-flop 121 is reset and outputs an L level signal.

  The OR circuit 125 supplies a signal indicating a logical sum of the output of the flip-flop 121 and the output of the flip-flop 124 to the flip-flop 123 and the flip-flop 124, and at least one of the outputs of the flip-flop 121 and the flip-flop 124 is H When the level is reached, the flip-flop 123 and the flip-flop 124 are reset. Further, when the output of the flip-flop 124 becomes H level, the flip-flop 122 is reset. The output of the flip-flop 122 is logically inverted by the NOT circuit 126 and input to the AND circuit 128. The AND circuit 128 outputs a logical product of the clock signal CLKH and the logically inverted output of the flip-flop 122 as the clock signal DCLK.

  The dummy clock generation circuit 120 detects the rising edge of the clock signal TCLK, masks the clock signal CLKH, and suppresses pulse generation of the clock signal DCLK. When the second rising edge of the clock signal CLKH from the rising edge of the clock signal TCLK is detected, the suppression is canceled and a pulse of the clock signal DCLK is generated. Therefore, the clock signal DCLK from which one pulse immediately after the rising edge of the clock signal TCLK is deleted is generated.

  The operation of the load current stabilization circuit 115 will be described with reference to FIG.

  The oscillator 130 constantly oscillates at a predetermined frequency and outputs a clock signal CLKH (FIG. 4A). On the other hand, the oscillator 170 changes the oscillation frequency under the control of the CPU 190 and outputs the clock signal TCLK (FIG. 4B). Here, the oscillator 170 oscillates at the same frequency as the clock signal CLKH in the period T1 and in the oscillation stopped state during the period T2. The oscillator 170 oscillates at a frequency of 1/2 in the period T5, a frequency of 1/4 in the period T4, and a frequency of 1/8 in the period T3, and outputs a clock signal TCLK.

  Therefore, in the period T1, since the oscillator 170 is stopped, the clock signal TCLK has no pulse (FIG. 4B), and the clock signal DCLK generated by the dummy clock generation circuit 120 is generated by the oscillator 130. It becomes the same signal as the clock signal CLKH (FIG. 4 (c) period T1). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK is the same as the number of pulses of the clock signal CLKH and is constant. Here, since there is no pulse appearing in the clock signal TCLK, the rising edge of the pulse included in the clock signal DCLK is substantially the same as the temporal distribution of the rising edge of the pulse included in the clock signal CLKH. The number (density) of pulses appearing in a predetermined unit time is equally constant.

  In the period T2, since the oscillator 170 oscillates at the same frequency as the oscillator 130, the same number of pulses as the clock signal CLKH appear in the clock signal TCLK (FIG. 4B). The dummy clock generation circuit 120 does not output a pulse, and no pulse appears in the clock signal DCLK during this period (period T2 in FIG. 4C). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK is the same as the number of pulses of the clock signal CLKH and is constant. Here, since there are no pulses appearing in the clock signal DCLK, the rising edges of the pulses included in the clock signal TCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH. The number of pulses (density) appearing in a predetermined unit time is equally constant.

  In the period T3, the clock signal TCLK having a period eight times the clock signal CLKH is input (FIG. 4B). Since the dummy clock generation circuit 120 does not output one of the pulses immediately after the rising edge of the clock signal TCLK, seven pulses appear in the clock signal DCLK during one cycle of the clock signal TCLK (FIG. 4C). Period T3). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK is the same as the number of pulses of the clock signal CLKH and is constant. That is, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant.

  In the period T4, the oscillator 170 outputs the clock signal TCLK that is four times the cycle of the clock signal CLKH (FIG. 4B). Since the dummy clock generation circuit 120 does not output one of the pulses immediately after the rise of the clock signal TCLK, three pulses appear in the clock signal DCLK during one cycle of the clock signal TCLK (FIG. 4C). Period T4). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK is the same as the number of pulses of the clock signal CLKH and is constant. That is, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant.

  In the period T5, the oscillator 170 outputs the clock signal TCLK that is twice the cycle of the clock signal CLKH (FIG. 4B). Since the dummy clock generation circuit 120 does not output one of the pulses immediately after the rising edge of the clock signal TCLK, one pulse appears in the clock signal DCLK during one cycle of the clock signal TCLK (FIG. 4C). Period T5). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK is the same as the number of pulses of the clock signal CLKH and is constant. That is, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant.

  As described above, the dummy clock generation circuit 120 generates the clock signal DCLK, and the driver circuit 152 drives the dummy load circuit 142 by the clock signal DCLK. The total number of pulses per fixed time of the clock signal TCLK and the clock signal DCLK substantially matches the number of pulses of the clock signal CLKH. The number of pulses is constant regardless of the frequency of the clock signal TCLK. That is, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant. The current load of the regulator 110 is the sum of the current that drives the load circuit 141 that is the original load by the clock signal TCLK and the current that drives the dummy load circuit 142 by the clock signal DCLK. The fact that the sum (density) of the number of pulses per fixed time of the clock signal TCLK and the clock signal DCLK substantially matches the number of pulses (density) of the clock signal CLKH means that the load circuit 141 which is the original load by the clock signal CLKH. Therefore, the same current load as that when driving is applied to the regulator 110 regardless of the frequency of the clock signal TCLK. As a result, even if the frequency of the clock signal TCLK varies, the current load of the regulator 110 can be kept substantially constant.

  Normally, the regulator 110 always tries to output a constant voltage, but the response is not in time when the current load changes, and the output voltage fluctuates. Therefore, at the instant when the clock frequency changes, that is, when the pulse density changes, the output voltage changes transiently due to the change in the current load. For example, as shown in FIG. 5, a load current (FIG. 5B) flows in response to the operation clock (FIG. 5A), and the output voltage (FIG. 5C) varies. That is, when the operation clock changes from high speed (high frequency) to low speed (low frequency), the load current decreases. At the moment when the load current decreases, the response of the regulator 110 is not in time and the output voltage rises transiently. Conversely, when the operating clock changes from low speed (low frequency) to high speed (high frequency), the load current increases. At the instant when the load current increases, the response of the regulator 110 is not in time, and the output voltage decreases transiently.

  On the other hand, when the load current stabilization circuit 115 of the present invention is provided, the current load can be kept constant with respect to the clock frequency fluctuation, and the output voltage is kept constant even at the moment when the clock frequency fluctuates. It becomes possible to keep it. As a result, it is not necessary to consider the fluctuation of the output voltage of the regulator in the circuit design. The power supply voltage fluctuation margin can be compressed, and the effects of improving the circuit performance and reducing the circuit area can be obtained. In general, in order to suppress fluctuations in the output voltage of the regulator, it is necessary to connect a stabilization capacitor to the power supply. This stabilizing capacity requires a large area. According to the present invention, it is not necessary to connect a large stabilization capacitor, so that the effect of area reduction can be obtained.

(Second Embodiment)
A second embodiment will be described with reference to the drawings.

  In the semiconductor integrated circuit device according to the second embodiment, one of the high-speed clock signal and the low-speed clock signal is selected by a switch and used. The high-speed clock signal and the low-speed clock signal are generated by different oscillators. The semiconductor integrated circuit device can instantaneously switch the operating frequency by switching the switch.

  The high-speed clock signal CLKH is used during normal operation. Since a certain level of accuracy is required, it is generally generated using a PLL (Phase Locked Loop) circuit. Since the PLL circuit has a long oscillation stabilization time, it takes a long time to switch the frequency, but can stably output a clock having a constant frequency. On the other hand, the low-speed clock CLKL is used during standby operation. Since accuracy is not so much required, it is generally generated using a ring oscillator or the like. Since the ring oscillator has a short oscillation stabilization time, the time required for switching the frequency is short. When such two types of clock signals are provided, the high-speed clock signal CLKH always oscillates regardless of the operating frequency of the semiconductor integrated circuit device. Therefore, a dummy is used instead of the oscillator 130 in the first embodiment. It can be used to generate the clock signal DCLK.

  FIG. 6 shows a configuration of a semiconductor integrated circuit device according to the second embodiment. The semiconductor integrated circuit device according to the second embodiment includes a CPU 290, a flash memory unit 200, a high frequency oscillator 270, and a low oscillator 280. The flash memory unit 200 includes a regulator 210 that generates a power supply voltage to be used, and operates based on the high-speed clock signal CLKH and the low-speed clock signal CLKL supplied from the oscillators 270 and 280.

  The CPU 290 selects one of the high-speed clock signal CLKH and the low-speed clock signal CLKL supplied from the oscillators 270 and 280, executes a program based on the selected clock signal, and accesses the flash memory unit 200. The CPU 290 gives a selection signal CLKSEL indicating the operating frequency to be used to the flash memory unit 200. In addition, the CPU 290 changes the oscillation frequency of the oscillator 280 according to the operation status. Here, it is assumed that the operation is based on the high speed clock signal CLKH when the selection signal CLKSEL indicates “H”, and the operation is based on the low speed clock signal CLKL when the selection signal CLKSEL indicates “L”.

  The oscillator 270 always oscillates at a constant frequency and outputs a high-speed clock signal CLKH. The high-speed clock signal CLKH indicates the maximum operating frequency of the flash memory unit 200. The oscillator 280 changes the frequency of oscillation in response to an instruction from the CPU 290 and outputs a low-speed clock signal CLKL. Therefore, the frequency of the low-speed clock signal CLKL is 0 Hz to the maximum operating frequency (CLKH).

  FIG. 7 is a block diagram showing the periphery of the regulator 210 built in the flash memory unit 200. The flash memory unit 200 includes a load circuit 241, a driver circuit 251, a load current stabilization circuit 215, and a selection circuit 230 that switches a clock signal around the regulator 210. The load current stabilization circuit 215 includes a dummy clock generation circuit 220, a dummy load circuit 242, and a driver circuit 252.

  The selection circuit 230 selects one of the input high-speed clock signal CLKH and low-speed clock signal CLKL based on the selection signal CLKSEL, and outputs it as the clock signal TCLK. The dummy clock generation circuit 220 generates and outputs a clock signal DCLK that drives the dummy load circuit 242 based on the selection signal CLKSEL, the high-speed clock signal CLKH, and the low-speed clock signal CLKL. The regulator 210 supplies power to the driver circuits 251 and 252. The driver circuit 251 inputs the clock signal TCLK and drives the load circuit 241. The driver circuit 252 inputs the clock signal DCLK and drives the load circuit 242.

  The load circuit 241 is an original load of the flash memory unit 200 and is exemplified by a word line of the flash memory cell. That is, the driver circuit 251 charges and discharges the load circuit 241 such as the word line of the flash memory cell based on the clock signal TCLK. The dummy load circuit 242 is a circuit that simulates the load circuit 241. If the load circuit 241 is a capacitive load, the dummy load circuit 242 is also a capacitive circuit, and the capacitance value is set to the same value. Therefore, the driver circuit 252 charges and discharges the load circuit 242 based on the clock signal DCLK.

  As shown in FIG. 8, the dummy clock generation circuit 220 includes D-type flip-flops 221, 222, 223, and 224 having asynchronous reset inputs, an OR circuit 225, NOT circuits 226 and 227, and AND circuits 228 and 229. With.

  The flip-flop 222 is connected to the data input node D at the H level (power supply voltage VDD), takes in the H level in synchronization with the rising edge of the clock signal TCLK, and outputs it from the output node Q. The flip-flop 223 takes in the output of the flip-flop 222 in synchronization with the rising edge of the high-speed clock signal CLKH, and outputs it from the output node Q. The flip-flop 224 takes in the output of the flip-flop 223 in synchronization with the rising edge of the high-speed clock signal CLKH, and outputs it from the output node Q. The flip-flop 221 takes in the output of the flip-flop 223 in synchronization with the rising edge of the clock signal TCLK, and outputs it from the output node Q. When the flip-flop 221 becomes H level, the flip-flop 221 is reset and outputs an L level signal.

  The OR circuit 225 supplies a signal indicating the logical sum of the output of the flip-flop 221 and the output of the flip-flop 224 to the flip-flop 223 and the flip-flop 224, and at least one of the outputs of the flip-flop 221 and the flip-flop 224 is H When the level is reached, the flip-flops 223 and 224 are reset. Further, when the output of the flip-flop 224 becomes H level, the flip-flop 222 is reset. The output of the flip-flop 222 is logically inverted by the NOT circuit 226 and input to the AND circuit 228. The AND circuit 228 outputs a logical product of the high-speed clock signal CLKH and the logically inverted output of the flip-flop 222. This signal corresponds to the clock signal excluding the pulse immediately after the rise of the clock signal TCLK (corresponding to the clock signal CLKL) described in the first embodiment, and the clock signal when the selection signal CLKSEL indicates “L”. It becomes. Therefore, the AND circuit 229 takes a logical product of a signal obtained by logically inverting the selection signal CLKSEL by the NOT circuit 227 and the output of the AND circuit 228, and outputs the logical product as a dummy clock signal DCLK. When the selection signal CLKSEL indicates “H”, the clock signal TCLK supplied to the load circuit 241 is the high-speed clock signal CLKH, and no pulse is necessary for the dummy clock signal DCLK. Thus, since the high-speed clock signal CLKH is supplied from the outside, the oscillator 130 described in the first embodiment is not necessary.

  The operation of the load current stabilization circuit 225 will be described with reference to FIG.

  The CPU 290 switches and uses the clock signal according to the operation status. A selection signal CLKSEL indicating the clock signal to be used is supplied to the flash memory unit 200 (FIG. 9A). In the period T1 and the periods T3 to T5, the selection signal CLKSEL indicates “L”, and the low-speed clock signal CLKL is selected. In the period T2, the selection signal CLKSEL indicates “H”, and the high-speed clock signal CLKH is selected.

  The high-speed clock signal CLKH constantly supplies pulses at a predetermined frequency (periods T1 to T5) (FIG. 9B). The low-speed clock signal CLKL receives control from the CPU 290, and does not supply a pulse in a stopped state during the periods T1 and T2. The low-speed clock signal CLKL supplies a pulse with a period eight times that of the high-speed clock signal CLKH in the period T3, supplies a pulse with a period four times the high-speed clock signal CLKH in the period T4, and supplies a pulse with a period four times that of the high-speed clock signal CLKH Pulses are supplied at a double cycle (FIG. 9C).

  In the period T1, the selection signal CLKSEL indicates “L”, and the low-speed clock signal CLKL being stopped is selected and supplied as the clock signal TCLK to the load circuit 241 that is the original load (FIG. 9D). . Further, since the low-speed clock signal CLKL does not include a pulse, the dummy clock generation circuit 220 supplies the high-speed clock signal CLKH to the dummy load circuit 242 as the clock signal DCLK (FIG. 9 (e)). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK in the period T1 is the same as the number of pulses appearing in the high-speed clock signal CLKH, and is constant. Here, since the high-speed clock signal CLKH is supplied as the clock signal DCLK, the pulse included in the clock signal DCLK and the pulse included in the high-speed clock signal CLKH appear at substantially the same timing. That is, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant.

  In the period T2, since the selection signal CLKSEL indicates “H”, the high-speed clock signal CLKH is selected and supplied to the load circuit 241 as the clock signal TCLK (FIG. 9D). Since the selection signal CLKSEL indicates “H”, the dummy clock generation circuit 220 outputs the clock signal DCLK including no pulse by the AND circuit 229 (FIG. 9E). Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK in the period T2 is the same as the number of pulses appearing in the high-speed clock signal CLKH, and is constant. Here, the high-speed clock signal CLKH is selected as the clock signal TCLK, a pulse appears in the clock signal TCLK at almost the same timing as the high-speed clock signal CLKH, and no pulse is included in the clock signal DCLK. Therefore, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are substantially evenly distributed in the same manner as the time distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant.

  In the periods T3 to T5, since the selection signal CLKSEL indicates “L”, the low-speed clock signal CLKL is selected and supplied to the load circuit 241 as the clock signal TCLK (FIG. 9D). The dummy clock generation circuit 220 detects the rising edge of the low-speed clock signal CLKL, generates a clock signal DCLK from which a pulse immediately after the high-speed clock signal CLKH is deleted, and supplies the clock signal DCLK to the dummy load circuit 242 (FIG. 9 (e)). . Therefore, the total number of pulses appearing in the clock signal TCLK and the clock signal DCLK in the periods T3 to T5 is the same as the number of pulses appearing in the high-speed clock signal CLKH, and is constant. That is, the rising edges of the pulses included in the clock signal TCLK and the clock signal DCLK are distributed almost evenly in the same manner as the temporal distribution of the rising edges of the pulses included in the clock signal CLKH, and appear in a predetermined unit time. The number (density) is equally constant.

  In this manner, the dummy clock generation circuit 220 generates the clock signal DCLK, and the driver circuit 252 drives the dummy load circuit 242 with the clock signal DCLK. The total number of pulses per fixed time of the clock signal TCLK and the clock signal DCLK coincides with the number of pulses of the high-speed clock signal CLKH and becomes constant. The current load of the regulator 210 is the sum of the current that drives the load circuit 241 that is the original load by the clock signal TCLK and the current that drives the dummy load circuit 242 by the clock signal DCLK. The fact that the sum of the number of pulses per fixed time of the clock signal TCLK and the clock signal DCLK matches the number of pulses of the high-speed clock signal CLKH drives the load circuit 241 that is the original load by the high-speed clock signal CLKH. The same current load as the case is always applied to the regulator 210 regardless of the frequency of the clock signal TCLK. This makes it possible to keep the current load of the regulator 210 substantially constant even when the frequency of the clock signal TCLK varies. Since the oscillator corresponding to the oscillator 130 in the first embodiment is not necessary, the area can be further reduced.

  The embodiment has been described above by taking the flash macro circuit as an example of the circuit having the regulator. However, the circuit is not limited to the flash macro circuit as long as the circuit has the regulator inside. In this way, in a circuit having a regulator inside, the output voltage of the regulator that supplies power to the driver circuit that drives the load based on the operation clock is changed transiently because the load current changes when the frequency of the operation clock changes. Fluctuates. The load current stabilization circuit of the present invention suppresses a change in load current due to a change in the frequency of an operation clock, thereby reducing a transient output voltage fluctuation.

  If the original load circuit driven by the driver circuit is a capacitive load, a dummy load circuit having the same capacity as the load circuit is provided, and the dummy load circuit has the same power supply as the driver circuit that drives the original load circuit. Driven by another driver circuit having the same size. The load current stabilization circuit includes a dummy clock generation circuit that generates a dummy clock signal for driving the dummy load circuit, a dummy load circuit, and a driver circuit.

  The dummy clock signal is generated based on a clock signal having the highest frequency or higher frequency of the operation clock signal, and detecting the rising of the operation clock signal and suppressing the generation of the pulse of the dummy clock signal immediately after. Therefore, the sum of the number of pulses included in the operation clock signal per fixed time and the number of pulses included in the dummy clock signal is constant regardless of the frequency of the operation clock signal. The dummy load circuit is set so that the load current charged and discharged in one pulse of the clock signal is substantially the same between the operation clock signal and the dummy clock signal. Therefore, the load current is constant regardless of the change in the frequency of the operation clock signal. By generating the dummy clock signal in this way, fluctuations in the output voltage of the regulator can be suppressed. Therefore, it is possible to compress the power supply voltage fluctuation margin necessary for the operation of the circuit using the regulator as a power source, and the effect of improving the circuit performance and reducing the circuit area can be obtained. In addition, it is possible to reduce the stabilization capacity that suppresses fluctuations in the power supply voltage, and an area reduction effect can be obtained.

  As described above, the present invention has been described with reference to the embodiment. However, the above embodiment can be implemented in combination as long as there is no contradiction. The present invention is not limited to the above-described embodiment, and various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 100 Flash memory part 110 Regulator 115 Load current stabilization circuit 120 Dummy clock generation circuit 121, 122, 123, 124 Flip-flop 125 OR circuit 126 NOT circuit 128 AND circuit 130 Oscillator 141 Load circuit 142 Dummy load circuit 151, 152 Driver circuit 170 Oscillator 190 CPU
200 Flash Memory Unit 210 Regulator 215 Load Current Stabilization Circuit 220 Dummy Clock Generation Circuit 221, 222, 223, 224 Flip-Flop 225 OR Circuit 226, 227 NOT Circuit 228, 229 AND Circuit 230 Selection Circuit 241 Load Circuit 242 Dummy Load Circuit 251 252 Driver circuit 270, 280 Oscillator 290 CPU

Claims (8)

A dummy load circuit that simulates a load circuit driven by a load driver circuit based on a first clock signal of variable frequency;
A dummy clock generation circuit for generating a dummy clock signal for driving the dummy load circuit;
A load current stabilization circuit comprising: a dummy driver circuit that is supplied with power from a regulator that supplies power to the load driver circuit and drives the dummy load circuit based on the dummy clock signal. The dummy clock generation circuit is configured such that the sum of the number of pulses included in the first clock signal within a predetermined period and the number of pulses included in the dummy clock signal within the predetermined period is constant. The load current stabilization circuit according to claim 1, wherein the dummy clock signal is generated. An oscillator that oscillates at a frequency equal to or higher than a maximum frequency of the first clock signal;
The load current stabilization circuit according to claim 1, wherein the dummy clock generation circuit generates the dummy clock signal based on a second clock signal output from the oscillator. The load current stabilization circuit according to claim 3, wherein the dummy clock generation circuit generates the dummy clock signal by masking a pulse of the second clock signal that rises immediately after a rise of the pulse of the first clock signal. The dummy clock generation circuit receives a third clock signal whose frequency is fixed to the highest frequency of the first clock signal, and generates the dummy clock signal based on the third clock signal. 2. The load current stabilization circuit according to 2. The dummy clock generation circuit includes:
When the frequency of the first clock signal is equal to the frequency of the third clock signal, a pulse of the dummy clock signal is not generated,
When the frequency of the first clock signal is lower than the frequency of the third clock signal, the dummy clock signal is generated by masking the pulse of the third clock signal that rises immediately after the rise of the pulse of the first clock signal. The load current stabilization circuit according to claim 5. The load current stabilization circuit according to any one of claims 1 to 6, wherein the dummy load circuit includes a capacitor having a capacitance value equal to a capacitance value of the load circuit. The load current stabilization circuit according to any one of claims 1 to 7,
A semiconductor integrated circuit device comprising: a dummy driver circuit of the load current stabilizing circuit; and a regulator for supplying power to the load driver circuit.

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