JP2012222136A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can achieve a high ON/OFF ratio of a driving current and stable characteristics with inhibiting increase in element area.SOLUTION: A semiconductor device comprises an insulation layer, a semiconductor layer formed on the insulation layer and a partially depleted transistor 10 formed on the semiconductor layer. The transistor 10 includes a gate electrode 14 formed on the semiconductor layer via an insulation film, a source 15 or a drain 16 formed on the semiconductor layer under both sides of the gate electrode 14 and impurity layers 17, 18 provided on a bottom of a body. The impurity layers 17, 18 are formed on both end parts of the bottom of the body region and do not contact the source 15 and the drain 16.

Description

  The present invention relates to a semiconductor device including a transistor formed in a semiconductor layer on an insulating film, and a manufacturing method thereof.

  Technology (SOI: Silicon On Insulator) for forming a semiconductor device on a thin semiconductor film formed on an insulating film has been developed and put into practical use as a next-generation low-power semiconductor device. SOI has features such as a sub-threshold characteristic with a steep drive current, low noise, and low parasitic capacitance, and its application to integrated circuits used in watches and portable devices is advancing. Currently, MISFETs (Metal Insulator Semiconductor Field Effect Transistors) having an SOI structure are used in various semiconductor integrated circuits. Particularly, a MISFET having a partially depleted (PD) SOI structure (hereinafter referred to as a PD-SOI MISFET) that can be easily manufactured in the same manner as a conventional bulk structure MISFET manufacturing method is widely used in semiconductor products. Has been. The structure of the PD-SOI MISFET is disclosed in Patent Document 1, for example.

  FIGS. 14A and 14B are typical structures of PD-SOI MISFETs that have been widely known. In the PD-SOI MISFET shown in FIGS. 14A and 14B, the depletion layer does not reach the insulating layer due to the operation of the MISFET in the region of the semiconductor layer immediately below the gate, that is, the region called the body region, and is not fully depleted. This body region that remains undepleted remains electrically isolated from other regions by an element isolation layer and an insulating layer (also referred to as a BOX layer), and its potential (hereinafter referred to as body potential) Is floating and unstable. For this reason, the structure shown in FIGS. 14A and 14B is called a body floating type, and the device characteristics are affected and fluctuated by the floating body potential. This phenomenon is called a substrate floating effect, and variations in device characteristics due to this phenomenon may lead to a serious problem in circuit operation. In particular, the phenomenon called the history effect is important and may need to be considered when designing a circuit. Here, the history effect is the influence of the substrate floating effect, and due to the history of voltage conditions applied to the gate, drain, and source, the body potential varies, and the drain current varies due to the body potential variation, It is a phenomenon that device characteristics become unstable.

  The history effect can be suppressed by a known body potential fixing method as shown in FIG. FIGS. 13A and 13B are cross-sectional views illustrating a configuration example of a PD-SOI MISFET according to a conventional example. As shown in FIGS. 13A and 13B, the PD-SOI MISFET 90 includes a gate insulating film 93 formed on the surface of the SOI layer 92 on the BOX layer 91, and an SOI layer via the gate insulating film 93. Gate electrode 94 formed on insulating film 99 on 92, N-type source 95a or drain 95b formed on SOI layer 92 below both sides of gate electrode 94, and SOI layer in a region immediately below gate electrode 94 (That is, a P-type impurity layer 96 connected to the body region) 92.

In this PD-SOI MISFET 90, as shown in FIG. 13B, the depletion layer 92a does not reach the BOX layer and a neutral region (body region) 92b that is not depleted remains. Further, since the potential of the body region 92 (that is, the body potential) is fixed to a desired potential (for example, ground potential) via the contact 97 and the P-type impurity layer 96, the substrate floating effect is suppressed and the history effect is improved. It is suppressed. Such a structure is called a body contact or a body tie, and is disclosed in Patent Document 2, for example. In FIG. 13A, the interlayer insulating film 98 shown in FIG. 13B is omitted in order to avoid complication of the drawing.
Further, in order to suppress the history effect, for example, as disclosed in Patent Document 3, the impurity concentration between the body region and the source / drain region is lowered to increase the parasitic resistance between the body, the source and the drain. There is a method for reducing fluctuations in body potential.

JP 2004-128254 A JP 2004-119884 A JP 2010-232270 A

  However, in the partially depleted SOI MISFET 90, when the body potential is fixed from the outside using a technique such as a body tie, the device characteristics are stabilized, but a large parasitic capacitance is generated in the body region. Therefore, there is a problem that the ON (ON) current of the MISFET decreases, the ON / OFF ratio of the drain current decreases, and the subthreshold swing value (S value) increases. That is, there is a problem that the drive current of the partially depleted MISFET 90 is reduced, and the current drive capability is comparable to that of a conventional bulk silicon MISFET. For this reason, the structure shown in FIGS. 13A and 13B may not be able to fully utilize the advantages of SOI.

  Further, in the structure shown in FIGS. 13A and 13B, the contact 97 for fixing the body potential is necessary. Therefore, for example, compared with the body floating structure shown in FIGS. 14A and 14B. There is also a problem that the element area increases and the degree of integration decreases.

  Also, as disclosed in Patent Document 3, there is a method of reducing the fluctuation of the body potential, but even in this case, the movement of charge from the body region to the source and drain regions exists to the extent that it cannot be ignored, and the stability of the transistor In order to realize the operation, there is a possibility that the reduction of the body potential fluctuation is not sufficient. In other words, there is room for further improvement, and in order to further improve the stability of operation, there is a problem that it is necessary to suppress the movement of charges from the body region to the source and drain regions to a negligible level.

  Accordingly, some aspects of the present invention have been made in view of such circumstances, and in the partially depleted transistor formed in the semiconductor layer on the insulating film, while suppressing an increase in element area. An object of the present invention is to provide a semiconductor device capable of realizing an ON / OFF ratio with high drain current and a stable operation, and a method for manufacturing the same.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms.

  Application Example 1 A semiconductor device according to this application example includes an insulating layer, a semiconductor layer formed on the insulating layer, and a partially depleted transistor formed on the semiconductor layer. A gate electrode formed on the semiconductor layer via an insulating film; a source or drain of a first conductivity type formed in the semiconductor layer under both sides of the gate electrode; and the semiconductor layer directly under the gate electrode A first impurity region of a first conductivity type provided in a region located on both sides of the body region, which is a region of the source region, wherein the first impurity region is present in the body region, and the source and drain regions It is arranged at a position that does not contact with.

  Here, the “insulating layer” is also called a BOX layer, for example, and the “semiconductor layer” is also called an SOI layer, for example. In addition, a “partially depleted transistor” means that the body region is not completely depleted during transistor operation, but is partially depleted, that is, the neutral region remains without the depletion layer reaching the insulating layer. It is a transistor. The “first conductivity type” is one of P type and N type, and the “second conductivity type” is the other of P type and N type. Note that the insulating layer between the gate electrode and the semiconductor layer may be an oxide film formed by thermal oxidation of the semiconductor layer, or may be another insulating film (for example, a High-k film). Also good.

  In the configuration shown in this application example, a PNP (or NPN) structure is formed between the body region and the source or drain region by the first impurity layer. For this reason, due to the reverse bias effect of the PN junction diode, the charge from the body region to the source or drain during the operation of the transistor (that is, the hole when the body region is P-type, and the electron when it is N-type). ), The body potential is stabilized, and at the same time, a high driving current can be obtained by the bias effect due to the charge accumulated in the body potential. As a result, the history effect can be reduced, and a semiconductor device that can simultaneously realize an ON / OFF ratio with a high drain current and a stable operation while suppressing an increase in the element area can be provided.

  Application Example 2 In the semiconductor device according to the application example described above, the source or drain may include an LDD region, and the first impurity region may be disposed at a position not in contact with the LDD region. .

  The source or drain has an LDD structure having an LDD region. Here, the “LDD structure” is a lightly doped drain, and is composed of a portion where impurities are introduced at a low concentration (ie, a low concentration layer) and a portion where impurities are high (ie, a high concentration layer). It is the made structure. With such a configuration, for example, a wide width between the source and the drain necessary for forming the first impurity layer can be secured, so that the formation of the first impurity layer is facilitated. Further, parasitic resistance generated in the channel portion can be reduced. Therefore, the effect of increasing the ON current can be obtained.

  Application Example 3 The semiconductor device according to the application example described above may have a sidewall structure on both side walls of the gate electrode.

  According to this application example, the LDD structure can be easily formed, and a wide width between the source and the drain necessary for forming the first impurity region can be secured. Therefore, the manufacture of the semiconductor device according to the present invention can be facilitated.

  Application Example 4 A manufacturing method of a semiconductor device according to this application example is a manufacturing method of a semiconductor device having a partially depleted transistor in a semiconductor layer on an insulating film, and the insulating film is formed on the semiconductor layer. A step of forming a gate electrode on the semiconductor layer through the insulating film, and a region located on both sides of the body region, which is a region of the semiconductor layer immediately below the gate electrode, in a region not in contact with the source or drain Forming a first impurity region of a first conductivity type; and forming a source or drain in the semiconductor layer under both sides of the gate electrode.

  According to such a manufacturing method, a semiconductor device with a reduced history effect can be manufactured, and a semiconductor device capable of simultaneously realizing an ON / OFF ratio with a high drain current and a stable operation while suppressing an increase in element area. Can be provided.

  Application Example 5 The semiconductor device manufacturing method according to the application example may further include a step of forming an LDD structure in the source or drain region.

  According to such a manufacturing method, the source or drain can have an LDD structure having an LDD region. With this configuration, for example, a wide width between the source and the drain necessary for forming the first impurity layer can be secured, so that the formation of the first impurity layer is facilitated. Further, parasitic resistance generated in the channel portion can be reduced. Therefore, the effect of increasing the ON current can be obtained.

  Application Example 6 In the method of manufacturing a semiconductor device according to the application example, the step of introducing impurities into the semiconductor layer using the gate electrode as a mask before the step of forming the first impurity layer, and the gate electrode Forming sidewalls on both side walls of the substrate, and forming the source or drain includes forming the sidewalls and then forming the semiconductor layer on the semiconductor layer using the gate electrode and the sidewalls as a mask. Impurities may be introduced.

  According to such a manufacturing method, the LDD structure and the first impurity layer can be manufactured by self-alignment using the gate electrode as a mask, and the alignment accuracy when forming the LDD structure and the first impurity layer is high. Improved and easier to manufacture. Further, the source 15 and the drain 16 can be formed by self-alignment using the side wall as a mask, which further facilitates manufacture. Further, since the first impurity layer can be formed between the gate electrode, the source 15 and the drain 16, there is an effect that the formation of the first impurity layer is further facilitated.

1 is a diagram illustrating a configuration example of a semiconductor device according to a first embodiment. FIG. 6 is a view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a view showing the method for manufacturing the semiconductor device according to the first embodiment. The figure which shows the structural example of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. The figure which shows the structure of the semiconductor device of a prior art example. The figure which shows the structure of the semiconductor device of a prior art example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted. Moreover, in order to make each layer and each member recognizable, the scale of each layer and each member is made different from the actual scale. In FIG. 1A, FIG. 7A, FIG. 13A, and FIG. 14A shown below, the description of the interlayer insulating film 5 is omitted in order to avoid complication of the drawings. .

(First embodiment)
FIGS. 1A and 1B are a plan view and a cross-sectional view showing a configuration example of the semiconductor device according to the first embodiment of the present invention. As shown in FIGS. 1A and 1B, this semiconductor device uses, for example, a silicon substrate having a buried oxide film (BOX layer) and a single crystal silicon layer (SOI layer) on the upper surface thereof, that is, an SOI substrate. An SOI layer 2 formed on the BOX layer 1, an element isolation layer 3 surrounding the SOI layer 2 in plan view, an N-channel transistor 10 formed on the SOI layer 2, and interlayer insulation covering the transistor 10 And a film 5. The BOX layer 1 is, for example, a silicon oxide film (SiO ₂ ), and the SOI layer 2 is, for example, a single crystal silicon layer (Si).

The transistor 10 includes, for example, a gate electrode 14 formed on the SOI layer 2 via the insulating film 13, an N-type source 15 or drain 16 formed on the SOI layer 2 below both sides of the gate electrode 14, Have The insulating film 13 is, for example, a gate oxide film (SiO ₂ or SiON) formed by thermal oxidation of the SOI layer 2 or a High-K film. Also. The gate electrode 14 is made of, for example, polysilicon containing impurities such as phosphorus and boron, or metal.

  The transistor 10 is a partially depleted MISFET (that is, PD-SOI MISFET), and during its operation (that is, when a voltage higher than a threshold is applied to the gate electrode 14 and the transistor 10 is turned on), As shown in FIG. 1B, in the SOI layer (that is, the body region) 2 immediately below the gate electrode 14, the depletion layer does not reach the BOX layer 1 and a neutral region remains. The body region 2 is not fixed in potential. That is, it has a body float structure. Further, the transistor 10 has an N-type impurity layer 17 provided on both lower sides in the body region and an N-type impurity layer 18 similarly. The impurity layers 17 and 18 are disposed in the body region, the impurity layer 17 is not in contact with the source 15, and the impurity layer 18 is not in contact with the drain 16. The impurity layers 17 and 18 are, for example, silicon single crystals implanted with P-type semiconductor ions such as boron.

According to the semiconductor device according to the first embodiment described above, the following effects can be obtained.
The impurity layers 17 and 18 form a P—N—P structure between the body region and the source or drain, and charge (ie, electrons or holes) flows between the body region and the source or drain. Is suppressed. Accordingly, since the body potential is stabilized, the history effect is suppressed. Furthermore, charges are accumulated in the body potential, and an increase in drain current can be obtained due to the body bias effect on the PD-SOI transistor. With these effects, it is possible to provide a semiconductor device having both an ON / OFF ratio with a high drain current and a stable operation at the same time without increasing the element area.
Next, a method for manufacturing this semiconductor device will be described.

  2 to 6 are a plan view and a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 2A and 2B, first, an SOI substrate having a BOX layer 1 formed on a supporting substrate (not shown) and an SOI layer 2 formed thereon is prepared. The SOI layer is made of, for example, single crystal silicon. This SOI substrate is formed by, for example, a SIMOX (Separation by Implanted Oxygen) bonding method. Next, the element isolation layer 3 is formed by partially thermally oxidizing the SOI layer 2 by, for example, a LOCOS (Local Oxidation of Silicon) method. A region surrounded by the element isolation layer 3 in plan view is an element region.

  Next, as shown in FIGS. 3A and 3B, for example, a P-type impurity such as boron is ion-implanted into the SOI layer 2. As a result, the conductivity type of the SOI layer 2 is changed to the P type. Next, impurity layers 17 and 18 are formed in two deep portions of the SOI layer 2. For example, as shown in FIGS. 4A and 4B, a resist pattern R1 is formed on the SOI substrate by opening the upper two portions of the SOI layer 2 and covering the other portions. Then, N-type impurity ions such as phosphorus and arsenic are implanted using the resist pattern R1 as a mask. A body region is formed between the impurity layer 17 and the impurity layer 18 formed by this process. Here, the implantation energy is adjusted so that almost all of the N-type impurity ions reach the lower part of the body region and do not stay on the upper part. Thereby, the impurity layer 17 can be formed only in the lower part, not in the upper part on both sides of the body region. Thereafter, the resist pattern R1 is removed.

  Next, as shown in FIGS. 5A and 5B, the surface of the SOI layer 2 is thermally oxidized to form an insulating film 13. Then, a film (for example, a polysilicon film or a metal film) serving as a material for the gate electrode is formed on the insulating film 13, and this film is patterned so as to include the regions of the impurity layers 17 and 18. 14 is formed. Next, as shown in FIGS. 6A and 6B, N-type impurity ions such as phosphorus or arsenic are implanted into the SOI layer 2 using the gate electrode 14 as a mask, and the SOI under both sides of the gate electrode 14 is implanted. A source 15 or a drain 16 is formed in the layer 2. As a result, a PN structure can be formed between the lower portion (that is, the deep portion) of the source 15 or the drain 16 and the end portion of the body region.

  Next, heat treatment is performed on the SOI substrate to diffuse the P-type impurity and the N-type impurity introduced into the SOI layer 2 respectively. Next, an interlayer insulating film (not shown) is formed on the SOI substrate. Then, openings (not shown) are formed on the source 15, the drain 16, and the gate electrode 14, respectively. Further, a conductive member such as tungsten is embedded in these openings to form contact electrodes 19a, 19b, 19c (see FIG. 1A). Finally, a wiring pattern made of a conductor such as aluminum or copper is formed. Thereby, the transistor 10 shown in FIGS. 1A and 1B is completed.

  As described above, according to the first embodiment of the present invention, the impurity layers 17 and 18 are formed between the P-type body region 2 and the N-type source 15 and drain 16. Due to the impurity layers 17 and 18, a P—N—P structure exists below the source 15 and between the body region 2. Therefore, when the transistor 10 is operated, the source 15 and the drain from the neutral region are operated. The discharge and injection of holes h + to 16 can be suppressed, and the body potential can be stabilized. Thereby, in the transistor 10, the history effect can be reduced, and a high ON / OFF ratio and stable operation can be realized while suppressing an increase in the element area.

(Second Embodiment)
7A and 7B are a plan view and a cross-sectional view showing a configuration example of a semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the present embodiment will be described with reference to these drawings. In addition, about the component same as 1st Embodiment, the same number is used and the overlapping description is abbreviate | omitted.

  As shown in FIGS. 7A and 7B, this semiconductor device includes an SOI layer 2 formed on the BOX layer 1, an element isolation layer 3 surrounding the SOI layer 2 in plan view, and an SOI layer 2. The N-channel type transistor 20 formed in the above structure and the interlayer insulating film 5 covering the transistor 20 are configured.

  Among these, the transistor 20 includes, for example, an insulating film 13, a gate electrode 14, and an N-type source 15 or drain 16. This transistor 20 is a PD-SOI MISFET, and its body region 2 has an externally fixed potential, that is, a body float structure.

Further, this transistor 20 has an LDD structure on the upper part of the SOI layer under both sides of the gate. This LDD region (second impurity layer) is single crystal silicon into which, for example, phosphorus, arsenic or the like is implanted. The transistor 20 has a sidewall structure on both side walls of the gate electrode. The material of the sidewall 31 is an insulator such as silicon oxide.
The transistor 20 has an N-type impurity layer 17 provided on both lower sides of the body region and an N-type impurity layer 18. The impurity layers 17 and 18 are in contact with the body region on both sides of the body region, the impurity layer 17 is not in contact with the source, and the impurity layer 18 is not in contact with the drain. The impurity layers 17 and 18 are not in contact with the LDD region. The impurity layers 17 and 18 are silicon single crystals into which N-type semiconductor ions such as phosphorus and arsenic are implanted. The impurity layers 17 and 18 form a P—N—P structure between the lower portion of the body region 2 and the lower portions of the source 15 and the drain 16.

According to the semiconductor device according to the second embodiment described above, the following effects can be obtained.
Similar to the first embodiment, the impurity layers 17 and 18 form a PNP structure between the body region and the source or drain, and charged particles (that is, between the body region and the source or drain (ie, The flow of electrons or holes) is suppressed. In addition, an increase in drain current due to a so-called body bias effect due to potential accumulation in the body region can be expected.
In addition, since the source and drain have an LDD structure, a wide width between the source and drain necessary for forming the impurity layers 17 and 18 can be secured, so that the impurity layers 17 and 18 can be easily formed. Further, parasitic resistance generated in the channel portion can be reduced. Therefore, the effect of increasing the ON current can be obtained.
Next, a method for manufacturing this semiconductor device will be described.

  8 to 12 are a cross-sectional view and a plan view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 8A and 8B, the processes up to the step of introducing P-type impurities into the SOI layer 2 to make the SOI layer 2 P-type are the same as those in the first embodiment. In the second embodiment, after that, the surface of the SOI layer 2 is thermally oxidized to form the insulating film 13. Then, a film (for example, a polysilicon film or a metal film) serving as a material for the gate electrode is formed on the insulating film 13, and this film is patterned to form the gate electrode 14. Next, impurity layers 17 and 18 are formed in two deep portions of the SOI layer 2. For example, as shown in FIGS. 9A and 9B, a resist pattern R2 that opens above the SOI layer 2 and includes the region of the gate electrode 14 and covers the other portions is formed on the SOI substrate. Form. Then, N-type first impurity layers 17 and 18 are formed on both sides of the body region by implanting N-type impurity ions such as phosphorus and arsenic using the resist pattern R2 and the gate electrode 14 as a mask. Here, the implantation energy is adjusted so that almost all of the N-type impurity ions reach the lower part of the body region and do not stay on the upper part. Thereby, the impurity layer 17 can be formed only in the lower part, not in the upper part on both sides of the body region. Thereafter, the resist pattern R2 is removed.

  Next, as shown in FIGS. 10A and 10B, a resist pattern R3 is formed on the SOI substrate so as to open a region including the element region and cover other portions. Using this resist pattern R3 and gate electrode 14 as a mask, N-type impurity ions such as phosphorus and arsenic are implanted. Thereby, the second impurity layers 32 and 33 are formed in shallow portions other than the region of the gate electrode 14 in the element region. Here, the implantation energy is adjusted so that the N-type impurity ions remain in a shallow portion of the element region and do not contact the impurity layers 17 and 18. Thereafter, the resist pattern R3 is removed.

  Next, for example, a silicon oxide film or the like is deposited on the substrate by a vapor deposition method or the like, and the entire surface of the substrate is etched. Thus, sidewalls 31 are formed on both side walls of the gate electrode 14 as shown in FIGS. After the sidewall 31 is formed, a region including the element region is opened as shown in FIGS. 12A and 12B, and a resist pattern R4 covering the other region is formed on the SOI substrate. Using the resist pattern R4 and the gate electrode 14 as a mask, N-type impurity ions such as phosphorus and arsenic are implanted to form the source 15 and the drain 16 in the SOI layer 2 below both sides of the gate electrode 14 and the sidewall 31. Thereafter, the resist pattern R4 is removed. As a result, a PN structure can be formed between the lower portion (that is, the deep portion) of the source 15 or the drain 16 and the end portion of the body region.

  Next, heat treatment is performed on the SOI substrate to diffuse the P-type impurity and the N-type impurity introduced into the SOI layer 2 respectively. Next, an interlayer insulating film (not shown) is formed on the SOI substrate. Then, openings (not shown) are formed on the source 15, the drain 16, and the gate electrode 14, respectively. Further, a conductive member such as tungsten is embedded in these openings to form contact electrodes 19a, 19b, 19c (see FIG. 1A). Finally, a wiring pattern made of a conductor such as aluminum or copper is formed on the interlayer insulating film and the contact electrodes 19a, 19b, and 19c. Thereby, the transistor 20 shown in FIGS. 7A and 7B is completed.

(Other embodiments)
In the first and second embodiments, the BOX layer 1 corresponds to the “insulating layer” of the present invention, and the SOI layer 2 corresponds to the “semiconductor layer” of the present invention. The transistor 10 corresponds to the “partially depleted transistor” of the present invention. Further, the impurity layers 17 and 18 correspond to the “first impurity layer” of the present invention. The N type corresponds to the “first conductivity type” of the present invention, and the P type corresponds to the “second conductivity type” of the present invention.

In the first to second embodiments, the case where the “first conductivity type” of the present invention is the N type and the “second conductivity type” is the P type has been described. However, the present invention is not limited to this. The “first conductivity type” may be P-type, and the “second conductivity type” may be N-type.
For example, the transistor 10 described in the first embodiment may be a P-channel type. In such a configuration, the P-type impurity layer 17 forms an N-PN structure between the lower portion of the source 15 and drain 16 and the body region 2 to increase the resistance. During the operation of 10, the discharge and injection of charges from the neutral region to the source and drain can be suppressed, and the body potential can be stabilized. Therefore, the history effect can be suppressed in the transistor 10, and a high ON / OFF ratio and stable operation can be realized while suppressing an increase in the element area.

  DESCRIPTION OF SYMBOLS 1 ... BOX layer, 2 ... SOI layer (body region), 3 ... Element isolation layer, 5 ... Interlayer insulating film, 10, 20 ... Transistor (PD-SOI MISFET), 13 ... Insulating film, 14 ... Gate electrode, 15 ... Source, 16 ... drain, 17, 18 ... impurity layer (first impurity layer), 19a, 19b, 19c ... contact electrode, 31 ... side wall, 32, 33 ... second impurity layer.

Claims (6)

An insulating layer, a semiconductor layer formed on the insulating layer, and a partially depleted transistor formed on the semiconductor layer,
The transistor includes a gate electrode formed on the semiconductor layer via an insulating film;
A source or drain of a first conductivity type formed in the semiconductor layer below both sides of the gate electrode;
A first impurity region of a first conductivity type provided in a region located on both sides of the body region, which is a region of the semiconductor layer immediately below the gate electrode,
The semiconductor device according to claim 1, wherein the first impurity region is disposed at a position in contact with the body region and not in contact with the source / drain regions.   The semiconductor device according to claim 1, wherein the source or drain has an LDD region, and the first impurity region is disposed at a position not in contact with the LDD region.   The semiconductor device according to claim 1, wherein sidewalls on both side walls of the gate electrode have a sidewall structure. A method of manufacturing a semiconductor device having a partially depleted transistor in a semiconductor layer on an insulating film,
Forming an insulating film on the semiconductor layer;
Forming a gate electrode on the semiconductor layer via the insulating film;
Forming a first impurity region of a first conductivity type in a region located on both sides of a body region, which is a region of the semiconductor layer immediately below the gate electrode, and not in contact with a source or a drain;
Forming a source or drain in the semiconductor layer under both sides of the gate electrode;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of forming an LDD structure in the source or drain region. A method of manufacturing a semiconductor device according to claim 4,
Introducing an impurity into the semiconductor layer using the gate electrode as a mask before the step of forming the first impurity layer;
Forming sidewalls on both side walls of the gate electrode, and
5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step of forming the source or drain, impurities are introduced into the semiconductor layer using the gate electrode and the sidewall as a mask.

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