JP2012221119A - Semiconductor integrated circuit design support device, design method, and design support program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate insertion of a CG cell that is not effective for reduction of power consumption regardless of a specific operation pattern.SOLUTION: In the present invention, an assertion description for verifying whether insertion of a clock gating circuit into a circuit to be verified is effective for reduction of the power consumption of the circuit to be verified is generated. On the basis of the assertion description, a formal simulation for verifying the operation of the circuit to be verified is performed. On the basis of the result of the formal simulation, an insertion constraint, in which whether the clock gating circuit should be inserted into the circuit to be verified is described, is generated.

Description

    The present invention relates to a semiconductor integrated circuit design support apparatus, a design method, and a design support program, and more particularly to a method for setting restrictions in logic design.

  In recent years, in order to realize low power consumption, a clock gating (Clock Gating: CG, also referred to as gated clock (GC)) technique that temporarily blocks unnecessary clock input to a flip-flop circuit has been applied. As a method of inserting a clock gating cell (hereinafter referred to as a CG cell) into a semiconductor device, there is a method of explicitly inserting it into an RTL (Register Transfer Level) description. In order to cope with this, automatic insertion during logic synthesis has become the mainstream.

  A logic synthesis tool automatically inserts a CG cell by automatically converting an enable signal of a flip-flop circuit (hereinafter referred to as F / F) according to an RTL description. Netlists generated by logically synthesizing RTL descriptions are not uniquely determined, and different netlists can be generated from the same RTL description. For example, the minimum necessary number of CG cells may be inserted in logic synthesis, or a useless CG cell without a low power consumption effect (gating effect) by gating may be inserted. In addition, in the case of automatic insertion according to the bit width of F / F according to the input constraint at the time of logic synthesis, CG cells are automatically inserted uniformly with respect to the bit width of F / F, so that there is no gating effect. A CG cell may also be inserted into / F. When a CG cell having no gating effect is inserted as described above, layout processing due to an increase in area or wiring congestion becomes severe, so that it is necessary to redo and correct logic synthesis. Therefore, a technique for efficiently inserting a CG cell effective for reducing power consumption is required.

  A technique for selectively inserting a CG cell having a power consumption effect is described in, for example, Japanese Patent Application Laid-Open No. 2002-92065 (see Patent Document 1). In Patent Document 1, a simulation according to a test vector is performed on an RTL description in which a correspondence relationship between an enable signal that is an operation condition of a flip-flop (hereinafter referred to as F / F) and the F / F is described. . Then, the active rate of the enable signal for the F / F is obtained based on the simulation result, and the F / F for inserting the CG cell is determined based on the active rate.

  In Patent Document 1, an F / F into which a CG cell is inserted is determined before logic synthesis, and a gated F / F (an F / F into which a CG cell is inserted) is reflected in the RTL description. For this reason, in logic synthesis, a CG cell is inserted only in the F / F selected based on the active rate, and the power consumption can be effectively reduced.

JP 2002-92065 A

  In Patent Document 1, an F / F for inserting a CG cell is determined using a simulation result according to a test vector. In the case of simulation using a test vector, only the active rate for a specific motion pattern is obtained. That is, in the technique of Patent Document 1, it is effective to insert a CG cell for a circuit that can be determined to have a power consumption reduction effect in a specific operation. However, an appropriate determination as to whether or not to insert a CG cell cannot be made for a circuit whose power consumption reduction effect is not obtained by a specific operation pattern. For example, in the case of the specific operation pattern, even if the circuit seems to have no effect of reducing the power consumption and it can be determined that the CG cell should not be inserted, the CG cell is inserted in the case of another different operation pattern. This is because there is a possibility that an effect of reducing power consumption can be obtained. However, exhaustively simulating all patterns using test vectors is not realistic. Therefore, in the technique of Patent Document 1, only CG cells can be inserted based on the effect of reducing the power consumption when the circuit performs a specific operation, and the CG accurately reflecting the reduction in the power consumption of the circuit. There is a problem to be solved that a cell cannot be inserted.

  In order to solve the above problems, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention] The number / symbol used in [Form] is added. However, the added numbers and symbols should not be used to limit the technical scope of the invention described in [Claims].

  A design support device for a semiconductor integrated circuit according to the present invention includes an assertion generation unit, a simulation unit, and a clock gating effect constraint generation unit. The assertion generation unit generates an assertion description for verifying whether the effect of reducing the power consumption of the verification target circuit can be obtained by inserting the clock gating circuit into the verification target circuit. The simulation unit performs a formal simulation for verifying the operation of the circuit to be verified based on the assertion description. The clock gating effect constraint generation unit generates an insertion constraint that describes whether or not the clock gating circuit should be inserted into the circuit to be verified, based on the result of the formal simulation.

  The semiconductor integrated circuit design method according to the present invention provides an assertion description for verifying whether an effect of reducing power consumption of a circuit to be verified can be obtained by inserting a clock gating circuit into the circuit to be verified. Based on the steps generated by the assertion generation unit, the formal simulation unit verifies the operation of the circuit to be verified based on the assertion description generated by the assertion generation unit, and the clock based on the result of the formal simulation. And a step of generating an insertion constraint describing whether or not the clock gating circuit should be inserted into the circuit to be verified.

  The above-described semiconductor integrated circuit design method is preferably realized by a design support program executed by a computer.

  In the present invention, since the insertion effect of clock gating is verified by assertion-based verification, the insertion location of clock gating can be determined without using a specific operation pattern.

  Therefore, according to the present invention, it is possible to eliminate insertion of a CG cell that is not effective in reducing power consumption without depending on a specific operation pattern.

FIG. 1 is a diagram showing the configuration of a semiconductor integrated circuit design support apparatus according to the present invention. FIG. 2 is a functional block diagram in the embodiment of the design support apparatus according to the present invention. FIG. 3A is a flowchart showing an example of a method for designing a semiconductor integrated circuit according to the present invention. FIG. 3B is a flowchart showing an example of a method for designing a semiconductor integrated circuit according to the present invention. FIG. 4 is a diagram showing an example of the structure of verification point information according to the present invention. FIG. 5 is a diagram showing an example of a power consumption result log used as verification point information according to the present invention. FIG. 6 is a diagram showing an example of verification point information according to the present invention. FIG. 7 is a diagram showing an example of an assertion description according to the present invention. FIG. 8 is a diagram showing an example of a logical synthesis result (net list) when the CG insertion restriction script according to the present invention is not used. FIG. 9 is a diagram showing an example of a logical synthesis result (net list) when a CG insertion restriction script according to the present invention is used. FIG. 10 is a diagram showing another example of the logic synthesis result (net list) when the CG insertion restriction script according to the present invention is used. FIG. 11A is a flowchart showing another example of the method for designing a semiconductor integrated circuit according to the present invention. FIG. 11B is a flowchart showing another example of the method for designing a semiconductor integrated circuit according to the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same or similar reference numerals indicate the same, similar, or equivalent components.

(Overview)
A semiconductor integrated circuit design support apparatus (hereinafter referred to as a design support apparatus) according to the present invention adds formal assertion (also referred to as formal verification) by adding an assertion description (assertion monitor) to a DUT (Device Under Test) based on RTL description. The CG cell to be inserted in the logic synthesis is determined based on the simulation result. In the formal simulation, since the operation of the part to which the assertion monitor is added is verified by the assertion description, all the operations of the verification target part can be comprehensively verified. For this reason, it is possible to determine the CG cell to be inserted before logic synthesis without depending on a specific operation pattern.
(Constitution)
With reference to FIG.1 and FIG.2, the structure of the design support apparatus 10 by this invention is demonstrated. FIG. 1 is a configuration diagram of an embodiment of a design support apparatus 10 according to the present invention. The design support apparatus 10 includes a CPU 11, a RAM 12, a storage device 13, an input device 14, and an output device 15 that are connected to each other via a bus 16. The storage device 13 is an external storage device exemplified by a hard disk and a memory. The input device 14 outputs various data to the CPU 11 and the storage device 13 by being operated by a user such as a keyboard and a mouse. The output device 15 is exemplified by a monitor and a printer, and outputs the layout result of the semiconductor device output from the CPU 11 so as to be visible to the user.

  The storage device 13 stores DUT information 20, a restriction script 30, and a design support program 40. In response to the input from the input device 14, the CPU 11 executes the design support program 40 in the storage device 13, determines a CG cell to be inserted (generates a CG insertion constraint), and creates a netlist by logic synthesis. . At this time, various data and programs from the storage device 13 are temporarily stored in the RAM 12, and the CPU 11 executes various processes using the data in the RAM 12. Note that the CG insertion constraint generation process and the logic synthesis process may be realized by different programs and apparatuses.

  The DUT information 20 is a design target circuit (DUT) based on the RTL description. Here, the RTL description of the logic synthesis target circuit is recorded as the DUT information 20. The DUT information 20 is preferably an RTL description used in general logic synthesis. The restriction script 30 is a script that defines the use conditions and restrictions of the DUT. For example, there are operating conditions (temperature and operating voltage) of a DUT (semiconductor integrated circuit) as usage conditions, and there are a clock frequency and a delay value as constraints. As the constraint script 30, a script in which usage conditions and constraints used in general logic synthesis are defined is preferably used.

  The design support program 40 is executed by the CPU 11 to realize the functions of the assertion generation unit 41, the simulation unit 42, the CG insertion constraint generation unit 43, and the logic synthesis unit 44 shown in FIG.

  The assertion generation unit 41 extracts an assertion verification target from the DUT information 20 and uses an assertion description (assertion monitor) defining an operation specification of the monitoring target as an assertion language (example: SVA (System Verilog Assertion) or PSL (Property Specification Language). )). The generated assertion monitor is recorded in the storage device 13 as an assertion description file 22. The simulation unit 42 is a logic simulator for notifying the designer of an output when a signal is input to a circuit to be verified with a signal value or RTL description set by the designer as an input, or the power consumption of the circuit to be verified. This is realized by the CPU 11 executing a program such as a power consumption analysis tool that outputs a value and notifies the designer. As will be described later, the simulation unit 42 may perform formal verification (formal simulation). In this case, the simulation unit 42 functions as a hardware resource that executes formal verification when the CPU 11 executes the formal verification tool. In the formal verification, unlike the logic simulator and power consumption analysis tool described above, the signal value corresponding to the specific signal value is not output as the output result based on the specific signal value designated by the designer. In other words, formal verification is performed by mathematically analyzing and proving the result that the circuit may output from the RTL description of the circuit to be verified. For example, the simulation unit 42 derives a state transition diagram of a circuit to be verified from the RTL description, and derives all combinations that become outputs of the circuit by following the state transition diagram. That is, the formal verification is characterized in that a comprehensive analysis result that does not depend on the signal value specified by the designer can be obtained unlike the logic simulator and the power consumption analysis tool described above. Hereinafter, in this specification, a flip-flop or a register including a plurality of flip-flops is exemplified as a specific example of the circuit to be verified. However, the circuit to be verified is not limited to this, and other circuits may be used. There may be.

  The simulation unit 42 generates DUT information for simulation by inserting an assertion monitor into the DUT information 20 and performs a formal simulation on the DUT information. The simulation unit 42 may perform a dynamic simulation according to a predetermined test pattern before the formal simulation. Here, the dynamic simulation means a simulation executed by the above-described logic simulator, and what kind of signal value the verification target circuit outputs according to the signal value designated by the designer. To analyze. This point will be described in the second embodiment.

  The CG insertion constraint generation unit 43 sets CG cells to be inserted into the DUT based on the formal simulation result (sets CG cells that are prohibited from being inserted into the DUT). Alternatively, the CG insertion constraint generation unit 43 sets the position of the CG cell to be inserted into the DUT based on the formal simulation result (sets the position of the CG cell that is prohibited from being inserted into the DUT). Based on this setting, the CG insertion constraint generation unit 43 generates a CG cell constraint script to be inserted into the DUT (inhibition of insertion into the DUT), and records it in the storage device 13 as the CG insertion constraint script 24.

  The logic synthesis unit 44 analyzes the DUT information 20 (RTL description) and converts it into a logical expression to generate a netlist 25, as in a general logic synthesis tool. At this time, circuit optimization (for example, logic compression and circuit area reduction) is performed according to the constraint script 30 and the CG insertion constraint script 24. In the present invention, CG cells that are unnecessary for reducing power consumption are deleted by optimization according to the CG insertion restriction script 24 (or only CG cells necessary for reducing power consumption are selectively inserted).

  With the configuration as described above, the design support apparatus 10 according to the present invention performs a formal simulation using DUT information (RTL description) in which an assertion description (assertion monitor) is inserted, and is unnecessary for reducing power consumption based on the result. Constraints for eliminating unnecessary CG cells are generated. Further, by using this restriction in logic synthesis, it is possible to create a net list from which CG cells unnecessary for reducing power consumption are eliminated.

(Operation)
First Embodiment Hereinafter, a first embodiment of a semiconductor integrated circuit design method according to the present invention will be described with reference to FIGS. 3A to 8. 3A and 3B are flowcharts showing an example of a method for designing a semiconductor integrated circuit according to the present invention.

  The assertion generation unit 41 first analyzes the DUT information 20 and specifies an assertion verification point that is an insertion position of the assertion monitor (step S101). Specifically, the assertion generation unit 41 analyzes the DUT information 20 and specifies a place where an assertion monitor is inserted, that is, a place where an operation is verified by an assertion description (assertion verification point). In the present invention, a monitoring point is a location where a CG cell can be inserted in logic synthesis. Therefore, the assertion generation unit 41 specifies a clock gating condition (for example, an enable signal) that is a condition for inserting a CG cell in logic synthesis as an assertion verification point.

  The assertion verification point specified in step S101 is recorded in the storage device 13 as verification point information 21. FIG. 4 is a diagram showing an example of the structure of the verification point information 21 according to the present invention. The logic synthesizer 44 identifies the location where the CG cell is inserted by a clock signal, an enable signal, and a register (or F / F). For this reason, the assertion generation unit 41 extracts at least a clock signal, an enable signal, and information (clock identifier 211, enable identifier 212, register identifier 213) indicating a register (or F / F) from the DUT information 20, and supports each of them. In addition, it is recorded as verification point information 21. As the verification point information 21, at least the combination of the enable signal and the register (or F / F) may be extracted, and therefore the clock identifier 211 can be omitted.

  For example, a general power consumption analysis tool is preferably used as the verification point information 21 extraction tool. Specifically, the SpyGlass-Power tool by Alenta is used. For this purpose, first, the CPU 11 accesses the storage device 13 to read and execute the logic simulator in the design support program 40 in order to realize the function of the logic simulator described above. Based on the execution, the simulation unit 42 obtains the output result of the circuit to be verified, for example, the register that operates based on the enable signal, based on the signal value and RTL description specified by the designer. Next, the CPU 11 reads out and executes a power consumption analysis tool included in the design support program 40, for example, the above-described SpyGlass-Power tool from the storage device 13. The simulation unit 42 receives the execution result of the logic simulator as input and analyzes the power consumption of the circuit to be verified. Here, the power consumption result created by executing the power consumption analysis tool indicates an enable signal, a register related to the enable signal, and a clock signal input to the register. The power consumption analysis tool is preferably used as an extraction tool for the verification point information 21 in the present invention, because it extracts all combinations of registers related to enable signals in the DUT regardless of the register operation rate (Duty-Cycle). obtain. The assertion generation unit 41 can exhaustively extract the verification point information 21 from the DUT information 20 by using such a tool. For example, the simulation unit 42 writes and stores the execution result of the power consumption analysis tool in the storage device 13 and outputs it via the output device 15 to notify the designer of the execution result.

  FIG. 5 is a diagram illustrating an example of a power consumption result log obtained by the SpyGlass-Power tool. Referring to FIG. 5, the power consumption result log includes a register size related to the clock signal (Clock) and the enable signal (Enable), an operation rate (Duty-Cycle (Enable)), an effective clock ( Activity (Clock)), power consumption when there is no gating (Power (w / o gating)), power consumption when gating (Power (gating)), power consumption difference between presence / absence of gating (Power (w)) Difference)), module hierarchy (register location (Hierarchy)), and register identifier (Registers Affected). Here, the register identifier in the upper row is described as “¥ r1_reg [0:35]”, and the register identifier in the lower row is described as “¥ r3_reg [0:35]”. These mean the names of the registers. In this example, the register “r1” can store a 36-bit value. Specifically, the register “r1” has 36 flip-flops (F / F) which are 1-bit storage elements. The same applies to the register named “r3”. An enable signal is input to each of these F / Fs. Note that the circuit described in the register identifier is a circuit to be verified by the power consumption analysis tool. In the following, as a specific example, it is assumed that these registers are circuits to be verified.

  The clock signal (Clock) in FIG. 5 is a clock signal output from an oscillation circuit such as a PLL provided in the semiconductor integrated circuit, for example, and is transmitted to each circuit in the semiconductor integrated circuit via the clock tree. . In FIG. 5, there are two descriptions of “mc_top.clk_i 211”. “Mc_top.clk_i” is the name of the clock signal. Therefore, these clock signals having the same name have the same frequency, and are clock signals that toggle in the same phase if there is no clock skew. In this example, the clocks input to the registers “r1” and “r3” are both “mc_top.clk_i 211”, and the same clock signal is input to each F / F of each register.

  In the column of the operation rate (Duty-Cycle (Enable)), “0.00” is described in the upper row and “1.00” is described in the lower row. Here, a clock signal and an enable signal are input to the clock gating circuit. When the enable signal is active, the gating circuit outputs a pulse of the clock signal to the subsequent circuit, and when the enable signal is inactive, the gating circuit does not output the pulse. The simplest example of such a clock gating circuit is a two-input AND gate that inputs a clock signal and an enable signal. If the value of the operation rate (Duty-Cycle (Enable)) is “0.00”, this indicates that the enable signal is always inactive during the simulation (power supply analysis simulation). If it is 1.00 ", it means that the enable signal is always active during the simulation (power supply analysis simulation). In FIG. 5, only two types of values “0.00” and “1.00” are shown as the values of the operation rate, but in reality, “0.3”, “0.5”, “0” .7 "may be used. The operation rate value is an input to the logic simulator executed by the CPU 11 before the power consumption analysis simulation, and is a signal value set by the designer. Further, it is understood that the enable signal input to the upper row, that is, the register “r1” is “enable 1”, and the enable signal input to the lower row, that is, the register “r3” is “enable 2”. . Since the names are different, these are separate enable signals. Note that the enable signal may be generated as a result of a logical operation of a plurality of logic circuits due to the circuit configuration. For example, “enable 1” may be generated as a result of an AND operation of one bit of a signal designating an address for a memory and a write enable signal in an actual semiconductor integrated circuit. The same applies to “enable 2”.

  The effective clock (Activity (Clock)) in FIG. 5 indicates the frequency of the clock signal actually input to the circuit to be verified, in this description as a specific example, the registers “r1” and “r3”. In the example of FIG. 5, both the register “r1” and the register “r3” have values of “2.00”. When the value of the effective clock is “2.00”, it means that the maximum frequency in the semiconductor integrated circuit including the registers “r1” and “r3” is input to the registers “r1” and “r3”. When the value of the effective clock is “1.00”, a frequency that is ½ of the maximum frequency described above is input to the circuit to be verified.

  As for the power consumption (Power (w / o gating)) when there is no gating, it can be seen that the registers “r1” and “r3” both consume “186 μW”. On the other hand, when looking at the power consumption (Power (gating)) when gated, the register r1 consumes 18.7 μW while the register “r3” consumes “800 μW”. ing. This means that the register “r1” has an operation rate (Duty-Cycle (Enable)) value of “0.00”, so that power consumption can be effectively suppressed by inserting a gating circuit. Yes. On the other hand, since the register “r3” has an operation rate value of “1.00” and the enable signal is always active, the gating circuit uses the power consumed by the register “r3” even when the gating circuit is inserted. Since the power consumed by itself is added, the value is increased to “800 μW”. The power consumption difference (Power (Difference)) between the presence and absence of gating is the difference between the power consumption when there is no gating (Power (w / o gating)) and the power consumption when gating (Power (gating)). is there.

  The module hierarchy (register location (Hierarchy)) describes the name of the module, and the name of the module to which the registers “r1” and “r3” belong can be found from this description.

  Since the power consumption analysis tool performs power consumption simulation using a test pattern as in the prior art, specific simulation results such as the value of power consumed by the circuit to be verified are not used in the present invention. However, the assertion generation unit 41 according to the present invention uses the clock identifier 211, the enable identifier 212, and the register identifier 213 extracted as a result of the execution of the power consumption analysis tool for the verification point information 21. For example, the assertion generation unit 41 extracts the verification point information 21 illustrated in FIG. 6 from the power consumption analysis result illustrated in FIG. Here, a combination of a clock identifier 211 “mc_top.clk_i”, an enable identifier 212 “enable 1”, a register identifier 213 “¥ r1_reg [0:35]”, a clock identifier 211 “mc_top.clk_i”, an enable identifier 212 “enable”. 2 ”and the register identifier 213“ ¥ r3_reg [0:35] ”are extracted as the verification point information 21.

  It should be noted that a module hierarchy (Hierarchy) for specifying the register position may be extracted as the verification point information 21. In the example shown in FIG. 5, “mc_top. Indicating the location of the register“ ¥ r1_reg [0:35] ”. u3. “0” and “mc_top.u3.u0” indicating the position of the register “¥ r3_reg [0:35]” may be extracted as the verification point information 21, respectively.

  In this embodiment, the extraction method of the verification point information 21 using a general power consumption analysis tool is taken as an example. However, the present invention is not limited to this, as long as combinations of all enable signals and related registers can be extracted from the DUT information 20. Absent. Extraction of the verification point information 21 using the power consumption analysis tool described above is an example, and the present invention can be clearly understood without limiting the description of the claims to using the result of the power consumption analysis tool. is there.

  Subsequently, the assertion generation unit 41 generates a CG effect check assertion using the verification point information 21 (step S102). The assertion for checking the CG effect here is more generally verified whether the effect of reducing the power consumption of the circuit to be verified can be obtained by inserting the clock gating circuit into the circuit to be verified. Means an assertion description for In the CG effect check assertion, the operation specification (expected operation) of the related register according to the enable signal is defined in order to verify the power saving effect of the CG cell. The effect of reducing power consumption by the CG cell can be verified by whether or not the output of the related register is generated (signal change) in response to the generation of the enable signal (signal change). Specifically, verifying whether the signal value output from each F / F of the register to be verified changes when the signal value of the enable signal changes to an active logic value. Thus, it can be verified whether each F / F can effectively reduce power consumption by inserting a gating circuit. Assertion-based verification is performed individually for each F / F of the register, but the entire register may be the target of verification. In the following description, for ease of understanding, a specific description will be given assuming that each F / F is verified. The active logic value means a high level (1) logic value if the circuit is positive logic, and a low level (0) logic value if the circuit is negative logic.

  For example, if the value of a signal output from each F / F of the register corresponding to the enable signal does not change even when the enable signal transitions to an active logic value, the gating effect for each F / F cannot be expected. In this case, it can be determined that “a low power effect due to clock gating on each F / F of the register cannot be expected (hereinafter referred to as“ no CG effect ”).” Alternatively, the signal value of the enable signal is active logic. When the value of the signal output from each F / F of the corresponding register changes in response to the transition to the value, the operation of each F / F can be stopped by gating. It can be determined that a low power effect due to clock gating can be expected (hereinafter referred to as “with CG effect”). Since assertion-based verification is performed for each F / F, the F / F configuring the register corresponding to the enable signal In some cases, the F / F output value of at least one portion of the F / F does not change and the F / F output value of the other portion changes. In that case, even if the gating circuit is inserted into the F / F of the part where the output value has not changed, there is no effect of suppressing power consumption, and the gating circuit is inserted into the F / F of the other part. Therefore, it can be determined that there is an effect of suppressing power consumption.

  The F / F whose output value does not change even when the enable signal transitions to an active logic value is redundantly provided in design, for example, and is not used or used in actual circuit operation. This is a register with a low frequency. As a specific example, each F / F constituting the counter circuit can be considered. When developing a new product of a semiconductor integrated circuit, the development period is shortened by diverting the functional circuit used in the previous product. At this time, there may be no problem if the new product repeats counting up to the number of digits smaller than the number of digits counted by the counter circuit mounted in the previous product. In that case, the F / F that holds the value of the upper bit of the counter circuit in the new product always holds a logical value of 0, and the held value never changes from 0 to 1. In such an F / F, it is not necessary to insert a clock gating circuit. If it is inserted, the power consumption of the entire chip due to the power consumed by the gating circuit and the chip area will be increased. . In addition to the above example, a control signal having a fixed signal value needs to be output from the F / F for circuit operation, and there may be an F / F that always holds a fixed value. The present invention prevents such an unnecessary gating circuit from being inserted into the F / F.

  FIG. 7 is a diagram showing an example of an assertion description according to the present invention. In the assertion description “AST1”, “the enable signal Enable (enable 1) transitions to an active logic” is defined as an operation condition, and “someday the register“ r1_reg [0] ”is output as an expected operation (expected specification). It is specified that the value of the signal changes. AST1 is a description for determining whether or not the 0th bit F / F of the register “r1” has a gating effect. Here, the implication operator “| =>” means that the property verification (right side) is performed when the preceding (left side) sequence (condition) is satisfied. Here, the enable signal (enable) is used. It is defined as a condition that 1) transitions to active logic. The cycle count “## [0: $]” on the right side indicates the time until the signal value output from the register r1_reg [0] changes. Here, an infinite time is defined. The same applies to “AST2”. For the 36-bit register “r1”, the assertion generation unit 41 generates “AST36” from “AST1” as an assertion description.

  In the example shown in FIG. 7, the period from the transition of the signal value of the enable signal to the transition of the value of the output signal of the register is defined as infinite. However, the present invention is not limited to this, and a predetermined period may be designated. .

  The created assertion description (assertion monitor) is linked to the verification point information 21 and recorded in the storage device 13 as an assertion description file 22.

  The simulation unit 42 performs a formal simulation for verifying the operation of the circuit to be verified based on the assertion description generated by the assertion generation unit 41. Specifically, the simulation unit 42 executes a formal simulation for the DUT using the DUT information 20, the verification point information 21, and the assertion description file 22 (step S103). Specifically, the CPU 11 accesses the storage device 13 and reads the formal verification tool included in the design support program 40 from the storage device 13 and executes it. When the CPU 11 executes the formal verification tool, the CPU 11 becomes the simulation unit 42 that executes the formal verification. As an example, the simulation unit 42 inserts the assertion description file 22 into the DUT information 20 to create DUT information for simulation. At this time, the simulation unit 42 inserts the assertion description extracted from the assertion description file 22 read from the storage device 13 into the verification point information 21 associated with the assertion description. As a result, an assertion monitor for verifying the gating effect is inserted into the verification point in the DUT information 20 specified in step S101. The simulation unit 42 executes a formal simulation using the DUT information in which the assertion description is inserted. The formal verification executed here can be realized by, for example, a general property checking method. That is, in the present invention, the verification target circuit is verified by formal verification based on the assertion description described above. Formal verification is not a method in which the designer gives a specific input signal to the circuit to be verified as described above, but because all output results of the circuit are mathematically proved by a method based on a state transition diagram. It is. Specifically, in the present embodiment, the output value of each F / F (or the output value of the register) derived by formal verification is verified based on the assertion description described above. That is, when the signal value of the enable signal transitions and changes to an active logical value from the result of formal verification, the signal value output from the register to be verified or each F / F constituting the register changes. It is verified whether or not to do so. As a result, verification that is not a determination based on a limited output result corresponding to a specific input pattern can be realized. The assertion description may not be inserted into the DUT information 20. In this case, the DUT information 20 and the assertion description are separately input to the simulation unit 42 that performs formal verification.

  The simulation unit 42 inputs the output value of the register “r1”, which is the circuit to be verified, or the output value of each F / F constituting the register “r1” to the register “r1” or each F / F. It is verified by formal verification whether the enable signal changes when transitioning to active logic.

  Next, the CPU 11 performs the CG effect determination by reading the design support program 40 from the storage device 13 and executing it. In this case, the CPU 11 serves as a clock gating effect constraint generation unit that generates an insertion constraint that describes whether or not a clock gating circuit should be inserted into a circuit to be verified based on the result of the formal simulation. More specifically, when the design support program 40 is executed, the CPU 11 becomes the CG insertion constraint generation unit 43 and realizes the CG effect determination. The CG insertion constraint generation unit 43 performs CG effect determination based on the formal simulation result (step S104). Here, the CG effect determination is performed for each verification point subjected to the assertion verification. For example, when the entire register having a plurality of F / Fs is used as a verification point, CG effect determination is performed for the entire register. When each of a plurality of F / Fs is used as a verification point, the CG effect is determined for each F / F. A determination is made.

  For example, if the register (F / F) “¥ r1_reg [0: 1]” (output) does not change even when the enable signal “enable 1” changes to an active logical value, the CG insertion constraint generation unit 43 The register (F / F) “¥ r1_reg [0: 1]” is determined to have no CG effect. Alternatively, when the register “¥ r1_reg [0: 1]” (output) changes when the enable signal “enable 1” changes, the CG insertion constraint generation unit 43 registers the register (F / F) “¥ r1_reg [0]. : 1] ”is determined to have a CG effect.

  The CG insertion constraint generation unit 43 sets a register (F / F) to insert a CG cell (or a register (F / F) to prohibit insertion of a CG cell) according to the CG effect determination result of step S104, as a CG effect register. The file 23 is recorded in the storage device 13 (step S105). Here, the CG insertion constraint generation unit 43 records the register (F / F) determined to have the CG effect in the CG effect register file 23 as a register to be inserted into the CG cell. Alternatively, the CG insertion constraint generation unit 43 records the register (F / F) determined as having no CG effect in the CG effect register file 23 as a register for prohibiting the insertion of the CG cell, and writes it in the storage device 13. The storage device 13 stores the CG effect register file 23.

  The CG insertion constraint generation unit 43 creates the CG insertion constraint script 24 based on the CG effect register file 23 (step S106). The CG insertion constraint script 24 is used as a CG cell insertion constraint during logic synthesis. The CG insertion restriction script 24 includes information for specifying a register (F / F) for inserting a CG cell or information for specifying a register (F / F) for prohibiting insertion of a CG cell.

  The logic synthesis unit 44 performs logic synthesis based on the DUT information 20, the constraint script 30, and the CG insertion constraint script 24, and generates a net list 25 for the DUT (step S107). The logic synthesis unit 44 selectively inserts CG cells according to the CG insertion restriction script 24 or eliminates unnecessary insertion of CG cells. As a result, the number of CG cells to be inserted can be reduced compared to the automatic insertion of a number of CG cells corresponding to the bit width of the register.

  With reference to FIGS. 8 to 10, the effect of reducing CG cells by the design method according to the present invention will be described.

  FIG. 8 is a diagram showing an example of a logical synthesis result (net list) when the CG insertion restriction script 24 according to the present invention is not used. Referring to FIG. 8, a register 100 is a 4-bit register specified by a clock identifier 211 “mc_top.clk_i” enable identifier 212 “enable 1” and a register identifier 213 “¥ r1_reg [0: 4]”. F / Fs 111, 112, 113, and 114 are provided. Here, when CG cells capable of driving a maximum of three F / Fs are inserted without using the CG insertion restriction script 24, at least two CG cells are inserted into the register 100. For example, as shown in FIG. 8, the CG cell 122 is inserted into the F / Fs 111 and 112 and the CG cell 121 is inserted into the F / Fs 113 and 114 in the logic synthesis.

  On the other hand, when logic synthesis is performed according to the CG insertion restriction script 24 according to the present invention, insertion of a CG cell into a register (F / F) whose output does not fluctuate even if the enable signal changes is prohibited. The number of CG cells to be performed can be reduced. FIG. 9 is a diagram showing an example of a logical synthesis result (net list) when the CG insertion restriction script 24 according to the present invention is used. Here, an example of a logic synthesis result when insertion of a CG cell into the F / F 111 is prohibited by the CG insertion restriction script 24 is shown. When the structure of the register 100 and the drive capability of the CG cell are the same conditions as in the example shown in FIG. 8, one CG cell 120 is inserted into the F / Fs 112 to 114 other than the F / F 111 in the logic synthesis. In the example of FIG. 9, one CG cell is reduced compared to FIG. In this way, by controlling the insertion of CG cells for each F / F, the number of CG cells to be inserted into the register can be reduced.

  FIG. 10 is a diagram showing another example of the logic synthesis result (net list) when the CG insertion restriction script 24 according to the present invention is used. Here, an example of a logic synthesis result when insertion of CG cells into the entire register 100 is prohibited by the CG insertion restriction script 24 is shown. In this case, since no CG cell is inserted into the register 100, two CG cells are reduced compared to FIG.

  As described above, according to the present invention, by specifying a register (or F / F) having no CG effect by assertion-based verification and prohibiting insertion of a CG cell into the register (or F / F), Unnecessary CG cells that can be inserted during logic synthesis can be eliminated. Thus, by eliminating unnecessary insertion of CG cells, the circuit area of the semiconductor integrated circuit can be reduced. Further, by reducing useless CG cells, wiring congestion is also reduced, so that layout processing is facilitated. Furthermore, since logic synthesis can be performed while eliminating CG cells that are not effective in reducing power consumption, back-end processing for reducing CG cells is not required, and the design TAT of the layout semiconductor integrated circuit can be shortened.

Second Embodiment Next, a second embodiment of a semiconductor integrated circuit design method according to the present invention will be described with reference to FIGS. 11A and 11B. In the second embodiment, the verification points to be subjected to the formal simulation can be narrowed down by performing a dynamic simulation with a test pattern according to the user's specifications before the formal simulation in step S103. FIG. 11A and FIG. 11B are flowcharts showing an example of the design method according to the present invention using dynamic simulation together.

  Referring to FIG. 11A, the assertion generation unit 41 generates the assertion description file 22 by the processing in steps S101 and S102 similar to the operation shown in FIG. 3A.

  In the simulation unit 42 of this example, the simulation unit 42 executes a dynamic simulation for verifying the operation of the circuit to be verified with respect to a specific input signal, and whether or not the effect of reducing the power consumption can be obtained by the result of the dynamic simulation. Formal simulation is executed only for circuits where it is unknown. More specifically, before the formal simulation, the DUT information 20, the verification point information 21, the assertion description file 22, and the test pattern (not shown) are used to execute a dynamic simulation on the DUT (step S201). Specifically, the CPU 11 reads and executes the logic simulator stored in the storage device 13. The simulation unit 42 realized by the CPU 11 by executing the logic simulator inserts the assertion description file 22 into the DUT information 20 and creates DUT information for simulation. At this time, the simulation unit 42 inserts the assertion description extracted from the assertion description file 22 into the verification point information 21 associated with the assertion description. As a result, an assertion monitor for verifying the gating effect is inserted into the verification point in the DUT information 20 specified in step S101. The simulation unit 42 receives the DUT information 20 in which the assertion description is inserted and the test pattern as input, and executes a dynamic simulation for the verification target register (or F / F).

  The simulation unit 42 determines the CG effect based on the dynamic simulation result (step S202). Here, the CG effect determination is performed for each verification point subjected to the assertion verification according to the test pattern. Therefore, the determination result is a determination result for the verification point corresponding to the test pattern. The simulation unit 42 writes the determination result in the storage device 13. In step S202, the verification point (register) determined to have the CG effect has a CG effect at least during the operation corresponding to the test pattern, and thus can be set as a CG cell insertion target without a formal simulation. Therefore, the simulation unit 42 reads out the determination result obtained as a result of the dynamic simulation from the storage device 13, removes the verification point (register) determined to be effective in the dynamic simulation from the assertion verification target, and performs the next step A formal simulation is executed (step S103).

  The processing from step S103 to step S107 shown in FIG. 11B is the same as that in FIGS. 3A and 3B, but in this example, the register (F / F) that is subject to assertion verification is changed from the verification target according to the dynamic simulation result. Exclude and run formal simulation. In other words, only the assertion description narrowed down according to the result of the dynamic verification is added to the DUT information 20, and a formal simulation is performed on the DUT information. In formal simulation, only the narrowed assertion description (assertion monitor) needs to be verified, so that the verification time can be shortened.

  It should be noted that the assertion description (assertion monitor) used in the dynamic simulation and the assertion description (assertion monitor) used in the formal simulation are different from each other even if the same operation condition and operation specification are defined as long as the CG effect can be determined. Either of the operation specifications may be specified. For example, an assertion description that prescribes "when the enable signal changes, the register output changes" is used in dynamic simulation, and the assertion description that prescribes "the register output does not change when the enable signal changes" is formal. It may be used for simulation. In this case, in the dynamic simulation, a register whose register output changes when the enable signal changes is excluded from the formal verification target because of the CG effect.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. . In the above-described example, the assertion generation unit 41 has the functions of a logic simulator and a power consumption analysis tool for specifying an assertion verification point. However, the present invention is not limited to this, and the power consumption analysis output in other devices is possible. The verification point information 21 may be acquired using the result. That is, the design support program 40 may not include a logic simulator or a power consumption analysis tool.

10: Design support device 11: CPU
12: RAM
13: Storage device 14: Input device 15: Output device 16: Bus 20: DUT information 21: Verification point information 22: Assertion description file 23: CG effect register file 24: CG insertion restriction script 25: Net list 30: Restriction script 40 : Design support program 41: Assertion generation unit 42: Simulation unit 43: CG insertion constraint generation unit 44: Logic synthesis unit 100: Register 120 to 122: Clock gating cell (CG cell)
211: Clock identifier 212: Enable identifier 213: Register identifier

Claims (11)

An assertion generation unit for generating an assertion description for verifying whether or not an effect of reducing power consumption of the circuit to be verified can be obtained by inserting a clock gating circuit into the circuit to be verified;
Based on the assertion description, a simulation unit that performs a formal simulation for verifying the operation of the circuit to be verified;
Based on the result of the formal simulation, a clock gating effect constraint generator for generating an insertion constraint that describes whether or not a clock gating circuit should be inserted into the circuit to be verified;
A design support apparatus comprising:   The simulation unit executes a dynamic simulation for verifying an operation of the circuit to be verified with respect to a specific input signal, and it is unclear whether the effect of reducing the power consumption can be obtained also based on the result of the dynamic simulation. The design support apparatus according to claim 1, wherein the formal simulation is executed only for a circuit.   The design support apparatus according to claim 1, further comprising a logic synthesis unit that performs logic synthesis of a circuit including the circuit to be verified based on the insertion constraint.   The assertion generation unit generates an assertion description for verifying whether the value of the signal output from the verification target circuit changes when the value of the enable signal for the verification target circuit changes to an active logical value. The design support apparatus according to claim 1, wherein the design support apparatus is generated.   5. The design support apparatus according to claim 4, wherein the circuit to be verified is at least one flip-flop that operates in response to the enable signal, or a register including the plurality of flip-flops. An assertion generation unit generating an assertion description for verifying whether or not an effect of reducing power consumption of the verification target circuit can be obtained by inserting a clock gating circuit into the verification target circuit;
Based on the assertion description generated by the assertion generation unit, a formal simulation unit performs a formal simulation for verifying the operation of the circuit to be verified;
Based on the result of the formal simulation, the clock gating effect constraint generating unit generates an insertion constraint that describes whether or not a clock gating circuit should be inserted into the circuit to be verified; and
A method for designing a semiconductor integrated circuit, comprising: The simulation unit executing a dynamic simulation for verifying an operation of the circuit to be verified with respect to a specific input signal;
The simulation unit executes the formal simulation only for a circuit whose unknown whether or not the effect of reducing the power consumption can be obtained according to the result of the dynamic simulation;
The semiconductor integrated circuit design method according to claim 6, further comprising:   The method for designing a semiconductor integrated circuit according to claim 6, further comprising a step of performing logic synthesis of a circuit including the circuit to be verified by a logic synthesis unit based on the insertion constraint.   The assertion description is an assertion description for verifying whether the value of the signal output from the verification target circuit changes when the value of the enable signal for the verification target circuit changes to an active logical value. The method of designing a semiconductor integrated circuit according to claim 6.   10. The semiconductor integrated circuit according to claim 9, wherein the circuit to be verified is at least one flip-flop that operates in response to the enable signal, or a register including the plurality of flip-flops. Design method. Generating an assertion description for verifying whether or not an effect of reducing power consumption of the verification target circuit can be obtained by inserting a clock gating circuit into the verification target circuit;
Performing a formal simulation for verifying the operation of the verification target circuit based on the assertion description generated by the assertion generation unit;
A design support program for causing a computer to execute an insertion constraint that describes whether or not a clock gating circuit should be inserted into the circuit to be verified based on the result of the formal simulation.

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