JP2012216572A - Semiconductor chip, method of manufacturing the same, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip suitable for three-dimensional integration and having excellent electromagnetic interference tolerance, and to provide a semiconductor device using the semiconductor chip capable of achieving both high electromagnetic interference tolerance and a high processing capacity.SOLUTION: With respect to a semiconductor chip having an active element or a passive element, and a wiring part electrically connecting those elements, a conductive thin film is provided to coat the wiring part. Since the conductive thin film serves as a shield for shielding an unnecessary electromagnetic wave to the wiring part, the electromagnetic interference tolerance of the semiconductor chip is improved. In addition, by incorporating this semiconductor chip in a three-dimensional integrated semiconductor device, inter-chip crosstalk can be shielded even in the case that face-to-face connection between adjacent chips is performed.

Description

  The present invention relates to a semiconductor device, and more particularly to a structure and method for improving the electromagnetic interference resistance of a semiconductor chip, and a structure of a semiconductor device having excellent electromagnetic interference resistance.

  There is no end to the demands of electronic devices for miniaturization, high functionality, and multi-functionality. In order to meet this demand, semiconductor devices mounted on electronic devices are also required to be downsized and highly functional.

  A three-dimensional integrated semiconductor device in which a plurality of semiconductor chips and passive elements are three-dimensionally integrated is attracting attention as a method for realizing miniaturization, high functionality, and multi-function of a semiconductor device. This is because it is possible to easily obtain an effect equal to or higher than that of achieving a high function only with a single semiconductor chip.

  As a technique for realizing a three-dimensional integrated semiconductor device, a stacked die method and a package-on-package method have already been put into practical use. The stacked die method is a method in which a plurality of semiconductor chips are stacked three-dimensionally, and individual semiconductor chips and interposers are connected by bonding wires. The package-on-package method is a method of preparing a plurality of semiconductor chips mounted on an interposer, stacking them and then connecting them with solder balls.

  On the other hand, in recent years, development of a three-dimensional integrated semiconductor device using an electrode penetrating a semiconductor chip, which is also called 3D-SiP (3D-System in Package), has been actively performed (for example, Patent Document 1). In 3D-SiP, a plurality of stacked semiconductor chips are directly connected by a large number of through electrodes penetrating the semiconductor chips. Communication between semiconductor chips is much shorter than bonding wires and can be performed without going through an interposer, so the processing capability of the entire three-dimensional integrated semiconductor device can be reduced to the stacked die method or package-on-package method. Compared to a dramatic improvement.

FIG. 40 is an explanatory diagram illustrating a configuration of a typical 3D-SiP.
The 3D-SiP1 is configured by stacking three types of semiconductor chips 10, 110, and 210 including a circuit element 12 and a wiring portion 13 including wiring for electrical connection between the circuit elements in the thickness direction. ing. As for the semiconductor chip 10, the circuit element 12 on the surface is arrange | positioned downward in the figure. On the other hand, the semiconductor chips 110 and 210 are arranged so that the circuit element 12 faces upward in the drawing. That is, the semiconductor chips 10 and 110 are assembled in 3D-SiP1 with the surfaces on which the wiring portions 13 are formed facing each other. Such an assembly method is sometimes called face-to-face connection.

  The circuit element 12 formed in each semiconductor chip is an electrical component that realizes a predetermined circuit function. For example, an active element such as a transistor formed using a base substrate or a passive element formed on the surface of the base substrate.

  Inside each of the semiconductor chips 110 and 210, there are provided through electrodes 18 having one end exposed on the back surface (lower surface in the drawing) of the semiconductor chip. Further, a part of the wiring constituting the wiring part 13 is used for interconnection between the circuit element 12, the through electrode 18, and the through electrode 18. Each through electrode 18 is insulated from the semiconductor chip by an insulating film (not shown) formed so as to surround the through electrode.

  The semiconductor chip 10 and the semiconductor chip 110 and the semiconductor chip 110 and the semiconductor chip 210 are physically and electrically connected by the micro bumps 120, respectively. The micro bumps are electrically insulated from each other by an insulating material (not shown). Further, a pad 214 is present on the end surface on the chip back surface side of the through electrode 18 that penetrates the semiconductor chip 210. The 3D-SiP1 is electrically connected to the outside of the semiconductor chip via this pad.

  As described above, in a typical 3D-SiP, the wiring portions of the integrated semiconductor chip are close to each other with a distance of the micro bump height or a thickness of the semiconductor chip. In extreme cases, the distance is reduced to 20 μm or less.

Publication Gazette WO06 / 019156 JP 2006-179806 A Japanese Patent No. 3532788

  In such a structure in which a plurality of wiring portions are close to each other, crosstalk noise generated by propagation of an electromagnetic field radiated by a wiring included in one wiring portion to a wiring included in the other wiring portion increases. Powerful crosstalk noise causes a circuit element connected to the wiring carrying the noise to malfunction, thereby causing abnormal operation of the three-dimensional integrated semiconductor device.

  The invention disclosed in Patent Document 2 is exemplified as one type of structure for preventing crosstalk noise between semiconductor chips in a three-dimensional integrated semiconductor device. In the present invention, the metal film is formed on the surface of the semiconductor chip that is three-dimensionally integrated except for the portion where the wiring portion is formed. Further, the metal film is connected to a ground potential, and the metal film is used as a shield for shielding unnecessary electromagnetic waves.

  However, in the semiconductor device according to the invention, no protective means is applied to the surface on which the wiring portion is formed. Therefore, as in the semiconductor chips 10 and 110 in FIG. 40, when the semiconductor chips are integrated with the surfaces on which the wiring portions are formed facing each other, there is no way to avoid crosstalk noise.

  As a further example of a structure for preventing crosstalk noise between semiconductor chips in a three-dimensional integrated semiconductor device, the invention disclosed in Patent Document 3 is illustrated. In the present invention, a metal thin film is formed on the entire surface of the wiring portion for each of the three-dimensionally integrated semiconductor chips. This metal thin film serves as a bonding layer when the semiconductor chips are integrated by room temperature bonding technology, and also functions as a shield layer for suppressing radiation noise of the semiconductor chip. With the semiconductor device according to the present invention, it is possible to protect the wiring portion from unwanted electromagnetic waves.

  However, the semiconductor device based on the invention has a plurality of technical problems due to the room temperature bonding technique.

  The first problem is that the metal layer on the surface of the wiring layer must be formed extremely flat. The bonding layer in the room temperature bonding technology is required to have flatness on the order of submicrons. However, in a semiconductor chip, it is usual that unevenness of the order of μm exists on the surface of the wiring part. In addition, there is no process that can form a metal thin film flat on a surface with irregularities on the order of μm. Therefore, in order to put the invention into practice, in addition to the step of forming the metal layer on the surface of the wiring part, the step of flattening the metal layer is essential.

The second problem is that it becomes difficult to adopt a chip-to-wafer connection process.
In room temperature bonding technology, the cleanliness of the bonding surface greatly affects the bondability. Therefore, it is necessary to clean the surface immediately before joining.
This feature is not a problem for wafer-to-wafer connection. This is because many chips can be bonded together in a single process. On the other hand, when room temperature bonding technology is applied to chip-to-wafer connection, there is a concern that process costs will increase significantly. As described above, in the room-temperature bonding technique, a high cleanliness is required for the bonding surface, so that the surface on the wafer side needs to be kept clean throughout the entire chip bonding process. This can be done by performing the entire chip bonding process in a vacuum system. However, an apparatus for realizing the chip bonding process will be at an unacceptable level of the cost of the apparatus itself and the running cost.

  On the other hand, those skilled in the art will be able to devise a method of providing a conductor structure that shields unnecessary electromagnetic waves in the wiring portion as a measure against crosstalk between semiconductor chips. As an example, a method of providing a conductor pattern with a large area so as to cover a circuit element on any conductor layer of the wiring portion may be considered.

  However, with the above-described method, the wiring capacity of the wiring portion is reduced. This is an unavoidable problem as long as a conductor structure unnecessary for the function of the semiconductor chip is formed in the wiring portion. To solve this problem, there is no choice but to increase the number of conductor layers constituting the wiring portion. However, increasing the number of conductor layers in the wiring portion directly leads to an increase in the production cost of the semiconductor chip.

  In addition to this, in advanced semiconductor chips to which CMP (Chemical Mechanical Polishing) or copper wiring is applied, there is a technical difficulty in forming a conductor pattern with a large area. This is because, when a copper pattern of a large area is planarized by CMP, dishing (steps) that cause the copper layer surface to be concaved is generated, and subsequent processes are also hindered.

  The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor chip suitable for three-dimensional integration and having excellent electromagnetic interference resistance.

  According to a first aspect of the present invention for achieving the above object, a semiconductor substrate includes a base substrate including at least one layer of a semiconductor material, and one of an active element and a passive element on a surface of the base substrate. Formed by the circuit elements configured as described above and insulating layers and conductor layers alternately arranged on the surface where the circuit elements exist, external wiring for electrically connecting the circuit elements and the outside of the semiconductor chip An external connection pad connected to the external wiring and a conductive layer on which the external connection pad is formed. And a passivation layer made of an insulator having an opening that exposes the external connection pad to the outside of the chip, and further, with respect to the base substrate A conductive thin film made of at least one kind of metal or alloy is provided at a position separating the line portion and the passivation layer, and a portion corresponding to the external connection pad in the conductive thin film has a second opening. A semiconductor chip is provided with a portion.

  The invention according to claim 2 is the semiconductor chip according to claim 1, further comprising a through electrode penetrating the base substrate in the thickness direction.

The invention according to claim 3 is the semiconductor chip according to claim 2, including at least one of the following 1) and 2).
1) Internal wiring disposed in the wiring portion for electrically connecting the through electrode and the circuit element.
2) A through electrode pad that is formed in a layer farthest from the base substrate among the conductor layers forming the wiring portion and is not connected to the external wiring, and electrically connects the through electrode pad and the through electrode A through-wiring line disposed in the wiring portion in order to

  The invention according to claim 4 is the semiconductor chip according to claim 2 or 3, wherein the through electrode penetrates the wiring portion in the thickness direction in addition to the base substrate.

  The invention according to claim 5 is the semiconductor chip according to claim 2, wherein the inside of the through electrode is embedded with a conductive material.

  The invention according to claim 6 is the semiconductor chip according to claim 5, wherein the conductive material and the material forming the conductive thin film include a common material.

  According to a seventh aspect of the present invention, there is provided a base substrate including at least one layer of a semiconductor material among semiconductor chips, and a circuit element including at least one of an active element and a passive element on a surface of the base substrate. A wiring section formed of insulating layers and conductor layers alternately arranged on the surface on which the circuit element exists, and including an external wiring for electrically connecting the circuit element and the outside of the semiconductor chip; and the wiring section Of the conductor layer that is formed farthest from the base and covers the external connection pad connected to the external wiring and the conductor layer on which the external connection pad is formed, and the pad is outside the chip. And a passivation layer made of an insulator having an opening to be exposed, and at least one kind at a position separating the wiring part from the base substrate A semiconductor chip comprising a conductive thin film made of a conductor containing a semiconductor material, and a portion corresponding to the external connection pad in the conductive thin film is provided with a second opening. is there.

  The invention according to claim 8 is the semiconductor chip according to claim 7, wherein the semiconductor material contained in the conductive thin film exhibits a specific resistance of 1.5 Ω · cm or less.

  The invention according to claim 9 is the semiconductor chip according to claim 7 or 8, further comprising a through electrode penetrating the base substrate in the thickness direction.

The invention according to claim 10 is the semiconductor chip according to claim 9, wherein the wiring portion includes at least one of the following 1) and 2).
1) Internal wiring disposed in the wiring portion for electrically connecting the through electrode and the circuit element.
2) A through electrode pad that is formed in a layer farthest from the base substrate among the conductor layers forming the wiring portion and is not connected to the external wiring, and electrically connects the through electrode pad and the through electrode A through-wiring line disposed in the wiring portion in order to

  The invention according to an eleventh aspect is the semiconductor chip according to the ninth and tenth aspects, wherein the through electrode penetrates the wiring portion in a thickness direction.

  The invention according to a twelfth aspect is the semiconductor chip according to the ninth to eleventh aspects, characterized in that the inside of the through electrode is filled with a conductive material.

  The invention according to claim 13 is the semiconductor chip according to claim 12, wherein the conductive material and the material forming the conductive thin film include a common material.

  The invention according to claim 14 is the semiconductor chip according to claims 1 to 13, wherein the conductive thin film is provided for shielding unnecessary electromagnetic waves.

  The invention according to a fifteenth aspect is the semiconductor chip according to the first to fourteenth aspects, wherein the conductive thin film is connected to a portion of the wiring portion that supplies a power supply potential.

  According to a sixteenth aspect of the present invention, an electrical connection between the conductive thin film and the wiring portion for supplying the power supply potential is obtained by covering the external connection pad for supplying the power supply potential with the conductive thin film. The semiconductor chip according to claim 15, wherein the semiconductor chip is a semiconductor chip.

  The invention according to claim 17 is the semiconductor chip according to claim 1, wherein the conductive thin film is connected to a portion of the wiring portion that supplies a ground potential.

  According to an eighteenth aspect of the present invention, an electrical connection between the conductive thin film and the wiring portion for supplying the ground potential is obtained by covering the external connection pad for supplying the ground potential with the conductive thin film. The semiconductor chip according to claim 17, wherein the semiconductor chip is a semiconductor chip.

  The invention according to claim 19 is a three-dimensional integrated semiconductor device characterized in that a plurality of semiconductor chips including at least one of the semiconductor chips according to claims 1 to 18 are three-dimensionally integrated.

  The invention according to claim 20 is the three-dimensional integrated semiconductor device according to claim 19, wherein the second semiconductor chip electrically connected to the semiconductor chip according to claim 1 is made of a semiconductor material, The semiconductor chip according to claim 1, further comprising: a second base having at least one surface; and a second wiring portion formed on the surface of the second base substrate. The chip is integrated so that a surface of the base substrate on which the circuit elements are formed and a surface of the second base substrate on which the second wiring portion is formed are close to each other. Item 20. A three-dimensional integrated semiconductor device according to Item 19.

The invention according to claim 21 is a method for manufacturing a semiconductor chip, comprising the following steps (a) to (c).
(A) Of the semiconductor chip, the circuit element is composed of any one or more of an active element and a passive element, and is formed of insulating layers and conductor layers alternately arranged on the surface where the circuit element exists, A wiring portion including external wiring for electrically connecting the circuit element and the outside of the semiconductor chip and a conductor layer forming the wiring portion are formed in a layer farthest from the circuit element and connected to the external wiring. Preparing a semiconductor chip having external connection pads.
(B) forming a conductive thin film on the surface of the wiring portion;
(C) The process of providing a 2nd opening part in the part which has coat | covered the said external connection pad among electroconductive thin films.

According to a twenty-second aspect of the present invention, there is provided a semiconductor chip manufacturing method including the following steps (a) to (f):
(A) Of the semiconductor chip, the circuit element is composed of any one or more of an active element and a passive element, and is formed of insulating layers and conductor layers alternately arranged on the surface where the circuit element exists, A wiring part including external wiring for electrically connecting the circuit element and the outside of the semiconductor chip and a conductor layer forming the wiring part are formed in a layer farthest from the circuit element and connected to the external wiring. Preparing a semiconductor chip comprising the external connection pads.
(B) The process of processing the hole used as a penetration electrode in the said semiconductor chip.
(C) A step of forming an insulating film on the side surface of the hole.
(D) A step of forming a film of a conductive material inside the hole and conducting both surfaces of the semiconductor chip.
(E) A step of forming a conductive thin film on the surface of the wiring portion.
(F) The process of providing a 2nd opening part in the part which has coat | covered the said external connection pad among the said electroconductive thin films.

The invention according to claim 23 is a method for manufacturing a semiconductor chip, comprising the following steps (a) to (c).
(A) Of the semiconductor chip, the circuit element is composed of any one or more of an active element and a passive element, and is formed of insulating layers and conductor layers alternately arranged on the surface where the circuit element exists, A wiring part including external wiring for electrically connecting the circuit element and the outside of the semiconductor chip and a conductor layer forming the wiring part are formed in a layer farthest from the circuit element and connected to the external wiring. Preparing a semiconductor chip comprising the external connection pads and the trenches whose sides are covered with a conductive material.
(B) forming the conductive thin film on the surface of the wiring portion;
(C) A step of grinding the back surface of the semiconductor chip to partially expose the conductive material formed in the trench.
(D) A step of providing a second opening in a portion of the conductive thin film covering the external connection pad.

  A feature of the present invention resides in that a conductive thin film for shielding unwanted electromagnetic waves is formed on the surface of a semiconductor chip on which circuit elements and wiring portions are formed. By providing a semiconductor chip with a conductive thin film that is difficult or inefficient to form inside the wiring portion, it is possible to provide a semiconductor device that is resistant to malfunction caused by unnecessary electromagnetic waves.

  The conductive thin film is formed with a second opening that exposes the external connection pad of the semiconductor chip to the outside of the semiconductor chip. This is for connecting circuit elements formed inside the semiconductor chip and circuits outside the chip.

  The structure presented by the present invention can also be applied to a semiconductor chip having a through electrode. This is because the structure of the through electrode does not affect the effect of the present invention. In addition, any of the via first method, the viamidel method, and the via last method may be selected as the step of forming the through electrode on the semiconductor chip. Furthermore, whether or not the through electrode is filled with a conductive material can be selected according to the application.

  The material of the conductive thin film may be any of a single metal, an alloy, a semiconductor, and a combination of these. When using a semiconductor, it is desirable to reduce the specific resistance by a technique such as doping. Further, when the same material as the conductive material inside the through electrode is selected, a semiconductor chip can be manufactured with fewer steps.

  When the conductive thin film is connected to a power supply potential wiring that supplies a constant potential or a ground potential wiring, the ability to shield unwanted electromagnetic waves is improved.

  The semiconductor chip provided based on the present invention is suitable as a component of a three-dimensional integrated semiconductor device in which a plurality of semiconductor chips such as 3D-SiP are three-dimensionally integrated. In particular, when a plurality of semiconductor chips are opposed to each other so that both wiring portions are close to each other, the function of suppressing crosstalk and noise by the conductive thin film is maximized.

  When the semiconductor chip provided based on the present invention is used as a part of a three-dimensional integrated semiconductor device, there is no limitation on the material and method for joining the semiconductor chips. This is because the external connection pads originally provided in the semiconductor chip are exposed to the outside of the semiconductor chip even after the conductive thin film is formed. Therefore, the semiconductor chip bonding method is not limited to the room temperature bonding technique, and the known bonding method can be used as it is. Along with this, there is a merit that it is not necessary to obtain strict flatness in the conductive thin film.

  For the same reason, even when a chip-to-wafer connection process is used for integration of semiconductor devices, it is possible to avoid unnecessarily complicated processes and devices.

It is sectional drawing which showed typically an example of the semiconductor chip of one Embodiment of this invention. It is sectional drawing which showed the example of the three-dimensional integrated semiconductor device by the semiconductor chip of one Embodiment of this invention. It is sectional drawing which showed typically an example of the semiconductor chip of one Embodiment of this invention. 1 schematically shows a semiconductor chip according to an embodiment of the present invention and a three-dimensional integrated semiconductor device using the same. It is sectional drawing which showed the example of the three-dimensional integrated semiconductor device by the semiconductor chip of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is a figure which shows arrangement | positioning of the external connection pad of the semiconductor chip of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is a figure which shows the cross-section of each memory chip of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. 3 is a Schum plot of a three-dimensional integrated semiconductor device according to an embodiment of the present invention. 3 is a Schum plot of a three-dimensional integrated semiconductor device to which the present invention is not applied. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. It is sectional drawing explaining the processing procedure of the semiconductor chip and semiconductor device of one Embodiment of this invention. 3 is a Schum plot of a three-dimensional integrated semiconductor device according to an embodiment of the present invention. 3 is a Schum plot of a three-dimensional integrated semiconductor device to which the present invention is not applied. It is sectional drawing which shows an example of a structure of 3D-SiP.

  Hereinafter, a method of manufacturing a semiconductor chip according to the present invention will be described. In addition, the Example described below was taken up for convenience in order to explain the concept of the invention, and does not limit the embodiment of the invention.

In each of the following charts, the same number is assigned to the same component in a plurality of charts unless otherwise specified.

  FIG. 1 schematically shows an example of a semiconductor chip manufactured according to the present invention.

The semiconductor chip 10 includes a base substrate 11, circuit elements 12 formed on the surface of the base substrate, and wiring portions 13 formed by alternately laminating insulating layers and conductor layers on the circuit element forming surface of the base substrate. Further, among the conductor layers constituting the wiring portion, the layer farthest from the base substrate is the external connection pad 14. Further, a passivation film 15 made of an insulating material is disposed on the surface of the wiring portion on the side facing the base substrate. However, an opening is formed in the portion of the passivation film 15 corresponding to the external connection pad.

The base substrate 11 must be a member provided with at least one layer made of a semiconductor material. However, the material and configuration of the semiconductor material are arbitrary.
Regarding the configuration, a base substrate made entirely of a single material can be used. Further, a structure in which layers of different semiconductor materials are stacked directly or via an insulator, such as an SOI (Silicon on Insulator) structure, may be employed.
Examples of typical materials include single crystal silicon and single crystal germanium as single semiconductors. Compound semiconductors such as silicon carbide, gallium arsenide, and indium phosphide can also be used as the material of the base substrate 11.

The type of the circuit element 12 included in the semiconductor chip 10 is not a limitation in applying the present invention. The present invention can be applied to a chip including an active element such as a transistor or a diode, a chip including a passive element such as a resistor, or a chip including both.

The insulating layer constituting the wiring part 13 only needs to be formed of an insulator, and the conductor layer only needs to be formed of a conductor. Similarly, the passivation film 15 may be a film containing one or more kinds of insulators.

A conductive thin film 16 is formed on the passivation film 15. This conductive thin film functions as a shield that blocks the propagation of unwanted electromagnetic waves, and improves the electromagnetic interference resistance of the semiconductor chip 10. As a constituent material of the conductive thin film, various single metals, alloys, semiconductor materials, and a combination of these can be adopted. The process of forming the conductive thin film can be arbitrarily selected according to the employed material.

The conductive thin film 16 is provided with an opening 17 for exposing the entire surface of the external connection pad 14 to the outside of the semiconductor chip 10.

Here, it is not always necessary to expose all the external connection pads 14. This is because the electromagnetic interference resistance of the semiconductor chip can be increased more easily.

As a method for improving the electromagnetic wave shielding performance of the conductive thin film 16, it is conceivable to stabilize the potential of the conductive thin film 16 by some method. This is realized by electrically connecting the conductive thin film 16 and a wiring having a stable potential in the wiring layer 12, that is, a wiring for supplying a power supply potential or a wiring for supplying a ground potential. If the conductive thin film 16 covers the external connection pad 141 that supplies the power supply potential or the external connection pad 142 that supplies the ground potential, the conductive thin film can be stabilized in potential without any additional wiring. Can be connected to the selected wiring.

FIG. 2 shows an example of a three-dimensional integrated semiconductor device using the semiconductor chip thus manufactured.

The three-dimensional integrated semiconductor device 100 includes a semiconductor chip 10 and a second semiconductor chip 110. Also in the second semiconductor chip, the base substrate 11 on which the circuit element 12 is formed, the wiring portion 13, the passivation film 14, and the external connection pad 15 exist. The semiconductor chips 10 and 110 are stacked so that the circuit element forming surfaces of the base substrates face each other, and the external connection pads are connected by the micro bumps 120. The microbumps are also responsible for electrical connection between the two semiconductor chips, and include at least one kind of single metal or alloy as the material. In view of known techniques, solder, gold bumps, resin bumps with metal films, and the like may be suitable.

The three-dimensional integrated semiconductor device 100 is mounted on the interposer 300. The three-dimensional integrated semiconductor device 100 and the interposer 300 are electrically connected via external connection pads of the semiconductor chip 110. As the method, first, there is a method using wire bonding 310 as shown in FIG. Further, it is possible to apply a method in which the base substrate 11 is thinned by a known method and then connected by metal bumps or solder balls. The interposer 300 is, for example, a printed wiring board, a multilayer wiring board, a lead frame, or the like. However, it is desirable to use a wiring board corresponding to the formation of fine wiring, such as a build-up multilayer wiring board or a silicon wiring board.

  FIG. 3 schematically shows an example of a semiconductor chip manufactured according to the present invention.

The semiconductor chip 10 includes a base substrate 11, circuit elements 12 formed on the surface of the base substrate, and wiring portions 13 formed by alternately laminating insulating layers and conductor layers on the circuit element forming surface of the base substrate. Further, among the conductor layers constituting the wiring portion, the layer farthest from the base substrate is the external connection pad 14. Further, a passivation film 15 made of an insulating material is disposed on the surface of the wiring portion on the side facing the base substrate. However, an opening is formed in a portion of the passivation film 15 corresponding to the external connection pad 14.

The base substrate 11 must be a member provided with at least one layer made of a semiconductor material. However, the structure of the member and the material of the semiconductor material are arbitrary.
As a configuration, a base substrate made entirely of a single material can naturally be used. Alternatively, a structure in which layers of different semiconductor materials such as an SOI structure are stacked directly or via an insulator may be used.
Examples of typical materials include single crystal silicon and single crystal germanium as single semiconductors. Compound semiconductors such as silicon carbide, gallium arsenide, and indium phosphide can also be used as the material of the base substrate 11.

The type of the circuit element 12 included in the semiconductor chip 10 is not a limitation in applying the present invention. The present invention can be applied to a chip including an active element such as a transistor or a diode, a chip including a passive element such as a resistor, or a chip including both.

The insulating layer constituting the wiring part 13 only needs to be formed of an insulator, and the conductor layer only needs to be formed of a conductor. Similarly, the passivation film 15 may be a film containing one or more kinds of insulators.

The semiconductor chip 10 is provided with a through electrode 18 that conducts the front and back of the semiconductor chip. The through electrode 18 has an insulating film 181 on its side surface, and electrically separates the through-electrode from the base substrate 11 and the passivation film 14 and the wiring in the wiring portion 13 that should not be connected. The shape of the through electrode and the processing process are arbitrary. A structure in which the inside of the through electrode is completely filled with the conductive material may be used, or a conformal structure in which the conductive material is formed only on the side surface of the through electrode may be used.

Any material that exhibits conductivity can be used as the conductive material that is responsible for the conductivity of the through electrode. A single metal, an alloy, a semiconductor, or a resin in which a conductive filler is dispersed may be used. Moreover, the mixture and laminated body which combined some from these can also be used.

A conductive thin film 16 is formed on the passivation film 15. As the constituent material of the conductive thin film, various single metals, alloys, semiconductors, and combinations of these can be used. The conductive thin film 16 has an opening 17 for exposing the entire surface of the external connection pad 14 to the outside of the semiconductor chip.

Here, if it is permitted that at least a part of the material of the conductive thin film 16 and the conductive material constituting the through electrode 18 are the same, the process can be simplified.
In the process of embedding a conductive material in the through electrode, an extra conductive material layer is often formed not only inside the through electrode but also on the wafer surface on the side where the conductive material is embedded. In a general process, the excess conductive material is completely removed by etching, CMP, or the like, and then used for the next step. However, if the conductive thin film 16 and the through electrode 18 can be formed of the same material, the conductive thin film 16 can serve as an extra conductive material layer. Thereby, the removal process of the excess conductive material can be simplified or omitted.

Further, if the conductive thin film 16 covers the external connection pad 141 for supplying a power supply potential or the external connection pad 142 for supplying a ground potential, the potential of the conductive thin film 16 is increased without adding wiring to the wiring portion 12. Can be connected to stable wiring. Stabilization of the potential of the conductive thin film 16 leads to improvement in electromagnetic wave shielding performance.

Similar to the conductive thin film 16, a through electrode pad 19 is formed on the passivation film 15. Since the through electrode 18 penetrates the passivation film 14, the through electrode 18 and the through electrode pad 19 are directly electrically connected.

  FIG. 4 schematically shows a semiconductor chip manufactured according to the present invention and a three-dimensional integrated semiconductor device using the semiconductor chip.

The semiconductor chip 10 includes a base substrate 11, circuit elements 12 formed on the surface of the base substrate, and wiring portions 13 formed by alternately laminating insulating layers and conductor layers on the circuit element forming surface of the base substrate. Further, among the conductor layers constituting the wiring portion, the layer farthest from the base substrate includes the external connection pad 14 and the through electrode pad 19. Further, a passivation film 15 made of an insulating material is disposed on the surface of the wiring portion on the side facing the base substrate. However, an opening 17 is formed in a portion of the passivation film 15 corresponding to the external connection pad and the through electrode pad.
In addition to the above, there is a through electrode 18 that penetrates the base substrate 11. The through electrode 18 and the base substrate 11 are separated by an insulating film 181. In addition, with respect to a part of the through electrode 18, one end thereof and the through electrode pad 19 are electrically connected by the wiring in the wiring portion 12.

The base substrate 11 must be a member provided with at least one layer made of a semiconductor material. However, the structure of the member and the type of semiconductor material are arbitrary.
As a configuration, a base substrate made entirely of a single material can naturally be used. Alternatively, a structure in which layers of different semiconductor materials such as an SOI substrate are stacked directly or via an insulator may be used.
Examples of typical materials include single crystal silicon and single crystal germanium as single semiconductors. Compound semiconductors such as silicon carbide, gallium arsenide, and indium phosphide can also be used as the material of the base substrate 11.

The type of the circuit element 12 included in the semiconductor chip 10 is not a limitation in applying the present invention. The present invention can be applied to a chip including an active element such as a transistor or a diode, a chip including a passive element such as a resistor, or a chip including both.

The insulating layer constituting the wiring part 13 only needs to be formed of an insulator, and the conductor layer only needs to be formed of a conductor. Similarly, the passivation film 15 may be a film containing one or more kinds of insulators.

The through electrode 18 electrically connects the circuit element forming surface of the base substrate and the back surface thereof, or the circuit element itself and the back surface of the base substrate. The structure and processing process of the through electrode are arbitrary. A structure in which the inside of the through electrode is completely filled with a conductive material may be used, or a conformal structure in which a film of the conductive material is formed only on the side surface and the bottom surface of the through electrode may be used.

Any material that exhibits conductivity can be used as the conductive material that is responsible for the conductivity of the through electrode. A single metal, an alloy, a semiconductor, or a resin in which a conductive filler is dispersed may be used. Moreover, the mixture and laminated body which combined some from these can also be used.

A conductive thin film 16 is formed on the passivation film 15. As the constituent material of the conductive thin film, various single metals, alloys, semiconductors, and combinations of these can be used. The conductive thin film 16 has an opening 17 through which the external connection pad 14 and the through electrode pad 19 are exposed.

Here, if the conductive thin film 16 covers the external connection pad 141 for supplying the power supply potential or the external connection pad 142 for supplying the ground potential, the conductive thin film 16 is not added to the wiring portion 12 without adding the wiring. It can be connected to wiring with stable potential. Stabilization of the potential of the conductive thin film 16 leads to improvement in electromagnetic wave shielding performance.

FIG. 5 shows an example of a three-dimensional integrated semiconductor device using the semiconductor chip thus manufactured.

The three-dimensional integrated semiconductor device 100 includes a semiconductor chip 10, a second semiconductor chip 110, and a third semiconductor chip 210. Also in the second and third semiconductor chips, there are a base substrate 11 on which circuit elements 12 are formed, a wiring portion 13, a passivation film 14, and an external connection pad 15. The third semiconductor chip 210 has the through electrode 18 and the through electrode pad 19. The semiconductor chips 10 and 110 are stacked so that the circuit element forming surfaces of the base substrates face each other, and the external connection pads are connected by the micro bumps 120. On the other hand, the semiconductor chips 10 and 210 are laminated so that the circuit element formation surfaces of the base substrates face each other with the base substrate interposed therebetween. The semiconductor chip 10 and the semiconductor chip 210 are connected by micro bumps 220 that join the end faces of the through electrodes. The micro bump is composed of at least one of a single metal and an alloy. In view of known techniques, solder, gold bumps, resin bumps with metal films, and the like may be suitable.

The three-dimensional integrated semiconductor device 100 is mounted on the interposer 300. The three-dimensional integrated semiconductor device 100 and the interposer 300 are electrically connected via the external connection pad 14 and the through electrode pad 19 of the semiconductor chip 210. For connection, in addition to the method using the metal bump 320 as shown in FIG. 2, a bonding wire, ACF, or the like can be applied. The interposer 300 is, for example, a printed wiring board, a multilayer wiring board, a lead frame, or the like. However, it is desirable to use a wiring board corresponding to the formation of fine wiring, such as a build-up multilayer wiring board or a silicon wiring board.

  In this embodiment, a procedure for manufacturing a semiconductor chip having high electromagnetic interference resistance based on a semiconductor chip having no through electrode will be described. Further, a procedure for manufacturing a three-dimensional integrated semiconductor device using the semiconductor chip will be described. 6 to 13 are diagrams for explaining the processing procedure of the semiconductor chip and the semiconductor device.

  As a first preparation step, the first test chip 20 that was separated into pieces was prepared. As shown in FIG. 6, the first test chip 20 includes a base substrate 11 made of single crystal silicon, a driver 22 using CMOS transistors, a wiring portion 23, an external connection pad 24 made of aluminum, and also for power supply made of aluminum. An external connection pad 241 and a polyimide passivation film 15 are provided. The passivation film was provided with a circular opening having a diameter of 70 μm in order to expose all external connection pads to the outside of the semiconductor chip.

  As a second preparation step, an individualized second test chip 30 was prepared. The rough configuration of the second test chip 30 is as shown in FIG. 7, and includes a base substrate 11 made of single crystal silicon, a wiring portion 33, an external connection pad 34 made of aluminum, and an external power supply for supply made of aluminum. A connection pad 341 and a polyimide passivation film 15 are provided. Of the pads 34 and 341, those included in the region 301 are arranged in an array corresponding to the pads 24 and 241 of the first test chip. (Refer to the plan view of FIG. 8)

As a first step, a copper thin film 26 provided with an opening 27 was formed on the surface of the first test chip 20 on the side where the passivation film 25 was formed. The opening 27 is provided so as to expose the external connection pad 24, while the power supply pad 241 is covered with the copper thin film 26. The thickness of the copper thin film was 0.7 μm.
The 1st process was performed by the combination of 1 and 2 of the 1st supplement process shown below.

As one of the first supplementary steps, a copper thin film 26 was formed on the entire surface of the first test chip 20 where the passivation film 25 was formed by sputtering. (Not shown)
As the second auxiliary step, the opening 17 was formed in the copper thin film 26 by patterning using the photoresist 1000 and selective wet etching as shown in FIG. The opening 17 has a circular shape with a diameter of 75 μm, and the center thereof coincides with the opening of the passivation film 15. In the wet etching, a known etching solution that removes the copper thin film and does not attack aluminum is used.
Thereafter, the photoresist 1000 was removed, and the process proceeded to the next step.

  In addition, the first step could also be completed by performing the following first to third steps.

As the third supplementary process, a photoresist pattern was formed on the surface of the first test chip 20 where the passivation film 25 was formed. (Not shown)
As a subsequent first supplementary step, a copper thin film was formed by sputtering.
Then, as the fifth supplementary step, the photoresist pattern was lifted off together with the copper thin film on the surface. From the above auxiliary process, a copper thin film 26 having an opening 17 at a desired position was obtained as shown in FIG.

  As a second step, a stud bump 130 made of gold was formed on the surface of the pad 24 of the first test chip 20 and the surface of the electroless copper thin film 26. A schematic diagram after the stud bump formation is shown in FIG. The stud bump 130 was formed by a known method using a wire bonder and a gold wire. The height of the stud bump was 30 μm.

As a third step, the three-dimensional integrated semiconductor device 100 was assembled.
First, the second test chip 30 was fixed to the surface of the interposer 300 with the adhesive 140 so that the pad 34 was exposed.
Subsequently, the first test chip 20 was flip-chip connected to the second test chip 30. The electrical connection between the two chips was realized using the stud bump 130.
Finally, a thermosetting underfill material 330 was filled in the gaps between the chips and heat-cured in the atmosphere. (Fig. 11)

  As a fourth step, the three-dimensional integrated semiconductor device 100 and the interposer 300 were electrically connected. (FIG. 12) This electrical connection was realized by connecting the external connection pad 34 and the interposer 300 with the bonding wire 310.

  The electrical characteristics of the completed three-dimensional integrated semiconductor device were evaluated.

  FIG. 13 is a schematic diagram in which the three-dimensional integrated semiconductor device 100 is abstracted focusing on the electrical structure. Regarding the driver 22 in the test chip 20, both the input signal wiring 231 and the output signal wiring 232 are drawn out to the wiring portion 33 of the test chip 30 via the external connection pads 24 and the bumps 130. These wirings are further connected to an evaluation system outside the apparatus via an external connection pad 34. In addition, the wiring portion 33 of the test chip 30 includes a monitoring wiring 331 arranged in parallel with the wirings 231 and 232 separately from the above-described system. This wiring is also connected to a measurement system outside the apparatus.

Table 1 shows the measurement results of crosstalk noise generated in the monitor wiring 331 when the driver 22 is operated. The target example in Table 1 is a measurement result of the same device as the three-dimensional integrated semiconductor device 100 assembled with a test chip without the copper thin film 16.

  In this embodiment, a process when a semiconductor chip including a through electrode and exhibiting high electromagnetic interference resistance is manufactured will be described. Also, a process for manufacturing a three-dimensional integrated semiconductor device including the manufactured semiconductor chip will be described. 15 to 24 are diagrams for explaining the processing procedure of the semiconductor chip and the semiconductor device.

As a first preparation step, a memory wafer 400 having a memory chip 40 formed on one surface was prepared. The wafer diameter was 200 mm, and the wafer thickness was 405 μm.
FIG. 14 shows a cross-sectional structure of each memory chip. When viewed individually, the memory chip 40 includes a base substrate 11 made of an SOI substrate (detailed structure is not shown), a memory circuit 42 made of CMOS transistors and passive elements, a wiring portion 13, and aluminum covered with gold. An external connection pad 14 made of gold, an external connection pad 142 made of gold-coated aluminum for supplying a ground potential, and a passivation film 15 made of silicon nitride are provided. The passivation film was provided with a circular opening having a diameter of 50 μm in order to expose all external connection pads to the outside of the semiconductor chip.

In the wiring part 13, in order to obtain conduction between the through electrode and the wiring part, a land structure 143 arranged in the same layer as the external connection pad 14, an internal wiring for connecting the land structure 143 and the memory circuit, and a memory circuit and external connection External connection wiring connecting the pads was arranged. (Neither shown)

  As a second preparation step, a microcomputer chip 50 was prepared. The rough configuration of the microcomputer chip 50 is as shown in FIG. 15, and includes a base substrate 11 made of single crystal silicon, a microcomputer circuit 52, a wiring portion 13, an external connection pad 14 made of aluminum covered with gold, and also gold-coated aluminum. An external connection pad 142 for supplying a ground potential made of polyimide and a passivation film 15 made of polyimide are provided. The passivation film was provided with a circular opening having a diameter of 50 μm in order to expose all external connection pads to the outside of the semiconductor chip.

As a first step, a through hole 182 serving as a base of the through electrode was formed at a predetermined position of the memory wafer 400. (FIG. 16) The predetermined position mentioned here includes a portion where the land structure is arranged. A Bosch process, which is a known method, was used for processing the through hole 182. The cross section of the hole was a circle having a diameter of 35 μm. The pitch of the holes was 150 μm at the narrowest part.

  As a second step, an insulating film 181 for insulating the wiring in the base substrate 11 and the wiring portion 13 from the through electrode was formed. As shown in FIG. 17, a silicon dioxide thin film 181 was formed on the entire surface of the memory wafer 400 by plasma CVD (chemical vapor deposition) using tetraethoxysilane as a material. The average thickness of the thin film 481 was 0.17 μm on the side surface of the through hole 182.

  As a third step, portions of the insulating film 181 that cover the external connection pads 14 and 142 and the land structure 143 were removed. An unnecessary portion of the insulating film 181 could be removed by a known selective etching process using a photosensitive etching resist and dry etching. A schematic diagram of the memory wafer after removal of the etching resist is shown in FIG.

  As a fourth step, the conductive thin film 46 and the through electrode pad 49 were formed, and the conductor material part was formed on the side surface of the through hole 482. This was performed by the process shown in the following four supplementary steps 1 to 5.

  As one of the fourth auxiliary steps, a titanium nitride thin film 183 serving as a barrier metal was formed on the entire exposed surface of the memory wafer 400 by sputtering. A schematic diagram at the end of the process is shown in FIG. The barrier metal thickness on the side surface of the through-hole 182 was 0.08 μm on average.

  As the second supplementary step, a copper thin film to be a plating seed layer was formed on the entire front and back surfaces of the memory wafer 400 by sputtering. (Not shown) The thickness of the copper thin film on the side surface of the through hole 182 was 0.54 μm on average.

  As the third supplementary process, a plating resist pattern (not shown) for forming the conductive thin film 46 and the through electrode pads 49 and 491 having a desired shape was formed.

  As the fourth complementary step, the conductive thin film 46 having the opening 17 with respect to the external connection pad 14, the through electrode pads 49 and 491, and the conductor material portion on the side surface of the through hole 182 were formed. This auxiliary process was performed by electrolytic copper plating using a titanium nitride thin film as a seed layer. The thickness of the electrolytic copper was 5 μm on the average on the memory wafer surface and 3.4 μm on the side surface of the through electrode. After the plating was completed, the plating resist pattern was removed.

  As the fifth supplementary process, unnecessary portions of the copper thin film and the titanium nitride thin film 183 were removed by wet etching. (Fig. 20)

  As a fifth step, a second memory wafer 401 that has been subjected to the above fourth step is prepared, and gold stud bumps 130 and 1301 are formed on the surfaces of the external connection pads 14 and 142 and the through electrode pads 49 and 491 of the wafer. Formed. (FIG. 21) The stud bump 130 was formed by a known method using a wire bonder and a gold wire. The height of the stud bump 130 was 40 μm, and the height of the stud bump 1301 was 20 μm.

As a sixth step, the memory wafer 400 and the second memory wafer 401 were bonded.
An uncured thermosetting underfill material 330 was applied to the back surface of the memory wafer 400 in advance, and the through electrode pads 491 of both memory wafers were joined by a known crimping process using the stud bumps 130. Thereafter, the underfill material 330 was cured. (Fig. 22)

  As a seventh step, two bonded memory wafers were divided to obtain individual stacked memory chips 101. A known wafer dicing technique was used for dividing the wafer (not shown).

  As an eighth step, the stacked memory chip 101 was mounted on the interposer 300. As shown in FIG. 23, the laminated memory chip 101 and the interposer 300 were electrically connected by crimping with gold stud bumps 1301. Thereafter, a thermosetting underfill material 330 was injected and thermally cured.

  As a ninth step, the microcomputer chip 50 and the stacked memory chip 101 were joined to complete the three-dimensional integrated semiconductor device 100. (FIG. 24) Gold stud bumps 130 having a height of 20 μm were formed on the external connection pads 14 of the microcomputer chip 50, and the external connection pads of both chips were connected physically and electrically.

  The characteristics of the completed three-dimensional integrated semiconductor device 100 were evaluated. FIG. 25 shows a Schum plot of the three-dimensional integrated semiconductor device 100 manufactured in this example. On the other hand, FIG. 26 shows a Schum plot of a three-dimensional integrated semiconductor device prototyped with a microcomputer chip and a memory chip to which the present invention is not applied as a target example. In FIG. 25, the colored portion of the background is a portion where the memory characteristics are improved by the effect of the present invention.

  In this embodiment, a process when a semiconductor chip having high electromagnetic interference resistance is manufactured using a semiconductor chip having a through electrode will be described. Also, a process for assembling a three-dimensional integrated semiconductor device including the manufactured semiconductor chip will be described. 27 to 37 are diagrams for explaining the processing procedure of the semiconductor chip and the semiconductor device.

As a first preparation step, a memory wafer 600 having a memory chip 60 formed on one surface was prepared. The wafer diameter was 150 mm, and the wafer thickness was 625 μm.
FIG. 27 shows a cross-sectional structure of each memory chip. When viewed individually, the memory chip 60 includes a base substrate 61 (not shown in detail) made of an SOI substrate, a memory circuit 42 made of CMOS transistors and passive elements, a wiring portion 13, and aluminum coated with gold. An external connection pad 14 made of gold, an external connection pad 142 made of gold-coated aluminum for supplying a ground potential, and a passivation film 15 made of silicon nitride are provided. The passivation film was provided with a circular opening having a diameter of 50 μm in order to expose all external connection pads to the outside of the semiconductor chip.

A via hole 682 filled with conductive silicon is formed in the base substrate 61. The via hole 682 has a cylindrical shape with a diameter of 10 μm and a depth of 110 μm, and an insulating film 681 made of silicon dioxide is provided on the side wall thereof. The pitch between via holes was 25 μm at the narrowest place. The via hole 681 is electrically connected to the through electrode pad 19 via the wiring portion 13.

  As a second preparation step, a microcomputer chip 50 was prepared. This is exactly the same as the microcomputer chip used in the second embodiment. (See FIG. 15) For the microcomputer chip 50, a stud bump 130 made of gold and having a height of 30 μm was formed on the external connection pads 14 and 142 by a known method.

  As a third preparation step, a blank wafer 1010 made of gallium arsenide in which a gallium arsenide thin film 66 and a gallium indium arsenide thin film 661 were laminated was prepared. (FIG. 28) The supporting wafer was circular with a diameter of 150 mm, and a circular aluminum arsenic thin film 661 with a thickness of 1.2 μm was formed on the surface thereof. Furthermore, a circular gallium arsenide thin film 66 having a diameter of 145 mm and a thickness of 10 μm was formed thereon. The gallium arsenide thin film was doped with carbon, and its resistivity was 1.47 Ω · cm.

  As a first step, an opening 17 was formed in the gallium arsenide thin film 66. The opening was formed by removing a predetermined portion of the gallium arsenide thin film 66 by wet etching using a known etchant. A blank wafer 1010 after the opening 17 is formed is shown in FIG. The diameter of the opening 17 was 58.5 μm.

  The gallium arsenide thin film 66 is transferred to the memory wafer 600 in a later process. Therefore, the arrangement of the opening 67 is determined so that the external connection pad 64 and the through electrode pad 69 are all exposed when the gallium arsenide thin film 66 is transferred.

As a second step, the memory wafer 600 and the blank wafer 1010 were bonded together.
First, a photosensitive adhesive 1401 containing polyimide as a main component was attached to the wiring layer side surface of the memory wafer 600, and then a pattern exposing all the external connection pads 14 and 142 and the through electrode pads 69 was formed.
Next, the memory wafer 600 and the blank wafer 1020 were bonded using a photosensitive adhesive 1401. At this time, the surface of the blank wafer 1010 on which the gallium arsenide thin film 66 was formed was used as an adhesive surface.
At the end of the second step, the photosensitive adhesive 1401 was thermally cured to completely fix the two wafers. A schematic view of the wafer when the second step is completed is shown in FIG.

As a third step, the via hole 682 embedded in the base substrate 61 was exposed on the back surface to form the through electrode 68. The memory wafer 600 was ground from the base substrate side to a thickness of 100 μm using BG (Back Grinding) and CMP. Thereafter, as shown in FIG. 31, a silicon dioxide passivation film 651 is formed on the entire ground surface of the memory wafer 600 by low temperature CVD. However, only the end portion of the through electrode 68 was exposed without being covered with the passivation film 651.

As a fourth step, a metal post 150 for stacking semiconductor chips was provided at the end of the through electrode 68 on the base substrate 61 side. The metal post 150 was made of copper, and the height from the surface of the base substrate was 5 μm. In addition, a tin thin film 1501 having a thickness of 2 μm was formed on the top surface of the metal post 150. (Fig. 32)
The metal post 150 and the tin thin film 1501 were formed by a known electrolytic plating additive process using sputtered copper as a plating seed layer.

As a fifth step, the blank wafer 1010 was peeled from the memory wafer 600. First, a glass support wafer 1020 was attached to the base substrate side of the memory wafer 600 with an acid resistant adhesive film 1030. At this time, the entire metal post 150 was embedded in the adhesive film. Next, the memory wafer 600 was immersed in hydrochloric acid, and the gallium indium arsenide thin film 681 was removed. A schematic diagram of the wafer 600 at the completion of the fifth step is shown in FIG.

As a sixth process, a second memory wafer 601 to which the above-described fourth process was applied was prepared, and electrically and physically joined to the memory wafer 600. (FIG. 34) The external connection pads 64 and the metal posts 150 and the through electrode pads 69 and the metal posts 150 corresponding to each other between the wafers were aligned, and then joined together by reflow. Thereafter, an underfill material (not shown) was filled and cured between the wafers.

As the seventh step, the blank wafer 1010 bonded to the second memory wafer was removed as in the fifth step.

  As an eighth step, a second support wafer 1021 made of glass was newly attached to the exposed surface of the external connection pad 14 and the support wafer 1020 was peeled off. (Fig. 35)

  As a ninth step, the memory wafers 600 and 601 and the support wafer 1021 were diced together and separated into individual stacked memories 102. (Not shown)

  As a tenth step, the stacked memory 102 was mounted on the interposer 330 using a build-up multilayer substrate. A metal post 150 was used for mounting. Thereafter, the separated support wafer 1021 was peeled off. (Fig. 36)

  As an eleventh step, the microcomputer chip 50 and the stacked memory chip 101 were joined to complete the three-dimensional integrated semiconductor device 100. (Fig. 37)

The characteristics of the completed three-dimensional integrated semiconductor device 100 were evaluated. FIG. 38 shows a Schum plot of the three-dimensional integrated semiconductor device 100 manufactured in this example. On the other hand, FIG. 39 shows a Schum plot of a three-dimensional integrated semiconductor device prototyped with a microcomputer chip and a memory chip to which the present invention is not applied as a target example. In FIG. 38, the colored portion of the background is a portion where the memory characteristics are improved by the effect of the present invention.

1 ... 3D-SiP
DESCRIPTION OF SYMBOLS 10, 110, 210 ... Semiconductor chip 11, 61 ... Base substrate 12 ... Circuit element 13, 23, 33 ... Wiring part 14, 24, 34 ... External connection pad 15 ... Passivation film 16 ... Conductive thin film 17 ... Conductive thin film Opening 18, 68 ... Through electrode 19, 49 ... Through electrode pad 20, 30 ... Test chip 22 ... Driver by CMOS 26 ... Copper thin film 40, 60 ... Memory chip 42, 62 ... Memory circuit 50 ... Microcomputer chip 52 ... Microcomputer circuit DESCRIPTION OF SYMBOLS 66 ... Gallium arsenide thin film 100 ... Three-dimensional integrated semiconductor device 101 ... Stacked memory chip 120 ... Micro bump 130, 1301 ... Stud bump 140, 1401 ... Adhesive 141, 241, 341 ... External connection pad 142 for power supply 142 ... Ground External connection pad for potential supply 143 .. land structure DESCRIPTION OF SYMBOLS 150 ... Metal post 181 ... Insulating film of a through-electrode side 182 ... Through-hole 183 ... Barrier metal 231 ... Input signal wiring 232 ... Output signal wiring 300 ... Interposer 310 ... Bonding wire 320 ... Solder bump 330 ... Underfill material 331 ... Monitor wiring 400, 401, 600, 601 ... memory chip wafer 491 ... penetrating electrode pad on the back side of the semiconductor chip 651 ... passivation film on the back side 681 ... insulating film on the side surface of the via hole 682 ... via hole 1000 ... photoresist 1010 ... blank wafer 1020, 1021 ... support Wafer 1030 ... adhesive film 1501 ... tin thin film

Claims (23)

Of the semiconductor chips
A base substrate comprising at least one layer of semiconductor material;
On the surface of the base substrate, a circuit element composed of at least one of an active element and a passive element;
A wiring portion formed of insulating layers and conductor layers alternately arranged on the surface on which the circuit element exists, and including an external wiring for electrically connecting the circuit element and the outside of the semiconductor chip;
Of the conductor layers forming the wiring portion, formed in a layer farthest from the base substrate, external connection pads connected to the external wiring,
A passivation layer made of an insulator that covers the conductor layer on which the external connection pad is formed and has an opening that exposes the external connection pad to the outside of the chip;
Comprising:
And a conductive thin film made of at least one kind of metal or alloy at a position separating the wiring portion and the passivation layer from the base substrate,
The semiconductor chip is characterized in that a second opening is provided in a portion of the conductive thin film corresponding to the external connection pad.   2. The semiconductor chip according to claim 1, further comprising a through electrode penetrating the base substrate in a thickness direction. The semiconductor chip according to claim 2, wherein the wiring portion includes at least one of the following 1) and 2).
1) Internal wiring disposed in the wiring portion for electrically connecting the through electrode and the circuit element.
2) A through electrode pad that is formed in a layer farthest from the base substrate among the conductor layers forming the wiring portion and is not connected to the external wiring, and electrically connects the through electrode pad and the through electrode A through-wiring line disposed in the wiring portion in order to   4. The semiconductor chip according to claim 2, wherein the through electrode penetrates the wiring portion in the thickness direction in addition to the base substrate. 5.   The semiconductor chip according to claim 2, wherein the inside of the through electrode is embedded with a conductive material.   The semiconductor chip according to claim 5, wherein the conductive material and the material forming the conductive thin film include a common material. Of the semiconductor chips
A base substrate comprising at least one layer of semiconductor material;
On the surface of the base substrate, a circuit element composed of at least one of an active element and a passive element;
A wiring portion formed of insulating layers and conductor layers alternately arranged on the surface on which the circuit element exists, and including an external wiring for electrically connecting the circuit element and the outside of the semiconductor chip;
Of the conductor layers forming the wiring portion, formed in a layer farthest from the base, external connection pads connected to the external wiring,
A passivation layer made of an insulator that covers the conductor layer on which the external connection pad is formed and has an opening that exposes the external connection to the outside of the chip;
Comprising:
further,
Provided with a conductive thin film made of a conductor containing at least one kind of semiconductor material at a position separating the wiring part from the base substrate,
The semiconductor chip is characterized in that a second opening is provided in a portion of the conductive thin film corresponding to the external connection pad.   The semiconductor chip according to claim 7, wherein the semiconductor material contained in the conductive thin film exhibits a specific resistance of 1.5 Ω · cm or less.   9. The semiconductor chip according to claim 7, further comprising a through electrode penetrating the base substrate in a thickness direction. The semiconductor chip according to claim 9, wherein the wiring portion includes at least one of the following 1) and 2).
1) Internal wiring disposed in the wiring portion for electrically connecting the through electrode and the circuit element.
2) A through electrode pad that is formed in a layer farthest from the base substrate among the conductor layers forming the wiring portion and is not connected to the external wiring, and electrically connects the through electrode pad and the through electrode A through-wiring line disposed in the wiring portion in order to   11. The semiconductor chip according to claim 9, wherein the through electrode penetrates the wiring portion in a thickness direction.   The semiconductor chip according to claim 9, wherein the inside of the through electrode is filled with a conductive material.   The semiconductor chip according to claim 12, wherein the conductive material is the same as a material forming the conductive thin film.   The semiconductor chip according to claim 1, wherein the conductive thin film is provided for shielding unnecessary electromagnetic waves.   The semiconductor chip according to claim 1, wherein the conductive thin film is connected to a portion of the wiring portion that supplies a power supply potential.   The electrical connection between the conductive thin film and the wiring portion for supplying the power supply potential is obtained by covering the external connection pad for supplying the power supply potential with the conductive thin film. Item 16. The semiconductor chip according to Item 15.   The semiconductor chip according to claim 1, wherein the conductive thin film is connected to a portion of the wiring portion that supplies a ground potential.   The electrical connection between the conductive thin film and the wiring portion for supplying the ground potential is obtained by covering the external connection pad for supplying the ground potential with the conductive thin film. Item 18. A semiconductor chip according to Item 17.   A three-dimensional integrated semiconductor device characterized in that a plurality of semiconductor chips including at least one semiconductor chip according to claim 1 are three-dimensionally integrated. The three-dimensional integrated semiconductor device according to claim 19, wherein the second semiconductor chip electrically connected to the semiconductor chip according to claims 1 to 18 is:
A second base made of a semiconductor material and having at least one surface;
A second wiring portion formed on the surface of the second base substrate;
With
The semiconductor chip according to claim 1 and the second semiconductor chip are formed with a surface of the base substrate on which the circuit elements are formed and the second wiring portion of the second base substrate. The three-dimensional integrated semiconductor device according to claim 19, wherein the surfaces are integrated so as to be close to each other. A method for manufacturing a semiconductor chip, comprising the following steps (a) to (c):
(A) Of the semiconductor chips,
A circuit element composed of at least one of an active element and a passive element;
A wiring portion formed of insulating layers and conductor layers alternately arranged on the surface on which the circuit element exists, and including an external wiring for electrically connecting the circuit element and the outside of the semiconductor chip;
A step of preparing a semiconductor chip including an external connection pad formed on a layer farthest from the circuit element among the conductor layers forming the wiring portion and connected to the external wiring;
(B) forming a conductive thin film on the surface of the wiring portion;
(C) The process of providing a 2nd opening part in the part which has coat | covered the said external connection pad among electroconductive thin films. A method for manufacturing a semiconductor chip, comprising the following steps (a) to (f):
(A) Of the semiconductor chips,
A circuit element composed of at least one of an active element and a passive element;
A wiring portion formed of insulating layers and conductor layers alternately arranged on the surface on which the circuit element exists, and including an external wiring for electrically connecting the circuit element and the outside of the semiconductor chip;
A step of preparing a semiconductor chip including an external connection pad formed on a layer farthest from the circuit element among the conductor layers forming the wiring portion and connected to the external wiring;
(B) The process of processing the hole used as a penetration electrode in the said semiconductor chip.
(C) A step of forming an insulating film on the side surface of the hole.
(D) A step of forming a film of a conductive material inside the hole and conducting both surfaces of the semiconductor chip.
(E) A step of forming a conductive thin film on the surface of the wiring portion.
(F) The process of providing a 2nd opening part in the part which has coat | covered the said external connection pad among the said electroconductive thin films. A method for manufacturing a semiconductor chip, comprising the following steps (a) to (d):
(A) Of the semiconductor chips,
A circuit element composed of at least one of an active element and a passive element;
A wiring portion formed of insulating layers and conductor layers alternately arranged on the surface on which the circuit element exists, and including an external wiring for electrically connecting the circuit element and the outside of the semiconductor chip;
Of the conductor layers forming the wiring portion, formed in the layer farthest from the circuit element, and external connection pads connected to the external wiring,
Preparing a semiconductor chip comprising a trench whose side surface is covered with a conductive material;
(B) forming the conductive thin film on the surface of the wiring portion;
(C) A step of grinding the back surface of the semiconductor chip to partially expose the conductive material formed in the trench.
(D) A step of providing a second opening in a portion of the conductive thin film covering the external connection pad.

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