JP2012216009A - Method for increasing speed of program by performing overtaking control of memory access instruction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for performing a program at high speed.SOLUTION: A program performing system comprises: a CPU having a store instruction including an overtaking permitting flag showing overtaking permission/non-permission of a load instruction and an instruction set including an instruction for blocking overtaking of the load instruction; a compiler having overtaking permitting flag setting means for setting the flag and overtaking blocking instruction creating means for creating the instruction; and an instruction reorder unit having overtaking blocking instruction registering means for registering the instruction for blocking overtaking into an instruction reorder buffer and instruction by-pass means for registering a memory access instruction into the instruction reorder buffer while referring to the store instruction to which the overtaking permitting flag is set.

Description

  The present invention relates to a technique for executing a program at high speed in a technical field using a CPU having an instruction for writing data to a storage device or reading data from the storage device.

  Conventionally, there are CPUs equipped with a plurality of instruction pipelines in order to execute instructions at high speed by increasing instruction level parallelism.

  FIG. 1 is a diagram showing a flow of an instruction pipeline in a conventional example. The instruction pipeline 11 basically includes four stages of an instruction fetch 12, an instruction decode 13, an execution 14, and a read / write 15, and each of these stages can be processed simultaneously. FIG. 1 shows an example of an instruction pipeline capable of simultaneously processing two instructions. In the memory access instruction, the address calculation is processed in the execution stage 14, and the memory read / write is processed in the read / write stage 15. A buffer which is a temporary storage area is prepared before and after each stage, and the result of the previous stage is waited in the buffer until the next stage can be processed.

  Using such an instruction pipeline, when memory access instructions are processed simultaneously, for example, when the memory area accessed by a load instruction and a store instruction is the same, the read / write order relationship by these instructions must be maintained. If this is the case, the correct execution result of the instruction cannot be obtained. Therefore, one of the load instruction and the store instruction is waited in the buffer immediately before the read / write stage 15. In general, since memory access instructions require time to execute, instructions that require the results of those instructions are similarly waited in buffers before and after each stage. Stopping the flow of the instruction pipeline in this way is called a pipeline hazard.

  As a method for avoiding pipeline hazards and speeding up the program, memory disambiguation of memory access instructions is performed before and after the read / write stage, and the order relationship between load and store for a certain memory area is determined. There is a way to start the load instruction as early as possible while keeping.

  FIG. 2 is a diagram showing a conventional example in which memory disambiguation of a memory access instruction is performed to increase the speed. The six-row instruction sequence shown in the upper left of the figure is an assembler image of an instruction input to the instruction pipeline. The number 21 in the leftmost column indicates the input order, and the next column 22 indicates whether it is a load or a store. The central portion 23 of the right column indicates the address of the area where loading and storing are performed, and the number 24 at the right end indicates the size of loading and storing. The address calculation unit 25 corresponds to the execution stage 14 and calculates the address of the memory area accessed by the memory access instruction. The result of the instruction decode stage 13 is input. The instruction reorder unit 26 performs memory disambiguation and loads and controls the execution order of store instructions. The memory access unit 28 corresponds to the read / write stage 15. It is assumed that the address calculation unit 25 and the memory access unit 28 can process two instructions simultaneously. The instruction reorder buffer 29 corresponds to a buffer immediately before the read / write stage 15 of the instruction pipeline.

  When the instruction reorder unit 26 receives the instruction and the calculated address from the address calculation unit 25, the instruction reorder unit 26 registers it in the empty entry of the instruction reorder buffer 29. Each row in the lower right table of FIG. 2 is an entry. If the entry is not free, wait until it is free. One entry of the instruction reorder buffer includes an entry “number” 211, a load and store “type” 212, a load and store “size” 213, a calculated “address” 214, and an instruction to be preceded. “Leading N” which is the number of the corresponding instruction reorder buffer entry (N is an integer from 1 to the number of instruction reorder buffer entries−1, in the case of FIG. 2, one of 1, 2, 3, 4 or 5) 215 is registered. The “instruction that must be preceded” is an instruction that must be completed before the execution of the instruction starts. Here, “execution completion” means completion of the read / write stage 15 of the instruction pipeline. In the assembler image that is the input of the instruction pipeline, the store instruction 218 with the input order 21 of 4 must not update the address value address1 before the load instructions with the order 1 and 3 finish. You have to wait for the execution to complete. Therefore, the “preceding 1” and “preceding 2” of the entry 210 of the instruction reorder buffer number 5 corresponding to the instruction of order 4 include the number “1” of the entry corresponding to the load instruction of order 1 and the The entry number “3” corresponding to the load instruction is registered. Also, since the load instruction 217 whose order is 2-1 is input must not be started before the execution of the store instruction 218 whose order is 4 is completed, the load instruction 217 whose order is 6 is input. The number “5” is registered in “preceding 1” of the entry 216 of number 4 of the corresponding instruction reorder buffer.

  The instruction reorder unit 26 passes to the memory access unit 28 an instruction corresponding to an entry in which all “preceding N” numbers are not set (indicated as “−” in the instruction reorder buffer 29). When the execution of the instruction is completed, the memory access unit 28 sends an instruction execution completion notification 27 to the instruction reorder unit 26. The instruction reorder unit 26 that has received the instruction execution completion notification 27 clears the entry in the instruction reorder buffer corresponding to the completed instruction to become “empty entry” and is registered in “preceding N” of other entries. Clear the entry number (set to "-"). When the instruction reorder buffer 29 becomes free in this way, a new instruction is registered in the instruction reorder buffer, and instructions are sequentially executed.

  There are also instructions for loading and storing data in a plurality of memory areas with one instruction such as a SIMD (Single Instruction Multi Data) instruction and a vector instruction.

  FIG. 3 is a diagram showing a conventional example in the case of having vector instructions that can be loaded and stored in four memory areas with one instruction. The DO loop 31 is described in the Fortran language that performs vector collection and vector diffusion. For the DO loop 31, the compiler generates an instruction sequence 32. Reg5 of the register 37 is a register (referred to as a vector register) that can hold four values. Registers reg1, reg2, reg3, reg4, and reg6 are also vector registers. The vector load instruction 33 is an instruction for reading four consecutive data pieces each having a size of 8 bytes from the memory area having the address value address1 at the top of the array IDX2, 38 with one instruction. FIG. 3 shows an example of the second repetition of the instruction sequence 32, in which values are read from the addresses of address address1 + 0, address1 + 8, address1 + 16, address1 + 24 and written to the vector register reg1. In the vector registers reg1, 39, four values 2, 5, 6, 6 are written. The vector collection instruction 34 is an instruction that calculates an address based on the values of the vector registers reg1 and 39 into which four values are written, and collects values from the four memory areas. Since four values 2, 5, 6, and 6 are written in the vector registers reg1 and 39, the vector collection instruction 34 uses the address address3 + (2-1) × 8, address3 + (5- 1) Values are read from x8, address3 + (6-1) x8, and values are written to vector registers reg3 and 311. Based on the result thus obtained, the vector addition instruction 35 performs four additions with one instruction, and the vector diffusion instruction 36 writes the result into the memory.

  Note that Patent Document 1 describes an arithmetic processing technique that eliminates as much as possible the waiting for processing during an address dependency check and speeds up processing involving access to a memory.

JP 2009-026260 A

  However, since the memory disambiguation of the memory access instruction is performed as described above, the instruction reorder buffer 29 is used in order to increase the number of load instructions that can be executed in advance and increase the program speed. The number of entries and the column of “preceding N” 215 must be increased. However, there is a problem that it is difficult to increase them due to physical restrictions of the CPU. Further, there is a problem that as the number increases, the processing amount of the instruction reorder unit 26 increases and the degree of performance improvement decreases.

  In addition, since the SIMD instruction and the vector instruction perform the processing as described above, it is necessary to wait for the completion of the instruction that must be preceded for every memory area to be accessed. Therefore, in order to start the load instruction as early as possible and speed up the program, it is necessary to register the addresses of all areas accessed by those instructions in the instruction reorder buffer as shown in FIG. Further, when the instruction reorder unit 26 registers an instruction for which address calculation has been completed in the instruction reorder buffer, it is necessary to check all addresses of each entry and obtain an instruction that must be preceded, and to issue an instruction execution completion notification 27. When received, all addresses in each entry must be examined and cleared. For this reason, there is a problem that not only the address registration area increases but also the time for checking increases, and the physical restrictions of the CPU and the benefits of performance improvement are few. Therefore, SIMD instructions and vector instructions It is not possible to speed up the program by executing the type of load instruction in advance.

  In view of such circumstances, the present invention provides a CPU including an instruction set that includes a store instruction having a flag indicating whether overtaking is permitted or not permitted by a load instruction, an instruction that blocks overtaking of a load instruction, setting of the flag, and generation of the instruction. By providing a compiler that does this, we intend to provide a method for executing a program at high speed.

  The present invention relates to a store instruction having an overtaking permission flag indicating permission / non-permission of overtaking of a load instruction, a CPU having an instruction set including an instruction for blocking overtaking of a load instruction, and overtaking permission flag setting means for setting the flag Memory access while referring to a compiler having an overtaking block instruction generation means for generating the instruction, an overtaking block instruction registration means for registering an instruction to block overtaking in the instruction reorder buffer, and a store instruction in which the overtaking permission flag is set An instruction reorder unit having an instruction bypass means for registering an instruction in an instruction reorder buffer;

  In this specification, writing data to the memory is referred to as a store, an instruction for executing the data is referred to as a store instruction, reading data from the memory is referred to as load, and an instruction for executing the data is referred to as a load instruction. A load instruction and a store instruction are collectively referred to as a memory access instruction.

  According to the present invention, the instruction subsequent to the first instruction whose overtaking permission flag is set to ON is processed simultaneously with the first instruction or overtaking the first instruction. As a result, the processing time can be shortened and the program can be speeded up.

It is a figure which shows the flow of the instruction pipeline in a prior art example. It is a figure which shows the prior art example when performing memory disambiguation of a memory access instruction and speeding up. It is a figure which shows the prior art example when it has a vector instruction which can be loaded and stored in four memory areas with one instruction. It is an example of an instruction reorder buffer. It is a block diagram which shows schematic structure of the program execution system which concerns on one Embodiment of this invention. It is a flowchart which shows operation | movement of the overtaking permission flag setting means in a present Example. It is a flowchart which shows operation | movement of the overtaking block command production | generation means in a present Example. It is a flowchart which shows operation | movement of the overtaking block command registration means in a present Example. It is a flowchart which shows the operation | movement of the command bypass means in a present Example. In this example, it is a figure which shows the effect in the case of a vector instruction. (A) is a figure which shows an example of the program 111 in another Example. (B) is a flowchart showing the operation of the overtaking permission flag setting means in this embodiment. It is a block diagram which shows the function structure of the compiler in the other Example of this invention. It is a figure which shows the other Example of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  FIG. 5 is a block diagram showing a schematic configuration of a program execution system according to an embodiment of the present invention. As shown in the figure, in this embodiment, the CPU instruction set includes store instructions 54, 55, 56 having an overtaking permission flag, and instructions for blocking overtaking instructions (hereinafter referred to as “overtaking block instructions”). 57.

  Further, the compiler 51 in the present embodiment stores the store instructions 54, 55, and 56 in the loop when the instruction line 516 for setting the overtaking permission flag of the store instruction in a loop of the program to ON (passing is permitted) is designated. When the overtaking permission flag setting means 52 for setting the overtaking permission flag of the vehicle and the instruction line 515 for designating that the overtaking of the load instruction after a certain point in the program is to be blocked are designated, the overtaking block instruction 57 is provided at that location. Has an overtaking block instruction generation means 53.

  The instruction reorder unit 59 performs memory disambiguation and loads and controls the execution order of store instructions. The instruction reorder unit 59 in this embodiment does not make the overtaking block instruction registration means 510 for registering the overtaking block instruction 57 in the instruction reorder buffer 517, an instruction that must precede the store instruction in which the overtaking permission flag is set to ON, In addition, an instruction bypass unit 511 that registers a load instruction in the instruction reorder buffer 517 as an instruction that must be preceded by the overtaking block instruction 57 in the instruction reorder buffer 517. The instruction reorder unit 59 includes the operations and functions described as the instruction reorder unit 26.

  The address calculation unit 58 corresponds to the execution stage 14 and calculates the address of the memory area accessed by the memory access instruction. The result of the instruction decode stage 13 is input. The memory access unit 513 corresponds to the read / write stage 15. In this embodiment, the address calculation unit 58 and the memory access unit 513 can process two instructions simultaneously, but the number of instructions that can be processed in parallel is not limited to this. The instruction reorder buffer 517 corresponds to a buffer immediately before the read / write stage 15 of the instruction pipeline. The instruction execution completion notification 512 is the same notification as the instruction execution completion notification 27.

  The program execution system in the present embodiment is realized by a computer. The program execution system includes a CPU for controlling the operation and processing of the system, a ROM and / or RAM for storing programs and necessary data, an input / output interface for external input and output, and an external A communication interface for data communication with the bus, a bus connecting these, and the like. Further, in this specification and the like, the means does not simply mean physical means, but the function of the means is realized by software, that is, the CPU is stored in a memory or an external storage device. This includes a case where it is realized by executing a predetermined program. At this time, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.

  Next, the operation in this embodiment will be described with reference to FIGS.

  FIG. 6 is a flowchart showing the operation of the overtaking permission flag setting means in the present embodiment. The overtaking permission flag setting means 52 of the compiler 51 in this embodiment is activated when the compiler processes a store instruction. As shown in FIG. 6, first, it is determined whether or not a store instruction is included in the loop (S61). When the store instruction is not included in the loop, the overtaking permission flag of the store instruction is set to OFF (S64). When the store instruction is included in the loop, it is determined whether or not the instruction line 516 for setting the overtaking permission flag to ON is designated for the loop (S62). If not specified, the overtaking permission flag of the store instruction is set to OFF (S64). If so, the overtaking permission flag of the store instruction is set to ON (S63).

  FIG. 7 is a flowchart showing the operation of the overtaking block instruction generation means in this embodiment. The overtaking block instruction generation means 53 of the compiler 51 in this embodiment is activated immediately before the compiler processes a statement. As shown in FIG. 7, first, it is determined whether or not an instruction line 515 for designating blocking of overtaking of a load instruction is designated immediately before a sentence (S71). If not specified, an instruction corresponding to the current sentence is generated as before (S73). If so, an overtaking block instruction is generated (S72). After that, an instruction corresponding to the current sentence is generated as usual (S73).

  FIG. 8 is a flowchart showing the operation of the overtaking block instruction registration means in this embodiment. The overtaking block instruction registration means 510 of the instruction reorder unit 59 in this embodiment is activated when the instruction reorder unit 59 registers the overtaking block instruction 57 in the instruction reorder buffer 517. As shown in FIG. 8, the overtaking block instruction registration unit 510 takes out an entry from the instruction reorder buffer 517 (S81). Next, it is determined whether or not the extracted entry is an empty entry (S82). If it is not an empty entry, the number of this entry is registered as an instruction that must precede the overtaking block instruction (S83). Next, it is determined whether or not the fetched entry is the last entry in the instruction reorder buffer 517 (S84). If it is not the last entry, the next entry is extracted from the instruction reorder buffer 517 (S81), and the process is repeated. If it is the last entry in step S84, the process is terminated. If the entry is an empty entry in step S82, it is determined whether the extracted entry is the last entry in the instruction reorder buffer 517 (S84). If it is not the last entry, the next entry is extracted from the instruction reorder buffer 517 (S81), and the process is repeated. If it is the last entry in step S84, the process is terminated.

  FIG. 9 is a flowchart showing the operation of the instruction bypass means in this embodiment. The instruction bypass unit 511 of the instruction reorder unit 59 in this embodiment is activated when the instruction reorder unit 59 registers an instruction in the instruction reorder buffer 517. As shown in FIG. 9, first, it is determined whether or not the entry taken out from the instruction reorder buffer 517 is an overtaking block instruction (S93). When the entry is for the overtaking block instruction, the entry number is registered as an instruction that must precede the instruction to be registered (S94). Thereafter, it is determined whether or not the fetched entry is the last entry in the instruction reorder buffer 517 (S95). If it is not the last entry, the next entry is extracted (S91). If it is the last entry, the instruction is registered in the empty entry of the instruction reorder buffer 517 as in the conventional case (S96).

  If the entry is not an entry for the overtaking block instruction in step S93, it is determined whether the entry is for a store instruction (S97). When the entry is not a store instruction, that is, when the entry is a load instruction, it is determined whether the instruction to be registered is a load instruction (S910). When it is a load instruction, it is determined whether or not the fetched entry is the last entry of the instruction reorder buffer 517 (S95), the next entry is processed (S91), the instruction is registered (S96), and the process ends. To do.

  If it is not a load instruction in step S910, that is, if it is a store instruction, the memory disambiguation of the memory access instruction is performed, and the entry number is registered as an instruction that must be preceded if necessary. And If the instruction is a SIMD instruction or a vector instruction, the instruction registered immediately before is registered as an instruction to be preceded (S911). Step S911 is a conventional process. Thereafter, it is determined whether or not the fetched entry is the last entry in the instruction reorder buffer 517 (S95), the next entry is processed (S91), the instruction is registered (S96), and the process is terminated.

  If the entry is for a store instruction in step S97, it is determined whether the instruction to be registered is a load instruction (S98). When the instruction is not a load instruction, that is, when it is a store instruction, memory disambiguation of a memory access instruction is performed, and an entry number is registered as an instruction that must be preceded if necessary. If the instruction is a SIMD instruction or a vector instruction, the instruction registered immediately before is registered as an instruction to be preceded (S911). Thereafter, it is determined whether or not the fetched entry is the last entry in the instruction reorder buffer 517 (S95), the next entry is processed (S91), the instruction is registered (S96), and the process is terminated.

  If it is a load instruction in step S98, it is determined whether or not the overtaking permission flag of the store instruction registered in the entry is ON (S99). When the overtaking permission flag is OFF (passing is impossible), memory disambiguation of a memory access instruction is performed, and an entry number is registered as an instruction that must be preceded if necessary. If the instruction is a SIMD instruction or a vector instruction, the instruction registered immediately before is registered as an instruction to be preceded (S911). Thereafter, it is determined whether or not the fetched entry is the last entry in the instruction reorder buffer 517 (S95), the next entry is processed (S91), the instruction is registered (S96), and the process is terminated.

  When the overtaking permission flag is ON (overtaking permission) in step S99, it is determined whether or not the extracted entry is the last entry in the instruction reorder buffer 517 (S95), whether the next entry is processed (S91), Is registered (S96), and the process is terminated.

  In this way, when there is a store instruction with the overtaking permission flag ON, the memory disambiguation of the load instruction can be omitted, and the SIMD instruction and the vector instruction type load instruction are executed in advance. And program execution is accelerated.

  FIG. 10 is a diagram illustrating an effect in the case of a vector instruction in the present embodiment. The source code 101 is a sample C program loop. In the figure, x, y, z and idx are pointers. In this loop, values are vector-loaded from the two pointers, and the vector addition result is stored by the instruction 102. The store of instructions 102 is commonly referred to as vector spreading. The instruction line 103 sets the overtaking permission flag of the store instruction in the loop to ON (passing is permitted). For this loop, the compiler of the present invention generates a vector instruction sequence 104 for one iteration of the source code 101 loop. The VSC instruction 105 is a store instruction (vector spread instruction) in which the overtaking permission flag is set to ON. VLD is a vector load instruction, and VADD is a vector addition instruction. In executing the program, the instruction sequence 104 is repeatedly input into the instruction pipeline. The instruction sequence 106 indicates the order in which the instruction sequence 104 is input to the instruction pipeline. The leftmost example 1010 shows the order of input. First, the VLD instruction 109 is input. Instruction 108 is the first VLD instruction of the next iteration, and instruction 107 is the first VLD instruction of the next iteration.

  The time series 1011 is the processing status at the read / write stage of the instruction pipeline in the prior art. Instructions flow from right to left. Conventionally, since the vector instruction is not overtaken, the VLD instruction 1013 is not processed at the same time as or before the VSC instruction 1012. The same applies to the VLD instruction 1022 following the subsequent VSC instruction 1021.

  On the other hand, the time series 1014 shows the processing status at the read / write stage of the instruction pipeline in the present invention. Since the overtaking permission flag of the VSC instruction 1016 is set to ON, the subsequent VLD instruction 1015 is processed simultaneously with the VSC instruction 1016. Since the overtaking permission flag of the VSC instruction 1017 is also set to ON, the subsequent VLD instruction 1018 and VLD instruction 1019 are processed by overtaking the VSC instruction 1017. Thereby, the time corresponding to the time 1020 is shortened, and the program is speeded up.

  As another embodiment of the present invention, there is a method in which an instruction line for setting an overtaking permission flag to ON is designated for each sentence instead of designating to a loop.

  FIG. 11A is a diagram illustrating an example of a program 111 in another embodiment. FIG. 11B is a flowchart showing the operation of the overtaking permission flag setting means in this embodiment. The instruction line 112 is an instruction line designated for the immediately following sentence. The operation of the overtaking permission flag setting means at this time determines whether or not an instruction line for setting the overtaking permission flag to ON is first designated for the sentence (S113). If it is specified, the overtaking permission flag of the store instruction generated for the sentence is set to ON (S114). Otherwise, the overtaking permission flag of the store instruction is set to OFF (S115).

  FIG. 12 is a block diagram showing a functional configuration of a compiler in another embodiment of the present invention. In this embodiment, instead of specifying the instruction line for setting the overtaking permission flag ON and the instruction line for blocking the overtaking of the load instruction for the loop and the statement, the programmer like the compiler of FIG. The store instruction detection means 121 that can be overtaken is added to the compiler, so that the compiler analyzes the program, and in which position the overtake block instruction is created, which store instruction overtake permission flag is set to ON, and OFF is set. There is a method for automatically determining whether to do this. At this time, the detection result is used by the overtaking permission flag setting unit 122 and the overtaking block instruction generation unit 123.

  FIG. 13 is a diagram showing another embodiment of the present invention. In this embodiment, instead of providing an overtaking permission flag in a store instruction, an instruction indicating overtaking permission (overtaking permission instruction) is added, and a store instruction in a section between the instruction and the overtaking block instruction is determined as overtaking permission. It is. In the figure, OVT 135 is an overtaking permission command. The overtaking permission instruction is generated by the overtaking permission instruction generation unit 132 of the compiler 131 at the designated position of the instruction line 1317. The instruction sequence 134 is an instruction sequence for the loop 1316 generated by the compiler 131 of this embodiment. An instruction 138 from LABEL to the last IF is an instruction sequence corresponding to one iteration of the loop. Immediately before that, an OVT 135 that is an overtaking permission command is generated. Then, an overtaking block instruction SOVT137 corresponding to the instruction line 1318 is generated at the exit of the loop. The overtaking block instruction is generated at the designated position by the overtaking block instruction generation means 133 of the compiler 131. At this time, all store instructions 136 executed between the OVT 135 and the SOVT 137 are overtaken.

  The address calculation unit 139, the instruction execution completion notification 1314, the memory access unit 1315, and the instruction reorder buffer 1319 have the same configuration as the corresponding configuration of the embodiment described in FIG.

  The instruction reorder unit 1310 of this embodiment includes an overtaking permission / block instruction registration means 1311. The overtaking permission instruction is registered in the instruction reorder buffer 1319 by the overtaking permission / block instruction registration means 1311 in the same procedure as the overtaking block instruction registration means of FIG. The overtaking block instruction is registered in the instruction reorder buffer 1319 by the overtaking permission / block instruction registration unit 1311 in the same procedure as the overtaking block instruction registration unit of FIG.

  The instruction bypass unit 1312 of this embodiment determines whether or not an overtaking block instruction has been executed even after execution of the overtaking permission instruction, instead of determining whether the overtaking permission flag in FIG. 9 is ON (S99). . When not executed, since overtaking is permitted, it is determined whether or not the extracted entry is the last entry in the instruction reorder buffer 1319 (S95), the next entry is processed (S91), or the instruction is registered (S96). ), The process is terminated. When an overtaking block instruction is executed, memory disambiguation of a memory access instruction is performed, and an entry number is registered as an instruction that must be preceded if necessary.

  If the instruction is a SIMD instruction or a vector instruction, the instruction registered immediately before is registered as an instruction to be preceded (S911). Thereafter, it is determined whether or not the fetched entry is the last entry in the instruction reorder buffer 1319 (S95), the next entry is processed (S91), the instruction is registered (S96), and the process is terminated. Otherwise, the operation is the same as the instruction bypass means of FIG.

  As another embodiment of the present invention, instead of the programmer supporting the position of the overtaking permission instruction and the overtaking block instruction in the instruction line, an overtaking store instruction detecting means is added to the compiler as in the compiler of FIG. There is also a method in which the compiler analyzes the program and automatically determines where to pass the overtaking permission instruction and overtaking block instruction.

  The present invention is not limited to the above-described embodiment, and can be implemented in various other forms without departing from the gist of the present invention. For this reason, the said embodiment is only a mere illustration in all points, and is not interpreted limitedly. For example, the above-described processing steps can be executed in any order or in parallel as long as there is no contradiction in the processing contents.

A part or all of the above embodiments can be described as in the following supplementary notes, but is not limited thereto.

  (Supplementary Note 1) A processor having an instruction set including a store instruction having an overtaking permission flag indicating permission or disapproval of overtaking of a load instruction, and an overtaking block instruction for blocking overtaking of a load instruction, and the overtaking permission flag An overtaking permission flag setting means to set; an overtaking block instruction generation means for generating the overtaking block instruction; an overtaking block instruction registration means for registering the overtaking block instruction in an instruction reorder buffer; and the overtaking permission flag. An instruction reorder unit having instruction bypass means for registering a memory access instruction in an instruction reorder buffer while referring to the set store instruction.

  (Supplementary Note 2) The instruction reorder unit is configured to process the instruction for the first instruction in which the overtaking permission flag is set to ON so that the subsequent instruction is processed simultaneously with or overtaking the first instruction. The program execution system according to appendix 1, which is registered in a reorder buffer.

  (Supplementary note 3) In a program execution system including a processor having an instruction set including a store instruction having an overtaking permission flag indicating permission or non-permission of overtaking of a load instruction, and an overtaking block instruction for blocking overtaking of a load instruction. A method of executing a program, wherein in a compiler, the overtaking permission flag setting step for setting the overtaking permission flag, in the compiler, the overtaking block instruction generation step for generating the overtaking block instruction, and the instruction reorder unit includes: An overtaking block instruction registration step for registering an overtaking block instruction in an instruction reorder buffer, and the instruction reorder unit refers to a store instruction in which the overtaking permission flag is set while referring to a memory access instruction. The method comprising the instruction bypass step of registering the Dabaffa, the.

  (Supplementary note 4) The instruction reorder unit is configured to process the subsequent instruction for the first instruction in which the overtaking permission flag is set to ON at the same time as or overtaking the first instruction. The method according to appendix 3, wherein the method is registered in a reorder buffer.

51,131 compiler, 52,122 overtaking permission flag setting means, 53,123,133 overtaking block instruction generation means, 58,139 address calculation unit, 59,1310 instruction reorder unit, 510 overtaking block instruction registration means, 511,1312 instructions Bypass means, 512, 1314 instruction execution completion notification, 513, 1315 memory access unit, 517, 1319 instruction reorder buffer, 121 overtaking store instruction detecting means, 132 overtaking permission instruction generating means, 1311 overtaking permission / block instruction registration means

Claims (4)

A processor having an instruction set including a store instruction having an overtaking permission flag indicating permission or disapproval of overtaking of the load instruction, and an overtaking block instruction for blocking overtaking of the load instruction;
A compiler having overtaking permission flag setting means for setting the overtaking permission flag and overtaking block instruction generation means for generating the overtaking block instruction;
An overtaking block instruction registration means for registering the overtaking block instruction in an instruction reorder buffer; and an instruction bypass means for registering a memory access instruction in the instruction reorder buffer while referring to the store instruction in which the overtaking permission flag is set. An instruction reorder unit;
A program execution system.   The instruction reorder unit registers, in the instruction reorder buffer, the subsequent instruction for the first instruction having the overtaking permission flag set to ON to be processed simultaneously with or overtaking the first instruction. The program execution system according to claim 1, wherein: A program is executed in a program execution system including a processor having an instruction set including a store instruction having an overtaking permission flag indicating permission or disapproval of overtaking of a load instruction and an overtaking block instruction for blocking overtaking of a load instruction A method,
In the compiler, an overtaking permission flag setting step for setting the overtaking permission flag;
In the compiler, an overtaking block instruction generation step for generating the overtaking block instruction;
An instruction reorder unit for registering the overtaking block instruction in an instruction reorder buffer;
An instruction bypass step in which the instruction reorder unit registers a memory access instruction in an instruction reorder buffer while referring to a store instruction in which the overtaking permission flag is set;
A method comprising:   The instruction reorder unit registers, in the instruction reorder buffer, the subsequent instruction for the first instruction having the overtaking permission flag set to ON to be processed simultaneously with or overtaking the first instruction. 4. The method of claim 3, wherein:

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