JP2012209337A - Method for manufacturing nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor memory device capable of solving a problem of a method for manufacturing a conventional MONOS type nonvolatile semiconductor memory device that a side etching is invaded because a wet-etching is used for etching process of a top insulating film, thereby an insulation quality between a charge storage layer and a gate electrode is damaged, an electrical leak is generated and electric characteristics such as an erasure property degrade.SOLUTION: In a method for manufacturing a nonvolatile semiconductor memory device, an area simultaneously forming a top insulation film and a side wall protective film is formed by using two sacrificial films and oxidation treatment. Thereby a side etching of a memory gate insulation film does not occur.

Description

  The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device that stores information by storing charges in a charge storage layer in a memory gate insulating film.

A nonvolatile semiconductor memory device has a characteristic of maintaining stored data even when power supply is interrupted.
At present, a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) type having a floating gate is widely used as a nonvolatile semiconductor memory device, and a stacked gate structure having a relatively simple manufacturing process is adopted in particular. ing.

  A non-volatile semiconductor memory device having a stacked gate structure is formed by sequentially stacking a floating gate (charge storage layer) composed of a tunnel insulating film, a conductive film, a gate interlayer insulating film, and a control gate electrode on a semiconductor substrate. In this structure, the source and drain are formed in the semiconductor substrate at both ends.

  Since the floating gate is electrically isolated from the control gate electrode and the semiconductor substrate and can hold charge freely, whether or not information is stored depends on whether or not the charge is held in the floating gate. It can be.

  In order to store information in such a nonvolatile semiconductor memory device, a predetermined write voltage is applied from the control gate electrode, and charges (electrons or holes) are injected from the semiconductor substrate side into the floating gate through the tunnel insulating film. It is common to make it. At this time, there are known a method in which high energy is given to the charge to inject it into hot carriers, a method in which a tunnel current is injected into the tunnel insulating film, and the like.

  Since the floating gate is electrically isolated from the others, it can stay there for a very long time, but since the charge in the injected floating gate is in a free charge state, the tunnel insulating film under the floating gate If even a portion is damaged, it will escape from it and lose all the charge stored in the floating gate. In order to avoid such a failure mode, a tunnel insulating film having a sufficient thickness is required in a nonvolatile semiconductor memory device having a floating gate.

  However, if the thickness of the tunnel insulating film increases, the probability of breakdown of the tunnel insulating film decreases, but it becomes difficult to inject charges from the semiconductor substrate side, so the write voltage applied from the control gate electrode also increases, and non-volatile The operating voltage of the conductive semiconductor memory device also increases. As a result, the power consumption of the entire nonvolatile semiconductor memory device also increases.

  In order to solve such a problem, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type non-volatile semiconductor memory device having a feature in a memory gate insulating film is proposed, although it is a MOSFET type non-volatile semiconductor memory device. Has been.

Here, a general MONOS type nonvolatile semiconductor memory device will be described with reference to FIG. FIG. 7 is a diagram schematically showing the cross section. In FIG. 7, 50 is a semiconductor substrate, 51 is a tunnel insulating film, 52 is an insulating charge storage layer, 53 is a top insulating film, 54 is a gate electrode, and 55 is a high concentration impurity layer serving as a source and drain. The tunnel insulating film 51, the charge storage layer 52, and the top insulating film 53 constitute a memory gate insulating film 56.

  The MONOS type nonvolatile semiconductor memory device has a memory gate insulating film 56 in which a tunnel insulating film 51, a charge storage layer 52, and a top insulating film 53 are sequentially stacked on a semiconductor substrate 50. A gate electrode 54 is provided on the memory gate insulating film. High concentration impurity layers 55 are provided in the semiconductor substrate 50 at both ends of the memory gate insulating film 56.

  Unlike the nonvolatile semiconductor memory device having a floating gate, the charge storage layer 52 of the MONOS type nonvolatile semiconductor memory device is formed of an insulating film. For this reason, since the accumulated charge is in a bound charge state, even if a part of the tunnel insulating film 51 is damaged, only a small amount of charge is lost.

Therefore, in the MONOS type nonvolatile semiconductor memory device, the thickness of the tunnel insulating film 51 can be made thinner than that of the nonvolatile semiconductor memory device having the floating gate. As a result, the MONOS type nonvolatile semiconductor memory device can be driven at a lower operating voltage, and its power consumption can be reduced.
Such a MONOS type nonvolatile semiconductor memory device has many proposals (see, for example, Patent Document 1).

JP-A-4-343477 (pages 3-4, Fig. 1)

  The prior art disclosed in Patent Document 1 refers to a general MONOS type nonvolatile semiconductor memory device. When manufacturing such a MONOS type nonvolatile semiconductor memory device, a tunnel insulating film, a charge storage layer, and a top insulating film are sequentially stacked on a semiconductor substrate, and then these films are etched and removed into a predetermined shape. Then, a memory gate insulating film is formed.

  However, according to a study by the inventors, it has been found that when the tunnel insulating film, the charge storage layer, and the top insulating film are removed by etching, the tunnel insulating film and the top insulating film are side-etched.

FIG. 8 shows the situation. FIG. 8 is a cross-sectional view schematically showing a manufacturing process of the MONOS type nonvolatile semiconductor memory device.
In FIG. 8, 60 is a silicon semiconductor substrate, 61a and 61b are tunnel insulating films (silicon oxide films), 62a and 62b are charge storage layers (silicon nitride films), and 63a and 63b are top insulating films (silicon oxide films). . Reference numeral 64 denotes a mask material (photoresist). Reference numeral 66 denotes a memory gate insulating film.

FIG. 8A shows a state in which a tunnel insulating film 61a, a charge storage layer 62a, and a top insulating film 63a are sequentially stacked on a silicon semiconductor substrate 60, and a mask material 64 is provided in a predetermined region above the tunnel insulating film 61a. Yes. In the subsequent manufacturing process, the memory gate insulating film 66 composed of the tunnel insulating film 61a, the charge storage layer 62a, and the top insulating film 63a is etched according to the shape of the mask material 64.
FIG. 8B shows a state after the memory gate insulating film 66 is sequentially etched along the mask material 64.

  As shown in FIG. 8B, the charge storage layer 62b is processed in accordance with the shape of the mask material 64, and the end portion of the mask material 64 is coincident with the end portion, and side etching is performed. Absent. However, the tunnel insulating film 61b and the top insulating film 63b are side-etched. In particular, the top insulating film 63b has a large amount of side etching.

This situation is related to etching using different etching conditions for each of the tunnel insulating film, the charge storage layer, and the top insulating film.
Wet etching using hydrofluoric acid is used for etching the top insulating film 63a and the tunnel insulating film 61a, and dry etching using fluorine-based gas is used for etching the charge storage layer 62a, but the tunnel insulating film 61a and the top insulating film 63a are used. This is because each uses wet etching.

  Since wet etching is isotropic in the first place, side etching tends to occur. For this reason, the tunnel insulating film is side-etched, but the top insulating film is exposed to the etching solution twice because it becomes a second etching environment when the tunnel insulating film is wet-etched. For this reason, the top insulating film is further side-etched.

The background to adopting such a manufacturing method is that the tunnel insulating film, the charge storage layer, and the top insulating film are thin, and that it is difficult to control the amount of overetching of the semiconductor substrate serving as the base film. It is done.
In other words, the tunnel insulating film, the charge storage layer, and the top insulating film are thin films of several to several tens of kilometers depending on the electrical characteristics of the nonvolatile semiconductor memory device. In addition, if the surface of the semiconductor substrate in the lower element formation region is etched, the impurity ion diffusion state changes when ion implantation is performed to form a source region and a drain region in a later manufacturing process. It will end up.

  Since the MONOS type nonvolatile semiconductor memory device is a MOSFET type element, when such a diffusion state change of impurity ions occurs, the threshold voltage shifts or a leak occurs. Get up.

  For this reason, the tunnel insulating film, the charge storage layer, and the top insulating film must be etched under conditions that have good selectivity with respect to the underlying semiconductor substrate.

If only the processing shapes of the tunnel insulating film and the top insulating film are considered, it is desirable to use dry etching with a very small side etching amount compared to wet etching. However, in dry etching, the in-plane uniformity of the etching rate is poor, and since high energy plasma is used, the selectivity with respect to the underlying film is poor.
Therefore, wet etching having high selectivity with respect to the semiconductor substrate must be used for etching the tunnel insulating film and the top insulating film.

Now, the MONOS type nonvolatile semiconductor memory device in which side etching occurs as shown in FIG. 8B has a big problem as a semiconductor element.
Originally, the top insulating film must have sufficient insulating properties so that unnecessary carrier injection from the upper gate electrode to the charge storage layer does not occur. However, in the state shown in FIG. 8B, since the top insulating film 63b is largely side-etched, the insulation with the gate electrode (not shown) is not maintained, and carriers from the gate electrode are not top insulating film. And may be injected into the charge storage layer.

When such a situation occurs, for example, a malfunction in the operation of the nonvolatile semiconductor memory device such as an erasure failure occurs.
An N-channel MONOS nonvolatile semiconductor memory device will be described as an example. In this case, since holes serve as carriers, electrons are stored in the charge storage layer in the information writing state. When erasing the information, an erasing voltage is applied from the gate electrode. At that time, in the state shown in FIG. 8B, electrons are injected from the gate electrode into the charge storage layer, and thus electrons accumulated in the charge storage layer cannot be excluded. For this reason, erasure failure occurs.

  As is apparent from the above description, when a general MONOS type nonvolatile semiconductor memory device is to be manufactured, the use of a manufacturing method that is intended to prevent deterioration of electrical characteristics such as threshold voltage shift and leakage is particularly top. Side etching occurs in the insulating film, the insulating property of the charge storage layer cannot be maintained, and operation defects such as erasure failure occur as a nonvolatile semiconductor memory device.

  The present invention has been made to solve such a problem, and provides a method for manufacturing a nonvolatile semiconductor memory device that protects a tunnel insulating film and a top insulating film from side etching.

  In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device of the present invention employs the following method.

A memory gate insulation film comprising a tunnel insulation film, a charge storage layer, and a top insulation film is formed on the surface of a semiconductor substrate having a source region and a drain region on a semiconductor substrate, and a channel region sandwiched between these regions. A method for manufacturing a non-volatile semiconductor memory device having a MIS transistor structure including a gate electrode mainly composed of metal on the memory gate insulating film,
An insulating film forming step of forming a tunnel insulating film and a charge storage layer on the surface of the semiconductor substrate in a region where the memory gate insulating film is to be formed, and a first end so as to cover the upper end surface and side end surfaces of the tunnel insulating film and the charge storage layer A first sacrificial film forming step for forming the sacrificial film, a second sacrificial film forming step for forming a second sacrificial film over the semiconductor substrate so as to cover the first sacrificial film, A second sacrificial film removing step of etching the second sacrificial film so as to remove the surface of the second sacrificial film that overlaps the sacrificial film in a planar manner to expose the upper end surface of the first sacrificial film; A first sacrificial film removing step of removing the sacrificial film 1 to expose the upper end surface and the side end surfaces of the tunnel insulating film and the charge storage layer; oxidizing the semiconductor substrate; and forming a top insulating film on the charge storage layer , Side wall protective film covering side end portions of tunnel insulating film and charge storage layer And the side wall protective film forming step of simultaneously forming, characterized by having a.

  In this way, side etching of the memory gate insulating film does not occur.

  In the insulating film forming step, the tunnel insulating film may be formed by oxidizing the semiconductor substrate.

  With such a configuration, a high-quality insulating film can be formed by a simple method.

  Nitrogen ions for ion-implanting nitrogen into the semiconductor substrate in the region between the side end face of the tunnel insulating film and the charge storage layer and the second sacrificial film between the first sacrificial film removing step and the sidewall protective film forming step You may make it have an injection | pouring process.

With such a configuration, the thickness of the top insulating film can be increased without changing the thickness of the sidewall protective film.

  After the side wall protective film forming step, a light doped region forming step for forming a light doped region having the same conductivity type as the source region and the drain region and having a low impurity concentration on the semiconductor substrate planarly overlapping the side wall protective film is provided. Also good.

  With such a configuration, when writing to the nonvolatile semiconductor memory device, a higher electric field can be applied to the boundary between the channel region and the source region and drain region, so that hot carrier injection is more stable. To be able to write.

  According to the present invention, side etching does not occur in the tunnel insulating film or the top insulating film. As a result, a nonvolatile semiconductor memory device can be manufactured in which insulation is maintained between the gate electrode and the charge storage layer and there are no operational problems.

1 is a cross-sectional view schematically illustrating a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view for sequentially explaining a first embodiment of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. It is sectional drawing shown typically in order to demonstrate 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device of this invention. It is sectional drawing for demonstrating sequentially 2nd Embodiment of the manufacturing method of the non-volatile semiconductor memory device of this invention. It is sectional drawing shown typically in order to demonstrate 3rd Embodiment of the manufacturing method of the non-volatile semiconductor memory device of this invention. It is sectional drawing for demonstrating sequentially 3rd Embodiment of the manufacturing method of the non-volatile semiconductor memory device of this invention. 1 is a cross-sectional view illustrating a known MONOS type nonvolatile semiconductor memory device. It is sectional drawing explaining the mode of the side etching of the known MONOS type non-volatile semiconductor memory device.

In the method for manufacturing a nonvolatile semiconductor memory device of the present invention, a sidewall protective film for protecting the sidewall of a memory gate insulating film composed of a tunnel insulating film, a charge storage layer, and a top insulating film is formed simultaneously with the top insulating film. Is a feature.
For this purpose, after forming the tunnel insulating film and the charge storage layer, the first sacrificial film and the second sacrificial film are formed so as to cover these stacked films, and the two sacrificial films are processed. Then, an empty space is provided around the laminated film of the tunnel insulating film and the charge storage layer. If this is called an oxide area, this oxide area is also filled with an oxide film when the top oxide film is formed. The buried oxide film becomes a side wall protective film.

  That is, the idea is to create a “mold” formed by processing two sacrificial films around the laminated film of the tunnel insulating film and the charge storage layer, and to oxidize the “mold”.

  By having this side wall protective film, side etching of the memory gate insulating film does not occur.

Further, by leaving the side wall protective film, the side wall portion of the memory gate insulating film can be protected from the entry of impurities and the like, so that the nonvolatile semiconductor memory device can be protected even after manufacturing.
In this way, the shape in which the side wall protective film is left as the side wall protective film has a structure similar to that of the side wall provided on the side wall portion of the gate insulating film.

  Hereinafter, a method for manufacturing a nonvolatile semiconductor memory device of the present invention will be described with reference to the drawings. There are three embodiments, the first embodiment shows a characteristic manufacturing method of the present invention, and the second embodiment shows a manufacturing method in which a lightly doped region is further provided, The third embodiment shows a manufacturing method in which the thickness of the sidewall protective film is adjusted by nitrogen implantation. Both are described using a MONOS type nonvolatile semiconductor memory device.

  In the description, the description will be made with reference to the drawings, but the drawings that are not instructed should also be referred to appropriately. Moreover, the same number is attached | subjected to the same structure and detailed description is abbreviate | omitted.

[Description of First Embodiment: FIGS. 1 and 2]
A first embodiment of a method for manufacturing a nonvolatile semiconductor memory device will be described with reference to FIGS.
FIG. 1 is a cross-sectional view schematically showing a structure of a nonvolatile semiconductor memory device, and FIG. 2 is a cross-sectional view schematically showing a manufacturing method in order. Note that the drawings used in the invention are schematic diagrams showing only parts necessary for explaining the invention, and metal wirings, final protective films and the like are omitted.

First, the structure will be described with reference to FIG.
In this structure, after the tunnel insulating film and the charge storage layer are manufactured, the top insulating film is formed, and at the same time, the side wall protective film is provided so as to protect the side wall of the memory gate insulating film.

  In FIG. 1, 1 is a semiconductor substrate, 2 is a tunnel insulating film, 3 is a charge storage layer, 4 is a top insulating film, 5 is a sidewall protective film, 6 is a gate electrode, and 7 is a high concentration impurity which becomes a source region or a drain region. Is a layer. Reference numeral 11 denotes a memory gate insulating film composed of the tunnel insulating film 2, the charge storage layer 3, and the top insulating film 4.

  For example, a silicon substrate can be used as the semiconductor substrate 1. Further, the tunnel insulating film 2 and the top insulating film 4 can be composed of a silicon oxide film. The charge storage layer 3 can be composed of a silicon nitride film.

  The high concentration impurity layer 7 serves as a source region and a drain region of the nonvolatile semiconductor memory device. Which is the source and which is the drain is determined by how the nonvolatile semiconductor memory device is operated and how the metal wiring (not shown) is arranged, and therefore cannot be determined in general.

  In the MONOS type nonvolatile semiconductor memory device, a tunnel insulating film 2, a charge storage layer 3, and a top insulating film 4 are sequentially stacked on a semiconductor substrate 1 to constitute a memory gate insulating film 11. A gate electrode 6 is provided on the memory gate insulating film 11. A sidewall protective film 5 is provided on the sidewall portion of the memory gate insulating film 11. A high concentration impurity layer 7 is provided inside the semiconductor substrate 1 at both ends of the memory gate insulating film 11 including the sidewall protective film 5.

In the example shown in FIG. 1, the sidewall protective film 5 is formed so as to have substantially the same height in the vertical direction as the memory gate insulating film 11, but the height is higher than that of the memory gate insulating film 11. It doesn't matter.
Since the sidewall protective film 5 needs to protect the sidewalls of the top insulating film 4 and the charge storage layer 3, it is preferable to form the sidewall protective film 5 higher than the memory gate insulating film 11 unless there is a structural limitation in the vertical direction.

  Although depending on the electrical characteristics of the MONOS type nonvolatile semiconductor memory device, the film thickness of the memory gate insulating film 11 is about 80 to 100 mm. When the sidewall protective film 5 is made thicker than the film thickness of the memory gate insulating film 11, a margin may be set in consideration of the amount of each film that is reduced during the etching process.

  Although the high concentration impurity layer 7 is provided so as not to overlap the side wall protective film 5 in a plan view, the high concentration impurity layer 7 is extended in the direction of the memory gate insulating film 11 (horizontal direction). Thus, the side wall protective film 5 may be overlapped in a planar manner.

Next, a manufacturing method is demonstrated using FIG.
In FIG. 2, 8 is a field insulating film, 9 is a first sacrificial film, and 10 is a second sacrificial film. Reference numeral 22 denotes an oxidation area. The oxidized area 22 is an empty space formed by processing two sacrificial films, and this name is used for convenience.
FIGS. 2A to 2D are views seen from the same direction as the cross-sectional view shown in FIG.

FIG. 2A is a diagram illustrating an insulating film forming process for forming the tunnel insulating film 2 and the charge storage layer 3 after the element isolation process.
FIG. 2B is a diagram for explaining a first sacrificial film forming process for forming the first sacrificial film 9 and a second sacrificial film forming process for forming the second sacrificial film 10.
FIG. 2C shows a second sacrificial film removing step in which the second sacrificial film 10 is etched only in a portion overlapping the first sacrificial film 9 in a planar manner to expose the upper surface of the first sacrificial film 9. Then, a first sacrificial film removing step for selectively removing the first sacrificial film 9 is described.
FIG. 2D shows a side wall protective film forming step in which the exposed surface of the semiconductor substrate 1 and the surface of the charge storage layer 3 are oxidized by the same oxidation process to form the side wall protective film 5 and the top insulating film 4; Then, the process of forming the gate electrode 6 and the high concentration impurity layer 7 is a figure explaining.

First, an element isolation process and an insulating film formation process will be described (FIG. 2A).
The semiconductor substrate 1 is selectively oxidized to form a field oxide film 8 that is an element insulating film. This manufacturing process is formed by a known selective oxidation method called a LOCOS (LoCal Oxidation of Silicon) method. The film thickness of the field oxide film 8 is, for example, about 5000 mm.

  After the field oxide film 8 is formed, the surface of the semiconductor substrate 1 is exposed, and this portion is an element formation region. In this element formation region, components such as a memory gate insulating film of the nonvolatile semiconductor memory device are formed. The field oxide film 8 ensures electrical insulation from the adjacent nonvolatile semiconductor memory device.

Next, the tunnel insulating film 2 and the charge storage layer 3 are formed in order. These films are formed only in the channel region, which is the region where the memory gate insulating film is to be formed, inside the element forming region surrounded by the field insulating film 8. At this time, the thickness of the tunnel insulating film 2 is about 15 to 20 mm, and the thickness of the charge storage layer 3 is about 70 to 90 mm.
Since FIG. 2 is a schematic diagram, it is described that the total film thickness of the tunnel insulating film 2 and the charge storage layer 3 is about half of the film thickness of the field oxide film 8. It is. Incidentally, the thickness of the field oxide film is about 5000 mm.

  The tunnel insulating film 2 is formed by first oxidizing the surface of the semiconductor substrate 1 including the field oxide film 8 to form the tunnel insulating film 2 on the semiconductor substrate 1. Next, the charge storage layer 3 is formed by a known CVD method or the like.

Thereafter, the channel region portion is covered using a predetermined mask material (not shown), and the charge storage layer 3 and the tunnel insulating film 2 are etched in this order.
Either dry etching or wet etching may be used for etching the charge storage layer 3, but a tunnel insulating film 2 is provided below the charge storage layer 3, and damage to the semiconductor substrate 1 due to overetching is caused. In consideration of the fact that it does not occur, in this case, dry etching that does not cause side etching is preferably used.

  Etching of the tunnel insulating film 2 must use wet etching. As already described, the lower part of the tunnel insulating film 2 is the semiconductor substrate 1, and if dry etching is used, the semiconductor substrate 1 is slightly etched by over-etching. This is because the impurity diffusivity changes and transistor characteristics vary. Therefore, here, the tunnel insulating film 2 is processed using wet etching having good selectivity with respect to the semiconductor substrate 1.

  At this time, the tunnel insulating film 2 is retracted in the horizontal direction by side etching. However, as described above, the tunnel insulating film 2 is a thin film having a thickness of about 15 to 20 mm, and the side etching itself is a small amount. Therefore, in FIG. Although the side end surfaces of the tunnel insulating film 2 are illustrated as being continuous in a vertical direction, in practice, it may be considered that the tunnel insulating film 2 is slightly retracted in the horizontal direction.

Next, a sacrificial film forming process will be described (FIG. 2B). This process includes a first sacrificial film forming process and a second sacrificial film forming process.
The first sacrificial film 9 and the second sacrificial film 10 are composed of thin films of different materials. For example, SOG (Spin on Glass) can be used for the first sacrificial film 9, and for example, a silicon nitride film can be used for the second sacrificial film 10.

A first sacrificial film forming step will be described.
Since the purpose of the first sacrificial film 9 is to cover the tunnel insulating film 2 and the charge storage layer 3, if the film thickness of these films is set to the above example, a film thickness of about 200 to 300 mm is required. is there. In the case of using SOG, SOG is coated on the entire upper surface of the semiconductor substrate 1 and then heat treated at about 300 to 400 ° C. to sinter and form a thin film.

Thereafter, the SOG is etched into a shape that covers the upper end surface and the side end surfaces of the laminated film of the tunnel insulating film 2 and the charge storage layer 3.
At this time, since the lower portion of the first sacrificial film 9 is the semiconductor substrate 1, wet etching is used as an etching method. Further, since the first sacrificial film 9 needs to protect the side end faces of the tunnel insulating film 2 and the charge storage layer 3, a certain width is given in the channel length direction so that these side end faces are not exposed. Mask and etch. That is, the masking is performed in consideration of a sufficient process margin so that the end of the laminated film of the tunnel insulating film 2 and the charge storage layer 3 is not exposed.

A second sacrificial film forming step will be described.
Since the second sacrificial film 10 has a role as a mask material in an oxidation process in the subsequent side wall protective film forming step, it has a sufficient film thickness so that oxygen molecules do not penetrate to the surface of the lower semiconductor substrate 1. Must be. Of course, this depends on what kind of film is used for the second sacrificial film 10, but when a silicon nitride film formed by the CVD method is used, for example, a film thickness of about 1500 mm is required. Incidentally, since the film grows in the CVD method so as to reflect the unevenness of the deposition surface, it has a shape covering the first sacrificial film 9 as shown in FIG.

Next, the second sacrificial film removal step will be described.
In this step, the surface of the second sacrificial film 10 in a portion overlapping the first sacrificial film 9 in a plan view is removed.
First, masking is performed using a predetermined mask material (not shown) so that the surface of the second sacrificial film 10 in a portion overlapping the first sacrificial film 9 is opened, and etching is performed. In this case, the lower part of the second sacrificial film 10 which is an etching region is only the upper surface part of the first sacrificial film 9, and it is not necessary to consider the influence of over-etching. Can be used.

Next, the first sacrificial film removal step will be described (FIG. 2C).
In this step, the exposed first sacrificial film 9 is removed, and a process for forming an oxidized area 22 by the second sacrificial film 10 around the laminated film of the tunnel insulating film 2 and the charge storage layer 3. It is.
When the exposed first sacrificial film 9 uses SOG, it can be removed with diluted hydrofluoric acid.

  Incidentally, the SOG used for the first insulating film 9 and the tunnel insulating film 2 are both the same silicon oxide film, but the tunnel insulating film 2 is a hard silicon oxide film (highly about 1000 ° C.) grown in an oxidation furnace ( SOG is a fragile film that is obtained by sintering a liquid silicon oxide film at a low temperature (about 300 to 400 ° C.). It is possible to give etching selectivity by adjusting.

  In this case, by diluting the concentration of hydrofluoric acid to about 10%, it becomes possible to form a wet etching solution in which only the SOG is etched and the thermal oxide film is not etched. Water or the like can be used as the diluent.

  By using such a wet etching solution, the tunnel insulating film 2 is etched even if the side end face of the tunnel insulating film 2 is exposed to the wet etching solution after the SOG as the first sacrificial film 9 is removed. Will never be done. Further, since the charge storage layer 3 and the second sacrificial film 10 are composed of a silicon nitride film, and the semiconductor substrate 1 is also silicon, both have resistance to a hydrofluoric acid solution. Therefore, in this step, the tunnel insulating film 2, the charge storage layer 3, the second sacrificial film 10, and the surface of the semiconductor substrate 1 are all selectively damaged without being damaged by etching. It can be removed.

By this step, the second sacrificial film 10 is shaped to be separated from the periphery of the laminated film of the tunnel insulating film 2 and the charge storage layer 3 by the amount of the removed first sacrificial film 9. This empty space is the oxidation area 22.
The oxidized area 22 is a portion that is filled with an oxide film in a side wall protective film forming process described later.

Next, the side wall protective film forming step will be described (FIG. 2D).
This step is a step of filling the oxide area 22 created by the previous step with an oxide film.
Since the second sacrificial film 10 is opened, the upper end surface and the side end surface of the laminated film of the tunnel insulating film 2 and the charge storage layer 3 are exposed. In this state, the semiconductor substrate 1 is oxidized. Since the charge storage layer 3 is composed of a silicon nitride film, a slight oxide film is also formed on the charge storage layer 3, which becomes a thin top insulating film 4. A sidewall protective film 5 is formed on the sidewall of the laminated film of the tunnel insulating film 2 and the charge storage layer 3. It is a feature of the present invention that the top insulating film 2 and the sidewall protective film 5 are formed simultaneously.

At this time, the top insulating film 4 and the sidewall protective film 5 are formed by the same oxidation process, but it should be noted that the oxidation rates are different.
The top insulating film 4 is formed by oxidation and growth of silicon and oxygen in the silicon nitride film that is the charge storage layer 3. The silicon nitride film is already in a stable state due to the reaction of silicon and nitrogen. Therefore, the oxidation rate is slow. On the other hand, the sidewall protective film 5 is formed by oxidizing the surface of silicon, which is the semiconductor substrate 1, and therefore has a high oxidation rate.

  As a result, the side wall protective film 5 can be grown to a thickness equivalent to that of the top insulating film 4. The side wall protective film 5 has a purpose of protecting the charge storage layer 3 made of the same material as that of the second sacrificial film 10 when the second sacrificial film 10 is peeled off in the subsequent process. The gate electrode 6 may be grown to a height that covers at least the side end face of the charge storage layer 3 in the direction. In order to ensure sufficient, it is desirable to grow to the same height as the top insulating film 4 in the vertical direction. Of course, if there is no factor limiting the height of the element in the vertical direction, it may be grown higher than the top insulating film 4.

Next, the subsequent steps will be described.
After the sidewall protective film 5 and the top insulating film 4 are formed, the second sacrificial film 10 is removed. Here, for example, by using phosphoric acid, only the silicon nitride film as the second sacrificial film 10 can be selectively removed. The charge storage layer 3 is also formed of the same silicon nitride film, but the side end face is protected by the side wall protective film 5 and the upper face thereof is protected by the top insulating film 4 and thus is not etched.

  After the second sacrificial film 10 is peeled off, the semiconductor substrate 1 between the sidewall protective film 5 and the field oxide film 8 is exposed, and thus a high concentration impurity layer 7 is formed in this region. The high concentration impurity layer 7 is formed by a known ion implantation technique. Thereafter, although not shown, a heat treatment process for activating impurity ions implanted into the semiconductor substrate 1 by an ion implantation technique may be performed immediately.

In the example shown in FIG. 2D, the case where the high concentration impurity layer 7 is formed between the sidewall protective film 5 and the field oxide film 8 is shown. Of course, the present invention is not limited to this.
For example, by using a known oblique implantation ion implantation technique, impurity ions can be implanted at an angle with respect to the semiconductor substrate 1, so that a predetermined region is formed with a mask material with right inclination, left inclination, and no inclination, respectively. By performing ion implantation three times while covering, the high concentration impurity layer 7 extending to the semiconductor substrate 1 below the side wall protective film 5 can be formed.

Then, a film (for example, polysilicon) as a material for the gate electrode is formed on the semiconductor substrate 1 by a known CVD method, masked using a mask material (not shown), and the material is etched. Thus, the gate electrode 6 is formed.
About the manufacturing process after forming this gate electrode 6, since a well-known technique is used, description is abbreviate | omitted.

[Description of Second Embodiment: FIGS. 3 and 4]
A second embodiment of a method for manufacturing a nonvolatile semiconductor memory device will be described with reference to FIGS. FIG. 3 is a sectional view schematically showing the structure of the nonvolatile semiconductor memory device, and FIG. 4 is a sectional view schematically showing the manufacturing method in order. In addition, these figures are schematic diagrams showing only the parts necessary for explaining the invention, like the figures already explained.

First, the structure will be described with reference to FIG.
In this structure, in the nonvolatile semiconductor memory device manufactured in the first embodiment described with reference to FIG. 1, the thickness of the top insulating film 4 is relatively changed without changing the thickness of the sidewall protective film 5. It is formed thickly.

The characteristic part of the present invention is that the top insulating film 4 and the sidewall protective film 5 are formed in the same process.
The simultaneous formation of the two films is characterized in that the film formation rate ratio does not change even when the oxidation conditions are changed when these films are formed by oxidation treatment. For example, the oxidation rate itself can be changed by changing the amount of oxygen introduced or changing the oxidation temperature as the oxidation condition, but the deposition rate of the top insulating film 4 is also the same as that of the sidewall protective film 5. Since the film speed also changes at the same rate, the film formation speed ratio does not change.

Thereby, a nonvolatile semiconductor memory device in which side etching of the memory gate insulating film does not occur can be manufactured. However, sometimes the thickness of the top insulating film is desired to be changed according to electric characteristics such as memory characteristics.
As described above, the top insulating film is a film provided to maintain the insulation between the upper gate electrode and the charge storage layer, and the surplus from the gate electrode during information writing or erasing. Has a role to prevent the injection of an unnecessary charge.
For this reason, there is a case where it is desired to set the thickness of the top insulating film to a predetermined value according to the desired memory characteristics.

  However, for the reason described above, if the top insulating film 4 is simply formed to be thick, the side wall protective film 5 is also formed to be thick. The fact that the sidewall protective film 5 is formed thickly means that an oxide film grows also in the depth direction of the semiconductor substrate 1, and the threshold voltage characteristics of the MOSFET may become high, which is a problem. is there.

  The second embodiment corresponds to such a background, and the top insulating film 4 can be made thick without changing the film thickness of the sidewall protective film 5. Specifically, nitrogen ions are implanted into the semiconductor substrate 1 to suppress oxidation of the sidewall protective film 5.

Next, the manufacturing method will be described with reference to FIG.
In FIG. 4, 33 is a nitrogen ion implantation region. 4 (a) to 4 (d) are views seen from the same direction as the cross-sectional view shown in FIG.

FIG. 4A is a diagram illustrating an insulating film forming process for forming the tunnel insulating film 2 and the charge storage layer 3 after the element isolation process.
FIG. 4B is a view for explaining a first sacrificial film forming step for forming the first sacrificial film 9 and a second sacrificial film forming step for forming the second sacrificial film 10.
FIG. 4C shows a second sacrificial film removal step in which the second sacrificial film 10 is etched only in a portion overlapping the first sacrificial film 9 to expose the upper surface of the first sacrificial film; Thereafter, a first sacrificial film removal step for selectively removing the first sacrificial film 9 and a nitrogen ion implantation step for forming a nitrogen ion implantation region 33 on the exposed surface of the semiconductor substrate 1 are described. is there. FIG.
4D shows a side wall protective film forming step in which the exposed surface of the semiconductor substrate 1 and the surface of the charge storage layer 3 are oxidized by the same oxidation step to form the side wall protective film 5 and the top insulating film 4. Then, the process of forming the gate electrode 6 and the high concentration impurity layer 7 is a figure explaining.

  First, the manufacturing process from FIG. 4A to FIG. 4C is the same as that of the first embodiment described with reference to FIG. 2A to FIG. To do.

A nitrogen ion implantation process will be described (FIG. 4C).
In this step, nitrogen ions are implanted into the semiconductor substrate 1 to suppress oxidation during the formation of the sidewall protective film 5 so that the thickness of the top insulating film 2 is increased.
By the process so far, the surface of the semiconductor substrate 1 in the oxidized area 22 is exposed. Nitrogen ion implantation is performed on the semiconductor substrate 1.

  At this time, since the surface of the charge storage layer 3 is exposed because there is no side wall protective film at the side end portion thereof, it is necessary to protect the surface with a mask material (not shown). The second sacrificial film 10 is composed of a silicon nitride film having a thickness of about 1500 mm, and nitrogen ions do not reach the lower semiconductor substrate 1, so that the second sacrificial film 10 may be exposed as it is. The implanted nitrogen ions are illustrated as a nitrogen ion implantation region 33.

Next, a side wall protective film forming step will be described (FIG. 4D).
Similar to the first embodiment, the top insulating film 4 and the sidewall protective film 5 are formed by the same process. At this time, the deposition rate of the sidewall protective film 5 decreases in inverse proportion to the amount of nitrogen ions implanted.
However, strictly speaking, not only the implantation amount of nitrogen ions but also the implantation energy, the depth of implantation, and the like are conditions, and therefore, the correlation with the oxidation rate cannot be quantified simply by the implantation amount alone.
Therefore, the relationship between the nitrogen ion implantation conditions and the oxidation rate and the relationship between these and the desired thickness of the top insulating film 4 should be determined in advance through experiments to set the conditions for nitrogen ion implantation. That's fine.

  In the subsequent steps, after the sidewall protective film 5 and the top insulating film 4 are formed, the second sacrificial film 10 is removed, and the high concentration impurity layer 7 and the gate electrode 6 are formed. Since it is described in the form, the description is omitted.

  Although not shown in FIG. 3, when the nonvolatile semiconductor memory device is completed, the nitrogen ion implantation region 33 remains in the semiconductor substrate 1 below the sidewall protective film 5. However, if the amount of nitrogen ions is adjusted so as to be consumed by oxidative growth of the sidewall protective film 5 in advance, there is no problem because the nitrogen ions remain. Even if a slight amount of nitrogen ions remain and react with the silicon below the sidewall protective film 5 to form a silicon nitride film, the silicon nitride film is not an insulating film (having low insulating properties). Even if the nitrogen ion implantation region 33 remains, there is no problem in terms of electrical characteristics.

[Explanation of Third Embodiment: FIGS. 5 and 6]
Next, a third embodiment of a method for manufacturing a nonvolatile semiconductor memory device will be described with reference to FIGS.
FIG. 5 is a sectional view schematically showing the structure of the nonvolatile semiconductor memory device, and FIG. 6 is a sectional view schematically showing the manufacturing method in order. In addition, these figures are schematic diagrams showing only the parts necessary for explaining the invention, like the figures already explained.

First, the structure will be described with reference to FIG.
In this structure, the lightly doped region 12 is provided in the nonvolatile semiconductor memory device manufactured in the first embodiment described with reference to FIG. In the following description, only differences from the first embodiment will be described.

A region of the semiconductor substrate 1 below the memory gate insulating film 11 is a channel region, and a lightly doped region 12 is provided between the channel region and the high concentration impurity layer 7. In the example shown in FIG. 5, it is provided inside the semiconductor substrate 1 that overlaps the side wall protective film 5 in a plan view. Of course, this is only an example, and the lightly doped region extends from the side wall protective film 5 toward the field oxide film (not shown). 12 may be manufactured in a shifted shape.
The lightly doped region 12 is a region having the same conductivity type as that of the high concentration impurity layer 7 which is a source region and a drain region, but having a low impurity concentration.

  By providing the light doped region 12, a higher write voltage can be applied to the gate electrode 6 of the nonvolatile semiconductor memory device. When a write voltage is applied, a current flows from the source region to the drain region. However, if the write voltage is high, charges obtained with high energy in the channel region near the drain region become hot carriers and are injected into the charge storage layer 3. It becomes easy to do. That is, more stable writing can be performed when hot carrier injection is performed.

In the writing of the nonvolatile semiconductor memory device, there is a case where the charge is not injected into the charge storage layer 3 in a single way, the case where the hot carrier injection is performed as described above, and the case where the tunnel current is supplied to the tunnel insulating film 2 for writing. is there. In any case, since it is related to the usage method of the nonvolatile semiconductor memory device and the specifications on the system, it is convenient to obtain a nonvolatile semiconductor memory device having a higher breakdown voltage because it can cope with a plurality of cases.
Thus, by providing the light doped region 12, more stable writing and the effect of increasing the breakdown voltage of the nonvolatile semiconductor memory device can be obtained.

Next, the manufacturing method will be described with reference to FIG.
In FIG. 6, 12 is a lightly doped region. FIGS. 6A to 6D are views seen from the same direction as the cross-sectional view shown in FIG.

FIG. 6A is a diagram illustrating an insulating film forming process for forming the tunnel insulating film 2 and the charge storage layer 3 after the element isolation process.
FIG. 6B is a view for explaining a first sacrificial film forming step for forming the first sacrificial film 9 and a second sacrificial film forming step for forming the second sacrificial film 10.
FIG. 6C shows a second sacrificial film removal step in which the second sacrificial film 10 is etched only in a portion overlapping the first sacrificial film 9 in a planar manner to expose the upper surface of the first sacrificial film 9. Then, a diagram for explaining a first sacrificial film removing step for selectively removing the first sacrificial film 9 and a light doped region forming step for forming the light doped region 12 on the exposed surface of the semiconductor substrate 1. It is.
6D shows a side wall protective film forming step in which the exposed surface of the semiconductor substrate 1 and the surface of the charge storage layer 3 are oxidized by the same oxidation process to form the side wall protective film 5 and the top insulating film 4. Then, the process of forming the gate electrode 6 and the high concentration impurity layer 7 is a figure explaining.

  First, the manufacturing process from FIG. 6A to FIG. 6C is the same as that of the first embodiment described with reference to FIG. 2A to FIG. To do.

The light dope region forming step will be described (FIG. 6C).
In this step, an impurity having the same conductivity type as that of the impurity forming the high-concentration impurity layer 7 formed in a later step is ion-implanted into the semiconductor substrate 1 with a small impurity amount. A characteristic point is that there is a step of forming the lightly doped region 12.

  At this time, since the surface of the charge storage layer 3 is exposed because there is no side wall protective film at the side end portion thereof, it is necessary to protect the surface with a mask material (not shown). The second sacrificial film 10 is composed of a silicon nitride film having a thickness of about 1500 mm, and nitrogen ions do not reach the lower semiconductor substrate 1, so that the second sacrificial film 10 may be exposed as it is. The implanted impurity ions are illustrated as lightly doped regions 12.

  Then, as in the other embodiments already described, the configuration shown in FIG. 4D is obtained through a series of steps including a side wall protective film forming step, but the description thereof is omitted.

  As described above, the manufacturing method of the nonvolatile semiconductor memory device of the present invention described with reference to the first, second, and third embodiments is characterized in that the top insulating film, the sidewall protective film, and the like are obtained by using two sacrificial films. It is the point that the area which forms can be created at the same time. As a result, side etching of the memory gate insulating film is prevented, the insulating property is maintained between the gate electrode and the charge storage layer, and there is no problem in operation, that is, a highly reliable nonvolatile semiconductor memory device is manufactured. Can do.

  The method for manufacturing a nonvolatile semiconductor memory device according to the present invention is suitable as a method for manufacturing a nonvolatile semiconductor memory device used for a highly reliable system, because the electrical characteristics such as erasure failure do not deteriorate.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Tunnel insulating film 3 Charge storage layer 4 Top insulating film 5 Side wall protective film 6 Gate electrode 7 High concentration impurity layer 8 Field insulating film 9 First sacrificial film 10 Second sacrificial film 11 Nitrogen implantation region 12 Light dope Region 22 Oxidation area 33 Nitrogen ion implantation region

Claims (4)

A memory gate insulating film in which a semiconductor substrate includes a source region and a drain region, and a tunnel insulating film, a charge storage layer, and a top insulating film are stacked on the surface of the semiconductor substrate in a channel region sandwiched between these regions. A non-volatile semiconductor memory device having a MIS transistor structure including a gate electrode mainly composed of a metal on the memory gate insulating film,
An insulating film forming step of forming the tunnel insulating film and the charge storage layer on the surface of the semiconductor substrate in a region for forming the memory gate insulating film;
A first sacrificial film forming step of forming a first sacrificial film so as to cover an upper end surface and a side end surface of the tunnel insulating film and the charge storage layer;
A second sacrificial film forming step of forming a second sacrificial film on the semiconductor substrate so as to cover the first sacrificial film;
Etching the second sacrificial film so as to remove the surface of the second sacrificial film that overlaps the first sacrificial film in a planar manner to expose the upper end surface of the first sacrificial film; A sacrificial film removal step;
A first sacrificial film removing step of removing the first sacrificial film and exposing an upper end surface and a side end surface of the tunnel insulating film and the charge storage layer;
A side wall protective film forming step of oxidizing the semiconductor substrate and simultaneously forming a top insulating film on the charge storage layer and a side wall protective film covering a side edge of the tunnel insulating film and the charge storage layer;
A method of manufacturing a nonvolatile semiconductor memory device, comprising:   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the insulating film forming step, the tunnel insulating film is formed by oxidizing the semiconductor substrate. Between the first sacrificial film removing step and the sidewall protective film forming step,
3. A nitrogen ion implantation step of ion-implanting nitrogen into the semiconductor substrate in a region between the tunnel insulating film and the side end face of the charge storage layer and the second sacrificial film. A method for manufacturing a nonvolatile semiconductor memory device according to claim 1.   After the sidewall protective film forming step, a light doped region forming step of forming a light doped region having the same conductivity type as the source region and the drain region and having a low impurity concentration on the semiconductor substrate planarly overlapping the sidewall protective film The method for manufacturing a nonvolatile semiconductor device according to claim 1, wherein:

Images