JP2012207993A - Test pattern generation system, test pattern generation method, and test pattern generation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for shortening generation time of a test pattern in ATPG.SOLUTION: A test pattern generation system equipped with: EDA tools (11-16); and a file storage part (9) which holds information to which the EDA tools (11-16) refer is constituted. The file storage part (9) includes: a net list (21) showing connection information of a circuit to be an object of generation of a test pattern; and a start/end point list (22) showing a terminal to be the start point of a failure detection object area among circuit to be shown on the net list. A logic cone extraction part (11) specifies logic cones (34)(35) using the start point to be shown on the start/end point list (22) as a peak. In addition, a failure list generation part (12) excludes nodes which do not match to the logic cones from all the nodes included in combination circuits (32)(33) to generate a failure list (24).

Description

  The present invention relates to a test pattern generation system, a test pattern generation method, and a test pattern generation program, and more particularly to a test pattern generation system, a test pattern generation method, and a test pattern generation program used for inspection of a semiconductor integrated circuit.

  A technique for inspecting a semiconductor integrated circuit using a test pattern is known (see, for example, Patent Document 1). Patent Document 1 describes a technique related to a test pattern generation method and apparatus for shortening the test pattern generation time. In the technique described in Patent Document 1, a circuit block that affects the value of the output terminal of a circuit is defined as a cone. A partial circuit as a pattern generation unit is created by extracting and collecting cones from the entire circuit in ascending order of the number of gates. Also, if the overlap between the extracted cone and the partial circuit during pattern generation exceeds the threshold, the cone is postponed, and if the corresponding cone does not remain, the threshold is increased. When a partial circuit is created, an undetected fault list included therein is created and removed from the undetected fault list of the entire circuit, and the partial circuit information and the fault list are passed to an empty CPU to generate a pattern. When the result is returned, a hypothetical fault that has not been generated (hereinafter referred to as a fault) is returned to the undetected fault list of the entire circuit. The above processing is repeated until the failure detection rate reaches the target value or the pattern of all cones is generated.

  As a technique for generating a test pattern used for testing a semiconductor integrated circuit, an ATPG (Automatic Test Pattern Generation) technique is widely used. Currently known tools using ATPG technology (ATPG tools) mainly generate test patterns for combinational circuits surrounded by scan flip-flops. With the ATPG tool, it is difficult to generate a test pattern for appropriately detecting a failure between a memory (RAM, ROM) of a semiconductor integrated circuit and a scan flip-flop. Therefore, for example, automatic test pattern generation and manual test pattern generation may be performed in parallel.

  In recent years, a test pattern generation technique using a sequential ATPG that can detect a failure of a sequential circuit element (flip-flop, latch, RAM, and ROM that is not a scan flip-flop) has been known as ATPG technology advances. By using the sequential ATPG technique, it is possible to automatically generate a test pattern of a circuit including a sequential circuit element in an area surrounded by scan flip-flops. However, when generating a test pattern for a circuit including a sequential circuit element, the complexity of test pattern generation increases dramatically, and a great deal of time is spent generating the test pattern.

  For example, when a failure of a circuit including a synchronous RAM is detected, an address value for writing data to the RAM and a data input value are supplied from a scan input terminal to a scan flip-flop by a scan shift operation. At this time, the value supplied to the scan flip-flop is determined in consideration of the logic (mainly the combinational circuit) between the scan flip-flop and the RAM. Thereafter, a clock is applied to the RAM by a capture operation to write data. Next, an address value for reading data in the RAM is supplied from the scan input terminal to the scan flip-flop by a scan shift operation. At this time, the value supplied to the scan flip-flop is determined in consideration of the logic between the scan flip-flop and the RAM as in the data write. Thereafter, a clock is applied to the RAM by a capture operation to read data. Next, data is taken into a scan flip-flop at the subsequent stage of the RAM, and an expected value with the scan output terminal is collated by a scan shift operation to determine whether or not a failure can be detected. The expected value to be collated is also determined in consideration of the logic of the RAM and the scan flip-flop.

  As described above, in the sequential ATPG of a circuit including a sequential circuit element, not only the combinational circuit but also the logic of the sequential circuit element is taken into consideration, and it is possible to determine a value to be supplied by a scan shift operation and to detect a failure. Judgment is necessary, and the complexity increases dramatically compared to ATPG that targets only combinational circuits surrounded by scan flip-flops. Furthermore, with the recent increase in the scale of semiconductor integrated circuits, the number of failure definitions subject to ATPG has become enormous, and the ATPG execution time has become even longer. A technique for shortening the ATPG execution time is known (see, for example, Patent Document 2).

  Patent Document 2 discloses a technique for reducing the execution time of ATPG. In the technique described in Patent Document 2, undetected faults are extracted by fault simulation, and a test pattern is generated only for undetected faults, thereby reducing ATPG execution time. FIG. 1 is a block diagram showing a configuration of a test pattern generation device described in Patent Document 2. As shown in FIG. The test pattern generation device described in Patent Document 2 stores a test pattern generation unit 101, a netlist storage unit 102 that stores a netlist, a memory unit 103 that stores generated data, and a function verification pattern. A function verification pattern storage unit 104 and a test pattern output unit 105 for outputting a test pattern.

  The test pattern generation unit 101 includes a failure simulation execution unit 101a that is a failure simulation execution function block and an ATGP execution unit 101b that is a test pattern generation function block. The failure simulation execution unit 101a reads the net list stored in the net list storage unit 102, generates a failure list in which all failures are picked up based on the read net list, and stores the generated failure list in the memory unit 103. Is stored in the failure list memory 103a. Further, the failure simulation execution unit 101 a detects a failure that cannot be detected by the function verification pattern, generates an undetected failure list, and an undetected failure list memory 103 b provided with the generated undetected failure list in the memory unit 103. Remember me.

  FIG. 2 is a flowchart showing the operation of the test pattern generation device described in Patent Document 2. As shown in FIG. 2, when the operation starts, the net list of the semiconductor integrated circuit that generates the test pattern is read from the net list storage unit (step S1). Next, all possible faults are picked up from the read netlist, a fault list is generated, and stored in the fault list memory 103a (step S2). And based on the function verification pattern memorize | stored in the function verification pattern memory | storage part, a failure simulation is performed by the failure simulation execution part (step S3).

  When the fault simulation is completed, faults that cannot be detected by the function verification pattern are extracted from the faults in the fault list (step S4). Then, an undetected failure list is generated based on the undetected failure and stored in the undetected failure list memory 103b (step S5). Next, a test pattern is automatically generated by executing ATPG by the ATPG execution unit for each failure listed in the undetected failure list (step S6). Then, the test pattern generated by ATPG is output to the storage device by the test pattern output unit (step S7).

  As described above, in the technique described in Patent Document 2, generation of a test pattern for a detected fault can be omitted by generating a test pattern for only an undetected fault. As a result, the ATPG execution time is shortened and the number of test patterns is reduced.

JP 2000-193725 A JP 2005-062017 A

In the technique described in Patent Document 2, in the generation of a fault list, all possible faults are picked up from the read net list to generate the fault list. Therefore, in a large-scale circuit, the number of failures included in the failure list becomes very large. When sequential ATPG is performed in a state where there are a large number of test pattern generation targets, the execution time of the sequential ATPG may become long.
The problem to be solved by the present invention is to provide a technique for shortening the test pattern generation time in ATPG.

  [Means for Solving the Problems] will be described below using the numbers used in [DETAILED DESCRIPTION]. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

A test pattern generation system including an EDA tool (11-16) and a file storage unit (9) that holds information referred to by the EDA tool (11-16) is configured. The file storage unit (9) includes a netlist (21) indicating connection information of a circuit for which a test pattern is to be generated, and a failure detection target area to be detected for failure among the circuits indicated in the netlist. A start / end list (22) indicating a terminal serving as a start point is provided.
Further, the EDA tool (11 to 16) is a logic cone extraction unit that extracts a portion of the combinational circuit (32) (33) sandwiched between failure detection target areas as a logic cone (34) (35). 11), a fault list generation unit (12) that extracts faults for nodes included in the logic cones (34) and (35) and generates a fault list (24), a fault list (24), and a net list (21) And an ATPG execution unit (13) that automatically generates a test pattern (31).
Here, the logic cone extraction unit (11) specifies the logic cones (34) and (35) whose apexes are the starting points shown in the start / end list (22). The failure list generation unit (12) generates a failure list (24) by excluding nodes that are not included in the logic cone from all nodes included in the combinational circuits (32) and (33).

  If the effect obtained by a representative one of the inventions disclosed in the present application is briefly described, there is an effect that the test pattern generation time in the ATPG can be shortened. In addition, as the scale of semiconductor integrated circuits increases, the number of failures for which test patterns are generated is increasing. By applying the present invention, the test pattern generation time can be shortened, and the occurrence of the problem that test pattern generation is not in time by the start of screening and inspection of large-scale semiconductor integrated circuit devices is suppressed. can do.

FIG. 1 is a block diagram showing a configuration of a test pattern generation device described in Patent Document 2. As shown in FIG. FIG. 2 is a flowchart showing the operation of the test pattern generation device described in Patent Document 2. FIG. 3 is a block diagram illustrating the configuration of the test pattern generation system 1 according to the first embodiment. FIG. 4 is a block diagram illustrating the configuration of the file storage unit 9 according to the first embodiment. FIG. 5 is a block diagram conceptually illustrating the configuration of the test pattern generation system 1 according to the first embodiment. FIG. 6 is a flowchart illustrating the operation of the test pattern generation system 1 according to the first embodiment. FIG. 7 is a description illustrating the configuration of the ATPG target netlist 21. FIG. 8 is a circuit diagram illustrating a part of the entire circuit that is a test pattern generation target. FIG. 9 is a circuit diagram illustrating a part of the entire circuit that is a test pattern generation target. FIG. 10 is a description illustrating the ATPG target start / end list 22. FIG. 11 is a description illustrating the configuration of the logic cone cell list 23. FIG. 12 is a circuit diagram illustrating the configuration of the logic cone specified by the logic cone extraction unit 11. FIG. 13 is a circuit diagram illustrating the configuration of the logic cone specified by the logic cone extraction unit 11. FIG. 14 is a description illustrating the configuration of the logic cone fault list 24. FIG. 15 is a description illustrating the configuration of the all fault list 25. FIG. 16 is a block diagram illustrating the configuration of the test pattern generation system 1 according to the second embodiment. FIG. 17 is a block diagram illustrating the configuration of the file storage unit 9 according to the second embodiment. FIG. 18 is a block diagram conceptually illustrating the configuration of the test pattern generation system 1 according to the second embodiment. FIG. 19 is a flowchart illustrating the operation of the test pattern generation system 1 according to the second embodiment. FIG. 20 is a description illustrating the configuration of the existing pattern detection failure list 26. FIG. 21 is a list illustrating the configuration of the undetected failure list 27.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. FIG. 3 is a block diagram illustrating the configuration of the test pattern generation system 1 of this embodiment. The test pattern generation system 1 according to the present embodiment includes a computer device body 2, an input device 3, and an output device 4.

  The computer apparatus body 2 performs information processing at high speed according to the procedure indicated by the computer program. The computer apparatus main body 2 of this embodiment provides a function as a test pattern generation apparatus. The computer apparatus body 2 has input, storage, calculation, control, and output functions. The input device 3 is a man-machine interface represented by a mouse or a keyboard. The input device 3 inputs data to the computer device body 2 in response to a user operation. The output device 4 is a man-machine interface typified by a liquid crystal display or a printer. The output device 4 outputs the processing result of the computer device body 2 in a format that can be recognized by the user. The computer device body 2 described above includes an arithmetic processing device 5 and an information storage device 6, which are connected via a bus 7.

  The arithmetic processing device 5 executes control and data processing of various devices provided in the computer device main body 2. The arithmetic processing unit 5 interprets and calculates the data received by the computer device body 2 via the input device 3 and outputs the calculation result by the output device 4 or the like. The information storage device 6 is a device for storing data represented by a RAM, a hard disk, and the like. The computer device body 2 may include a communication processing device for data communication with other devices via an external network.

  The information storage device 6 includes an EDA tool storage unit 8 and a file storage unit 9. The EDA tool storage unit 8 holds various tools (computer programs) necessary for EDA (Electronic Design Automation). The file storage unit 9 holds information and data used when the computer apparatus body 2 functions as the test pattern generation system 1 of the present embodiment. The file storage unit 9 holds information and data generated by the test pattern generation system 1.

  As shown in FIG. 3, the EDA tool storage unit 8 includes a logic cone extraction unit 11, a failure list generation unit 12, and an ATPG execution unit 13. The logic cone extraction unit 11 includes an input side logic cone analysis unit 14 and an output side logic cone analysis unit 15.

  The logic cone extraction unit 11 is a functional block that extracts a combinational circuit portion (hereinafter referred to as a logic cone) sandwiched between sequential circuits such as flip-flops. In the present embodiment, the circuit block extracted by the logic cone extraction unit 11 focuses on a shape similar to a cross section of a cone (a surface including a vertex and a bottom surface), and these circuit blocks are defined as cones or logic. Expressed as corn.

  The logic cone extraction unit 11 traces in the previous stage until reaching the input terminal (including the output pin of the sequential circuit element) with the output terminal as an end point among the circuit blocks including the input terminal, the output terminal, and the logic gate. Identify the circuit as a logic cone. Further, the logic cone extraction unit 11 specifies a circuit traced in the subsequent direction from the input terminal as a starting point until reaching an output terminal (including an input pin of a sequential circuit element) as a logic cone.

  The input side logic cone analysis unit 14 of the logic cone extraction unit 11 is a functional block that identifies a logic cone including an input terminal (input pin) of a sequential circuit. Since the logic cone specified by the input side logic cone analyzing unit 14 is traced from the output terminal of the circuit block to the input terminal side, it is expressed as an input side logic cone. The output-side logic cone analysis unit 15 of the logic cone extraction unit 11 is a functional block that identifies a logic cone including an output terminal (output pin) of a sequential circuit.

  The failure list generation unit 12 is a functional block that extracts a failure for a node such as a cell included in the logic cone extracted by the logic cone extraction unit 11. The ATPG execution unit 13 is a functional block that generates a test pattern.

  FIG. 4 is a block diagram illustrating the configuration of the file storage unit 9. The file storage unit 9 according to the first embodiment includes an ATPG target net list 21, an ATPG target start / end list 22, a logic cone cell list 23, a logic cone failure list 24, and an all failure list 25.

  The ATPG target netlist 21 indicates circuit connection information related to the entire semiconductor integrated circuit that is a target of test pattern generation by ATPG. The ATPG target start / end list 22 shows information on the start point and end point of a circuit that is to be a test pattern generation target. In the ATPG target start / end list 22, for example, when it is desired to generate a test pattern for detecting a failure of a circuit that is not easy to detect a failure such as a sequential circuit, the start point and the end point of the sequential circuit are designated.

  The logic cone cell list 23 shows information of cells existing on the logic cone. The logic cone failure list 24 indicates failures for the cells existing on the logic cones shown in the logic cone cell list 23. The all fault list 25 shows all faults that can be assumed for the net list (ATPG target net list 21).

  FIG. 5 is a block diagram conceptually illustrating the configuration of the test pattern generation system 1 according to the first embodiment. As shown in FIG. 5, the logic cone extraction unit 11 receives an ATPG target net list 21 and an ATPG target start / end list 22 as inputs. The logic cone extraction unit 11 generates a logic cone cell list 23 based on information shown in the ATPG target net list 21 and the ATPG target start / end list 22. The failure list generator 12 receives the logic cone cell list 23 and the ATPG target netlist 21 generated by the logic cone extractor 11 as inputs. The failure list generation unit 12 generates a logic cone failure list 24 based on information indicated in the logic cone cell list 23 and the ATPG target netlist 21. The ATPG execution unit 13 receives the ATPG target net list 21 and the logic cone failure list 24 as inputs. The ATPG execution unit 13 generates a test pattern file 31 based on information supported by the ATPG target net list 21 and the logic cone failure list 24.

  FIG. 6 is a flowchart illustrating the operation of the test pattern generation system 1 according to the first embodiment. In step S <b> 101, the logic cone extraction unit 11 of the test pattern generation system 1 reads the ATPG target netlist 21 and identifies circuit connection information regarding the entire circuit to be subjected to ATPG.

  FIG. 7 is a description illustrating the configuration of the ATPG target netlist 21. The ATPG target netlist 21 illustrated in FIG. 7 is expressed in conformity with the Verilog description. The description illustrated in FIG. 7 does not mean that the ATPG target netlist 21 of the present embodiment is limited to the Verilog description. In addition, the description of FIG. 7 illustrates only a part of the entire circuit that is the test pattern generation target as the ATPG target netlist 21.

  FIG. 7 shows that this module has input terminals TI31 to TI34, input terminals TI41 to TI45, output terminals TO31 to TO34, and output terminals TO41 to TO43. FIG. 7 also shows that this module has a circuit with instance names g301 to g305 and a circuit with instance names g401 to g404.

  FIGS. 8 and 9 are circuit diagrams illustrating only a part of the entire circuit that is the test pattern generation target. FIG. 8 illustrates the configuration of the ATPG target circuit 32 shown in the ATPG target netlist 21. FIG. 9 exemplifies the configuration of the ATPG target circuit 33 shown in the ATPG target netlist 21. In the circuit diagrams of FIGS. 8 and 9, reference numerals are assigned to the respective nodes that are the targets of failure detection. In the present embodiment, in order to facilitate understanding of the present invention, the instance name described in the ATPG target netlist 21 is used as the reference symbol.

  Referring to FIG. 8, the ATPG target circuit 32 includes a first input terminal TI31 to a fourth input terminal TI34, a first logic gate g301 to a fifth logic gate g305, and a first output terminal TO31 to a second output terminal TO32. I have. The first logic gate g301, the second logic gate g302, and the fifth logic gate g305 provide a function as an AND circuit. The third logic gate g303 provides a function as an OR circuit. The fourth logic gate g304 provides a function as an inverter.

  Referring to FIG. 9, the ATPG target circuit 33 includes a fifth input terminal TI41 to a ninth input terminal TI45, a third output terminal TO41 to a fifth output terminal TO43, and a sixth logic gate g401 to a ninth logic gate g404. I have. The sixth logic gate g401, the eighth logic gate g403, and the ninth logic gate g404 provide a function as an AND circuit. The seventh logic gate g402 provides a function as an OR circuit.

  Returning to FIG. 6, in step S <b> 102, the ATPG target start / end list 22 in which information on the start point and end point of the circuit to be generated as a test pattern is written is read. Circuits other than the scan flip-flop and the combinational circuit are exemplified as a circuit that is to be a test pattern generation target. For example, a circuit having a function of storing information, such as a sequential circuit. Further, it may be a RAM, a ROM, a latch, or a flip-flop not included in the scan chain. The ATPG target start / end list 22 of this embodiment defines at least one of an input pin and an output pin in such a region.

  FIG. 10 is a description illustrating only a part of the ATPG target start / end list 22 extracted. The character “#” at the beginning of the first line indicates that the line is a comment line. In a column corresponding to “type” in the first row, a character string for defining a start point or an end point is described. In a column corresponding to “pin_name” in the first row, a terminal name or a cell pin name is described. Referring to FIG. 10, the second line describes “SP”, which is a character string for defining the start point. “TI44” is defined as the start point by the “SP”. In the third line, “EP”, which is a character string for defining the end point, is described. The “EP” defines “TO32” as the end point.

  Returning to FIG. 6, in step S103, cells existing on the logic cone are extracted based on the circuit connection information of the ATPG target netlist 21 and the start / end point information described in the ATPG target start / end list 22. The extracted cell information is output as a logic cone cell list 23 to the subsequent stage. FIG. 11 is a description illustrating the configuration of the logic cone cell list 23. The character “#” at the beginning of the first line indicates that the line is a comment line. In a column corresponding to “type” in the first row, a character string for defining a terminal (pin) or a cell is described. In the column corresponding to “name” in the first row, an instance name corresponding to a terminal (pin) or a cell is described.

  FIGS. 12 and 13 are circuit diagrams illustrating the configuration of the logic cone specified by the logic cone extraction unit 11. FIG. 12 is a circuit diagram illustrating the input side logic cone 34 shown in the logic cone cell list 23. One input-side logic cone 34 is created for each output terminal, and when the logic gate is sequentially traced from a certain output terminal toward the input terminal, it passes through until reaching the input terminal. It is defined as the set of all logic gates, all input terminals reached, and the output terminal that is the starting point. In other words, a cone is formed by a collection of all the logic gates and input terminals that can propagate a logic value to a certain output terminal and the output terminal.

  In step S <b> 103, the input side logic cone analyzing unit 14 follows the circuit starting from the second output terminal TO <b> 32 described as the end point information of the ATPG target start / end list 22. A third logic gate g303 is connected to the second output terminal TO32. The input side logic cone analyzing unit 14 includes the third logic gate g303 in the cone. The second logic gate g302 is connected to one input pin of the third logic gate g303. The input side logic cone analyzing unit 14 includes the second logic gate g302 in the cone. The second input terminal TI32 and the first logic gate g301 are connected to one input pin of the second logic gate g302. The fourth logic gate g304 is connected to the other input pin of the second logic gate g302. The input side logic cone analyzing unit 14 includes the second input terminal TI32 and the fourth logic gate g304 in the cone.

  As shown in FIG. 12, the first logic gate g301 is not arranged in the direction of the input terminal. The input side logic cone analyzing unit 14 does not include the first logic gate g301 and the first output terminal TO31 in the cone. A cone is formed in such a procedure. The cone (input-side logic cone 34) includes a second output terminal TO32, a second logic gate g302 to a fifth logic gate g305, and a second input terminal TI32 to a fourth input terminal TI34. For the first output terminal TO31 that is not described as the end point information in the ATPG target start / end list 22, the input side logic cone analyzing unit 14 does not perform the input side logic cone extraction.

  FIG. 13 is a circuit diagram illustrating the output side logic cone 35 shown in the logic cone cell list 23. Based on the start point information in the ATPG target start / end list 22, the output side logic cone analysis unit 15 proceeds in the subsequent stage until reaching the output terminal (including the output pin of the sequential circuit element) from one start point described in the list. Trace and extract the logic cone on the output side. One output-side logic cone 35 is created for each input terminal, and when the logic gate is sequentially traced from a certain input terminal toward the output terminal, it passes until it reaches the output terminal. It is defined as the set of all logic gates, all output terminals reached, and the input terminal that is the starting point. In other words, one cone is formed by a set of all the logic gates and output terminals capable of propagating logic values in the output direction from one input terminal and the input terminal.

  The output side logic cone analyzing unit 15 traces the circuit starting from the eighth input terminal TI44 described as the starting point information of the ATPG target start / end list 22. An eighth logic gate g403 is connected to the eighth input terminal TI44. The output side logic cone analyzing unit 15 includes the eighth logic gate g403 in the cone. The seventh logic gate g402 and the ninth logic gate g404 are connected to the output pin of the eighth logic gate g403. The output side logic cone analyzing unit 15 includes the seventh logic gate g402 and the ninth logic gate g404 in the cone. Further, the fourth output terminal TO42 is connected to the output pin of the seventh logic gate g402. The output side logic cone analyzing unit 15 includes the fourth output terminal TO42 in the cone. A cone is formed in such a procedure.

  As shown in FIG. 13, the cone (output side logic cone 35) includes an eighth input terminal TI44, a seventh logic gate g402 to a ninth logic gate g404, a fourth output terminal TO42 to a fifth output terminal TO43. It is included. For the fifth input terminal TI41 to the seventh input terminal TI43 and the eighth input terminal TI44 that are not described as start point information in the ATPG target start / end list 22, the output side logic cone analyzing unit 15 performs the output side logic cone extraction. Not performed.

  Returning to FIG. 6, in step S104, based on the circuit connection information of the ATPG target netlist 21 and the cell information described in the logic cone cell list 23, a failure for the cell is extracted. Then, a logic cone fault list 24 is generated based on the extracted faults.

  FIG. 14 is a description illustrating the configuration of the logic cone fault list 24. The character “#” at the beginning of the first line indicates that the line is a comment line. In the column corresponding to “type” in the first row, “0”, “1”, or “01” is described. When “0” is written in the “type” column, it indicates that the failure is stack_at_0 or slow_to_rise. When “1” is described in the “type” column, it indicates that the failure is stack_at_1 or slow_to_fall. When “01” is written in the “type” column, it indicates that the failure is “both” (both type 0 and type 1).

  In the column corresponding to “class” in the first row, the state for the failure is described. When “DT” is described in the “class” column, the corresponding failure is processed as Detected (detected failure). When “ND” is described in the “class” column, the corresponding failure is processed as NotDetected (undetected failure). When “AU” is described in the “class” column, the corresponding failure is processed as an ATPG Untestable (undetectable failure). In the column corresponding to “pin_name” in the first row, the corresponding terminal name or cell pin name is described.

  Returning to FIG. 6, in step S <b> 105, a test pattern is generated for the circuit connection information of the ATPG target netlist 21 and the logic cone failure list described in the logic cone cell list 23. Thereafter, in step S106, the generated test pattern data is output to the test pattern file 31.

  As described above, the test pattern generation system 1 of the present embodiment narrows down the fault definition to the output-side circuit logic cone and the input-side circuit logic cone. Therefore, it is possible to specify the sequential circuit portion in a state in which the failure of the extra combinational circuit is removed, and the sequential ATPG can be executed only in that portion. Thereby, the execution time of ATPG can be shortened.

[Comparative example]
Below, the comparative example of this invention is demonstrated. FIG. 15 is a description exemplifying a configuration of the entire failure list 25 when all possible failures are picked up from the ATPG target netlist 21 and a failure list is generated. In the column corresponding to “type” in the first row, “0”, “1”, or “01” is described. When “0” is written in the “type” column, it indicates that the failure is stack_at_0 or slow_to_rise. When “1” is described in the “type” column, it indicates that the failure is stack_at_1 or slow_to_fall. When “01” is written in the “type” column, it indicates that the failure is “both” (both type 0 and type 1).

  In the column corresponding to “class” in the first row, the state for the failure is described. When “DT” is described in the “class” column, the corresponding failure is processed as Detected (detected failure). When “ND” is described in the “class” column, the corresponding failure is processed as NotDetected (undetected failure). When “AU” is described in the “class” column, the corresponding failure is processed as an ATPG Untestable (undetectable failure). In the column corresponding to “pin_name” in the first row, the corresponding terminal name or cell pin name is described.

  As shown in FIG. 15, the total number of faults shown in the total fault list 25 is 80. Here, referring to FIG. 14, the number of failures shown in the logic cone cell list 23 is 54. The test pattern generation system 1 of the present embodiment generates a test pattern for the circuit connection information of the ATPG target netlist 21 and the logic cone failure list described in the logic cone cell list 23. The logic cone cell list 23 is a list in a state in which unnecessary faults of the combinational circuit are removed, and the fault definition is narrowed down to the output side logic cone and the logic cone of the input side circuit. Therefore, the execution time of ATPG can be shortened.

  As described above, the test pattern generation system 1 includes the start point (sequential circuit element output pin) and the end point (sequential circuit element input pin) of a circuit to be subjected to test pattern generation, such as a circuit including a sequential circuit element. Is specified, and the logic cone starting from the start point and end point is extracted. Then, a fault list in which faults are defined only for the logic cone is generated. By using the failure list, the sequential ATPG can be executed only on the sequential circuit element portion with the failure of the combinational circuit removed.

  In addition, a test pattern that requires a plurality of scan shift operations in order to detect one failure may be generated. By configuring the test pattern generation system 1 as in the present embodiment, an increase in test time due to such a test pattern can be minimized.

  In general, in order to detect a failure of a sequential circuit element, it is necessary to apply an arbitrary value to the circuit element a plurality of times. It is difficult to apply the arbitrary value by a combination of one scan shift operation and one or more scan capture operations. Therefore, in the sequential ATPG that detects a failure of a circuit including a sequential circuit element, a test pattern for applying an arbitrary value to the sequential circuit element is generated by a plurality of scan shift operations and scan capture operations. .

  Since the scan pattern test time is proportional to the number of shift operations, if a test pattern that requires multiple scan shift operations is generated for a combinational circuit failure that can be detected by a single scan shift operation, The test time is increased by the number of scan shift operations in the pattern for detecting a circuit failure. The test pattern generation system 1 according to the present embodiment can execute sequential ATPG only in the sequential circuit element portion in a state in which an excessive combinational circuit failure is removed. Therefore, the test time of the semiconductor integrated circuit by the tester can be shortened.

[Second Embodiment]
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 16 is a block diagram illustrating the configuration of the test pattern generation system 1 according to the second embodiment. In addition to the configuration of the test pattern generation system 1 of the first embodiment, the test pattern generation system 1 of the second embodiment further includes an undetected fault list generation unit 16. The undetected fault list generation unit 16 refers to the existing pattern detected fault list 26 (the configuration of the existing pattern detected fault list 26 will be described later), and generates an undetected fault of the logic cone based on the logic cone fault list 24. A narrowed list (hereinafter referred to as an undetected fault list 27) is generated.

  FIG. 17 is a block diagram illustrating the configuration of the file storage unit 9 according to the second embodiment. In addition to the configuration of the file storage unit 9 of the first embodiment, the file storage unit 9 of the second embodiment further includes an existing pattern detection failure list 26 and an undetected failure list 27. The existing pattern detection failure list 26 is a function verification pattern created in advance by hand, a test pattern generated in advance by ATPG, or the like. The existing pattern detection fault list 26 shows faults that have been detected by simulation or previously executed ATPG. In the undetected fault list 27, the faults shown in the logic cone fault list 24 and the faults shown in the existing pattern detected fault list 26 are compared, and faults that do not match are extracted and held. In other words, the undetected fault list 27 may be configured to exclude the fault indicated in the existing pattern detected fault list 26 from the logic cone fault list 24.

  FIG. 18 is a block diagram conceptually illustrating the configuration of the test pattern generation system 1 according to the second embodiment. In the test pattern generation system 1 of the second embodiment, the logic cone extraction unit 11 receives the ATPG target netlist 21 and the ATPG target start / end list 22 as inputs, as in the logic cone extraction unit 11 of the first embodiment. . The logic cone extraction unit 11 generates a logic cone cell list 23 based on information shown in the ATPG target net list 21 and the ATPG target start / end list 22. The failure list generation unit 12 receives the logic cone failure list 24 and the ATPG target netlist 21 generated by the logic cone extraction unit 11 as inputs. The failure list generation unit 12 generates a logic cone failure list 24 based on information indicated in the logic cone cell list 23 and the ATPG target netlist 21.

  In the test pattern generation system 1 of the second embodiment, the undetected fault list generation unit 16 receives the existing pattern detected fault list 26 and the logic cone fault list 24 as inputs. The undetected failure list generation unit 16 generates an undetected failure list 27 based on the existing pattern detection failure list 26 and the logic cone failure list 24 and supplies it to the ATPG execution unit 13. The ATPG execution unit 13 receives the undetected failure list 27 and the ATPG target netlist 21 as inputs, and generates a test pattern file 31.

  FIG. 19 is a flowchart illustrating the operation of the test pattern generation system 1 according to the second embodiment. In the test pattern generation system 1 according to the second embodiment, steps S101 to S104 operate in the same manner as in the first embodiment.

  In step S <b> 201, the undetected fault list generation unit 16 reads the existing pattern detected fault list 26 and identifies a detected fault indicated in the existing pattern detected fault list 26. FIG. 20 is a description illustrating the configuration of the existing pattern detection failure list 26. The character “#” at the beginning of the first line indicates that the line is a comment line. In the column corresponding to “type” in the first row, “0”, “1”, or “01” is described. When “0” is written in the “type” column, it indicates that the failure is stack_at_0 or slow_to_rise. When “1” is described in the “type” column, it indicates that the failure is stack_at_1 or slow_to_fall. When “01” is written in the “type” column, it indicates that the failure is “both” (both type 0 and type 1).

  In the column corresponding to “class” in the first row, the state for the failure is described. When “DT” is described in the “class” column, the corresponding failure is processed as Detected (detected failure). When “ND” is described in the “class” column, the corresponding failure is processed as NotDetected (undetected failure). When “AU” is described in the “class” column, the corresponding failure is processed as an ATPG Untestable (undetectable failure). In the column corresponding to “pin_name” in the first row, the corresponding terminal name or cell pin name is described.

  Returning to FIG. 19, in step S <b> 202, the undetected fault list generation unit 16 extracts faults that exist in the logic cone fault list 24 and do not exist in the existing pattern detection fault list 26. In step S203, the undetected fault list generation unit 16 generates an undetected fault list 27 based on the extracted faults. FIG. 21 is a list illustrating the configuration of the undetected failure list 27. The character strings described in the column corresponding to “type”, the column corresponding to “class”, and the column corresponding to “pin_name” in the first row indicate the same semantic content as in the existing pattern detection failure list 26. Yes. Referring to FIG. 21, 45 faults are defined in the undetected fault list 27.

  Returning to FIG. 19, in step S204, test pattern data is generated for the circuit connection information of the ATPG target netlist 21 and the logic cone undetected fault list described in the undetected fault list 27. In step S205, the generated test pattern data is output to the test pattern file 31.

  As shown in FIG. 21, in the test pattern generation system 1 of the second embodiment, 45 faults are defined in the undetected fault list 27. The total number of failures shown in the all failure list 25 of FIG. 15 is 80. The total number of failures shown in the logic cone cell list 23 of FIG. 14 is 54. As described above, the test pattern generation system 1 according to the second embodiment can further reduce the ATPG execution time by using the fault list detected in the existing test pattern.

  As in the technique described in Patent Document 2, when a fault list is generated by extracting all possible faults from the read netlist, the faults included in the fault list become extremely large. End up. Assuming that 10 million faults exist in the fault list, even if a high detection rate of 99% is obtained by fault simulation, the number of faults that are subject to test pattern generation is 100,000. The 100,000 test pattern generation targets include sequential circuit elements and combinational circuits. As described above, when sequential ATPG is performed in a state where the number of test pattern generation target failures including sequential circuit elements and combinational circuits is large, sequential ATPG is performed including circuits composed only of combinational circuits.

  However, as described above, in the test pattern generation system according to the present embodiment, the start / end point list describing the start point or end point of the test pattern generation target circuit is used, and the output side circuit is based on the start / end point list. The failure of the logic cone and the failure of the logic cone of the input side circuit are extracted. Then, the sequential ATPG is executed only for the sequential circuit elements in a state in which the trouble of the extra combinational circuit is removed. In addition, the ATPG execution time can be shortened by narrowing down the logic cone failures in the output side circuit and the input side circuit using the fault definition list detected in the existing test pattern.

  The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Test pattern generation system 2 ... Computer apparatus main body 3 ... Input device 4 ... Output device 5 ... Arithmetic processor 6 ... Information storage device 7 ... Bus 8 ... EDA tool storage part 9 ... File storage part 11 ... Logic cone extraction part 12 ... failure list generation unit 13 ... ATPG execution unit 14 ... input side logic cone analysis unit 15 ... output side logic cone analysis unit 16 ... undetected failure list generation unit 21 ... ATPG target net list 22 ... ATPG target start / end list 23 ... logic Cone cell list 24 ... logic cone fault list 25 ... all fault list 26 ... existing pattern detected fault list 27 ... undetected fault list 31 ... test pattern file 32 ... ATPG target circuit 33 ... ATPG target circuit 34 ... input side logic cone 35 ... Output side logic cone TI31 ... first input terminal TI32 ... second input Terminal TI33 ... Third input terminal TI34 ... Fourth input terminal TI41 ... Fifth input terminal TI42 ... Sixth input terminal TI43 ... Seventh input terminal TI44 ... Eighth input terminal TI45 ... Ninth input terminal TO31 ... First output terminal TO32 2nd output terminal TO41 3rd output terminal TO42 4th output terminal TO43 5th output terminal g301 1st logic gate g302 2nd logic gate g303 3rd logic gate g304 4th logic gate g305 5th logic gate g401 ... 6th logic gate g402 ... 7th logic gate g403 ... 8th logic gate g404 ... 9th logic gate 101 ... Test pattern generation unit 101a ... Fault simulation execution unit 101b ... ATGP execution unit 102 ... Netlist storage unit 103 ... Memory unit 103a ... Fault list memory 103b ... Undetected fault list Use memory 104 ... function verification pattern storage unit 105 ... test pattern output unit

Claims (15)

EDA tool,
A file storage unit for holding information referred to by the EDA tool,
The file storage unit
A netlist indicating connection information of a circuit for which a test pattern is to be generated;
Among the circuits shown in the net list, comprising a start / end list indicating a terminal that is a starting point of a failure detection target area that is a target of failure detection,
The EDA tool is
A logic cone extraction unit for extracting a portion of the combinational circuit sandwiched between the failure detection target areas as a logic cone;
A fault list generation unit that generates a fault list by extracting faults for nodes included in the logic cone;
An ATPG execution unit that automatically generates the test pattern based on the failure list and the net list, and
The logic cone extraction unit
Specify a logic cone having the starting point shown in the start / end list as a vertex,
The failure list generator is
A test pattern generation system for generating the fault list by excluding nodes not included in the logic cone from all nodes included in the combinational circuit. The test pattern generation system according to claim 1,
The failure detection area is
Including a memory circuit having a function of storing information;
The start / end list is
A test pattern generation system including information on a terminal serving as a start point or an end point of the storage circuit. The test pattern generation system according to claim 2,
The memory circuit is
Including flip-flops not included in the scan chain,
The start / end list is
A test pattern generation system including information on a terminal which is a start point or an end point of the flip-flop. The test pattern generation system according to claim 3,
The logic cone extraction unit
An input side logic cone analyzing unit for extracting an input side logic cone having the end point as a vertex;
An output-side logic cone analyzing unit that extracts an output-side logic cone having the start point as a vertex; The test pattern generation system according to any one of claims 1 to 4,
The EDA tool further includes:
An undetected fault list generation unit that narrows down the undetected faults of the logic cone;
The file storage unit further includes:
It has an existing pattern detection fault list showing faults that have already been detected,
The undetected failure list generator is
Comparing the faults shown in the fault list with the faults shown in the existing pattern detection fault list, extracting faults that do not match, and generating the undetected fault list;
The ATPG execution unit
A test pattern generation system that automatically generates the test pattern based on the undetected fault list and the net list. A net list reading step of reading a net list indicating connection information of the semiconductor integrated circuit;
A start / end point list reading step for reading a start / end point list indicating a terminal that is a starting point of a failure detection target area that is a target of failure detection;
A logic cone extraction step for extracting a portion of the combinational circuit sandwiched between the failure detection target areas as a logic cone;
A fault list generating step of generating a fault list by extracting faults for nodes included in the logic cone;
An ATPG execution step of automatically generating the test pattern based on the failure list and the net list;
Comprising
The logic cone extraction step includes
Identifying a logic cone having the starting point shown in the start / end list as a vertex;
The failure list generation step includes:
A test pattern generation method including a step of generating the fault list by excluding nodes not included in the logic cone from all nodes included in the combinational circuit. The test pattern generation method according to claim 6,
The starting / ending point list reading step includes:
When the failure detection area includes a storage circuit having a function of storing information,
A test pattern generation method including a step of reading the start / end point list including information of a terminal that is a start point or an end point of the storage circuit. The test pattern generation method according to claim 7,
The starting / ending point list reading step includes:
When the storage circuit includes a flip-flop that is not included in the scan chain,
A test pattern generation method including a step of reading the start / end point list including information of a terminal which is a start point or an end point of the flip-flop. The test pattern generation method according to claim 8,
The logic cone extraction step includes
An input side logic cone analyzing step for extracting an input side logic cone having the end point as a vertex;
An output side logic cone analyzing step for extracting an output side logic cone having the start point as a vertex. The test pattern generation method according to any one of claims 6 to 9, further comprising:
An undetected fault list generation step of narrowing down the undetected faults of the logic cone,
The undetected fault list generation step includes:
Reading an existing pattern detection fault list indicating faults that have already been detected;
Comparing the faults shown in the fault list with the faults shown in the existing pattern detected fault list to extract faults that do not match and generating the undetected fault list,
The ATPG execution step includes
A test pattern generation method including a step of automatically generating the test pattern based on the undetected fault list and the net list. A test pattern generation program showing a procedure for causing a computer to function as a test pattern generation device, the test pattern generation program,
A net list reading step of reading a net list indicating connection information of the semiconductor integrated circuit;
A start / end point list reading step for reading a start / end point list indicating a terminal that is a starting point of a failure detection target area that is a target of failure detection;
A logic cone extraction step for extracting a portion of the combinational circuit sandwiched between the failure detection target areas as a logic cone;
A fault list generating step of generating a fault list by extracting faults for nodes included in the logic cone;
An ATPG execution step for automatically generating the test pattern based on the failure list and the net list is shown.
The logic cone extraction step includes
Identifying a logic cone having the starting point shown in the start / end list as a vertex;
The failure list generation step includes:
A test pattern generation program including a step of generating the fault list by excluding nodes not included in the logic cone from all nodes included in the combinational circuit. In the test pattern generation program according to claim 11,
The failure detection area is
Including a memory circuit having a function of storing information;
The start / end list is
A test pattern generation program including information on a terminal which is a start point or an end point of the storage circuit. The test pattern generation program according to claim 12,
The memory circuit is
Including flip-flops not included in the scan chain,
The start / end list is
A test pattern generation program including information on a terminal which is a start point or an end point of the flip-flop. In the test pattern generation program according to claim 13,
The logic cone extraction step includes
An input side logic cone analyzing step for extracting an input side logic cone having the end point as a vertex;
An output-side logic cone analyzing step for extracting an output-side logic cone having the start point as a vertex. The test pattern generation program according to any one of claims 11 to 14, further comprising:
Shows a procedure for performing an undetected fault list generation step of narrowing down the undetected faults of the logic cone;
The undetected fault list generation step includes:
Reading an existing pattern detection fault list indicating faults that have already been detected;
Comparing the faults shown in the fault list with the faults shown in the existing pattern detected fault list to extract faults that do not match and generating the undetected fault list,
The ATPG execution step includes
A test pattern generation program including a step of automatically generating the test pattern based on the undetected fault list and the net list.

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