JP2012205081A - Reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception circuit that demodulates an input signal while maintaining an optimum SNR by acquiring information on the amplitude of the signal via a simple circuit and reducing current consumption in accordance with the acquired information.SOLUTION: A digital section comprising a demodulator 170 demodulates an output of an analog section comprising a power detection section 180 for detecting a power of a received signal from an antenna 110, a switched current control section 190 as a control signal generation section for generating control signals in accordance with a detection output from the power detection section 180, a switched current section 150 for averaging a signal from a preceding antialiasing filter 140 in a mode depending on the control signals supplied from the switched current control section 190, and an AD converter 160 for AD-converting a signal from the switched current section 150.

Description

  The present invention relates to a receiving circuit for demodulating a modulated wave signal and reproducing an original signal.

FIG. 12 is a block diagram showing a conventional general receiving circuit for demodulating a modulated wave signal and reproducing an original signal (see Patent Document 1).
In FIG. 12, the RF signal (frequency f _RF ) received by the antenna 1210 is amplified by the low noise amplifier 1220 (output frequency f _LNA ), mixed with the local signal by the mixer 1230 at the next stage, and intermediate frequency signal (frequency f _IF ). Is converted to After this aliasing distortion is removed by the anti-alias filter 1240 (output frequency f _AAF ), this intermediate frequency signal is converted to a digital signal by an AD converter 1250 driven by a predetermined clock signal. This digital signal is demodulated by the demodulator 1260.
In the above configuration, the low noise amplifier 1220, the mixer 1230, the anti-alias filter 1240, and the AD converter 1250 that amplify the input signal from the antenna 1210 constitute an analog part, and the demodulator 1260 constitutes a digital part.

JP-A-5-292133

In the conventional receiving circuit described with reference to FIG. 12, a low-noise amplifier is the dominant factor of the signal to noise ratio (SNR). Thus, when improving a low noise amplifier which becomes a dominant factor of SNR, there exists a problem that power consumption and a circuit scale become large.
In particular, in order to ensure the SNR regardless of the amplitude of the input signal, the current consumption of the low-noise amplifier is increased in accordance with the case where the amplitude of the input signal is small. Even when there is a large signal power, the current consumption of the low-noise amplifier remains large, and there is a problem that the current consumption is wasted.
The present invention has been made in view of the situation as described above, and obtains information on the amplitude of an input signal by a simple circuit and optimizes the SNR while suppressing current consumption based on the obtained information. An object of the present invention is to realize a receiving circuit that can maintain and demodulate a signal.

In order to solve the above problems, the following technologies are proposed here.
(1) A receiving circuit for demodulating a modulated wave signal to reproduce an original signal,
A power detector for detecting the power of the received signal;
A control signal generation unit that generates a control signal based on a detection output by the power detection unit;
A switched current unit that averages a signal from an anti-alias filter placed in front of the filter in a manner according to a control signal supplied from the control signal generation unit;
An AD converter for AD converting the signal from the switched current unit;
A receiving circuit comprising:

(2) The switched current section is
A current converter for converting a signal from the anti-alias filter circuit into a current;
A plurality of N (N is a natural number) switched current circuits connected in parallel for sampling the current from the current conversion circuit and transferring the sampled signal to the next stage;
An adder for adding each output current from the plurality of switched current circuits;
The signal level including noise from the anti-alias filter is multiplied N times and the noise level is multiplied by √N times.

(3) The receiving circuit according to (2), wherein the switched current circuit is a self-biased switched current circuit.
(4) The switched current circuit is:
A transistor and a capacitor connected to the gate of the transistor,
In the sample period, input current is input to the capacitor.
In the holding period, the potential of the gate voltage of the transistor is held by the capacitor, and an output current is output from the drain of the transistor.

(5) The receiving circuit according to (1), wherein the power detector detects the power of the received signal from an antenna through a low noise amplifier.
(6) The reception according to (1), wherein the power detector detects the power of the reception signal from the antenna through a low-noise amplifier, a filter downstream of the low-noise amplifier, and a mixer downstream of the filter. circuit.
(7) The receiving circuit according to (1), further comprising a demodulator connected to a subsequent stage of the sample and hold circuit.

  Realizing a receiving circuit capable of acquiring amplitude information of an input signal with a simple circuit and demodulating a signal while suppressing current consumption based on the acquired information and maintaining the SNR in the best state it can.

It is a block diagram which shows the receiving circuit as one embodiment of this invention. It is a figure which shows one specific example of the power detector in the receiving circuit of FIG. It is a figure which shows the timing chart of the signal of each node in the power detector of FIG. FIG. 2 is a diagram illustrating a specific example of a switched current control unit in the receiving circuit of FIG. 1. FIG. 5 is a diagram illustrating a timing chart of signals at each node in the switched current control unit in FIG. 4. FIG. 2 is a diagram illustrating a specific example of a switched current unit in the receiving circuit of FIG. 1. It is a figure which shows the timing chart of the signal of each node in the switched current part of FIG. It is a figure which shows one specific example of the switched current circuit in the switched current part of FIG. FIG. 9 is a timing chart illustrating the operation of the switched current circuit of FIG. 8. It is a figure for demonstrating that the output current of the switched current circuit of FIG. 8 is insensitive to the offset of the transistor applied to this circuit. It is a block diagram which shows the receiving circuit as other embodiment of this invention. It is a block diagram showing the conventional common receiving circuit.

Hereinafter, the present invention will be clarified by describing embodiments of the present invention in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a receiving circuit as one embodiment of the present invention.
The receiving circuit 100 includes a low noise amplifier 120 that amplifies a signal received by the antenna 110, a mixer 130 at the next stage, an anti-alias filter 140 at the next stage, and a switched current unit 150 at the next stage, Furthermore, the AD converter 160 of the next stage and the demodulator 170 of the next stage are provided. Furthermore, a power detector 180 for detecting the received signal strength (received signal power) from the output of the low noise amplifier 120 and a switched current control unit 190 at the next stage are provided.

The antenna 110, the low noise amplifier 120, the mixer 130, the anti-alias filter 140, the switched current unit 150, the AD converter 160, the power detector 180, and the switched current control unit 190 constitute an analog unit, and a demodulator 170. Constitutes the digital part.
In this receiving circuit 100, the RF signal (frequency f _RF ) received by the antenna 110 is amplified by the low noise amplifier 120 (output frequency f _LNA ), the signal path passing through the mixer 130 and the anti-alias filter 140, and power detection After the power is detected by the detector 180, the power is detected via the switched current control unit 190 as a control signal generation unit that generates an SI control signal for controlling the switched current unit 150 based on the detection output of the power detector 180. Divided into paths.

As described above, the received signal received by the antenna 110 is amplified by the low noise amplifier 120. The amplified signal S _LNA is mixed with the local signal by the mixer 130 and converted to an intermediate frequency signal (frequency f _IF ). This intermediate frequency signal is subjected to band limitation by the anti-alias filter 140 and aliasing distortion is removed, and then converted to a digital signal by the AD converter 160 via the switched current unit 150. This digital signal is demodulated by the demodulator 170.
As described above, in the signal path, the received signal is subjected to the same signal processing as that of a general receiving circuit except that it passes through the switched current unit 150 and is output.

On the other hand, in the power detection path, after the received signal is amplified by the low noise amplifier 120, the power of the received signal is detected by the power detector 180 as described above. The detected signal is compared with the reference voltage in the switched-current control unit 190, as a comparison result, a control signal h ₀ ~h _N-1 in synchronism with the predetermined clock to output to the switched-current portion 150.
The switched current unit 150 is a circuit having an averaging function, and is a circuit intended to improve SNR. The switched current unit 150 performs serial addition after performing N parallel signal charges. By this processing, although the signal level is increased by N times, the noise level is limited to √N times, so that the SNR can be increased by √N times.

The switched current unit 150 is based on the control signals h _{0 to} h _N−1 from the switched current control unit 190 so that the output signal does not exceed the input range (dynamic range) of the AD converter 160. Thus, the SNR is improved by averaging the input signals that have passed through the signal path. For example, when the amplitude of the input signal is large, the number of times of averaging is reduced, while when the amplitude of the input signal is small, the number of times of averaging is increased to optimize the SNR.
That is, the switched current unit 150 averages the signal from the anti-alias filter 140 disposed in front thereof in a manner corresponding to the control signal supplied from the switched current control unit 190 as the control signal generation unit. To do.

FIG. 2 is a diagram showing a specific example of a power detector in the receiving circuit of FIG. FIG. 3 is a timing chart of signals at each node in the power detector of FIG.
The power detector 180 includes a squarer 181 having transistors MP and MN and a load resistor RL, an LPF unit 182 having a resistor R1 and a capacitor C1, and a buffer unit 183 having a transistor MSF and a current source IB.

The signal S _LNA (differential signals IP and IN) amplified by the low noise amplifier 120 is input to the gates of the transistors MP and MN. Since the drains of the transistors MP and MN are connected to each other and connected to the load resistor RL, the full-wave rectified signal N1 is obtained at the connection node n1 between the drain and the load resistor RL. The obtained full-wave rectified signal N1 is smoothed by the primary LPF by the resistor R1 and the capacitor C1. The smoothed signal is buffered by a source follower including a transistor MSF and a current source IB, and the buffered output signal OUT is output to the switched current control unit 190.
The power detector is not limited to the configuration shown in FIG. 2 and may be a full-wave rectifier circuit or a half-wave rectifier circuit using a diode as another example.

FIG. 4 is a diagram showing a specific example when N = 5 of the switched current control unit 190 in the receiving circuit of FIG. FIG. 5 is a diagram showing a timing chart of signals at each node in the switched current control unit 190 of FIG.
The switched current control unit 190 includes a resistance unit 41 including a plurality of resistance elements R, R,... Connected in series, and a plurality of comparators CMP1 to CMP4. One end of the resistor 41 is connected to the reference voltage FS, and the other end is grounded to VSS.

  The switched current control unit 190 is a circuit for preventing the output of the switched current unit 150 from overloading the AD converter 160 at the next stage. SI control signals h1 to h4, which are control signals for the switched current control unit 190, are generated so as to output signals as close to full scale as possible as well as not exceeding the full scale of the AD converter 160.

Comparators CMP1 to CMP4 are the output signal from the power detector and the voltage 4/5 × FS, 3/5 × FS, 2/5 × FS, 1/5 × FS obtained by dividing the reference voltage FS by the resistor 41. Are respectively input, and SI control signals h1 to h4 are output.
The comparators CMP1 to CMP4 compare the output signal from the power detector with the above-mentioned divided voltages at the edge of the clock signal clock, and binarize and output the result, so-called flash AD conversion Perform the operation.

FIG. 6 is a diagram illustrating a specific example of the switched current unit in the receiving circuit of FIG.
The switched current unit 150 is a circuit that increases the SNR of the signal by √N times by increasing the amplitude of the signal by N times as N signals are added. This signal processing can be realized by, for example, the VI converter 61, the switched current circuit unit 62 at the next stage, and the adder 63 at the next stage.

That is, the switched current unit 150 includes a V-I converter 61 that receives an input signal S _AAF and converts it into a current and outputs it, and a plurality of switches that sample / transfer the current from the V-I converter 61 using a clock. Switched current circuit unit 62 including current circuits SI (0) to SI (N-1) and a plurality of switched current circuits SI (0) to SI (N-1) of switched current circuit unit 62 And an adder 63 that adds the output currents I _{SI0 to} I _SIN-1 from the output.

FIG. 7 is a diagram showing a timing chart of signals at each node in the switched current section of FIG.
First, the input signal S _AAF is converted into a current signal by the VI converter 61, and is supplied to N switched current circuits SI (0) to SI (N-1) arranged in parallel in the switched current circuit section 62. Led.
The output currents I _{SI0 to} I _SIN-1 (each current value I _{S0 to} I _SN-1 ) from the switched current circuits SI (0) to SI (N ₋₁ ) are added by the adder 63, and the output current I _out Is output as

As shown in FIG. 7, assuming that the SI control signals h _{0 to} h _N-1 are all H, output currents are output from the switched current circuits SI (0) to SI (N−1), respectively. At this time, if I _S0 = I _S1 =... = I _S4 ≡I _sout , the total output signal I _out is I _S1 + I _S2 +... + I _S4 = N × I _sout . Therefore, the output is √N times the input.
When SI control signal h ₀ of the SI control signal h ₀ to h _N-1, only h ₁ is other is H is assumed to be L, the switched-current circuits SI (0), from two of the SI (1) Output current is output. At this time, if I _S0 = I _S1 ≡I _sout , the total output signal I _out is I _S0 + I _S1 +... + 0 = I _S0 + I _S1 = 2 × I _sout . Therefore, the output is √2 times the input.

FIG. 8 is a diagram showing a specific example of the switched current circuit in the switched current section of FIG.
FIG. 9 is a timing chart showing the operation of the switched current circuit of FIG.
The switched current circuits SI (0) to SI (N-1) are composed of switches SW1 and SW2, a capacitor C, and a transistor M1.
In phase 0 (sample period), the switch SW1 is closed by the clock Φ1, the switch SW2 selects the input side terminal by the clock Φ2, and the current I _in is guided to the capacitor C. In Phase 1 (hold period), the switch SW1 opens by the clock [Phi _1, the potential of the gate voltage of the transistor M1 holds in capacitor C, to select the switch SW2 is output terminal by a clock [Phi _2, transistor M1 The drain is connected to the output side and outputs _Iout .

Usually, the parallel number N is limited by each offset due to a transistor or the like constituting each switched current circuit.
However, since the switched current circuit of this embodiment is a self-bias type, it is insensitive to the offset of the transistor M1. Therefore, according to the switched current circuit of the present embodiment, the output currents I _{SI0 to} I _SIN-1 (the respective current values I _{S0 to} I _SN− ) from the switched current circuits SI (0) to SI (N−1). ₁ ) is a function of only the input current I _in and the parallel number N.

FIG. 10 is a diagram for explaining that the output currents I _{SI0 to} I _SIN-1 from the switched current circuits SI (0) to SI (N−1) are insensitive to the offset of the transistor M1.
First, the gate-source voltage of the transistor M1 is obtained. If the input current during sample operation is I _in ,
I _in = k´M1 {Vgs1- (Vth1 + ΔVoff1)} ²
Therefore, the gate-source voltage V _gs1 of the transistor M1 is
∴ V _gs1 = √ (Iin / k´M1) + (Vth1 + ΔVoff1)
It becomes.

Here, k′M1 is the voltage-current conversion coefficient of the transistor M1, V _gs1 is the gate-source voltage of the transistor M1, V _th1 is the threshold voltage of the transistor M1, and ΔVoff1 is the transistor M1 offset voltage. Because of the offset voltage, the actual threshold voltage of the transistor M1 is Vth1 + ΔVoff1.
On the other hand, if the output current during hold operation is _Iout ,
I _out = k′M1 {Vgs1- (Vth1 + delta Voff1)} ²
= K'M1 [(√ (Iin / k'M1) + (V _th1 + ΔV _off1 ))-(V _th1 + ΔV _off1 )] ²
= I _in
It can be expressed.

That is, the offset voltage of the transistor M1, it can be seen that not an error of the current mirror operation from I _in the I _out.
Thus, by using a self-biased switched current circuit, output currents I _{SI0 to} I _SIN-1 from the switched current circuits SI (0) to SI (N−1) (each current value is I _S0 Is equal to the input current value I _S0 and the function I _S0 × N having only the parallel number N, and the output is √N times the input. Therefore, theoretically, the effect of improving the SNR can be further increased according to the N number.

(Embodiment 2)
FIG. 11 is a block diagram showing a receiving circuit as another embodiment of the present invention.
The receiving circuit 100a includes a low-noise amplifier 120 that amplifies a signal received by the antenna 110, a next-stage filter 125, a next-stage mixer 130, a next-stage anti-alias filter 140, and a next-stage filter. A switched current unit 150, an AD converter 160 at the next stage, and a demodulator 170 at the next stage are provided. Furthermore, a power detector 180a for detecting the received signal strength from the output of the low noise amplifier 120 and a switched current control unit 190 at the next stage are provided.

The receiving circuit 100a detects the power of the received signal using the output of the mixer 130.
In this receiving circuit 100a, the signal received by the antenna 110 is amplified by the low noise amplifier 120 and band-limited by the filter 125, and then the signal path passing through the mixer 130 and the anti-alias filter 140, and the power detector 180a After detecting the output power, it is divided into a power detection path via a switched current control unit 190 for conversion to a switched current control signal.

As in the first embodiment, the received signal is subjected to the same signal processing as that of a general receiving circuit except for passing through the filter 125 and the switched current unit 150 in the signal path and output.
On the other hand, in the power detection path, the received signal is amplified by the low noise amplifier 120, passes through the filter 125 and the mixer 130, and then the power is detected by the power detector 180a. The detected signal is compared with the reference voltage by the switched current control unit 190 as in the first embodiment, and the SI control signals h _{0 to} h _N-1 are synchronized with the clock as a comparison result. Output to the switched current unit 150.

The switched current unit 150 uses the SI control signals h _{0 to} h _N-1 so that the output signal of the switched current unit 150 does not exceed the input range of the AD converter 160. Averaging is performed to improve the SNR. When the amplitude of the input signal is large, the number of times of averaging is reduced. On the other hand, when the amplitude of the input signal is small, the number of times of averaging is increased to optimize the SNR.

  In the embodiment of FIG. 11, power detection is performed on a relatively low frequency signal converted into an intermediate frequency signal by the mixer 130. Further, since the power of the signal itself carrying the original information from which the image frequency and unnecessary waves have been removed by the filter 125 is measured, the SNR accuracy can be further improved as compared with the embodiment of FIG.

41 ……………………………… Resistance part 61 ……………………………… V-I converter 62 ……………………………… Switched current circuit Unit 63 ……………………………… Adder 100, 100a ……………… Receiver circuit 110, 1210 ……………… Antenna 120, 1220 ……………… Low noise amplifier 125… ………………………… Filter 130 ……………………… Mixers 140, 1240 ……………… Anti-alias filter 150 …………………………… Switch D current section 160, 1260 ... AD converter 170 ... Demodulator 180, 180a ... Power detector 190 ... ……… Switched current controller

Claims (7)

A receiving circuit for demodulating a modulated wave signal to reproduce an original signal,
A power detector for detecting the power of the received signal;
A control signal generation unit that generates a control signal based on a detection output by the power detection unit;
A switched current unit that averages a signal from an anti-alias filter placed in front of the filter in a manner according to a control signal supplied from the control signal generation unit;
An AD converter for AD converting the signal from the switched current unit;
A receiving circuit comprising: The switched current section is
A current converter for converting a signal from the anti-alias filter circuit into a current;
A plurality of N (N is a natural number) switched current circuits connected in parallel for sampling the current from the current conversion circuit and transferring the sampled signal to the next stage;
An adder for adding each output current from the plurality of switched current circuits;
2. The receiving circuit according to claim 1, wherein the signal level including noise from the anti-alias filter is increased N times and the noise level is increased to √N times.   The receiving circuit according to claim 2, wherein the switched current circuit is a self-biased switched current circuit. The switched current circuit is:
A transistor and a capacitor connected to the gate of the transistor,
In the sample period, input current is input to the capacitor.
4. The receiving circuit according to claim 3, wherein in the hold period, the potential of the gate voltage of the transistor is held by the capacitor, and an output current is output from the drain of the transistor.   The receiving circuit according to claim 1, wherein the power detector detects the power of the received signal from an antenna through a low noise amplifier.   2. The receiving circuit according to claim 1, wherein the power detector detects power of the received signal that has passed from an antenna through a low-noise amplifier, a filter downstream of the low-noise amplifier, and a mixer downstream of the filter. .   The receiving circuit according to claim 1, further comprising a demodulator connected to a subsequent stage of the sample and hold circuit.

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