JP2012204425A - Semiconductor substrate, method of manufacturing the same, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate using carbon nanotubes and having excellent characteristics, a method of manufacturing the same, and an electronic device.SOLUTION: A semiconductor substrate comprises: a base that has a lower electrode in its first primary surface; an interlayer insulating film that is provided on a portion except for the lower electrode on the base; a catalyst layer that is provided on the lower electrode; a plurality of carbon nanotubes that are provided on the catalyst layer and extend in the direction perpendicular to a first primary surface of the lower electrode; an upper electrode that is provided on the carbon nanotubes and faces the lower electrode; a first buried film that covers the catalyst layer and ends of the carbon nanotubes at the catalyst layer side; and a second buried film that is filled between the other ends of the carbon nanotubes and has higher density than the first buried film.

Description

  Embodiments described herein relate generally to a semiconductor substrate having carbon nanotubes, a method for manufacturing the same, and an electronic device.

  With the miniaturization of LSIs, the wiring is naturally miniaturized. Cu, which is currently used as a wiring material, has reached a limit in terms of current resistance density or fine structure formation, and it is expected to adopt a new wiring material. Carbon nanotubes (CNT) are one of the materials attracting attention as next-generation wiring materials because they have a high current density capacity and can be easily grown into a fine region.

  Wirings using carbon nanotubes are known in which the carbon nanotubes are filled with an embedding material such as a resin containing a fixing component for stability. However, when the carbon nanotubes are long or the embedding material has a high density, the embedding material sometimes fails to fill the space between the carbon nanotubes. In such a case, there is a possibility that the carbon nanotubes are peeled off from the growth substrate. Further, when the embedding material has a low density, the space between the carbon nanotubes is filled, but it is difficult to obtain the stability of the carbon nanotubes.

JP 2008-41954 A

  The problem to be solved by the invention is to provide a semiconductor substrate having good characteristics using carbon nanotubes, a manufacturing method thereof, and an electronic device.

  A semiconductor substrate according to an aspect of the present invention includes a substrate having a lower electrode on one main surface, an interlayer insulating film provided on a portion other than the lower electrode on the substrate, and a catalyst provided on the lower electrode. A plurality of carbon nanotubes provided on the catalyst layer and extending in a direction perpendicular to one main surface of the lower electrode, an upper electrode provided on the carbon nanotube and facing the lower electrode, The first embedded film covering the catalyst layer and the end of the carbon nanotube on the catalyst layer side and the other end of the carbon nanotube are filled, and the second embedded film has a higher density than the first embedded film. And a buried film.

A method of manufacturing a semiconductor substrate according to an aspect of the present invention includes forming a catalyst layer on the lower electrode of a substrate provided with a lower electrode and an interlayer insulating film surrounding the lower electrode on one main surface,
A plurality of carbon nanotubes are formed on the catalyst layer so as to protrude from the interlayer insulating film,
By infiltrating the first material between the carbon nanotubes, to form a first embedded film that covers the catalyst layer side end of the carbon nanotubes and the catalyst layer,
By penetrating a second material having a density higher than that of the first material between the carbon nanotubes, a second embedded film that fills between the other ends of the carbon nanotubes is formed.
Removing the other end of the carbon nanotube and a part of the second embedded film;
An upper electrode is provided on the carbon nanotube so as to face the lower electrode.

  An electronic device according to an aspect of the present invention includes a substrate having a lower electrode on one main surface, an interlayer insulating film provided on a portion of the substrate other than the lower electrode, and a catalyst provided on the lower electrode. A plurality of carbon nanotubes provided on the catalyst layer and extending in a direction perpendicular to one main surface of the lower electrode, an upper electrode provided on the carbon nanotube and facing the lower electrode, The first embedded film covering the catalyst layer and the end of the carbon nanotube on the catalyst layer side and the other end of the carbon nanotube are filled, and the second embedded film has a higher density than the first embedded film. And a buried substrate.

Sectional drawing which shows the semiconductor substrate of 1st Embodiment. The enlarged view which shows a part of semiconductor substrate. The figure which shows the manufacturing method of the semiconductor substrate of 1st Embodiment. The figure which shows the manufacturing method of the semiconductor substrate of 1st Embodiment. Sectional drawing which shows the semiconductor substrate of a comparative example. The figure which shows the manufacturing method of the semiconductor substrate of a comparative example. Sectional drawing which shows the semiconductor substrate of 2nd Embodiment. The figure which shows the manufacturing method of the semiconductor substrate of 2nd Embodiment. FIG. 10 is a diagram illustrating a cross section of an electronic device according to a third embodiment.

  Below, the outline of the embodiment of the present invention is explained in detail, referring to drawings. Each figure is a schematic diagram for promoting explanation and understanding of the invention. The shape, dimensional ratio, etc. may be different from the actual one. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings. These can be appropriately modified in consideration of the following description and known techniques, and the present invention is not limited to these specific examples.

  Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described.

  FIG. 1 is a cross-sectional view showing a semiconductor substrate 100 included in the electronic device according to the first embodiment. The semiconductor substrate 100 is provided on the substrate 1 having the lower electrode 2 on one main surface, the interlayer insulating film 3 provided on the substrate 1 and having the via hole 11 exposing the lower electrode 2, and the lower electrode 2. On the barrier metal layer 4, the first catalyst layer 5 provided on the barrier metal layer 4, the catalyst layer 6 formed in an island shape or the like on the first catalyst layer 5, and the catalyst layer 6 A plurality of carbon nanotubes 7 that are provided and extend in a direction perpendicular to the main surface of the lower electrode 2, and a first embedded film 10 that covers the bottom portion of the via hole 11 of the carbon nanotube 7 and the second catalyst layer 6. A second buried film 8 filled between the other end portions of the carbon nanotubes 7 near the upper portion of the via hole 11, an upper electrode 9 provided so as to cover the via hole 11 and facing the lower electrode 2, Have A portion other than the carbon nanotubes 7 between the first buried film 10 and the second buried film 8 is a space 13.

  The electronic device has a transistor, a capacitor, and the like on such a semiconductor substrate 100.

  The first buried film 10 and the second buried film 8 are, for example, resin. The density of the first buried film 10 is lower than the density of the second buried film 8. The first embedded film 10 fixes the carbon nanotube 6 to the lower electrode 2. The second embedded film 8 fixes the carbon nanotubes 7 when the planarization process is performed before the upper electrode 9 is provided.

  The second embedded film 8 has a density that is strong enough to fix the carbon nanotubes 7. As will be described later, the second embedded film 8 is formed by using a liquid material for the second embedded film 8 and allowing it to penetrate between the carbon nanotubes 7 from above the via holes 11 and then curing. Depending on the density of the material forming the second embedded film 8 and the density of the carbon nanotubes 7 in the via hole 11, there is a possibility that the bottom of the via hole 11 may not be penetrated. In such a case, the carbon nanotubes 7 may be separated from the lower electrode 2. However, when a liquid material having a lower density than the material of the second buried film is used as the first buried film 10, the material can be easily penetrated to the bottom of the via hole 11. It can be fixed to the electrode 2.

  For example, when the material for forming the first embedded film 10 and the second embedded film 8 is an organic solvent containing a resin, the resin concentration of the material of the second embedded film 8 is higher than that of the material of the first embedded film 10. Lower.

For example, polysiloxy acid can be used as the fixing component, and isopropyl alcohol can be used as the organic solvent. The density of the fixed component of the first embedded film 10 can be 5% or more and 10% or less. The density of the fixed component of the second embedded film 8 can be 10% or more and 20% or less. As the first buried film 10 and the second buried film 8, a metal or an oxide can be used in addition to the resin. As the metal, for example, aluminum or copper can be used. As the oxide, for example, silicon oxide (SiO ₂ ) can be used. Even when a metal or an oxide is used, the second buried film 8 has a higher density than the first buried film 10.

  As the carbon nanotubes 7, multiwalled carbon nanotubes (MWCNTs) composed of a plurality of graphene sheets can be used.

  When MWCNT is used as the carbon nanotube 7, the electrical conductivity can be increased by performing a process of flattening the tip after the growth. The upper electrode 9 side of the carbon nanotube 7 after growth is closed. FIG. 2A is an enlarged view showing a part of the semiconductor substrate 100 when the carbon nanotube 7 is not flattened (closed end state), and FIG. It is a figure which expands and shows a part of semiconductor substrate 100 in the case (open end state). In any of the figures, the location where the current 12 flows is indicated by an arrow.

When the upper electrode 9 is formed directly on the closed carbon nanotube 7, only the outermost carbon nanotube layer can contribute to conduction, as shown in FIG. Can not. Therefore, before the upper electrode 9 is formed, chemical mechanical polishing (CMP) is performed on the tip of the carbon nanotube 7 to flatten the upper surface, and at the same time, the carbon nanotube 7 is opened. That is, the tip of the carbon nanotube 7 is cut by CMP treatment. By forming the upper electrode 9 on the carbon nanotube 7, the inner carbon nanotube layer also electrically connects the upper electrode 9 and the lower electrode 2 as shown in FIG. A method for manufacturing the semiconductor substrate 100 as shown in FIG. 1 will be described. 3 and 4 are cross-sectional views showing a method for manufacturing the semiconductor substrate 100. As shown in FIG.

Until the process of opening the via hole 11, a conventional LSI wiring process is used. That is, as shown in FIG. 3A, after the lower electrode 2 is formed on the substrate 1, the interlayer insulating film 3 is formed. For example, a silicon oxide film (SiOC film) containing carbon is used for the interlayer insulating film 3. This SiOC film may be a film containing pores (micropores) for the purpose of lowering the dielectric constant. When SiO ₂ is used as the interlayer insulating film 3, it may be formed by a plasma CVD method using tetraethoxy (TEOS) gas or the like. Next, a protective film called a cap layer (not shown) is formed on the SiOC film which is the interlayer insulating film 3. This is for suppressing damage in a later process such as an etching process or a CMP process. For example, a silicon oxide film (SiO ₂ ) or the like is used for the Cap layer. In the case where a SiOC film containing no pore is used for the interlayer insulating film 3, it is not necessary to form a cap layer.

  Next, a via hole 11 is formed in the interlayer insulating film 3. The via hole 11 is formed by, for example, a dry etching method called a reactive ion etching method using a plasma method or a wet etching method using a chemical solution. After the via hole 11 is formed in the interlayer insulating film 3, a contact layer (for example, a single metal such as tungsten (W), copper (Cu), or aluminum (Al)) is used as a conductive material to make contact with the lower layer wiring 2. (Not shown) is provided on the lower electrode 2. In the present embodiment, the barrier metal layer 4 is inserted for the purpose of preventing metal diffusion of the contact layer, which is a conductive material. In this embodiment, the TaN layer that is the barrier metal layer 4 is formed by sputtering. Other examples of the material used for the barrier metal layer 4 include tantalum (Ta), titanium (Ti), ruthenium (Ru), manganese (Mn), cobalt (Co), and nitrides thereof. A lower electrode 2 is provided at the bottom of the via hole 11, and the interlayer insulating film 3 surrounds the lower electrode 2.

  Next, carbon nanotubes 7 are grown in the via hole 11 as a via wiring material. A first catalyst layer 5 and a second catalyst layer 6 that play an important role for growth are sequentially formed on the barrier metal layer 4. Examples of the first catalyst layer 5 and the second catalyst layer 6 include titanium nitride (TiN) and cobalt (Co), respectively. In the growth of carbon nanotubes, only the second catalyst layer 6 can be used as the catalyst layer. However, a promoter such as TiN is placed under the first catalyst layer 6 made of Co as the first catalyst layer 5. As a result, the growth of the carbon nanotubes 7 is further promoted.

  The catalyst layer is not limited to the laminated structure composed of the first catalyst layer 5 and the second catalyst layer 6 /, but for example, a laminated structure such as Co / Ti, Co / Ta, Ni / TiN, Ni / Ta, etc. There may be. Alternatively, a single layer such as a Co layer or a Ni layer may be used. The manufacturing method is not limited to the sputtering method, and other manufacturing methods such as a vacuum deposition method may be used as long as the manufacturing method does not impair the catalyst layer function. Here, the island-like structure is formed at the time of formation. However, since the second catalyst layer 6 is thin, the second catalyst layer 6 is formed when the second catalyst layer 6 is a continuous film. May be exposed to plasma, or the temperature of the second catalyst layer 6 may be increased for a short time to make the second catalyst layer 6 have an island structure. The diameter of the carbon nanotube 7 is controlled by the diameter of the first metal particle 16. Therefore, the average particle diameter of the second catalyst layer 6 can be in the range of about 2 nm to about 10 nm, desirably about 4 nm to about 6 nm.

  Thereby, the tubular carbon nanotube 7 can be grown in the direction perpendicular to the main surface of the substrate 1 in the via hole 11.

  Next, as shown in FIG. 3B, in order to manufacture the carbon nanotubes 7 only in the via holes 11, the first catalyst layer 5 in a region other than the bottom of the via holes 11 (herein referred to as a field region) and The second catalyst layer 6 is removed. Therefore, Ar ion milling is used as a means in this embodiment. An angle is set so that Ar ions are incident on the substrate 1 obliquely, and the substrate 1 is rotated as appropriate, so that the side surfaces of the field region and the via hole 11 perpendicular to the substrate 1 are irradiated with ions. The removal of the catalyst layer in the field region is not limited to the above method, and any method may be used as long as the first catalyst layer 5 and the second catalyst layer 6 remain only at the bottom of the via hole 11.

FIG. 3C is a diagram schematically showing a state in which the growth in the via hole of the CNT 7 has been completed. As shown in FIG. 3C, the carbon nanotubes 7 are grown in the via holes 11 by the plasma CVD method. The carbon nanotubes 7 are made longer than the thickness of the interlayer insulating film 3, and the tip portions protrude from the via holes 11. The island-shaped second catalyst layer 6 is provided in advance at the bottom of the via hole 11, and the carbon nanotubes 7 grow on each island-shaped second catalyst layer 6. The surface density is, for example, approximately 10 ¹² pieces / cm ² . A plasma CVD method is used to form the carbon nanotubes 7.

Methane (CH ₄ ) gas is used as the source gas, and hydrogen gas (H ₂ ) is used as the dilution gas. The source gas and the dilution gas are not limited to the above gases, and a hydrocarbon gas such as ethylene gas (C ₂ H ₄ ) or acetylene gas (C ₂ H ₂ ) may be used as the source gas. As the dilution gas, an inert gas such as helium gas (He), nitrogen gas (N ₂ ), or argon gas (Ar) may be used. Alternatively, only the source gas can be used. The substrate temperature can be in the range of 400 ° C. to 600 ° C., and the reaction pressure can be 5 Torr. However, the carbon nanotubes 7 can be grown even when the temperature exceeds this range.

  Further, as shown in FIG. 3C, since the first catalyst layer 5 and the second catalyst layer 6 on the side wall of the field region and the via hole 11 are removed, the carbon nanotubes 7 can be formed only from the bottom of the via hole 11. Will not grow. Moreover, since the second catalyst layer 6 at the bottom of the via hole 11 has an island shape, a large number of tubular carbon nanotubes 7 grow correspondingly. Each carbon nanotube 7 electrically connects the lower electrode 2 and the upper wiring 9 in the substrate 1, and a “CNT bundle” that is an aggregate of the CNTs 7 functions as a via wiring layer. As an example, when the depth of the via hole is about 120 nm, the growth time of the carbon nanotube 7 is adjusted so that the carbon nanotube 7 protrudes about 50 nm from the substrate surface.

The next step is a step of forming the first buried film 10 in the via hole 11 and fixing the carbon nanotube 7 and the lower electrode 2 to the substrate 1 as shown in FIG. As the material (first material) of the first buried film 10, as described above, for example, a SiO ₂ film such as liquid SOG (SPIN On Glass) is used.

  However, when ordinary SOG is used, the material of the first buried film 10 does not penetrate to the bottom of the via hole 11 as described above. As the material of the first buried film 10, a material whose density is lower than that of the SOG film and whose permeability is increased is used. When the first embedded film 10 is prepared by dissolving a fixed component with an organic solvent, a film having a high organic solvent concentration is used. By reducing the concentration of the fixing component, the material of the first embedded film 10 penetrates to the bottom of the via hole 11, and the adhesion strength between the lower layer wiring 2 and the carbon nanotube 7 can be increased.

  Next, as shown in FIG. 4E, SOG as the material (second material) of the second embedded film 8 is provided. The SOG of the second embedding material 8 has a normal concentration. The first buried film 10 and the second buried film 8 can be formed by dropping SOG on the surface of the substrate 1 and applying it by spin coating using a spin coater, followed by curing by heating.

  In order to cure the material of the first embedded film 8 and the material of the second embedded film 10 after being applied, for example, heating or ultraviolet irradiation may be used. In the curing procedure, the material of the first embedded film 10 is applied and cured, and then the second embedded film 8 is applied and cured. These may be cured at once after the first embedded film 10 is applied and the second embedded film 10 is applied continuously, but it is preferable that the first embedded film 10 is cured in the order described above.

  Thereafter, CMP (chemical mechanical polishing) is performed on the upper surface of the via hole 11 and the upper surface of the interlayer insulating film 3 in order to remove the upper portion of the carbon nanotube 7 protruding from the via hole 11 and the second embedded film between the protruding carbon nanotubes 7. Process. Since the density of the fixed component is high in the second embedded film 8, the strength of the surface to be subjected to the CMP process is increased.

FIG. 4F is a schematic diagram showing a state after the CMP process. As shown in FIG. 4 (f), the lower electrode 2 and the carbon nanotube 7 have high adhesion due to the first embedded film 10. The second buried film 8 in the field portion is uniformly polished by CMP, and the carbon nanotubes 7 protruding from the via holes are also polished together with the buried film 8 made of SiO ₂ . As a result, the entire surface of the substrate 1 is flattened, and the carbon nanotubes 7 are in an open end state as shown in FIG.

  Finally, as shown in FIG. 4G, the upper electrode 9 is formed on the via hole 11 planarized by CMP. As the material of the upper electrode 9, a laminated structure of titanium (Ti), aluminum (Al), Ti, Al alone, or another metal material for electrodes is used and formed by a technique such as sputtering or vacuum deposition. In this way, the semiconductor substrate 100 is completed.

  As described above, according to the first embodiment, the second buried film 8 is formed after the first buried film 10 is formed, so that the lower electrode 2 is formed even if the CMP process is performed as a planarization process. The carbon nanotubes 7 do not peel off. As a result, the carbon nanotubes 7 can function as via wiring, and as a result, the yield reduction of the semiconductor substrate 100 can be suppressed.

(Comparative example)
FIG. 5 is a cross-sectional view showing a semiconductor substrate 200 included in the electronic device of the comparative example. In the comparative example, the embedded film 208 is of one type, and the density of the fixed component is set so that the carbon nanotubes 7 can be stabilized. When one kind of buried film 14 is used, the one kind of buried film is interposed between the carbon nanotubes 7 in order to stabilize the carbon nanotube 7 while fixing the end of the carbon nanotube 7 on the via hole 11 side to the substrate 1. It is necessary to satisfy with 208.

  However, depending on the density of the fixed component contained in the buried film 208 and the density of the carbon nanotubes 7, the material of the buried film 208 may not penetrate to the bottom of the via hole 11. As shown in FIG. Thus, there is a possibility that the bottom end of the via hole 11 of the carbon nanotube 7 may be peeled off from the substrate 1.

  A case where such a problem occurs will be described. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor substrate 200 of the comparative example. The process is the same as in the first embodiment until the carbon nanotubes 7 are formed in the via holes 11 (FIG. 6A).

  Thereafter, a buried film 208 is provided on the carbon nanotubes 7 and the interlayer insulating film 3 and penetrates into the via holes 11. When the bottom portion in the via hole 11 does not penetrate (FIG. 6 (b)), the adhesion between the lower electrode 1, the second catalyst layer 6 and the carbon nanotube 7 is not so strong. A phenomenon occurs in which the carbon nanotubes 7 are peeled off from the lower electrode 2 due to the pulling force (FIG. 5C). The electrical characteristics of the semiconductor substrate 200 obtained by forming the upper electrode 9 in such a state (FIG. 5D) are measured. When half of the carbon nanotubes 7 grown in the via hole are peeled off from the lower electrode 2, the wiring resistance is doubled and desired characteristics cannot be obtained. As described above, the CMP process is aimed at the flattening process and the open end process of the carbon nanotubes 7, and therefore the material of the buried layer 208 must be a strong material. Therefore, a coating material having a high concentration of the fixing component is used for the buried layer 208. As the density of the carbon nanotubes 7 grown in the via hole 11 increases, the degree of penetration of the material of the buried layer 208 decreases and a phenomenon that does not reach the via bottom 11 occurs. If a buried material with a low concentration of the fixed component is used for the buried layer 208, the buried material penetrates to the bottom of the via hole 11. However, since the strength is weakened, the carbon nanotube is not polished and is not polished when the CMP process is performed. It will peel off.

  When metals or metal oxides are used as the first buried film 10 and the second buried film 8, they are solidified after being penetrated into the via hole 11 at a high temperature when formed.

  In the present embodiment, the number of catalyst layers is two, but the first embedded film 10 covers the catalyst layer and the ends of the carbon nanotubes 7 even when the number of layers is one.

  As described above, in the conventional semiconductor substrate 200, the carbon nanotubes 7 may be peeled off from the lower electrode 2, and the yield of the semiconductor substrate 200 is reduced.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing a semiconductor substrate 300 included in the electronic device according to the second embodiment. The second embodiment is different from the first embodiment in that the first buried film 10 and the second buried film 8 are formed in contact with each other.

  A method for manufacturing such a semiconductor substrate 300 will be described with reference to FIG. The steps up to the step of forming the first buried film 10 are the same as those in the first embodiment, and are therefore omitted. FIG. 8A shows a state after the first buried film 10 is provided.

  Subsequently, as shown in FIG. 8B, the second embedded film 8 is provided so as to fill the space between the carbon nanotubes 7 on the first embedded film 10. At this time, the first buried film 10 and the second buried film 8 are in contact with each other.

  Subsequently, as shown in FIG. 8C, the first buried film 10, the second buried film 8 and the carbon nanotubes 7 protruding from the via hole 11 on the interlayer insulating film 3 are planarized by CMP. .

Further, as shown in FIG. 8D, the upper electrode 9 is provided so as to cover the via hole 11, and the semiconductor substrate 300 is obtained.

  In such a configuration, the second buried film 8 is continuously formed after the first buried film 10 is formed, and the first buried film 10 and the second buried film 8 are heated and cured at a time. It becomes possible. Also in this embodiment, the same effect as that of the first embodiment can be obtained.

(Third embodiment)
An electronic device can be formed using the semiconductor substrate as described above as a connection wiring such as a transistor or a capacitor.

  FIG. 9 is a cross-sectional view illustrating an example of an electronic device. Here, the semiconductor substrate 100 according to the first embodiment will be described. The electronic device includes a semiconductor substrate 100 having the first substrate 1 and a second substrate 14 provided on the upper electrode 9.

  The first substrate 1 and the second substrate 14 are provided with elements such as transistors and capacitors. With such a configuration, the first substrate 1 and the second substrate 14 can be electrically connected. Examples of the electronic device include a micro electro mechanical system (MEMS) device.

1: Substrate 2: Lower electrode 3: Interlayer insulating film 4: Barrier metal layer 5: First catalyst layer 6: Second catalyst layer 7: Carbon nanotube 8: Second embedded film 9: Upper electrode 10: First Embedded film 11: via hole 12: current 13: space 14: second substrate 208: buried film 100: semiconductor substrate 200 of the first embodiment: semiconductor substrate 300 of the comparative example 300: semiconductor substrate of the second embodiment

Claims (9)

A substrate having a lower electrode on one principal surface;
An interlayer insulating film provided on a portion other than the lower electrode on the substrate;
A catalyst layer provided on the lower electrode;
A carbon nanotube provided on the catalyst layer and extending in a direction perpendicular to one main surface of the lower electrode;
An upper electrode provided on the carbon nanotube and facing the lower electrode;
A first embedded film covering the catalyst layer and an end portion of the carbon nanotube on the catalyst layer side;
A second embedded film filled between the other end portions of the carbon nanotubes and having a higher density than the first embedded film;
A semiconductor substrate.   The semiconductor substrate according to claim 1, wherein the first embedded film is a resin, a metal, or an oxide, and the second embedded film is a resin, a metal, or an oxide.   The semiconductor substrate according to claim 2, wherein the first buried film and the second buried film include at least one of polysiloxy acid, aluminum, copper, and silicon oxide. Forming a catalyst layer on the lower electrode of the substrate provided with a lower electrode and an interlayer insulating film surrounding the lower electrode on one main surface;
A plurality of carbon nanotubes are formed on the catalyst layer so as to protrude from the interlayer insulating film,
By infiltrating the first material between the carbon nanotubes, to form a first embedded film that covers the catalyst layer side end of the carbon nanotubes and the catalyst layer,
By penetrating a second material having a density higher than that of the first material between the carbon nanotubes, a second embedded film that fills between the other ends of the carbon nanotubes is formed.
Removing the other end of the carbon nanotube and a part of the second embedded film;
A method for producing a semiconductor substrate, comprising providing an upper electrode on the carbon nanotube so as to face the lower electrode.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first buried film is formed by heating the first material after impregnating the first material between the carbon nanotubes.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the second embedded film is formed by heating the second material after infiltrating the second material between the carbon nanotubes.   5. The method of manufacturing a semiconductor device according to claim 4, wherein after the first material is infiltrated between the carbon nanotubes, the first embedded film is formed by irradiating the first material with ultraviolet rays. 6.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the second embedded film is formed by irradiating the second material with ultraviolet light after allowing the second material to penetrate between the carbon nanotubes.   A substrate having a lower electrode on one main surface, an interlayer insulating film provided on a portion other than the lower electrode on the substrate, a catalyst layer provided on the lower electrode, and provided on the catalyst layer A plurality of carbon nanotubes extending in a direction perpendicular to one main surface of the lower electrode, an upper electrode provided on the carbon nanotube and facing the lower electrode, the catalyst layer, and the catalyst layer of the carbon nanotube A semiconductor substrate having a first buried film covering an end portion on the side and a second buried film filled between the other end portions of the carbon nanotubes and having a higher density than the first buried film. Electronic device with.

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