JP2012203005A - Pattern forming method and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern forming method capable of manufacturing a semiconductor device at a high yield and a low cost.SOLUTION: The pattern forming method which forms a mask pattern corresponding to a pattern on a substrate so as to be capable of forming the pattern on the substrate according to a design pattern includes: forming the mask pattern on the basis of a relative relationship that the design patterns are required to satisfy so that the mask patterns corresponding to the design patterns satisfy the relative relationship.

Description

  Embodiments described herein relate generally to a pattern creation method and a semiconductor device manufacturing method.

  In the design and manufacture of semiconductor devices, circuit patterns with a small design margin are increasing with the miniaturization of patterns. For this reason, there is a tendency that the number of locations that are vulnerable to dimensional variations (locations where electrical desired functions cannot be achieved) increases. Furthermore, a circuit that is sensitive to noise and variation, such as an analog circuit, needs to satisfy predetermined constraints in order to exhibit desired device performance. For example, constraints include not only the dimensions of individual patterns but also the relative positions, sizes, shapes, lengths, etc., between patterns (between design blocks and circuits).

  However, in the conventional technique, it is difficult to extract the above constraints as a designer's intention and use it on the manufacturing side. For example, in the design stage, a circuit pattern (design layout) is created in consideration of electrical characteristics such as timing, crosstalk, and reliability, and in consideration of relative relationships between blocks and patterns. However, what is sent and received on the manufacturing side is a design layout composed of a plurality of layers. In the manufacturing process, pattern formation processing is performed to realize the dimensions and shape of the layout. For this reason, it is difficult to carry out a manufacturing process in consideration of a location important in electrical characteristics and a relative positional relationship between patterns, and there is a problem that a circuit yield is lowered.

  In addition, since it is difficult to assign a specification based on the positional relationship between patterns to a design layout, there is a method in which an excessive margin is taken into consideration at the design stage. This method has a problem that the chip area increases because it is necessary to design all design layouts with excessively large dimensions. Therefore, it is desired to manufacture a semiconductor device with high yield and low cost.

JP 2008-269299 A

  The problem to be solved by the present invention is to provide a pattern forming method and a semiconductor device manufacturing method capable of manufacturing a semiconductor device with high yield and low cost.

  According to the embodiment, a pattern creation method is provided. In the pattern creation method, when creating a mask pattern according to the on-substrate pattern so that a pattern on the substrate according to the design pattern can be formed, the design pattern is based on a relative relationship that must be satisfied between the design patterns. The mask pattern is created so that the mask patterns corresponding to each other satisfy the relative relationship.

FIG. 1 is a diagram showing a configuration of a mask pattern creation system according to the first embodiment. FIG. 2 is a diagram illustrating an example of a constraint condition. FIG. 3 is a diagram for explaining an example of a mask pattern creation process based on relative information. FIG. 4 is a diagram showing a configuration of a mask pattern creation system according to the second embodiment. FIG. 5 is a diagram for explaining the relationship between the design layout and the pattern on the wafer. FIG. 6 is a diagram for explaining mask pattern correction processing for a circuit pattern that requires area symmetry. FIG. 7 is a diagram for explaining mask pattern correction processing for a circuit pattern that requires length symmetry. FIG. 8 is a flowchart showing a processing procedure of a dose map creation process based on relative information. FIG. 9 is a diagram illustrating a hardware configuration of the mask pattern creating apparatus.

  Exemplary embodiments of a pattern creating method and a semiconductor device manufacturing method will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
When creating a mask pattern, lithography simulation is repeated so that a pattern on the wafer having a desired shape can be formed, thereby optimizing the mask pattern. However, even if the input layout group (design pattern) and adjacent design patterns have the same shape, the grid (lattice point) shifts and grid shifts (grid errors) in the lithography simulation accumulate, and OPC (Optical Proximity Correction) Mask pattern shapes may not be equal. Therefore, in this embodiment, when the design layout is shipped, a file indicating constraint information (hereinafter referred to as relative information) with respect to the relative relationship between the design pattern groups is shipped together with the design layout. Based on this relative information, a mask pattern is created. For example, when there is a pair of design patterns that should have the same mask pattern shape, the design pattern is converted into a mask pattern having the same shape.

  FIG. 1 is a diagram showing a configuration of a mask pattern creation system according to the first embodiment. The mask pattern creation system 100A includes a mask pattern creation device 1A, a design layout creation device 2, and a relative information creation device 3.

  The design layout creation apparatus 2 is a computer or the like that creates a design layout (data such as the shape, dimension, and arrangement position of a plurality of design patterns) of a semiconductor device (semiconductor integrated circuit). The design layout creating apparatus 2 creates a design layout so as to satisfy a constraint condition 5 described later. The constraint condition 5 is a condition that each design pattern should satisfy in order for the semiconductor device to satisfy the circuit function. The design layout creation device 2 sends the created design layout to the relative information creation device 3.

  The relative information creation device 3 is a computer or the like that creates relative information for the mask pattern corresponding to the design pattern based on the design layout and the constraint condition 5 on the design pattern in the design layout. The constraint condition 5 on the design pattern is a constraint on design patterns (between design blocks, circuits, and individual patterns). Relative information is information relating to restrictions between mask patterns or between patterns on a wafer. The relative information used in the present embodiment is information related to the restriction between mask patterns.

  The relative information creation device 3 includes an input unit 31, a constraint condition storage unit 32, a relative information creation unit 33, and an output unit 34. The input unit 31 inputs the constraint condition 5 for each design pattern and sends it to the constraint condition storage unit 32. The constraint condition storage unit 32 is a memory that stores the constraint condition 5 or the like.

  Here, the constraint condition 5 will be described. FIG. 2 is a diagram illustrating an example of a constraint condition. The constraint condition 5 is a condition for defining a relative relationship between patterns on the wafer, and “constraint name” and “constraint content” are associated with each other. Examples of the “constraint name” include “differential pair”, “distance”, “equal delay wiring”, “equal length wiring”, “equal design parameter”, “symmetric arrangement”, “same shape”, and the like.

  The “differential pair” is a restriction that requires that wiring patterns be wired as a differential pair. For example, a circuit functioning as a differential pair needs to be symmetrically wired by aligning the length of the pair circuit, the number of bends (number of bends), the bend angle, left-right symmetry, and the number of vias.

  “Distance” is a constraint value related to the distance from the pattern wiring. “Equal delay wiring” is a constraint for matching propagation delay between bus wirings between patterns. In the “equal delay wiring”, in order to align the delay between patterns, for example, the equal length of the pattern, the equal area, and the like are defined.

  “Equal length wiring” is a constraint that makes the dimensions of the pattern the same length. “Equal design parameter” is a constraint for equalizing design parameters such as channel length and channel width of transistors. In an element group in which the characteristics of transistors should be uniformed, it is necessary to pay attention to channel length, channel width, and shape in order to suppress manufacturing variations.

  Furthermore, there is a circuit that emphasizes symmetry, such as a current mirror. “Symmetrical arrangement” is a constraint for arranging a pattern at a symmetrical position such as line symmetry by placing the pattern symmetrically with respect to a set axis. “Same shape” is a constraint for arranging the same pattern (a pattern having the same shape and the same size) as a pattern.

  The relative information creation unit 33 extracts constraints given to each design pattern based on the constraint condition 5 and creates relative information. For example, the relative information creation unit 33 calculates the relationship between the relative positional relationship between the circuit patterns and the dependency of the circuit characteristics based on the electrical characteristics of the circuit patterns extracted from the design layout, and the constraint condition 5 Create relative information to achieve

  For example, when the constraint of “same shape” is defined in the constraint condition 5 for two design patterns (for example, the design pattern Ax and the design pattern Bx), the relative information creation unit 33 selects the two design patterns. Information in which Ax, Bx and “same shape” are associated is created as relative information (Ax = Bx). The output unit 34 outputs the design layout and the relative information created by the relative information creation unit 33 to the mask pattern creation device 1A.

  The design layout creation device 2 may be configured to have the function of the relative information creation device 3. In this case, the design layout creating apparatus 2 may perform the design layout creating process and the relative information creating process at the same time. For example, when the pattern data of the design patterns Ax and Bx is created, if the design pattern Ax and Bx has the constraint condition 5 of “same shape”, the design patterns Ax and Bx are created with the same shape. And the relative information which matched design pattern Ax, Bx and "same shape" is produced.

  The mask pattern creation device 1A is a computer that creates a mask pattern based on the design layout and relative information. The mask pattern creation apparatus 1A includes an input unit 11, a relative information storage unit 12, a design layout storage unit 13, a mask pattern creation unit 14A, and an output unit 15.

  The input unit 11 inputs the relative information sent from the relative information creation device 3 and sends it to the relative information storage unit 12. Further, the input unit 11 inputs the design layout sent from the relative information creation device 3 and sends it to the design layout storage unit 13. Note that the input unit 11 may input a design layout from the design layout creating apparatus 2. The relative information storage unit 12 is a memory that stores relative information, and the design layout storage unit 13 is a memory that stores a design layout.

  The mask pattern creation unit 14A creates a mask pattern using the relative information and the design layout. The mask pattern creation unit 14A creates a lithography target by performing target MDP (mask data processing) processing on the design data. Furthermore, the mask pattern creation unit 14A creates a mask pattern after OPC by performing OPC on the lithography target. The mask pattern creation unit 14A according to the present embodiment may perform mask pattern creation based on relative information when performing OPC processing, or mask pattern correction based on relative information for the mask pattern subjected to OPC processing. May be performed.

  For example, when the relative information is “same shape” (Ax = Bx) and the mask patterns to be created for the design patterns Ax and Bx are the mask patterns Am and Bm, the mask pattern creation unit 14A determines that the mask pattern Am Mask patterns Am and Bm are created so that the mask pattern Bm is the same mask pattern. The output unit 15 outputs the mask pattern created by the mask pattern creation unit 14A to an external device (such as a display device or an electron beam drawing device).

  Next, a mask pattern creation process based on relative information will be described. FIG. 3 is a diagram for explaining an example of a mask pattern creation process based on relative information. Here, a case where the relative information is “same shape” will be described. FIG. 3A shows an example of a design pattern. Here, a case where the design pattern includes the design patterns A1 to H1 is shown.

  When a fine pattern is exposed on a substrate (such as a wafer), a pattern on the wafer having a desired shape cannot be formed due to effects such as light refraction and interference (optical proximity effect). Therefore, pattern correction (optical proximity effect correction (OPC) is performed on the mask so that a desired pattern on the wafer can be obtained. FIG. 3B shows an OPC process without considering relative information. The mask patterns A2 to H2 created in this way are mask patterns corresponding to the design patterns A1 to H1, respectively.

  In the present embodiment, when performing the OPC process, the mask pattern creation unit 14A creates a mask pattern based on the relative information. FIG. 3C shows a mask pattern created by OPC processing based on relative information. Here, a case where the relative information “same shape” is “A1 = B1 = C1 = D1”, “E1 = F1”, and “G1 = H1” will be described. In this case, the mask patterns A3 to D3 corresponding to the design patterns A1 to D1 are created to be the same mask pattern. Similarly, the mask patterns E3 and F3 corresponding to the design patterns E1 and F1 are created to be the same mask pattern, and the mask patterns G3 and H3 corresponding to the design patterns G1 and H1 are the same mask pattern. Created.

  Further, when creating a mask pattern, a dummy pattern such as SRAF (Sub Resolution Assist Features) may be arranged in the vicinity of the mask pattern. FIG. 3D shows a mask pattern created by arranging dummy patterns. In the present embodiment, when the mask pattern creation unit 14A places a dummy pattern in the vicinity of the mask pattern, an equivalent dummy pattern is placed in a pattern group that should have the same shape.

  The mask pattern creating unit 14A here arranges dummy patterns d having the same shape at the same relative positions with respect to the mask patterns A3 to D3 corresponding to the design patterns A1 to D1. In other words, the dummy pattern d is arranged so that the pattern group composed of each mask pattern and the dummy pattern d arranged in the vicinity of each mask pattern becomes the same pattern group. For example, the pattern group consisting of the mask pattern A3 and the dummy pattern d arranged in the vicinity of the mask pattern A3 is the same as the pattern group consisting of the mask pattern B3 and the dummy pattern d arranged in the vicinity of the mask pattern B3. A dummy pattern d is arranged so as to form a pattern group.

  Similarly, the mask pattern creation unit 14A arranges the dummy pattern d having the same shape with respect to the mask patterns E3 and F3 at the same relative position, and the dummy pattern d having the same shape with respect to the mask patterns G3 and H3. Place in relative position.

  As a result, effects (such as an optical proximity effect) that depend on the diversity of pattern arrangement are reduced, and variations in the shape of the pattern on the wafer are reduced. Therefore, it is possible to form a pattern on the wafer having the same shape.

  The mask pattern creation by the mask pattern creation system 100A is performed for each layer of the wafer process, for example. Then, a semiconductor device is manufactured using the mask pattern created by the mask pattern creation device 1A. Specifically, a mask (circuit original plate) is produced using the created mask pattern, a resist-coated wafer is exposed using the mask, and then the wafer is developed to form a resist pattern on the wafer. It is formed. Then, the lower layer side of the resist pattern is etched using the resist pattern as a mask. Thereby, an actual pattern corresponding to the resist pattern is formed on the wafer. When manufacturing a semiconductor device, the above-described relative information creation process, mask pattern creation process, exposure process, development process, etching process, and the like are repeated for each layer.

  In the present embodiment, the case where the line pattern is arranged according to the restriction information has been described, but a hole pattern such as a via or a contact may be arranged according to the restriction information.

  As described above, according to the first embodiment, since the mask pattern is created based on the relative information, it is possible to form an on-wafer pattern corresponding to the design intention for the pattern group intended for the design. . For this reason, variation in the shape of the pattern on the wafer is reduced, a circuit having desired electrical characteristics can be formed, and the product yield is improved. Therefore, it becomes possible to manufacture a semiconductor device with high yield and low cost.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the mask pattern or the like is corrected (corrected) so that the pattern on the wafer satisfies the relative information.

  FIG. 4 is a diagram showing a configuration of a mask pattern creation system according to the second embodiment. Among the constituent elements in FIG. 4, constituent elements that achieve the same functions as those of the mask pattern creation system 100 </ b> A of the first embodiment shown in FIG. 1 are given the same numbers, and redundant descriptions are omitted. Note that the relative information used in the present embodiment is information relating to restrictions between patterns on the wafer.

  The mask pattern creation system 100B includes a mask pattern creation device 1B, a design layout creation device 2, and a relative information creation device 3. The mask pattern creation device 1B includes an input unit 11, a relative information storage unit 12, a design layout storage unit 13, a mask pattern creation unit 14B, an output unit 15, a determination unit 41, and a correction unit 42.

  The mask pattern creation unit 14B creates a mask pattern after OPC using the design layout. The mask pattern creation unit 14B sends the created mask pattern to the determination unit 41.

  When the on-wafer pattern is formed on the wafer using the mask pattern created by the mask pattern creation unit 14B, the determination unit 41 determines whether or not the on-wafer pattern that satisfies the relative information can be formed (determination OK or determination NG). Determine. The determination unit 41 according to the present embodiment performs pattern determination on a mask pattern corresponding to a design pattern defined by relative information. Note that the determination unit 41 may perform pattern determination on all mask patterns. The determination unit 41 sends the pattern determination result indicating which portion of the mask pattern is the determination NG and the mask pattern to the correction unit 42.

  The correction unit 42 corrects the mask pattern determined to be unable to form the on-wafer pattern that satisfies the relative information. The correction unit 42 corrects the mask pattern so that an on-wafer pattern that satisfies the relative information can be formed. The correction unit 42 sends the corrected mask pattern to the output unit 15. When there is no determination NG mask pattern, the correction unit 42 sends the mask pattern to the output unit 15 without correction.

  Next, a procedure for determining whether or not an on-wafer pattern satisfying relative information can be formed will be described. FIG. 5 is a diagram for explaining the relationship between the design layout and the pattern on the wafer. The design layout 51 is created by the design layout creation device 2 or the like.

  In the mask pattern creating apparatus 1B, the mask pattern creating unit 14B creates a mask pattern using the design layout 51. At this time, the mask pattern creation unit 14B creates a lithography target by performing target MDP processing on the design data. Furthermore, the mask pattern creation unit 14B creates a mask pattern after OPC by performing OPC on the lithography target. Thereafter, the determination unit 41 performs lithography simulation using the mask pattern after OPC, and thereby predicts the pattern shape of the on-wafer pattern 52. Then, the determination unit 41 determines whether or not the pattern shape of the on-wafer pattern 52 satisfies relative information.

  Next, mask pattern correction processing will be described. FIG. 6 is a diagram for explaining mask pattern correction processing for a circuit pattern that requires area symmetry. Here, a description will be given of a case where a constraint that should make the areas of the mask patterns equal is set as relative information.

  The mask pattern creation unit 14B creates a pair of mask patterns R1 and R2 (not shown) using a pair of design patterns in which the constraint that the areas should be equalized is defined by relative information. Then, as shown in FIG. 6A, the determination unit 41 predicts a pair of on-wafer patterns P1, P2 corresponding to the pair of mask patterns R1, R2 by lithography simulation or the like.

  For example, an on-wafer pattern (ideal pattern) that is axisymmetric to one of the on-wafer patterns P1 is defined as an on-wafer pattern Q2. The determination unit 41 compares the area of the on-wafer pattern P2 with the area of the on-wafer pattern Q2, and determines whether or not the compared shape difference (area difference) between the on-wafer patterns P2 and Q2 is equal to or less than a threshold value. judge.

  At this time, the determination unit 41 may use dimensions, areas, etc. of the on-wafer patterns P2, Q2 as a determination criterion. When the area difference satisfies a predetermined standard, the determination unit 41 adopts the mask patterns R1 and R2 corresponding to the on-wafer patterns P1 and P2 as usable (OK determination). For example, when deformation due to the optical proximity effect or the like occurs symmetrically with respect to a pattern group that requires symmetry, it is not necessary to modify the mask pattern because the desired device performance is satisfied unless the deformation deviates from a predetermined range.

  On the other hand, the determination unit 41 determines NG when the area difference does not satisfy the predetermined criterion. In this case, the correction unit 42 corrects the mask pattern R2 corresponding to the on-wafer pattern P2 so that the area difference satisfies a predetermined criterion. For example, the correcting unit 42 corrects the mask pattern R2 corresponding to the on-wafer pattern P2 so that the area of the on-wafer pattern P2 approaches the area of the on-wafer pattern Q2, which is an ideal pattern.

  The determination unit 41 may correct the mask pattern R1 corresponding to the on-wafer pattern P1. Further, the determination unit 41 may correct both the mask patterns R1, R2 corresponding to the on-wafer patterns P1, P2.

  After the mask pattern R2 corresponding to the on-wafer pattern P2 is corrected, the determination unit 41 predicts the on-wafer pattern corresponding to the corrected mask patterns R1, R2 by lithography simulation or the like.

  As shown in FIG. 6B, for example, by correcting the mask pattern R2, the on-wafer pattern P2 becomes the on-wafer pattern P4 having approximately the same area as the on-wafer pattern Q2. When the area difference between the on-wafer patterns P1 and P4 satisfies a predetermined standard, the determination unit 41 adopts the mask patterns corresponding to the on-wafer patterns P1 and P4 as usable.

  On the other hand, when the area difference between the on-wafer patterns P1 and P4 does not satisfy the predetermined reference, the mask pattern correction processing by the correction unit 42 and the area difference determination processing by the determination unit 41 are performed until the area difference satisfies the predetermined reference. Repeated.

  FIG. 7 is a diagram for explaining mask pattern correction processing for a circuit pattern that requires length symmetry. Here, a description will be given of a case where a constraint that should make the lengths of the mask patterns equal is set as relative information.

  The mask pattern creation unit 14B creates a pair of mask patterns R5 and R6 (not shown) using a pair of design patterns in which the constraint that the lengths should be equal is defined by relative information. Then, as shown in FIG. 7A, the determination unit 41 predicts a pair of on-wafer patterns P5 and P6 corresponding to the pair of mask patterns R5 and R6 by lithography simulation or the like.

  For example, an on-wafer pattern (ideal pattern) that is symmetric with respect to one of the on-wafer patterns P5 is defined as an on-wafer pattern Q6. The determination unit 41 compares the length of the on-wafer pattern P6 with the length of the on-wafer pattern Q6, and determines whether or not the difference in length between the compared on-wafer patterns P6 and Q6 is equal to or less than a threshold value.

  The determination unit 41 calculates the length of the on-wafer patterns P6 and Q6, for example, by dividing each area of the on-wafer patterns P6 and Q6 by each average width (lateral width). The determination unit 41 may calculate a line segment connecting the center positions in the horizontal width direction of the on-wafer patterns P6 and Q6 as the length of the on-wafer patterns P6 and Q6.

  When the length difference satisfies a predetermined criterion, the determination unit 41 adopts the mask patterns R5 and R6 corresponding to the on-wafer patterns P5 and P6 as usable (OK determination). For example, when deformation due to the optical proximity effect or the like occurs symmetrically with respect to a pattern group that requires symmetry, it is not necessary to modify the mask pattern because the desired device performance is satisfied unless the deformation deviates from a predetermined range.

  On the other hand, the determination unit 41 determines NG when the length difference does not satisfy the predetermined criterion. In this case, the correcting unit 42 corrects the mask pattern R6 corresponding to the on-wafer pattern P6 so that the length difference satisfies a predetermined criterion. For example, the correcting unit 42 corrects the mask pattern R6 corresponding to the on-wafer pattern P6 so that the length of the on-wafer pattern P6 approaches the length of the ideal pattern Q6 on the wafer.

  The determination unit 41 may correct the mask pattern R5 corresponding to the on-wafer pattern P5. Further, the determination unit 41 may correct both the mask patterns R5 and R6 corresponding to the on-wafer patterns P5 and P6.

  After the mask pattern R6 corresponding to the on-wafer pattern P6 is corrected, the determination unit 41 predicts the on-wafer pattern corresponding to the corrected mask patterns R5 and R6 by lithography simulation or the like.

  As shown in FIG. 7B, for example, by correcting the mask pattern R6, the on-wafer pattern P6 becomes the on-wafer pattern P7 having substantially the same length as the on-wafer pattern Q6. When the length difference between the on-wafer patterns P5 and P7 satisfies a predetermined criterion, the determination unit 41 adopts the mask pattern corresponding to the on-wafer patterns P5 and P7 as usable.

  On the other hand, when the length difference between the on-wafer patterns P5 and P7 does not satisfy the predetermined reference, the mask pattern correction processing by the correction unit 42 and the length difference by the determination unit 41 until the length difference satisfies the predetermined reference. The determination process is repeated.

  The on-wafer pattern may be derived by a transfer experiment on the wafer instead of the lithography simulation. In this case, a mask is created using the mask pattern created by the mask pattern creation unit 14B, and the resist on the wafer is exposed using the created mask. Then, a resist pattern obtained by developing the wafer is used as an on-wafer pattern, and this on-wafer pattern is measured by an SEM (Scanning Electron Microscope) or the like. This measurement result becomes a pattern on the wafer.

  The on-wafer pattern may be a post-etch pattern. The post-etching pattern is a pattern after the wafer is etched from above the resist pattern. In this case, for example, the pattern shape of the post-etching pattern is calculated using a processing simulation such as an etching simulation. In addition, etching may be performed on a resist pattern obtained by a transfer experiment on a wafer to obtain an on-wafer pattern after etching.

  As explained in FIG. 6 and FIG. 7, the pattern shape that may not satisfy the circuit characteristics is corrected, and the pattern whose deformation does not affect the circuit characteristics is included in the specifications, so the product yield is improved. can do. In addition, when the mask used in the transfer experiment is within the specification, it can be used for manufacturing a semiconductor device without being discarded as a mask out of the reference, so that mask discard can be reduced.

  In the present embodiment, the mask pattern is corrected so as to satisfy the relative information. However, the process conditions such as the design layout and the illumination condition may be corrected so as to satisfy the relative information. In this case, the correction unit 42 calculates the correction amount of the design layout, the correction amount of the process condition, and the like.

  Process conditions to be optimized are, for example, optical proximity correction, lithography compliance check, and the like. Process conditions to be optimized include illumination shape, illumination distribution, NA, polarization state, dynamic focus setting, mask type, exposure amount, aberration, resist type, resist film thickness, PEB (Post Exposure Bake), and development conditions. It may be.

  As described above, according to the second embodiment, the pattern on the wafer is determined based on the relative information, and in the case of determination NG, the mask pattern is corrected based on the relative information. On the other hand, it is possible to form a pattern on the wafer according to the design intention. For this reason, variation in the shape of the pattern on the wafer is reduced, a circuit having desired electrical characteristics can be formed, and the product yield is improved. Therefore, it becomes possible to manufacture a semiconductor device with high yield and low cost.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, the mask pattern creating apparatus 1B sets an exposure dose map so that the on-wafer pattern satisfies relative information. Therefore, the relative information used in the present embodiment is information relating to restrictions between patterns on the wafer.

  FIG. 8 is a flowchart showing a processing procedure of a dose map creation process based on relative information. After the design layout is created (step S10), a length measurement location such as a pattern dimension is selected from the design layout (step S20). This selection may be performed using a predetermined program or according to an instruction from the user. For example, a design pattern having a predetermined width is selected.

  Thereafter, the mask pattern creation unit 14B creates a mask pattern using the design layout, and the determination unit 41 measures the length of the created mask pattern (step S30). Then, the determination unit 41 calculates a dimensional deviation amount distribution of the mask pattern dimension (step S40). Further, the determination unit 41 calculates a dimensional deviation amount distribution of the pattern size on the wafer in consideration of MEF (Mask Error Factors) and the like (step S50).

  Then, the correction unit 42 sets the exposure dose distribution (dose map) based on the relative information (step S60). For example, the dose map is set so that the pattern is thickened or thinned with respect to the pattern position where the possibility of electrical failure is higher than a predetermined value. Thereby, the exposure dose is optimized using the dose mapping method in exposure. Specifically, dose variation in the slit direction on the exposure surface and dose variation in the scan direction are measured, and exposure is performed by mapping the optimum dose for each location (step S70).

  Conventionally, an exposure dose is determined by calculating a dose shift based on a mask pattern dimension distribution and a wafer pattern dimension distribution. In this way, the dose is determined without considering the important points in the circuit and the places where symmetry is required, so there is a high possibility that the electrical characteristic margin will be insufficient or the device characteristics will be defective. It was. Therefore, in the present embodiment, the exposure dose is mapped in consideration of a circuit-important place and a place where symmetry is required. At this time, the dose is adjusted in the direction of improving the symmetry. As a result, the symmetry of the pattern on the wafer is improved, so that the performance and yield can be improved and the chip cost can be reduced.

  Next, the hardware configuration of the mask pattern creating apparatuses 1A and 1B will be described. Since the mask pattern creating apparatuses 1A and 1B have the same hardware configuration, the hardware configuration of the mask pattern creating apparatus 1A will be described here.

  FIG. 9 is a diagram illustrating a hardware configuration of the mask pattern creating apparatus. The mask pattern creating apparatus 1A includes a CPU (Central Processing Unit) 91, a ROM (Read Only Memory) 92, a RAM (Random Access Memory) 93, a display unit 94, and an input unit 95. In the mask pattern creating apparatus 1A, the CPU 91, the ROM 92, the RAM 93, the display unit 94, and the input unit 95 are connected via a bus line.

  The CPU 91 determines a pattern using a mask pattern creation program 97 which is a computer program. The display unit 94 is a display device such as a liquid crystal monitor, and displays a design pattern, constraint conditions, relative information, a mask pattern, and the like based on an instruction from the CPU 91. The input unit 95 includes a mouse and a keyboard, and inputs instruction information (such as parameters necessary for creating a mask pattern) externally input from the user. The instruction information input to the input unit 95 is sent to the CPU 91.

  The mask pattern creation program 97 is stored in the ROM 92 and is loaded into the RAM 93 via the bus line. FIG. 9 shows a state in which the mask pattern creation program 97 is loaded into the RAM 93.

  The CPU 91 executes a mask pattern creation program 97 loaded in the RAM 93. Specifically, in the mask pattern creation device 1A, the CPU 91 reads the mask pattern creation program 97 from the ROM 92 and expands it in the program storage area in the RAM 93 in accordance with an instruction input from the input unit 95 by the user, and performs various processes. Execute. The CPU 91 temporarily stores various data generated during the various processes in a data storage area formed in the RAM 93.

  The mask pattern creation program 97 executed by the mask pattern creation device 1A has a module configuration including a mask pattern creation unit 14A, and these are loaded on the main storage device and generated on the main storage device. . The mask pattern creation program 97 executed by the mask pattern creation device 1B has a module configuration including a mask pattern creation unit 14B, a determination unit 41, and a correction unit 42.

  As described above, according to the third embodiment, since the exposure dose map is set so that the on-wafer pattern satisfies the relative information, the on-wafer pattern corresponding to the design intention is formed for the design intended pattern group. It becomes possible to do. For this reason, variation in the shape of the pattern on the wafer is reduced, a circuit having desired electrical characteristics can be formed, and the product yield is improved. Therefore, it becomes possible to manufacture a semiconductor device with high yield and low cost.

  As described above, according to the first to third embodiments, it is possible to create a mask pattern capable of manufacturing a semiconductor device with high yield and low cost.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1A, 1B ... Mask pattern production apparatus, 3 ... Relative information production apparatus, 5 ... Restriction conditions, 14A, 14B ... Mask pattern production part, 41 ... Determination part, 42 ... Correction part, 100A, 100B ... Mask pattern production system, A1 ˜H1... Design pattern, A3 to H3. Mask pattern, P1, P2, P4 to P7.

Claims (6)

  When creating a mask pattern according to the on-substrate pattern so that a pattern on the substrate according to the design pattern can be formed, a mask corresponding to the design pattern based on a relative relationship that needs to be satisfied between the design patterns A pattern generation method comprising: a mask pattern generation step of generating the mask pattern so that patterns satisfy the relative relationship. A mask pattern creating step for creating a mask pattern according to the pattern on the substrate so that a pattern on the substrate according to the design pattern can be formed;
An on-substrate pattern deriving step for deriving the on-substrate pattern using the mask pattern;
Based on the derived on-substrate pattern and the relative relationship that needs to be satisfied between the design patterns, the mask pattern or the design pattern is set so that the corresponding on-substrate pattern between the mask patterns satisfies the relative relationship. A pattern correction step to be corrected;
A pattern creating method characterized by comprising:   The relative relationship includes symmetry between the design patterns, identity between the design patterns, length between the design patterns, shape between the design patterns, number of vias between the design patterns, and bending between the design patterns. The pattern creating method according to claim 1, wherein the pattern creating method includes at least one of numbers. When creating a mask pattern according to the on-substrate pattern so that a pattern on the substrate according to the design pattern can be formed, a mask corresponding to the design pattern based on a relative relationship that needs to be satisfied between the design patterns A mask pattern creating step for creating the mask pattern so that the pattern satisfies the relative relationship;
A mask production step of producing a mask using the created mask pattern;
A pattern forming step of forming a pattern on the substrate on the substrate using the produced mask;
A method for manufacturing a semiconductor device, comprising: A mask pattern creating step for creating a mask pattern according to the pattern on the substrate so that a pattern on the substrate according to the design pattern can be formed;
An on-substrate pattern deriving step for deriving the on-substrate pattern using the mask pattern;
Based on the derived on-substrate pattern and the relative relationship that needs to be satisfied between the design patterns, the process condition correction that corrects the process condition so that the corresponding pattern on the substrate between the mask patterns satisfies the relative relationship Steps,
Forming a pattern on the substrate on the substrate using the modified process conditions; and
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the process condition is an illumination shape or an exposure dose distribution.

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