JP2012198127A - Inspection circuit for semiconductor device, inspection method for semiconductor device, and semiconductor device inspected by the inspection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection circuit for a semiconductor device that can select the semiconductor device at low cost, an inspection method for the semiconductor device, and the semiconductor device inspected by the inspection method.SOLUTION: An inspection circuit 50 for a semiconductor device inspects a semiconductor device 100 which has an insulation gate G, a first terminal S, and a second terminal D, and controls a current flowing between the first terminal and second terminal according to a voltage between the insulation gate and first terminal. The inspection circuit for the semiconductor device includes: a control part 10 which short-circuits the first terminal and insulation gate while applying a voltage between the first terminal and second terminal after applying a voltage to the insulation gate, first terminal, and second terminal so that the semiconductor device turns on; a measurement part 20 which measures a voltage or current between the first terminal and second terminal; and a determination part 30 which determines whether the semiconductor device is nondefective based upon the voltage or current measured by the measurement part after the first terminal and insulation gate are short-circuited.

Description

  The present invention relates to a semiconductor device inspection circuit, a semiconductor device inspection method, and a semiconductor device inspected by the inspection method.

  As a high-voltage MOSFET, a MOSFET composed of a plurality of cell transistors is known. In this MOSFET, each cell transistor has a gate made of polysilicon. The plurality of polysilicons are arranged in stripes, and their ends are connected to the gate fingers. With such a structure, the plurality of polysilicons constitute the gate electrode (insulated gate) of the MOSFET.

  By the way, in the manufacturing process of the MOSFET, when the resistance value of a part of the polysilicon constituting the gate electrode is increased due to process variations when forming the polysilicon, the MOSFET gate resistance is increased. There is. Such a MOSFET having a high gate resistance is used as a switching element such as an inverter, and when the switching operation is performed, the drain current is reduced under the condition that the gate-source voltage is substantially zero and the drain-source voltage is applied. It will flow. Hereinafter, the drain current flowing under this condition is referred to as an ID tail current. When this ID tail current flows, there is a problem that the temperature rises and the MOSFET is thermally runaway.

  Therefore, it is necessary to select such a MOSFET having a high gate resistance and an ID tail current in an inspection process or the like. As the selection method, for example, there is a method in which a gate resistance is measured using an LCR meter, and a MOSFET having a gate resistance of a certain value or more is regarded as defective. Further, for example, there is a method in which ΔVth is measured using a ΔVth measuring device, and a MOSFET having ΔVth of a certain value or more is determined to be defective. ΔVth is the difference between the threshold voltage Vth of the MOSFET before and after applying a predetermined negative voltage between the gate and the source. There is a possibility that the ID tail current flows in the MOSFET in which ΔVth is a certain value or more.

  As the LCR meter, for example, one described in Patent Document 1 is known.

JP-A-9-243684

However, there is a problem that the above-described LCR meter and ΔVth measuring device are expensive.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device inspection circuit capable of selecting semiconductor devices at low cost, a semiconductor device inspection method, and a semiconductor device inspected by the inspection method.

An inspection circuit for a semiconductor device according to an embodiment of one aspect of the present invention includes:
A semiconductor having an insulated gate, a first terminal, and a second terminal, and controlling a current flowing between the first terminal and the second terminal according to a voltage between the insulated gate and the first terminal A device inspection circuit,
In a state where a voltage is applied between the first terminal and the second terminal after applying a voltage to the insulated gate, the first terminal, and the second terminal so that the semiconductor device is turned on. A controller for short-circuiting the first terminal and the insulated gate;
A measuring unit for measuring a voltage or current between the first terminal and the second terminal;
And a determination unit that determines whether the semiconductor device is good or not based on a voltage or current measured by the measurement unit after short-circuiting the first terminal and the insulated gate.

In the inspection circuit of the semiconductor device,
The determination unit may determine that the semiconductor device is defective when the voltage measured by the measurement unit is lower than a voltage determination value or when the current measured by the measurement unit is larger than a current determination value. .

In the inspection circuit of the semiconductor device,
The controller is
A first switch connected between a first power source and the first terminal;
A second switch connected between a second power source and the insulated gate;
A third switch connected between a third power source and the second terminal;
A fourth switch for switching whether to short-circuit the insulated gate and the first terminal;
A switch control unit for controlling the first to fourth switches,
The switch control unit turns on the semiconductor device by turning on the first to third switches and turning off the fourth switch, turns off the second switch, and turns on the fourth switch. The first terminal and the insulated gate may be short-circuited by controlling the switch to be on.

In the inspection circuit of the semiconductor device,
The controller is
A first resistor connected in series to the second switch;
And a second resistor connected in series to the third switch.

In the inspection circuit of the semiconductor device,
The switch control unit controls the fourth switch to off after controlling the fourth switch for a predetermined short-circuit time,
The short-circuiting time may be set so that a voltage of the first terminal and the insulated gate after the fourth switch is controlled to be off is equal.

In the inspection circuit of the semiconductor device,
The determination unit may determine pass / fail of the semiconductor device based on a voltage or current measured by the measurement unit after the fourth switch is controlled to be turned off.

In the inspection circuit of the semiconductor device,
The semiconductor device may be a MOSFET, the first terminal may be a source, and the second terminal may be a drain.

In the inspection circuit of the semiconductor device,
The insulated gate of the MOSFET may be composed of a plurality of gates arranged in stripes.

In the inspection circuit of the semiconductor device,
The semiconductor device may be an insulated gate bipolar transistor, the first terminal may be an emitter, and the second terminal may be a collector.

A method for inspecting a semiconductor device according to an embodiment of one aspect of the present invention includes:
A semiconductor having an insulated gate, a first terminal, and a second terminal, and controlling a current flowing between the first terminal and the second terminal according to a voltage between the insulated gate and the first terminal A device inspection method,
A first step of applying a voltage to the insulated gate, the first terminal, and the second terminal so that the semiconductor device is turned on;
After the first step, a second step of short-circuiting the first terminal and the insulated gate with a voltage applied between the first terminal and the second terminal;
After the second step, a third step of measuring a voltage or current between the first terminal and the second terminal;
And a fourth step of determining pass / fail of the semiconductor device based on the voltage or current measured in the third step.

In the inspection method of the semiconductor device,
In the fourth step, when the measured voltage is lower than the voltage determination value, or when the measured current is larger than the current determination value, the semiconductor device may be determined as defective.

In the inspection method of the semiconductor device,
A voltage may be applied to the insulated gate via a first resistor, and a voltage may be applied to the second terminal via a second resistor.

In the inspection method of the semiconductor device,
In the second step, the first terminal and the insulated gate are released after being short-circuited for a predetermined short-circuit time,
The short-circuiting time may be set so that the voltages of the first terminal and the insulated gate after being released are equal.

In the inspection method of the semiconductor device,
The semiconductor device may be a MOSFET, the first terminal may be a source, and the second terminal may be a drain.

In the inspection method of the semiconductor device,
The insulated gate of the MOSFET may be composed of a plurality of gates arranged in stripes.

In the inspection method of the semiconductor device,
The semiconductor device may be an insulated gate bipolar transistor, the first terminal may be an emitter, and the second terminal may be a collector.

  A semiconductor device according to an embodiment of the present invention is a semiconductor device inspected by the semiconductor device inspection method.

  According to the inspection circuit for a semiconductor device according to one aspect of the present invention, after applying a voltage to the insulated gate, the first terminal, and the second terminal so that the semiconductor device is turned on, the first terminal and the second terminal The first terminal and the insulated gate are short-circuited in a state where a voltage is applied between and the semiconductor device, and then the quality of the semiconductor device is determined based on the voltage or current measured by the measurement unit. In this case, after the first terminal and the insulated gate are short-circuited, a current flows for a longer time in the semiconductor device having a high gate resistance than the semiconductor device having a low gate resistance. Therefore, a semiconductor device having a high gate resistance can be selected based on the measured voltage or current. Thus, since the circuit configuration and control are simple, semiconductor devices can be selected at low cost.

1 is a circuit diagram of an inspection circuit for a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a timing chart of the semiconductor device inspection circuit according to the first embodiment of the present invention. FIG. 3 is a plan view of a part of the N-type MOSFET. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a waveform diagram showing signals at respective terminals of an N-type MOSFET used as a switching element of the inverter circuit.

  Prior to the description of the embodiments of the present invention, an N-type MOSFET 100 as an inspection object will be described with reference to FIGS.

  FIG. 3 is a plan view of a part of the N-type MOSFET 100. The N-type MOSFET 100 is a high-voltage MOSFET and includes a plurality of cell transistors 101 arranged in a stripe pattern. Two adjacent cell transistors 101 and 101 share one gate 102 made of polysilicon. The plurality of gates 102 are arranged in stripes, and both ends in the longitudinal direction thereof are connected to the corresponding gate fingers 103. With such a structure, a plurality of gates 102 connected to each other constitute an insulated gate G of the N-type MOSFET 100.

  4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 4A shows the structure of two cell transistors 101 and 101 having a low gate resistance in a good N-type MOSFET 100. FIG. 4B shows the structure of two cell transistors 101A and 101A having a high gate resistance in a defective N-type MOSFET 100. FIG. The structure of the gate 102 is different between a non-defective product and a defective product.

  As shown in FIG. 4A, a non-defective N-type MOSFET 100 includes an N-type gate 102, an N-type region 103 connected to the drain, P-type wells 104 and 104 as channel regions, and an N-type. Source regions 105, 105 and a gate oxide film 106.

  Two wells 104 and 104 are formed in the surface region of the N-type region 103 so as to be separated by a predetermined distance. A source region 105 is formed in the surface region of each well 104, 104. Above the well 104, the N-type region 103, and the well 104 sandwiched between the two source regions 105, 105, a gate oxide film 106 extends from the end of one source region 105 to the end of the other source region 105. Is formed. A gate 102 is formed on the gate oxide film 106. The gate 102 is formed by ion-implanting phosphorus into P-type polysilicon to form a low-resistance N-type polysilicon.

  As shown in FIG. 4B, in the defective N-type MOSFET 100, the structure of the gate 102A is different from that of the gate 102 in FIG. Other structures are the same as those in FIG. That is, due to process variations and the like, the gate 102A has an N-type region 102a at the top and a P-type region 102b at the bottom. With this structure, the gate resistance of the cell transistor 101A is higher than that of the cell transistor 101. This structure is considered to be formed due to insufficient diffusion of phosphorus into P-type polysilicon in the manufacturing process.

  In the N-type MOSFET 100 having at least a part of the cell transistor 101A having a high gate resistance, the gate resistance of the insulated gate G is increased.

  FIG. 5 is a waveform diagram showing signals at respective terminals of the N-type MOSFET 100 used as a switching element of the inverter circuit.

  FIG. 5A is a diagram showing temporal changes in the gate-source voltage VGS, the drain-source voltage VDS, and the drain current ID in the non-defective N-type MOSFET 100. FIG. 5B is an enlarged view of a part of FIG. In the non-defective N-type MOSFET 100, after the gate-source voltage VGS becomes substantially 0 V and the drain-source voltage VDS becomes 400 V at time ta, the drain current ID immediately approaches zero.

  FIG. 5C is a diagram showing temporal changes in the gate-source voltage VGS, the drain-source voltage VDS, and the drain current ID in the defective N-type MOSFET 100. FIG. 5D is an enlarged view of a part of FIG. FIG. 5C is the same scale as FIG. 5A, and FIG. 5D is the same scale as FIG. 5B. In the defective N-type MOSFET 100, after the gate-source voltage VGS becomes substantially 0 V and the drain-source voltage VDS becomes 400 V at the time ta, the drain current ID flows (ID tail current).

  As a result of repeating the experiment based on such a phenomenon, the inventors independently learned that the following characteristic difference exists between a non-defective product and a defective product when observing the electrical characteristics of the N-type MOSFET 100 alone. .

That is, as compared with the non-defective N-type MOSFET 100, the defective N-type MOSFET 100 accumulates in the cell transistor 101A having a high gate resistance when the insulated gate G and the source S are short-circuited and turned off from the on-state. Since the charge between the gate and the source is discharged to another good cell transistor 101 having a low gate resistance, the time until the transistor is turned off (the drain current ID becomes zero) is delayed and the drain-source voltage is reduced. I learned independently that there is a difference in changes in VDS.
The present inventor has made the present invention based on the above-mentioned unique knowledge.

  Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram of a test circuit 50 for a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 1, the inspection circuit 50 includes a control unit 10, a measurement unit 20, and a determination unit 30.

  In the present embodiment, the semiconductor device to be inspected by the inspection circuit 50 includes an insulated gate G, a source (first terminal) S, and a drain (second terminal) D. The insulated gate G and the source S This is an N-type MOSFET 100 that controls the current flowing between the source S and the drain D according to the voltage between them. The N-type MOSFET 100 may be packaged or not packaged. The insulated gate G, source S, and drain D of the N-type MOSFET 100 are connected to the gate connection terminal GT, source connection terminal ST, and drain connection terminal DT of the inspection circuit 50, respectively.

  The control unit 10 controls the voltage applied to each terminal of the N-type MOSFET 100 via the gate connection terminal GT, the source connection terminal ST, and the drain connection terminal DT.

  The measuring unit 20 measures the drain-source voltage VDS between the source S and the drain D of the N-type MOSFET 100.

  The determination unit 30 determines pass / fail of the MOSFET 100 based on the drain-source voltage VDS measured by the measurement unit 20 at a predetermined timing.

  The control unit 10 includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a first resistor R1, a second resistor R2, and a switch control unit. 11. In this embodiment, an N-type MOSFET is used as the fourth switch SW4.

  The first switch SW1 is connected between the first power supply P1 (for example, voltage 0V) and the source connection terminal ST (that is, the source S of the N-type MOSFET 100).

  The first resistor R1, the second switch SW2, and the fifth switch SW5 are arranged in this order between the second power source P2 (for example, voltage 15V) and the gate connection terminal GT (that is, the insulating gate G of the N-type MOSFET 100). They are connected in series.

  The second resistor R2 and the third switch SW3 are connected in series in this order between the third power supply P3 (for example, voltage 10V) and the drain connection terminal DT (that is, the drain D of the N-type MOSFET 100).

  The fourth switch SW4 has a drain connected to a connection point between the second switch SW2 and the fifth switch SW5, and a source connected to the first power supply P1. The fourth switch SW4 switches whether to short-circuit the insulated gate G and the source S of the N-type MOSFET 100.

  The switch controller 11 controls the first switch SW1 to the fifth switch SW5 to be on or off. The first switch SW1 and the third switch SW3 are controlled simultaneously. The switch control unit 11 supplies a short circuit signal to the gate of the fourth switch SW4.

  Next, the operation of the inspection circuit 50 (that is, the semiconductor device inspection method) will be described with reference to FIG.

  FIG. 2 is a timing chart of the semiconductor device inspection circuit 50 according to the first embodiment of the present invention. The voltage and time exemplified below are appropriate values in the present embodiment, and may be set to other appropriate values when the type of the N-type MOSFET 100 is changed.

  In the initial state, the first to fifth switches SW1 to SW5 are off. Therefore, the gate-source voltage VGS of the N-type MOSFET 100 is about 0V. Therefore, the N-type MOSFET 100 is in an off state.

  First, at time t1, the control unit 10 applies a voltage to the insulated gate G, the source S, and the drain D so that the N-type MOSFET 100 is turned on. That is, the switch control unit 11 turns on the N-type MOSFET 100 by controlling the first to third switches SW1 to SW3 and the fifth switch SW5 and turning off the fourth switch SW4. At this time, the gate-source voltage VGS is about 15V. Further, when the drain current ID flows, the drain-source voltage VDS becomes about 1 V due to the voltage drop of the second resistor R2. At this time, if the drain-source voltage VDS is higher than a predetermined voltage, the N-type MOSFET 100 is determined to be defective and the following measurement is not performed.

  Thereafter, at time t <b> 2, the control unit 10 short-circuits the source S and the insulated gate G in a state where a voltage is applied between the source S and the drain D. That is, the switch control unit 11 controls the second switch SW2 to be turned off, and controls the fourth switch SW4 to be turned on by turning on the short circuit signal. As a result, the switch control unit 11 short-circuits the source S and the insulated gate G via the first switch SW1, the fourth switch SW4, and the fifth switch SW5. As a result, the gate-source voltage VGS becomes about 0V. As a result, since the drain current ID decreases after time t2, the drain-source voltage VDS increases from 1V.

  Next, at time t3, the switch control unit 11 turns off the short circuit signal. That is, the switch control unit 11 controls the fourth switch SW4 to be turned off after being controlled to be turned on for a predetermined short-circuit time (time t3—time t2). The short circuit time is set so that the voltages of the source S and the insulated gate G after the fourth switch SW4 is controlled to be off (time t3) are substantially equal. The short circuit time is, for example, about 1.2 μs.

  Next, at time t4 (after time t3 from time t3), the determination unit 30 determines the N-type based on the drain-source voltage VDS measured by the measurement unit 20 after the fourth switch SW4 is controlled to be turned off. The quality of the MOSFET 100 is determined. Specifically, when the drain-source voltage VDS measured by the measurement unit 20 is lower than the voltage determination value LL (characteristic B), the determination unit 30 determines that the N-type MOSFET 100 is defective and determines the drain-source voltage. When VDS is equal to or higher than the voltage determination value LL (characteristic A), it is determined to be good.

  As described above, according to the present embodiment, after applying voltage to the insulating gate G, the source S, and the drain D so that the N-type MOSFET 100 is turned on (time t1), the source S and the drain D The source S and the insulated gate G are short-circuited with a voltage applied between them (time t2). Then, the quality of the N-type MOSFET 100 is determined based on the drain / source voltage VDS measured by the measuring unit 20 thereafter (time t4). In this way, after the source S and the insulated gate G are short-circuited, the drain current of the N-type MOSFET 100 (defect) having a high gate resistance of the insulated gate G is longer than that of the N-type MOSFET 100 (good) having a low gate resistance. Flowing. Therefore, the N-type MOSFET 100 having a high gate resistance can be selected based on the measured drain-source voltage VDS.

  As described above, the inspection circuit 50 according to the present embodiment can easily select the N-type MOSFET 100 at a low cost because the circuit configuration and control are simple.

  As mentioned above, although the Example of this invention was explained in full detail, a concrete structure is not limited to the said Example, A various deformation | transformation can be implemented in the range which does not deviate from the summary of this invention. Below, an example of a deformation | transformation is demonstrated.

(Inspection target)
In the first embodiment, an example of inspecting the N-type MOSFET 100 having the structure shown in FIGS. 3 and 4 has been described. However, the structure of the N-type MOSFET 100 is not limited to this. Further, a P-type MOSFET can be inspected instead of the N-type MOSFET 100.

  Further, in place of the N-type MOSFET 100, an insulated gate, an emitter (first terminal), and a collector (second terminal) are provided, and between the emitter and the collector according to the voltage between the insulated gate and the emitter. It is also possible to inspect an insulated gate bipolar transistor that controls the current flowing through the transistor.

  In other words, the inspection circuit 50 can be effectively selected as long as it is a semiconductor device in which an ID tail current flows when switching operation is performed using a switching element such as an inverter due to the high gate resistance of the insulated gate.

(Measurement part)
The measurement unit 20 may measure the drain current ID between the source S and the drain D of the N-type MOSFET 100. In this case, the determination unit 30 may determine that the N-type MOSFET 100 is defective when the current measured by the measurement unit 20 is larger than the current determination value at the same timing as in the first embodiment.

DESCRIPTION OF SYMBOLS 10 Control part 11 Switch control part SW1 1st switch SW2 2nd switch SW3 3rd switch SW4 4th switch SW5 5th switch R1 1st resistance R2 2nd resistance 20 Measurement part 30 Determination part 50 Test circuit 100 N-type MOSFET

Claims (17)

A semiconductor having an insulated gate, a first terminal, and a second terminal, and controlling a current flowing between the first terminal and the second terminal according to a voltage between the insulated gate and the first terminal A device inspection circuit,
In a state where a voltage is applied between the first terminal and the second terminal after applying a voltage to the insulated gate, the first terminal, and the second terminal so that the semiconductor device is turned on. A controller for short-circuiting the first terminal and the insulated gate;
A measuring unit for measuring a voltage or current between the first terminal and the second terminal;
A determination unit for determining whether or not the semiconductor device is good based on a voltage or a current measured by the measurement unit after the first terminal and the insulated gate are short-circuited. . The determination unit determines that the semiconductor device is defective when a voltage measured by the measurement unit is lower than a voltage determination value or when a current measured by the measurement unit is larger than a current determination value. An inspection circuit for a semiconductor device according to claim 1. The controller is
A first switch connected between a first power source and the first terminal;
A second switch connected between a second power source and the insulated gate;
A third switch connected between a third power source and the second terminal;
A fourth switch for switching whether to short-circuit the insulated gate and the first terminal;
A switch control unit for controlling the first to fourth switches,
The switch control unit turns on the semiconductor device by turning on the first to third switches and turning off the fourth switch, turns off the second switch, and turns on the fourth switch. The semiconductor device inspection circuit according to claim 1, wherein the first terminal and the insulated gate are short-circuited by controlling a switch to be turned on. The controller is
A first resistor connected in series to the second switch;
The semiconductor device inspection circuit according to claim 3, further comprising: a second resistor connected in series to the third switch. The switch control unit controls the fourth switch to off after controlling the fourth switch for a predetermined short-circuit time,
The short circuit time is set so that the voltage of the first terminal and the insulated gate after the fourth switch is controlled to be off is equal to each other. An inspection circuit for a semiconductor device according to claim 1. The semiconductor device according to claim 5, wherein the determination unit determines whether or not the semiconductor device is good based on a voltage or a current measured by the measurement unit after the fourth switch is controlled to be turned off. Device inspection circuit. The semiconductor device inspection circuit according to claim 1, wherein the semiconductor device is a MOSFET, the first terminal is a source, and the second terminal is a drain. The semiconductor device inspection circuit according to claim 7, wherein the insulated gate of the MOSFET includes a plurality of gates arranged in a stripe pattern. 7. The semiconductor device inspection according to claim 1, wherein the semiconductor device is an insulated gate bipolar transistor, the first terminal is an emitter, and the second terminal is a collector. circuit. A semiconductor having an insulated gate, a first terminal, and a second terminal, and controlling a current flowing between the first terminal and the second terminal according to a voltage between the insulated gate and the first terminal A device inspection method,
A first step of applying a voltage to the insulated gate, the first terminal, and the second terminal so that the semiconductor device is turned on;
After the first step, a second step of short-circuiting the first terminal and the insulated gate with a voltage applied between the first terminal and the second terminal;
After the second step, a third step of measuring a voltage or current between the first terminal and the second terminal;
And a fourth step of determining the quality of the semiconductor device based on the voltage or current measured in the third step. A method for inspecting a semiconductor device, comprising: The said 4th step WHEREIN: When the measured voltage is lower than a voltage determination value, or when the measured electric current is larger than a current determination value, the said semiconductor device is determined to be a defect. The inspection method of the semiconductor device as described. The method for inspecting a semiconductor device according to claim 10, wherein a voltage is applied to the insulated gate through a first resistor, and a voltage is applied to the second terminal through a second resistor. In the second step, the first terminal and the insulated gate are released after being short-circuited for a predetermined short-circuit time,
13. The semiconductor device according to claim 10, wherein the short-circuiting time is set so that voltages of the first terminal and the insulated gate after being released are equal to each other. Inspection method. The semiconductor device inspection method according to claim 10, wherein the semiconductor device is a MOSFET, the first terminal is a source, and the second terminal is a drain. The semiconductor device inspection method according to claim 14, wherein the insulated gate of the MOSFET includes a plurality of gates arranged in a stripe pattern. The semiconductor device inspection according to claim 10, wherein the semiconductor device is an insulated gate bipolar transistor, the first terminal is an emitter, and the second terminal is a collector. Method.   A semiconductor device inspected by the semiconductor device inspection method according to claim 10.

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