JP2012195794A - Encoded signal reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the total delay time from acquisition of a signal to output thereof in an encoded signal transmission/reception system via a network.SOLUTION: A system comprises means for synchronizing a reference time between a transmission side and a reception side, thereafter calculating, on the reception side, the phase of a synchronization signal on the transmission side for shortening a time from acquisition of a signal to output of the signal, and adjusting the phase of a reference synchronization signal.

Description

  The present invention relates to an encoded signal receiving apparatus. For example, the present invention relates to a technique for network transmission using a technique for compressing and expanding video and audio signals.

  As background art, there exists Unexamined-Japanese-Patent No. 2005-286453 (patent document 1), for example. In this publication, “[Problem] In video shooting by a plurality of monitoring cameras connected to each other via a network, video shooting timings among all the monitoring cameras are synchronized without using wiring other than the network. The network monitoring camera includes synchronization information communication means for transmitting and receiving synchronization information serving as a reference for photographing timing via the network, and a counter reading value for adjusting a reading value of a synchronization reference counter built in the monitoring camera based on the synchronization information. An adjustment circuit, a synchronization signal generation circuit that generates a horizontal / vertical synchronization signal based on the read value of the synchronization reference counter, and a video image in synchronization with the horizontal / vertical synchronization signal output from the synchronization signal generation circuit It has a camera module "(see summary).

JP 2005-286453 A

  There is a technology for compressing and transmitting video and audio signals to output high-quality and high-quality data within the limitation of the transmission band when the image and audio signals are communicated with other devices via a network. There is a camera system via a network using these technologies. For example, Patent Document 1 discloses a technique for synchronizing imaging timing between cameras in a network camera in which a plurality of cameras are connected to a network.

  However, in a system in which an audio / video system is communicated via a network, in an actual system, not only the time required for compression / decompression, but also an image or audio signal is input by an image sensor or a microphone, and then a display device or There is a demand for minimizing the total delay time until output from a speaker. In addition, in a system in which the video or audio signal decoded on the receiver side is transferred to the subsequent video object recognition and audio recognition system and other control is performed, the recognition system is determined based on the video or audio signal capture timing on the transmitter side. It is necessary that the delay time until is constant.

  In the above-mentioned Patent Document 1, there is no description of a specific technique for making the delay time from the transmitter side to the receiver constant and shortening in the system as described above.

  An object of the present invention is to improve the usability of an encoded signal receiving apparatus. For example, the network system which solves the said subject is provided at low cost. For example, a network camera that transmits a video / audio signal to another device via a network is connected to the network, and a single receiver receives the video / audio signal from the network group and captures the video / audio signal of each camera. Is to build a low-cost system that reduces the time until the video output timing on the receiver side, and improves its usability.

  The above object can be achieved by the invention described in the claims.

  According to the present invention, the usability of the encoded signal receiving apparatus is improved. For example, in a system that communicates video and audio systems via a network, the total time from when video is input by the image sensor to when it is output by the display device on the receiving side is made constant, and the delay is reduced within system constraints. Is possible.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

FIG. 3 is a diagram illustrating a block configuration of a transmitter according to the first embodiment. FIG. 3 is a diagram illustrating a protocol for performing time synchronization in the first embodiment. FIG. 6 is a diagram for explaining the timing of a synchronization phase adjustment packet in the first embodiment. The figure explaining the transition of the encoding signal storage amount of the transmitter in Example 1. FIG. FIG. 3 is a diagram illustrating a block configuration of a receiver according to the first embodiment. FIG. 3 is a diagram for explaining the transition of the encoded signal storage amount of the receiver in the first embodiment. FIG. 3 is a diagram illustrating control timing of each block in the first embodiment. FIG. 3 is a diagram illustrating an operation flow of a transmitter according to the first embodiment. FIG. 3 is a diagram illustrating an operation flow of the receiver in the first embodiment. 1 is a diagram of a network camera system in Embodiment 1. FIG.

  FIG. 1 shows a block diagram of Embodiment 1 of the present invention. Hereinafter, Example 1 will be described with reference to FIG. In this embodiment, a video image of 1920 × 1080 pixels captured at 30 frames / sec. H.264 / AVC (ISO / IEC14496-10) standard video encoding, 12-bit audio data with a sampling rate of 48 KHz is subjected to MPEG1 Layer II audio encoding processing, packet-multiplexed, and transmitted over the network Is a network camera. In the network, it is assumed that, for example, a method defined in the IEEE 802.3 standard, which is a data link protocol, is used as a protocol to be used. In the present embodiment, it is assumed that speech is subjected to conventional PCM sampling and encoded transmission by MPEG1LayerII is performed, and only the block configuration is shown in the drawing.

  In the network transmission / reception unit 29 in FIG. 1, after starting the system, a communication link is established with a receiver connected to a network (not shown) connected to the terminal 10 according to a protocol conforming to the IEEE 802.3 standard. An IEEE 802.3 input packet sequence is received as, for example, a LAN packet conforming to the IEEE 802.3 standard. IEEE 1588: IEEE 1588-2002 Precise Clock Synchronization Protocol for Networked Measurement and Control Systems A method according to PTP (Precision Time Protocol) may be used. In the present embodiment, a time synchronization system will be described assuming a simplified protocol.

  In this system, the receiver side is defined as a server for time synchronization, and the transmitter side is defined as a client side that matches the time on the server side.

FIG. 2 shows a packet transmission / reception method performed for time synchronization between the server side and the client side.
In order to achieve time synchronization, the server side transmits an initial packet for obtaining synchronization information at the T1 time point to the transmitter side. This packet is called a Sync packet, and the network transmission / reception unit 29 in FIG. 1 that receives this packet transmits the packet to the packet separation unit 11. Further, the packet separation unit 11 determines that the packet is a Sync packet from the identifier, and sends it to the time information extraction unit 12 at the subsequent stage. The time information extraction unit 12 obtains the packet transmission time (T1) on the server side described in the packet and the time (T2) when the packet arrived at the time information extraction unit 12 from the reference time counter 14 in the transmitter. The reference time counter counts up the reference time using the system clock generated in the reference clock recovery 13 as will be described later. Next, the delay information generation unit 15 generates a packet (DelayReq) to be transmitted from the client to the server and sends it to the network transmission / reception unit 29. The network transmitting / receiving unit 29 reads the timing (T3) at which this packet is transmitted from the reference time counter and transmits it to the receiver (server). At the same time, the information of T3 is transferred to the time information extraction unit 12. The server reads the arrival timing (T4) of the DelayReq packet, describes it in the DelayResp packet, and transmits it to the client side. The DelayResp packet that has arrived at the transmitter side (client) is transmitted to the packet separation unit 11, confirmed as a DelayResp packet, and then transmitted to the time information extraction unit 12. The time information extraction unit 12 extracts T4 information described in the DelayResp packet. In the above process, the time information extraction unit 12 can obtain time information of T1, T2, T3, and T4.

  The time difference at the time of packet transmission / reception between the server and the client is T2-T1 = Tnet + Toffset, T4-T3 = Toffset (client time−server time) between the transmission delay Tnet of the network and the reference time of both devices. Tnet-Toffset (however, the transmission delay of the network between the server and the client is assumed to be the same time for uplink and downlink), so Tnet = (T2−T1 + T4−T3) / 2, Toffset = T2−T1 It can be obtained as -Tnet.

  The time information extraction unit 12 calculates Toffset by the above calculation when the T1, T2, T3, and T4 information is obtained. Further, the time information extraction unit 12 controls to return the reference time counter 14 from the current time by Toffset.

  Similarly to the above, transmission / reception of Sync, DelayReq, and DelayResp packets is repeated a plurality of times, Toffset is calculated several times, and control information is sent to the reference clock recovery unit 13 in a direction where Toffset approaches 0. Specifically, the reference clock recovery unit 13 is configured by, for example, a VCXO (Voltage-Controlled Crystal Oscillator), and Toffset is a positive value. On the other hand, when the voltage to be supplied is lowered, and when Toffset is a negative value and the clock is to be advanced, the voltage supplied to the reference clock recovery unit 13 is increased.

  By providing this control with feedback control that changes the voltage control width according to the absolute value of Toffset, the clock sent from the reference clock recovery unit 13 to the reference time counter 14 is stabilized and converged to a frequency synchronized with the server side. It is possible to make it. In addition, the transmitter side can update the reference time counter 14 in synchronization with the receiver side.

  The network transmission / reception unit 29 transmits to the packet separation unit 11 not only a packet for time synchronization among packets received from the receiver side but also a packet including synchronization phase information. The packet separation unit 11 sends a packet including the synchronization phase information to the synchronization phase information extraction unit 16. This packet indicates the timing of the operation synchronization signal of the transmitter with reference to the reference time counter 14. For example, as shown in FIG. 3, the network transmission / reception unit 29 receives a packet 30 (hereinafter referred to as SyncPahse) including the received synchronization phase information and sends it to the synchronization phase information extraction unit 16.

  The synchronization phase information extraction unit 16 extracts a reference synchronization signal generation timing TA described in SyncPhase. TA indicates a reference time counter value at which the reference synchronization signal should be generated on the transmitter side.

  If the storage position in the packet is standardized on the transmission / reception side and the data is analyzed based on the syntax, it is possible to uniquely identify the storage position of the TA information and extract the data. The extracted timing TA is transferred to the reference synchronization signal generator 17.

  The reference synchronization signal generator 17 refers to the reference time sent from the reference time counter 14 as shown in FIG. 3, generates a reference synchronization signal 32 when the timing of TA is reached, and transmits the reference synchronization signal 32 to the sensor control unit 18. . Similarly, the reference synchronization signal 33 is generated as needed every time a packet after the subsequent SyncPhase 31 arrives. Upon receiving the reference synchronization signal, the sensor control unit 18 generates the sensor vertical synchronization signal generated by the free-run operation at a period Tms as shown in 34 and 35 in FIG. 3 at the timing of 32 reference synchronization signals. Change the generation timing of the sync signal.

  Thereafter, the period Tms is counted based on the reference clock received from the reference clock recovery 13, and a sensor vertical synchronization signal is generated every period Tms (36 to 39 in FIG. 3). Further, since the synchronization signal after the reference synchronization signal 33 is at the same timing as the vertical synchronization signal generated by the sensor control unit 18, the signal generation for each cycle Tms is continued as long as no phase shift is detected. To do.

  If it is confirmed once or several times that the phase with the sensor vertical synchronization generated by the sensor control unit 18 is the same or within a certain time range upon arrival of the reference synchronization signal, the receiver side and the transmitter Assuming that the timing of the synchronization signal assumed on the side is complete, a phase adjustment confirmation completion signal is transmitted to the system control unit 28.

  If a phase shift is found between the reference synchronization signal and the vertical synchronization signal (for example, 33 and 39), it is considered that the timing of the synchronization signal has changed due to an abnormality on the receiver side, and the system control unit 28 determines the phase shift. Notification of. As described above, even if the transmission interval timing of the information (SyncPhase) for phase adjustment is relatively longer than the generation cycle Tms of the vertical synchronization signal, the vertical synchronization signal generated in the sensor control unit 18 is once phase-adjusted. At this stage, it is possible to generate the vertical synchronization signal with high accuracy based on the reference clock and the reference time. In this respect, this system is also effective in reducing network traffic due to transmission.

  Further, it is possible to detect that the phase of the synchronization signal is shifted due to some abnormality of the system by using SyncPhase transmitted periodically, and it is possible to control error correction thereafter.

  After receiving the phase adjustment confirmation completion signal, the system control unit 28 controls the lens unit 19, the CMOS sensor 20, the digital signal processing unit 21, the video encoding unit 22, and the system Mux unit to start video encoding. As for video encoding, general digital video imaging and digital compression encoding are performed. For example, the lens unit 19 moves the lens unit for AF (AutoFocus) received from the system control unit 28, and the CMOS sensor 20 receives the light from the lens unit and amplifies the output value, and then outputs a digital signal as a digital image. The data is output to the processing unit 21. The digital signal processing unit 21 performs digital signal processing from, for example, Bayer array-shaped RAW data received from the CMOS sensor 20, converts the data into luminance and color difference signals (YUV signals), and then transfers them to the video encoding unit 22.

  The video encoding unit treats the image forces captured during each vertical synchronization as a unit as a picture and performs encoding processing. At this time, for example, an I picture (Intra Picture) using prediction in an intra frame or a P picture (Predictive Picture) is generated using only forward prediction so that the encoding delay time does not become several frame periods. . At this time, the video encoding unit 22 adjusts the encoding amount after encoding each MB (Macroblock) composed of 16 horizontal pixels × 16 vertical pixels so as to approach the bit generation amount at a constant bit rate. Specifically, the generated code amount for each MB can be controlled by adjusting the quantization step. Until the processing of several MBs is completed, the system Mux unit stores the bit stream in the internal buffer. When the predetermined number of MBs are stored, the system Mux unit stores the video stream as an MPEG2TS stream with a fixed length of 188 bytes. The TS packet is held and output. Further, the network transmission / reception unit 59 converts the packet into a MAC packet and transmits it to the receiver side via the network.

  FIG. 4 is a diagram illustrating a transition state of the stream accumulation amount of the internal buffer in the system Mux unit. In this figure, for convenience, a code obtained by encoding each MB for each MB period is instantaneously accumulated in the buffer, and a stream is output to the network at a constant throughput for each MB period.

  The output start timing of the stream in the system Mux unit is such that the code generation amount (throughput) of the bit stream fluctuates when output to the outside at a constant bit rate, and the encoded data stored in the buffer of the system Mux unit is the most Control is performed by waiting for a predetermined waiting time (91 in FIG. 4) in which the buffer of the system Mux unit is not depleted even when the time is reduced (90 timing in FIG. 4). In general, these controls monitor the actual coding amount, change the quantization step according to the transition of the buffer, thereby controlling the coding amount within a predetermined number of MBs, and reduce the throughput. It is possible to suppress the jitter range within a certain range with respect to the output bit rate. By providing the 91 minute period of FIG. 5 for the time required for convergence, a system in which the buffer of the system Mux unit is not exhausted can be realized.

  By defining this period as a specification on the transmitter side, it is possible to calculate the subsequent transmission delay on the receiver side.

  Next, the block configuration and the operation on the receiver side will be described with reference to FIG. The reference clock generation unit 51 generates a reference clock on the receiver side. This reference clock is a reference clock for time synchronization on the server side and the client side shown in FIG. 2, and is generated by a free-run operation at 51 without using other external synchronization by a crystal oscillator or the like. The

  Based on this clock, the reference time counter 52 counts the reference time on the server side. The time control packet generator 53 generates a packet (Sync) for time synchronization shown in FIG. 2 using this reference time. T1 described in the packet at the time of transmission of Sync is generated in this block. The generated (Sync) packet is multiplexed with other packets in the packet multiplexing unit 58, further modulated in the network transmission / reception unit 59, and transmitted to the transmission unit via the network connected from the network terminal 60 to the outside. The On the other hand, when the SyncReq packet received from the transmission unit is received, the reception timing is notified from the network transmission / reception unit 59, and the time control packet generation unit 53 records the reference time (T4 in FIG. 2). Using this T4, the time control packet generation unit 53 generates a DelayResp packet and transmits it to the transmitter side via the packet multiplexing unit 58 and the NW transmission / reception unit 59.

  FIG. 5 is a block diagram of the receiver side in this embodiment. Next, generation of vertical synchronization timing on the receiver side will be described. With the reference clock generated by the reference clock generation unit 51 as a reference, the output synchronization signal generation unit 55 generates a vertical synchronization signal at the time of output. This vertical synchronization signal is sent to the transmitter synchronization phase calculation unit 56. Here, as will be described later, the phase of the vertical synchronizing signal on the transmitter side is calculated from the phase of the vertical synchronizing signal at the time of output on the receiver side, and using the counter information in the reference time counter, the SyncPhase shown in FIG. Generate a packet. The SyncPhase packet is transmitted to the packet multiplexing unit, and transmitted to the transmitter side from the network transmission / reception unit 59 and the network terminal 60 in the same manner as the Sync packet.

  Next, a video decoding procedure in the receiver will be described. The MAC packet including the MPEG2TS stream related to the video received by the network transmission / reception unit 59 is transferred to the system Demux unit 61. The system demux unit 61 performs TS packet separation and video stream extraction. The extracted video stream is transferred to the video decoding unit 62. The audio stream is sent to the audio composite unit 65, and after digital / audio conversion is performed by the DA converter 66, it is output to the speaker.

  The system Demux unit 61 stores the stream in the internal buffer for a predetermined waiting time, then outputs the stream to the video decoding unit 62 and starts decoding.

  FIG. 6 shows an example of a transition situation when the stream is accumulated in the internal buffer in the system Demux unit 61. In this figure, for the sake of convenience, the stream is supplied from the network at a constant bit rate, and is modeled so that a stream for each MB is output instantaneously in the video decoding unit 62 at each MB unit time.

  Stream input is started from the stage of time T0, and after waiting for a period indicated by a period 92, decoding of the stream is started. This provides a waiting time to prevent underflow even when the storage amount of the stream becomes the smallest as shown at timing 93. This waiting time can be realized by defining a time longer than the convergence time as the waiting time when the transmitter knows the minimum convergence time necessary to converge the generated code amount to the transmission bit rate of the network. .

  The video stream read from the demux unit 61 is decoded by the video decoding unit 62 to generate a decoded image. The generated decoded image is transferred to the display processing unit 63, transmitted to the display 64 at a timing synchronized with the vertical synchronization, and displayed as a moving image. For example, the image signal is output from the external terminal 69 for transmission to an external image recognition device (not shown).

  FIG. 7 is a diagram illustrating the relationship of control timing in each functional block from the transmitter to the receiver.

  The vertical synchronization signal 40 in FIG. 7 is a vertical synchronization signal generated by the sensor control unit 18 in FIG. 1, the sensor readout signal 41 in FIG. 7 is the timing at which data is read from the CMOS sensor in FIG. 1, and the image in FIG. Capture 42 is a video input timing to the video encoding unit 22 in FIG. 1, encoded data output 43 in FIG. 7 is a timing at which a video encoded stream is output from the video encoding unit 22 in FIG. 7 is the timing at which the encoded data is input to the video decoding unit 62 in FIG. 5, and the decoded output vertical synchronization signal in FIG. 7 is sent from the display processing unit 63 in FIG. The vertical synchronization signal output to the terminal 69 and the decoded image output 46 of FIG. 7 indicate the effective pixel period of the image output from the display processing unit 63 of FIG. 5 to the display or the external terminal 69. The For convenience, it is considered that the vertical blanking period from the vertical synchronization timing 40 to the sensor readout timing 41 and the vertical blanking period from the decoding-side output vertical synchronization signal to the decoded image output 46 are the same.

  Here, from the image output start (start time of each frame 41 in FIG. 7) of the CMOS sensor (20 in FIG. 1) on the transmitter side, a packet received on the receiver side is received and displayed as a decoded image or other display Assume that the delay time (Tdelay in FIG. 7) until the time (46 in FIG. 7) to be output to the device can be specified by design specifications or the like. Tdelay is the delay time from the video capture on the transmitter side to the packet transmission via the encoding process and the network transfer delay, and the delay required from the packet capture on the receiver side to the output via the decoding process It can be defined by totaling time.

  7 calculates a reference time for the output timing (ta, tb, tc...) Of the output vertical synchronization signal 45 on the receiver side. This can be calculated by referring to the reference time of an output vertical synchronization signal of one sample and adding a reference time counter corresponding to the frame period Tms. After calculating ta, tb, tc, the time (TA, TB, TC...) going back from Tdelay is calculated. For example, TA = ta-Tdelay.

  TA, TB, and TC calculated in this way are transmitted to the transmitter by SyncPhase as shown in FIG.

  At this time, transmission is performed in consideration of the network delay time Tnet so that the time at which the SyncPhase storing the time information of TA, TB, TC arrives at the receiver side sufficiently arrives before TA, TB, TC, respectively. Send to the machine.

  Specifically, when the receiver side adjusts the phase of the synchronization signal on the transmission side at the time Tx in the SyncPhase packet, the transmission timing is Tsp, and the transmitter side analyzes the information in the SyncPhase after receiving the SyncPhase. It is possible to realize this by selecting Tx that satisfies Tsp + Tnet + Ty <Tx and generating a SyncPhase packet. In addition, each period that defines the control timing, such as Tdelay, Tnet, Ty, etc., when jitter occurs in that period due to processing load, etc., each is considered with the worst value of the corresponding period, so that equivalent control can be performed. Is possible.

  With this system, the phase difference between the vertical synchronization signals on the transmission side and the reception side can be adjusted to be equal to or close to the delay time Tdelay required from video capture to output. Tdelay can be defined as described above because it has means for determining the transmission delay of the network, and further, the buffer storage time is fixed at a predetermined time for the encoding delay of the transmitter and the decoding delay of the receiver. If the relationship is such that TA + Tdelay> ta without performing the control as in this embodiment, the video captured between TA and TB is output on the receiver side in the frame period starting from ta. The output timing needs to be delayed until tb. For this reason, even when Tdelay is sufficiently smaller than the vertical synchronization period, the time from imaging timing to video output is unnecessarily increased. According to the present embodiment, such a situation can be avoided, and the total delay time can be made closer to the delay time that can be realized with the transmission capability of the network and the delay times required for encoding and decoding of the transmitter and the receiver.

  The procedures relating to clock synchronization, time synchronization, reference synchronization signal phase adjustment, and transmission of an encoded stream described in the above embodiment are shown in FIGS. 8 and 9 for the transmitter and the receiver, respectively. By following these series of control procedures, it is possible to construct a network camera system that can reduce the delay from imaging to video output.

  FIG. 10 shows a system in which the network camera unit 1 and the receiver 5 using the transmitter described in this embodiment are connected via a network. By configuring the network camera system as described above, the total delay from imaging at the transmitter to video output on the receiver side is ensured while guaranteeing a delay time during which video information can continue to be sent without failure of the transmission system. It is possible to construct a video transfer system that is reduced in size.

  In addition, the phase of the synchronization signal for imaging on the transmitter side (the time difference between the most recent rise timings) becomes constant each time the system is started with respect to the timing of the synchronization signal for the receiver to output video. In addition, there is an effect that the design is facilitated even in a system that requires subsequent image processing and strict synchronization timing with other devices.

Note that it is obvious that the same effect can be obtained when the video output here is specified at the timing when the video is displayed on the display or at the output timing to the external device.
In addition, in this system, there is no need to provide a communication path for transmitting the control signal for aligning the timing of the synchronization signal other than the network for transmitting and receiving the encoded signal, which is effective from the viewpoint of reducing the system cost. It is.

  Further, in this embodiment, an example in which the phase of the vertical synchronization signal on the transmitter side is controlled from the receiver side is shown. However, the synchronization that indirectly or directly defines the video capture and encoding timing on the transmitter side is shown. If the signal or the control timing is used, it is obvious that phase information is transferred from the receiver side as an alternative to the vertical synchronization signal of the present embodiment, thereby providing the same effect as the present embodiment. In this embodiment, the time synchronization server has the same definition as the receiver, but the time synchronization server may be an individual device different from the receiver. In that case, if the receiver becomes a client as well as the transmitter, the clock synchronization, the reference time counter is synchronized with the server, and then the synchronization phase information is transmitted to the transmitter, the same as this embodiment Bring effect. In this case, it is useful when a plurality of receiving systems exist in the network and it is desired to control them with a common clock.

  In the present embodiment, an example conforming to the IEEE 802.3 standard is shown as a network layer standard. However, a network protocol IP (Internet Protocol) is used, and a TCP (Transmission Control Protocol) is used as a transport protocol higher than the network protocol. Alternatively, UDP (User Datagram Protocol) may be used. For transmission of video and audio, a higher-level application protocol such as RTP (Real-time Transport Protocol) or HTTP (Hyper Text Transfer Protocol) may be used. Alternatively, a protocol system defined by the IEEE 802.3 standard may be used.

DESCRIPTION OF SYMBOLS 1 ... Transmitter, 2 ... Receiver, 10 ... Network terminal, 11 ... Packet separation part, 12 ... Time information extraction part, 13 ... Reference clock recovery, 14 ... Reference time counter, 15 ... Delay information generation part, 16 ... Synchronous phase information extraction unit, 17 ... reference synchronization signal generator, 18 ... sensor control unit, 19 ... lens unit, 20 ... CMOS sensor, 21 ... digital signal processing unit, 22 ... video encoding unit, 24 ... microphone, 25 ... AD converter, 26 ... voice encoding unit, 27 ... system Mux, 28 ... system control unit, 29 ... network transmission / reception unit, 51 ... reference clock generation unit, 52 ... reference time counter, 53 ... time control packet generation unit, 55 ... Output synchronization signal generation unit, 56 ... Transmitter synchronization phase calculation unit, 58 ... Multiplexing unit, 59 ... Network transmission / reception unit, 60 ... NW terminal, 61 ... System Demux , 62 ... video decoder, 63 ... display unit, 64 ... display unit, 65 ... audio decoding unit, 66 ... DA converter unit, 67 ... speaker unit

Claims (6)

Receiving means for receiving an encoded signal from a network;
Decoding means for obtaining a decoded signal from the encoded signal within a predetermined decoding delay time;
Signal output means for outputting the decoded signal;
Transmission means for transmitting control information for adjusting the phase of the synchronization signal of the input signal, based on a delay time from the external transmitter connected to the network until the signal is output at the receiver,
An encoded signal receiving apparatus comprising: The encoded signal receiving device according to claim 1,
The phase adjustment of the synchronization signal of the input signal is realized by transmitting a reference time signal and the timing of the synchronization signal with respect to the reference time signal,
An encoded signal receiver characterized by the above. The encoded signal receiving device according to claim 1,
The control information for adjusting the phase of the synchronization signal of the input signal is controlled so that the transmission time required until the signal is output from the external transmitter connected to the network to the receiver becomes a predetermined time. Information
An encoded signal receiver characterized by the above. The encoded signal receiving device according to claim 1,
The control information for adjusting the phase of the sync signal of the input signal is shortened so that the delay time until the signal is output from the external transmitter connected to the network to the receiver is not broken. Information to control,
An encoded signal receiver characterized by the above. The encoded signal receiving device according to claim 1,
The encoded signal is a video encoded signal, and
The signal output means outputs a decoded video signal based on the output synchronization signal, calculates the synchronization signal phase of the input signal on the transmitter side based on the output signal, and transmits the control information,
An encoded signal receiver characterized by the above. Means for receiving an encoded signal from a network;
Decoding means for obtaining a decoded signal from the encoded signal;
Signal output means for outputting the decoded signal;
Transmitting means for transmitting control information for adjusting the phase of the synchronization signal of the input signal;
An encoded signal receiving apparatus comprising:

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