JP2012194833A - Test data generating program, device, and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device for generating test data taking account of a boundary value test.SOLUTION: A property storage unit 30 stores data of a logical formula representing restriction conditions related to an input value of software subject to an examination. A boundary value restriction generating unit 38 determines whether or not the logical formula stored in the property storage unit 30 includes an inequality sign with an equality sign. When it is determined to include the inequality sign with the equality sign, a boundary value restriction generating unit 38 converts the logical formula represented by the inequality sign with the equality sign into data of a logical formula represented by a logical sum between a logical formula formed by converting the inequality sign with equality sign into an equality sign and a logical formula formed by converting the inequality sign with the equality sign into an inequality sign.

Description

  The disclosed technology relates to a test data generation program, apparatus, and method.

  As a conventional technology that automatically generates test data for testing the operation of software programs in business systems, the satisfaction value is used as test data by solving the satisfiability determination problem of the constraint expression that expresses the situation to be tested. There is technology. As the constraint expression, a screen item, a DB item, or a logical expression using a program variable is used. For example, a test data generation technique for a white box test using an SMT (Satisfiability Modulo Theories) solver that solves the satisfiability problem is known (Non-Patent Document 1). This SMT solver first determines the satisfiability for each input constraint equation, and outputs one solution (satisfaction solution) that satisfies this constraint equation when it is determined that the constraint is satisfiable. The “one” means that one item is to be obtained for each item or variable.

Nikolai Tillmann and Jonathan de Halleux, "Pex-White Box Test Generation for .NET", TAP 2008, LNCS 4966, pp.134-153, 2008.

  When testing business system software, it is necessary to prepare test data based on the empirical rule that program errors are likely to occur at data boundaries. A test based on this rule of thumb is called a boundary value test. The boundary value test is a test performed by dividing an input into a valid data range and an invalid data range and using a boundary value, that is, a boundary value.

  This boundary value is a value included in the range of the sufficiency value of the constraint expression described above, and is not a value that is completely the same.

  For example, it is assumed that a constraint equation 5 ≦ A is given as a constraint equation representing the range of the data value of item A.

  The SMT solver can output any value of 5 or more as a sufficiency value for this constraint equation. On the other hand, the significant value as the boundary value test is 5.

  As described above, as a situation to be tested, even if a constraint expression in which the range of values of items and variables is expressed by a logical expression is solved using an SMT solver, a satisfactory solution that satisfies the above boundary value test condition, that is, There was no guarantee that test data could be obtained as boundary values.

  The problem to be solved by the disclosed technology is to convert a logical expression into a logical expression that can be output reliably by the SMT solver when the logical expression includes a constraint on the boundary value.

  The disclosed technique refers to a storage unit in which data of a logical expression indicating a constraint condition related to an input value of software to be examined is stored, and whether or not an inequality sign with an equal sign is included in the data of the logical expression. judge. When it is determined that the disclosed technique is included in the determination, the inequality sign with an equal sign stored in the storage unit is converted into an equal sign.

  According to the disclosed technique, when a constraint relating to a boundary value is included in a logical expression, there is an effect that the logical expression can be converted into a logical expression that allows the SMT solver to reliably output the boundary value. It is done.

It is the schematic which shows the structure of the information processing apparatus which concerns on this Embodiment. It is a functional block diagram of the information processing apparatus concerning this Embodiment. It is a figure which shows the logic formula data of a tree structure format typically. It is a figure which shows the example of storage of the logic formula data of a tree structure form. It is a figure for demonstrating the conversion law for removing an implication operator. It is a figure for demonstrating the conversion law for removing an implication operator. It is a figure for demonstrating the conversion law for removing double negation. It is a figure for demonstrating the conversion law for removing double negation. It is a figure for demonstrating the conversion law based on De Morgan's law. It is a figure for demonstrating the conversion law based on De Morgan's law. It is a figure for demonstrating the conversion law based on De Morgan's law. It is a figure for demonstrating the conversion law based on De Morgan's law. It is a figure which shows typically the logical formula data of a tree structure format before the conversion law based on De Morgan's law is applied. It is a figure which shows typically the logic formula data of the tree structure format converted by applying the conversion law based on De Morgan's law. It is a figure which shows the example of a storage of the logical formula data of a tree structure format before the conversion rule based on a De Morgan's law is applied. It is a figure which shows the example of a storage of the logical formula data of the tree structure format converted by applying the conversion law based on De Morgan's law. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing negation concerning an inequality operator. It is a figure which shows typically the logic formula data of a tree structure format before the conversion rule for removing negation concerning an inequality operator is applied. It is a figure which shows typically the logic formula data of a tree structure format converted by applying the conversion rule for removing negation concerning an inequality operator. It is a figure which shows the example of a storage of the logic formula data of a tree structure format before the conversion rule for removing negation concerning an inequality operator is applied. It is a figure which shows the example of storage of the logic formula data of a tree structure format converted by applying the conversion law for removing negation concerning an inequality operator. It is a figure for demonstrating the conversion law for removing the inequality operator with an equal sign. It is a figure for demonstrating the conversion law for removing the inequality operator with an equal sign. It is a figure for demonstrating the conversion law for removing the inequality operator with an equal sign. It is a figure for demonstrating the conversion law for removing the inequality operator with an equal sign. It is a figure which shows typically the logic formula data of a tree structure format before the conversion law for removing the inequality operator with an equal sign is applied. It is a figure which shows typically the logic formula data of the tree structure format converted by applying the conversion law for removing the inequality operator with an equal sign. It is a figure which shows the example of storage of the logical formula data of a tree structure format before the conversion law for removing the inequality operator with an equal sign is applied. It is a figure which shows the example of a storage of the logical formula data of the tree structure format converted by applying the conversion law for removing the inequality operator with an equal sign. It is a figure for demonstrating the conversion law based on a distribution law. It is a figure for demonstrating the conversion law based on a distribution law. It is a figure for demonstrating the conversion law based on a distribution law. It is a figure for demonstrating the conversion law based on a distribution law. It is a figure which shows the logical formula data of a tree structure format before the conversion rule based on a distribution rule is applied. It is a figure which shows typically the logic formula data of the tree structure format converted by applying the conversion law based on a distribution law. It is a figure which shows the example of a storage of the logical formula data of a tree structure format before the conversion rule based on a distribution rule is applied. It is a figure which shows the example of a storage of the logical formula data of the tree structure format converted by applying the conversion law based on a distribution law. It is a figure which shows the example of a test data table. It is a flowchart which shows the content of the test data generation process routine of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the test data generation process routine of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the implication removal process routine of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the double negation removal process routine of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the processing routine of conversion to the negative standard form by De Morgan's law of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the negative removal process routine of the inequality sign of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the conversion process routine of the inequality sign with an equal sign of the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows the content of the conversion process routine to the disjunctive standard form of the information processing apparatus which concerns on this Embodiment. It is a figure which shows a mode that the program memorize | stored in the recording medium is installed in HDD.

  Hereinafter, embodiments will be described in detail.

  As shown in FIG. 1, the information processing apparatus 10 includes a CPU 12, a ROM 14, a RAM 16, an HDD 18, a communication interface 20, and a bus 22 for connecting them together.

  The CPU 12 executes various programs. The ROM 14 stores various programs, parameters, and the like. The RAM 16 is used as a work area when the CPU 12 executes various programs. The HDD 18 serving as a recording medium stores various programs and various data including a program for executing a test data generation processing routine, which will be described later, and a program for performing satisfiability determination processing.

  When the information processing apparatus 10 is represented by functional blocks in accordance with a program for executing a test data generation processing routine and a program for performing a process for determining satisfiability, it is as shown in FIG. The information processing apparatus 10 includes a property storage unit 30, a logical expression tree structure generation unit 32, a negative normal form conversion unit 34, a negated inequality sign removal conversion unit 36, and a boundary value constraint generation unit 38. The information processing apparatus 10 further includes a test data generation unit 40, a data generation property storage unit 41, a satisfiability determination unit 42, and a test data storage unit 44. The boundary value constraint generation unit 38 is an example of an inequality sign conversion unit with an equal sign and a disjunctive standard form conversion unit.

  The property storage unit 30 stores properties that are information that is input to the information processing apparatus 10 and determines the logical specifications of the software to be inspected.

  The software to be inspected is, for example, software for a web system having a screen and a DB (database), and items such as “user”, “address”, “purchased quantity”, and “total” are included in the screen. include.

  Also, in this embodiment, for example, the property has a business specification that “the total is 5000 yen or more and the number of purchased items is 5 or less and the postage is free when the address is met in Tokyo or Kanagawa”. Has been.

  In addition, as the precondition in the above business specification, logical expression data indicating a constraint condition regarding the input value of the software to be verified is stored in the property storage unit 30. For example, the following logical formula data is stored.

Preconditions: ((Total ≧ 5000) 購入 (Purchased ≧ 1) ∧ (Purchased ≦ 5)) ∧ ((Address = “Tokyo”) ∨ (Address = “Kanagawa”))

  As described above, the logical expression data includes a character string, a numerical value, a logical operator (implication (→), logical sum (∨), logical product (∧), negation (¬)), relational operator (equal sign (= ), Inequality signs (>, <, ≧, ≦),), and parentheses.

  The logical expression tree structure generation unit 32 reads logical expression data indicating a precondition from the property storage unit 30, analyzes the logical structure of the read logical expression data, and displays a tree structure format as shown in FIGS. Is generated and stored in the RAM 16. FIG. 3 is a schematic diagram of data in a tree structure format. FIG. 4 is a diagram illustrating an example of tree-structured data stored in the RAM 16. The logical expression tree structure generation unit 32 performs “No”, “Value”, “Operator”, “Left Node”, “Right Node” shown in FIG. 4 for each node of the tree structure data shown in FIG. ] Are stored in the RAM 16. The uppermost node in FIG. 3 corresponds to a row in which “No” in FIG. 4 is 0.

  The negative standard form conversion unit 34 refers to the logical expression data in the tree structure format, and performs a process of converting the input logical expression into the negative standard form. The negation standard form is a logical expression in which negation is related only to an atomic logical expression that is a logical expression having no partial logical expression, and only logical sum and logical product are used as logical operators. Even if the input logical expression does not include an inequality sign with an equal sign indicating the constraint on the boundary value, by performing this process, it can be modified so that only the atomic logical expression is negated, and the constraint on the boundary value is reduced. It becomes possible to find the inequality part with the equal sign shown. Therefore, when the input logical expression is negative standard form, this processing by the negative standard form conversion unit 34 is not necessary.

  The negative normal form conversion unit 34 applies the conversion rule (1) as shown below to the logical structure data in the tree structure format, and does not include the implication operator for the subtree including the implication operator (→). Convert to a subtree (with the implication operator removed) (see FIGS. 5 and 6). Specifically, the negative standard form conversion unit 34 converts a logical expression including an implication operator into a negation of a logical expression described before the implication operator (left side) and after the implication operator (right side). Performs processing to convert to logical OR with the described logical expression.

  Note that when the implication operator is not included in the input logical expression, the application process of the conversion law (1) is unnecessary.

Conversion law (1): Convert “s1 → s2” to “¬s1∨s2”

  Here, s1 and s2 represent partial logical expressions or atomic logical expressions.

  The negative standard form conversion unit 34 repeats the process of applying the above conversion law (1) to the logical expression data until there is no implication operator from the logical expression data in the tree structure format. The implication operator can be removed, and the logical operators in the logical expression data can be only three types of logical product, logical sum, and negation.

  Further, the negative normal form conversion unit 34 applies the conversion rule (2) as shown below to the logical expression data in the tree structure format, and does not include the double negation for the subtree including the double negation ( (Refer to Fig. 7 and Fig. 8. Fig. 7 and Fig. 8 are diagrams each schematically showing logical expression data having the same tree structure.) And a storage example). In this process, an implication operator is included in the input logical expression, and negation (¬) occurs due to the application of the above conversion law (1) (removal processing of the implication operator). This is a process that is necessary when the expression is related to the negative (¬) that originally existed or when double negation is included even if the implication operator is not included. Therefore, when the input logical expression data does not include any subtree including an implication operator and negation, or a subtree including double negation, the application process of the conversion law (2) is unnecessary. is there.

Conversion law (2): ("¬¬s1" is converted to "s1")

  Here, s1 represents a partial logical formula or an atomic logical formula.

  The negative standard form conversion unit 34 repeats the process of applying the above conversion law (2) to the logical expression data from the logical expression data in the tree structure until the double negation disappears, thereby obtaining the logical expression data from the logical expression data. Double negation (redundant negation subtree) can be removed.

Further, the negative standard form conversion unit 34 applies conversion laws (3) and (4) known as De Morgan's law as shown below to logical expression data in a tree structure format. As a result, the negative standard form conversion unit 34 does not include the logical AND and the logical negation for the subtree including the logical AND and the logical negation (the logical AND negation and the logical negation are removed). (See FIGS. 9, 10, 11, and 12. Note that FIGS. 9, 11, 10, and 12 are respectively logical expressions of the same tree structure.) It is the figure which shows data, and the figure which shows the example of storage. Specifically, the negation standard form conversion unit 34 negates the logical product by negating the logical expression described before the logical product (left side) and the logical product described after the logical product (right side). The logical sum of the logical expression described in the logical sum with the negation of the expression, the negation of the logical sum, the negation of the logical expression described before the logical sum (the left side), and the logical expression described after the logical sum (the right side). Performs conversion to the logical product of negation.
Note that when the input logical expression is a negative standard form, the application process of the conversion laws (3) and (4) is not necessary.

Conversion law (3): “¬ (s1∧s2)” is converted to “¬s1∨¬s2” Conversion law (4): “¬ (s1∨s2)” is converted to “¬s1∧¬s2”

  Here, s1 and s2 represent partial logical expressions or atomic logical expressions.

  For example, as shown below, the negative normal form conversion unit 34 negates a logical product represented by a subtree to which a conversion law based on De Morgan's law can be applied (see FIGS. 13 and 15. FIG. 15 is a diagram schematically showing logical expression data having the same tree structure and a storage example, respectively. The logical OR of each of the two logical expressions represented by the subtree is shown in FIG. Refer to Fig. 16. Note that Fig. 14 and Fig. 16 are respectively a diagram schematically showing logical expression data having the same tree structure and a diagram showing a storage example.

¬ (Purchased quantity> 5∧Purchased quantity <10)
⇒¬ (Purchase quantity> 5) ∨¬ (Purchase quantity <10)

  The negative standard form conversion unit 34 applies the above conversion rule (3) to the logical expression data until the logical expression data in the tree structure format is converted into the logical expression data in the tree structure format in which negation is related only to the primitive logical expression. ) And (4) can be repeated to convert a logical expression including logical product, logical sum, and negation into a negative standard form.

  In this way, the negative normal form conversion unit 34 converts the conversion law (1) for removing the implication operator (→) and the conversion law (for removing double negation ( 2), and conversion laws (3) and (4) based on De Morgan's law. In this way, the negative standard form conversion unit 34 converts the logical structure data in the tree structure format indicating the precondition into a negative standard form in which negation is related only to the atomic logical expression and is combined with logical sum or logical product. Is converted into logical expression data in a tree structure format represented by

  The inequality sign removal conversion unit with negation 36 applies the conversion rules (5) to (8) as shown below to the tree-form logical expression data converted into the negative normal form logical expression data: Convert the negative subtree related to the inequality sign to a subtree that does not include the negation related to the inequality sign (the negation related to the inequality sign has been removed) (see FIGS. 17 to 24. Note that FIG. 17, FIG. 21, FIG. 118 and FIG. FIG. 22, FIG. 19, FIG. 23, FIG. 20 and FIG. 24 are a diagram schematically showing logical formula data having the same tree structure and a storage example, respectively. Specifically, the inequality sign removal conversion unit 36 with negation converts each logical expression in which negation is involved in the inequality sign into a logical expression using the inequality sign and the contradictory inequality sign.

  In addition, when the input logical formula is a conjunction standard form or a disjunctive standard form and does not include negation, the application process of the conversion laws (5) to (8) is not necessary.

Conversion law (5): “¬ (a1 <a2)” is converted to “a1 ≧ a2” Conversion conversion law (6): “¬ (a1 ≦ a2)” is converted to “a1> a2” Conversion conversion law (7): Conversion rule “¬ (a1> a2)” to “a1 ≦ a2” (8): Convert “¬ (a1 ≧ a2)” to “a1 <a2”

  Here, a1 and a2 represent partial logical expressions or atomic logical expressions.

  The inequality sign removal conversion unit with negation 36 is a subtree (¬ (purchase quantity> 5), ¬ (purchase quantity <10) to which a conversion law for removing negation related to the inequality sign as shown in FIGS. )) Is converted into a partial tree (purchased quantity ≦ 5, purchased quantity ≧ 10) as shown in FIGS.

  The negated inequality sign removal conversion unit 36 executes this process to convert the input logical expression from a logical expression indicating an invalid range indicated by a negated inequality sign to an effective range indicated by an inequality sign without negation. Can be converted into a logical expression indicating

  The boundary value constraint generating unit 38 applies the following conversion laws (9) and (10) to the tree-structured logical expression data from which negation related to the inequality sign is removed. Accordingly, the boundary value constraint generation unit 38 converts the logical expression using the inequality operator with an equal sign to the logical expression using the logical expression using the equal sign and the logical expression using the inequality operator without an equal sign. (See FIGS. 29, 30, 31, and 32. Note that FIGS. 29, 31, 30, and 32 respectively represent logical expression data having the same tree structure. It is the figure which shows typically, and the figure which shows the example of storage.

Conversion rule (9): “a1 ≧ a2” is changed to “(a1 = a2) ∨ (a1> a2)” Conversion rule (10): “a1 ≦ a2” is changed to “(a1 = a2) ∨ (a1 <a2) )"Conversion to

  Here, a1 and a2 represent partial logical expressions or atomic logical expressions.

  The boundary value constraint generation unit 38 repeats the process of applying the above conversion law (9) and conversion law (10) to the logical expression data until the inequalities with equal signs disappear from the logical expression data in the tree structure format. Thus, the inequality operator with an equal sign is converted from the logical expression data into a logical expression indicating a logical sum of the logical expression using the equal sign and the logical expression using the inequality sign.

  The boundary value constraint generating unit 38 shows, for example, a subtree (purchased number ≦ 5, purchased number ≧ 10) indicating a logical expression using inequalities with equal signs shown in FIGS. 33 and 35, as shown in FIGS. Convert to subtree ((purchased quantity = 5) ∨ (purchased quantity <5), (purchased quantity = 10) ∨ (purchased quantity> 10)).

  Here, a logical expression using an equal sign represents an upper limit boundary value or a lower limit boundary value related to an input value. A logical expression using an inequality sign represents a value smaller than the upper boundary value or a value larger than the lower boundary value as a representative value of the input value.

  By this processing, the boundary value constraint generation unit 38 indicates a logical expression represented by an equal sign with an equal sign representing a boundary value as a logical expression represented by an equal sign satisfying the constraint of the boundary value test and an inequality sign representing a representative value. Can be converted into logical expressions.

  In order to obtain data satisfying the boundary value test constraints, it is only necessary to obtain logical expressions using equal signs among the decomposed logical expressions. Therefore, the boundary value constraint generation unit 38 may convert an inequality sign with an equal sign into only an equal sign.

  The test data generation unit 40 applies the conversion rules (11) to (12) based on the distribution rules shown below to the logical structure data in the tree structure format converted by the boundary value constraint generation unit 38, The product (∧) and the logical sum (∨) are converted into logical expression data in a tree structure format represented by a continuous subtree (declared standard form). Specifically, the test data generation unit 40 performs logical product (∧) and logical sum (（) included in the logical expression data of the tree structure until there is no subtree in which the logical product (∧) and logical sum (∨) continue. Of the two subordinate nodes of the logical product (∧), the node that is not focused on as the logical sum (∨) and the lower-order nodes of the node that is focused on as the logical sum The process of converting into a subtree represented by the logical sum of two logical products (∧) is repeatedly executed. Accordingly, the test data generation unit 40 uses a logical expression that does not include a logical sum as one clause, and a logical expression in a tree structure format expressed in a disjunctive standard form in which a plurality of clauses are combined with a logical sum. Can be converted to data.

Conversion law (11): “s1∧ (s2∨s3)” is changed to “(s1∧s2) ∨ (s1∧s3)” Conversion law (12): “(s1∨s2) ∧s3” is changed to “(s1 ∧s3) ∨ (s2∧s3) ”

  Conversions to which the conversion rules (11) to (12) are applied are shown in FIGS. 37, 38, 39, and 40. FIG. 37, 39, 38, and 40 are a diagram schematically illustrating logical expression data having the same tree structure and a storage example, respectively.

  For example, as shown below, the test data generation unit 40 selects logical expression data in a tree structure format (see FIGS. 41 and 43) by combining a plurality of logical expressions not including logical sums. It is converted into logical formula data in a tree structure format expressed in the standard form.

((Purchase quantity = 5) ∨ (Purchase quantity <5)) ∧ ((Address = ”Tokyo”) ∨ (Address = “Saitama”))
⇒
((Purchase quantity = 5) ∧ (Address = "Tokyo")) ∨
((Number purchased = 5) ＝ (Address = “Saitama”)) ∨
((Purchased <5) ∧ (Address = “Tokyo”)) ∨
((Purchase quantity <5) ∧ (address = “Saitama”)) ∨
((Purchase quantity = 10) ∧ (Address = "Tokyo")) ∨
((Purchase quantity = 10) ∧ (Address = "Saitama")) ∨
((Purchased quantity> 10) ∧ (address = “Tokyo”)) ∨
((Purchased quantity> 10) ∧ (Address = “Saitama”))

  The test data generation unit 40 converts the logical expression data in the tree structure format expressed in the converted disjunctive standard form into the disjunctive standard form clauses (parts of logical expressions that do not include logical sums and are combined with logical products). ) For each subtree data. As a result, the preconditional expression expressed in the disjunctive standard form is divided into a plurality of preconditional expressions in which the truth value is uniquely determined. The test data generation unit 40 converts the subtree data of the section into logical expression data described by a character string, and stores the data in the data generation property storage unit 41 for each section. The test data generation unit 40 sequentially outputs the logical expression data of each clause stored in the data generation property storage unit 41 to the satisfiability determination unit 42. In addition, the test data generation unit 40 stores the satisfiability solution data output for each section from the satisfiability determination unit 42 as a set of test data input to the inspection target software in the test data storage unit 44. Stored in the test data table for each section.

  The satisfiability determination unit 42 determines the satisfiability of the constraint condition indicated by the input logical formula data, and generates satisfiability solution data obtained when it is determined that the constraint condition is satisfiable. To the unit 40.

  For example, when logical expression data of each section shown below is input to the satisfiability determination unit 42, satisfaction solution data as shown in FIG. 45 is output, and test data is stored as a plurality of sets of test data. It is stored in the test data table stored in the unit 44.

Formula data 1: (Purchase quantity = 5) ∧ (Address = "Tokyo")
Formula data 2: (Purchase quantity = 5) ∧ (Address = "Saitama")
Formula data 3: (Purchase quantity <5) ∧ (address = “Tokyo”)
Formula data 4: (Purchase quantity <5) ∧ (address = “Saitama”)
Logical data 5: (Purchase quantity = 10) ∧ (Address = “Tokyo”)
Formula data 6: (Purchase quantity = 10) ∧ (Address = “Saitama”)
Formula data 7: (Purchased quantity> 10) ∧ (address = “Tokyo”)
Formula data 8: (Purchased quantity> 10) ∧ (address = “Saitama”)

  By this processing, the test data generation unit 40 can generate a plurality of sets of test data in consideration of all combinations of variations of boundary values related to input values and variations of constraint conditions related to input values.

  Next, the operation of the present embodiment will be described.

  A property, which is information that defines the logical specification of the software to be inspected, is input to the information processing apparatus 10 from another apparatus via the communication interface 20 and stored in the property storage unit 30. The property stored in the property storage unit 30 has a business specification set therein, and includes logical formula data indicating a constraint condition regarding the input value of the verification target software as a precondition in the business specification.

  Then, the operator operates an operation unit (not shown) of the information processing apparatus 10 to instruct generation of test data related to the input value of the verification target software. As a result, the CPU 12 of the information processing apparatus 10 executes a program for executing the test data generation processing routine shown in FIGS. 46 and 47 stored in the HDD 18.

  First, in S100, the information processing apparatus 10 reads the property of the software to be verified from the property storage unit 30, analyzes the logical structure of logical expression data indicating the constraint condition included in the property, and generates logical expression data. Is converted into logical expression data in a tree structure format. The logical expression tree structure generation unit 32 stores a number for identifying the node in the item “No”. In the present embodiment, the logical expression tree structure generation unit 32 is “0” in the case of the highest node shown in FIG. 3, “1” in the case of the node ahead of the highest left branch, and the highest right. In the case of the node at the end of the branch, “2” is stored and the numbers in ascending order from the highest node are stored. The logical expression tree structure generation unit 32 stores the value that enters the node in the “value” item. In the present embodiment, the logical expression tree structure generation unit 32 stores a value only in a leaf (terminal node). The logical expression tree structure generation unit 32 adds “entailment (→)”, “logical sum (∨)”, “logical product (∧)”, “negative (¬)),“ equal sign ”to the items of“ operator ”. (=) ”Or“ inequality sign (>, <, ≧, ≦))) ”is stored.The logical expression tree structure generation unit 32 stores the left branch in the item“ left node ”. The No. of the previous node is stored, and the No. of the node ahead of the right branch is stored in the item “Right Node”. In the present embodiment, when there is only one previous node, the logical expression tree structure generation unit 32 stores the No of the previous node in the item of the left node (see FIG. 4).

  The logical expression tree structure generation unit 32 can be realized by incorporating an arbitrary known program known as a parser into a program for executing a test data generation processing routine, and the CPU 12 executing the parser. I will omit the explanation. Further, the data layout shown in FIG. 3B is an example, and does not preclude the use of other known tree structure format data layouts.

  In step S102, the information processing apparatus 10 executes implication operator removal processing.

  FIG. 18 shows a processing flowchart of implication operator removal by the information processing apparatus 10.

  In S201, the information processing apparatus 10 sequentially selects the “left node” item value and the “right node” item value from the highest node shown in FIG. 3, that is, the node whose “No” item value is “0” shown in FIG. Are searched for a node whose item value of “operator” is “entailment (→)”.

  Then, in S202, the information processing apparatus 10 determines whether or not a node whose item value “operator” is “entailment (→)” has been searched as a result of the search in S201.

  If the negative standard form conversion unit 34 determines in S202 that the search was successful, the value of the item “left node” is stored in a left node item value save area (not shown) of the RAM 16 in S203.

  Next, in S204, the information processing apparatus 10 updates the item value of the “operator” of this node stored in the RAM 16 from “entailment” to “logical sum”.

  In step S <b> 205, the information processing apparatus 10 updates the item value of “left node” of this node stored in the RAM 16 to “new number”. For example, the information processing apparatus 10 employs a value obtained by adding 1 to the maximum value of the No item in the RAM 16 as the “new number”. Note that any number that is not yet stored in the No item value of the RAM 16 may be adopted.

  Then, in S206, the information processing apparatus 10 uses “No” in the “No” item, “Negative” in the “Operator” item, and “Left node” item value in the “Left node” item. New node data each storing the value of the save area is generated and additionally stored in the RAM 16.

  Thereafter, the information processing apparatus 10 proceeds to the process of S201.

  When the information processing apparatus 10 determines that the node having the item value “operator” of “implicit (→)” cannot be searched as a result of the search in S201, the information processing apparatus 10 performs the process of removing the implication operator. finish. As described above, the information processing apparatus 10 repeatedly executes the implication operator removal process on the tree-structured logical expression data to be processed until the implication operator cannot be searched, thereby generating the logical structure data in the tree structure format. From this, the implication operator can be removed.

  The process flowchart for removing the implication operator is an example. For all the implication operators included in the logical expression, negation of the logical expression described in front of the implication operator (left side) and the implication operator The use of any other processing procedure for converting to a logical sum with the logical expression described after (right side) is not denied.

  In S106, the information processing apparatus 10 executes a double negation removal process on the logical structure data in the tree structure format from which the implication operator is removed.

  FIG. 49 shows a processing flowchart of double negative removal by the information processing apparatus 10.

  In S301, the information processing apparatus 10 sequentially selects the “left node” item value and the “right node” item value from the highest node shown in FIG. 3, that is, the node whose “No” item value is “0” shown in FIG. 2 is searched for a double negation subtree in which two nodes whose item value of “operator” is “negation (¬)” are consecutive.

  Next, in S302, as a result of the search in S301, the information processing apparatus 10 can search for a double negation subtree in which two nodes whose item value of “operator” is “negative (¬)” are continuous. It is determined whether or not.

  If the information processing apparatus 10 determines in S302 that the search has been completed, in S303, the information processing apparatus 10 acquires an item value other than No in the lower node of the lower node of the searched subtree. It should be noted that the lower nodes of the lower nodes of the searched subtree are the “left node” of the node whose operator item value of the upper node and the operator item value of its own node are “negation (¬)”. It is a node whose item value is No. The item values other than No are item values of “value”, “operator”, “left node”, and “right node”.

  Next, in S304, the information processing apparatus 10 updates the item values other than No stored in the RAM 16 for the upper nodes of the retrieved subtree to the item values acquired in S303, respectively.

  Thereafter, the information processing apparatus 10 proceeds to the process of S301.

  Then, as a result of the search in S301, the information processing apparatus 10 determines that a double-negative subtree in which two nodes whose item value of “operator” is “negative (¬)” is consecutive cannot be searched. In this case, the double negative removal process is terminated.

  In this way, the information processing apparatus 10 repeatedly executes the double negation removal processing until the double negation cannot be searched for the tree-structured logical formula data to be processed, thereby obtaining the logical data in the tree structure format. From this, double negation can be removed.

  Note that this double negation removal process flowchart is an example, and does not deny the use of any other processing procedure that removes all double negations included in the logical expression.

  In S110, the information processing apparatus 10 executes a process of converting the logical expression data in the tree structure format from which all double negations are removed into a negative normal form of the logical expression based on De Morgan's law.

  FIG. 50 shows a processing flowchart of conversion of a logical expression to a negative standard form based on De Morgan's law by the information processing apparatus 10.

  In S401, the information processing apparatus 10, in order from the highest node shown in FIGS. 3 and 13, that is, the node whose “No” item value is “0” shown in FIG. While following the pointer stored in the “Node” item value, the node whose “Operator” item value is “Negation (→)” and the logical operator (“logical sum (∨)” or “logical product (∧)”) Search for subtrees with consecutive nodes.

  Next, in S402, as a result of the search in S401, the information processing apparatus 10 determines that the item value of “operator” is “negative (→)” and the item value of “operator” is a logical operator (“ It is determined whether or not a subtree in which a node that is “logical sum” or “logical product”) continues can be searched.

  If the information processing apparatus 10 determines in S402 that the search was successful, it determines in S403 whether the operator item value is “logical sum (∨)”.

  If the information processing apparatus 10 determines in S403 that it is “logical sum (∨)”, in S404, the upper node of the searched subtree, that is, the node whose operator is “negative (¬)” is stored in the RAM 16. The stored item value of “operator” is updated from “negation (¬)” to “logical product (∧)”.

  On the other hand, if the information processing apparatus 10 determines in S403 that it is not “logical sum (∨)”, in S405, the RAM 16 for the upper node of the retrieved subtree, that is, the node whose operator is “Negative (¬)”. The item value of “operator” stored in is updated from “negation (¬)” to “logical sum (」) ”.

  In the above description of S403, it is determined whether or not a logical sum, but it may be determined whether or not it is a logical product. In this case, the process of S405 may be performed when it is determined that it is a logical product, and the process of S404 may be performed when it is determined that it is not a logical product.

  When the processing of S404 or S405 is completed, the information processing apparatus 10 proceeds to the processing of S406. In S406, the lower node of the searched subtree, that is, the operator is a logical operator (“logical sum (∨)” or “logical The item values of “left node” and “right node” of the node of product (∧) ”) are acquired.

  In S407, the information processing apparatus 10 updates the item values of the “left node” and “right node” of the upper node processed in S404 or S405 to “new numbers”, respectively. For example, the information processing apparatus 10 adds 1 to the maximum value of the No item in the RAM 16 as the “new number” of the “left node”, and sets the “left node” as the “new number” of the “right node”. A value obtained by adding 1 to “new number” is stored. In addition, you may make it store the arbitrary numbers which are not yet stored in the item value of No of RAM16, respectively.

  In S <b> 408, the information processing apparatus 10 stores “New Number” stored in the “Left Node” item of the upper node in S <b> 407 in the “No” item, “Negative” in the “Operator” item, “ In the “left node” item, data of a new node storing the item value of “left node” acquired in S 406 is generated and additionally stored in the RAM 16.

  Further, in S409, the information processing apparatus 10 sets “No” to the “new number” stored in the “right node” item of the upper node in S406 and “No” to the “operator” item. For the item “left node”, data of a new node storing the item value of “right node” acquired in S 406 is generated and stored in the RAM 16.

  Thereafter, the information processing apparatus 10 proceeds to the process of S401.

  Then, as a result of the search in S401, the information processing apparatus 10 determines that the item value of “operator” is “negative (→)” and the item value of “operator” is a logical operator (“logical sum” or If it is determined that a subtree continuous with a node that is “logical product” cannot be searched, the process of converting the logical expression to the negative normal form based on De Morgan's law is terminated.

  In this way, the information processing apparatus 10 has a node with the item value of “operator” “negative (→)” and a logical operator (“logical sum (∨)” or The process of converting the logical expression to the negative canonical form based on De Morgan's law is repeatedly executed until the subtree in which the node which is “logical product (∧)” cannot be searched is found. By executing this process, the negative standard form conversion unit 34 converts the logical formula data including the logical product, logical sum, and negation, and the negation included in the logical formula data only relates to the atomic logical formula. It can be converted into standard formula data.

  Note that the processing flow chart for converting a logical expression to the negative standard form based on De Morgan's law is an example, and a logical expression that does not include logical operators other than logical product, logical sum, and negation is converted to a negative standard form. Use of any other process procedure that can be converted is not denied.

  Through the processes of S102 to S110 (FIGS. 48 to 50), the logical expression represented by the logical structure data in the tree structure format is converted into a negative standard logical expression.

  In S <b> 114, the information processing apparatus 10 executes a process of removing the negation related to the inequality sign for the logical structure data in the tree structure format converted into the negative standard form. FIG. 51 shows a processing flowchart of the removal of negation related to an inequality sign by the information processing apparatus 10.

  In S501, the information processing apparatus 10 with negation is the “left node” item in order from the highest node shown in FIGS. 14 and 25, that is, the node whose item value “No” is “0” shown in FIGS. While following the pointer stored in the value and the “right node” item value, the item value of the “operator” is “negation (¬)” and the item value of the “operator” is an inequality sign (an inequality sign (<, >) And an inequality sign with negation (any one of ≦ and ≧) is searched for a subtree of inequality with negation.

  Next, in S502, the information processing apparatus 10 determines that the node value of the “operator” is “Negative (¬)” and the item value of the “operator” are inequality signs (inequalities ( It is determined whether or not a subtree with inequality with negation, which is continuous with nodes that are <,>) and inequality with equality (any one of ≦, ≧), can be searched.

  If the information processing apparatus 10 determines in S502 that the search has been completed, in S503, the subnode of the searched subtree, that is, the operator is an inequality sign (an inequality sign (<,>) and an inequality sign with an equal sign (≦, ≧). It is determined whether the operator item value “inequality sign” is “equal sign with equal sign (≧ or ≦)”.

  If the information processing apparatus 10 determines in S503 that it is an “inequality sign with equal sign (≧ or ≦)”, in S504, the upper node of the searched subtree, that is, a node whose operator is “Negative (¬)” The item value of “operator” stored in the RAM 16 is changed from “Negation (¬)” to “Inequality sign with equal sign (≧ or ≦)” which is the item value of “operator” of the lower node of this node. To "No equal sign in the opposite direction (<or>)". That is, when the item value of the “operator” of the lower node stored in the RAM 16 is “≧”, the negative standard form conversion unit 34 sets the item value of the “operator” of the upper node to “<”, When the item value of the “operator” of the node is “≦”, the item value of the “operator” of the upper node is updated to “>”.

  On the other hand, if the information processing apparatus 10 determines in S503 that it is not “an inequality sign with an equal sign (≧ or ≦)”, in S504, the upper node of the searched subtree, that is, the operator is “negative (¬)”. For the node, the item value of “operator” stored in the RAM 16 is changed from “negation (¬)” to “equal sign without equal sign” (> or < ) ", Which is contradictory to" No equal sign and reverse inequality sign (≤ or ≥) ". That is, when the item value of the “operator” of the lower node stored in the RAM 16 is “>” for the retrieved subtree, the negative standard form conversion unit 34 sets the “operator” of the upper node. When the item value is “≦” and the item value of the “operator” of the lower node is “<”, the item value of the “operator” of the upper node is updated to “≧”.

  In the above description of S503, it is determined whether or not it is an inequality sign with an equal sign, but it may be determined whether or not it is an inequality sign without integration. In this case, the process of S505 may be performed when it is determined that the inequality sign has no equal sign, and the process of S504 may be performed when it is determined that the inequality sign has no equal sign.

  When the process of S504 or S505 ends, the information processing apparatus 10 proceeds to the process of S506, and acquires the item values of “left node” and “right node” of the lower nodes of the searched subtree, respectively.

  In step S507, the information processing apparatus 10 stores the item values of the “left node” and “right node” of the upper nodes of the searched subtree stored in the RAM 16 in step S506. Update to the item value of “right node”.

  Thereafter, the information processing apparatus 10 proceeds to the process of S501.

  Then, as a result of the search in S501, the information processing apparatus 10 has a node whose item value of “operator” is “Negative (¬)” and an item value of “operator” is an inequality sign (an inequality sign (<,>)). And if it is determined that the subtree of the inequality with negation that is consecutive with the node that is an inequality with equality (any one of ≦, ≧) cannot be searched, the process of removing the negation related to the inequality is performed. finish.

  In this way, the information processing apparatus 10 has a node whose “operator” item value is “negation (¬)” and an “operator” item value that is inequality ( Processing of removal of negation related to inequality until no subtrees with inequality with negation can be searched that are consecutive with nodes that are inequality (<,>) and inequality with equality (any of ≦, ≧). Is repeatedly executed, the negation related to the inequality sign can be removed from the logical formula data in the tree structure format.

  Note that this processing flowchart for removing inequality with negation is an example, and does not deny the use of any other processing procedure that removes all inequality with negation included in a logical expression.

  In S <b> 118, is there a subtree to which the information processing apparatus 10 can apply the conversion rule for removing the inequality operator with an equal sign from the logical structure data in the tree structure format from which all negations related to the inequality are removed. Determine whether or not.

  FIG. 52 shows a processing flowchart of conversion of an inequality sign with an equal sign by the boundary value constraint generation unit 38.

  In step S601, the boundary value constraint generating unit 38 selects “left node” items in order from the highest node shown in FIGS. 26 and 33, that is, the node whose item value “No” is “0” shown in FIGS. The node in which the item value of “operator” is “inequality sign with equal sign (≦ or ≧)” is searched while following the value and the pointer stored in the “right node” item value.

  Next, in S602, the boundary value constraint generating unit 38 determines whether or not a node whose item value of “operator” is “equal sign with equal sign (≦ or ≧)” has been searched as a result of the search in S601. judge.

  If the boundary value constraint generating unit 38 determines in S602 that the search has been completed, in S603, the item value of the operator of the searched node stored in the RAM 16 is changed from “inequality sign with equal sign” to “logical sum (∨ ) ".

  Next, in S604, the boundary value constraint generating unit 38 sets the item values of the “left node” and “right node” of the searched nodes in the left node item value saving area and the right node item value saving area (not shown) of the RAM 16. Store.

  In step S605, the boundary value constraint generation unit 38 stores “new numbers” in the “left node” and “right node” items of the searched nodes. For example, the boundary value constraint generation unit 38 adds 1 to the maximum value of the No item in the RAM 16 as the “new number” of the “left node”, and sets the “left number” as the “new number”. A value obtained by adding 1 to “new number” of “node” is stored. In addition, you may make it store the arbitrary numbers which are not yet stored in the item value of No of RAM16, respectively.

  Then, in S606, the boundary value constraint generating unit 38 sets “new number” set in the “left node” item in S605 for the “No” item and “equal sign without equal sign” for the “operator” item. ”, The left node item value save area value of the RAM 16 in the“ left node ”item, and the right node item value save area value in the RAM 16 in the“ right node ”item. And are additionally stored in the RAM 16. That is, the boundary value constraint generation unit 38 stores “<” when the item value of “operator” is “≦”, and stores “>” when it is “≧”.

  Further, in S607, the boundary value constraint generating unit 38 sets “No” to the “new number” set in the “right node” item in S605 and “equal sign” to the “operator” item. , The value of the left node item value saving area of the RAM 16 is stored in the “left node” item, and the value of the right node item value saving area of the RAM 16 is set in the “right node” item. And is additionally stored in the RAM 16.

  Note that either of the processes of S606 and S607 may be performed first. The processing flowchart of conversion of inequality signs with equal signs is an example, and any other processing procedure for converting all inequality signs with equal signs contained in a logical expression into a logical sum of logical expressions of equal signs and inequality signs. Use is not denied. If only a solution satisfying the boundary value constraint needs to be obtained, the boundary value constraint generation unit 38 replaces the processing of S604 to S607 with the item value of the “operator” of the searched node as “equal sign”. Only the process of updating from “not equal sign (≦ or ≧)” to “equal sign (=)” may be performed.

  Thereafter, the boundary value constraint generating unit 38 proceeds to the process of S601.

  If the negative standard form conversion unit 34 determines that the result of the search in S601 could not be searched, the negative standard form conversion unit 34 ends the process of conversion of an inequality sign with an equal sign.

  In this way, the boundary value constraint generation unit 38 repeatedly performs the inequality operation with equal sign by repeatedly executing the conversion of the inequality with equal sign until the inequality with equal sign cannot be searched for the logical expression data to be processed. Decompose logical expressions using children. The boundary value constraint generation unit 38 decomposes a logical expression using an inequality operator with an equal sign into a logical expression using an equal sign and a logical expression using an inequality sign. Here, a logical expression using an equal sign represents an upper limit boundary value or a lower limit boundary value related to an input value. A logical expression using an inequality sign represents a value smaller than the upper boundary value or a value larger than the lower boundary value as a representative value of the input value. That is, in order to obtain data satisfying the boundary value test constraints, it is only necessary to obtain logical expressions using equal signs among the decomposed logical expressions. Therefore, the boundary value constraint generating unit 38 may convert an inequality sign with an equal sign to only an equal sign as described above.

In S122, the information processing apparatus 10 executes a conversion process to the disjunctive standard form for the tree-structured logical expression data from which all inequality operators with equal signs are removed.
FIG. 53 shows a processing flowchart of the conversion to the disjunctive standard form by the test data generating unit 40.

  In S701, the test data generation unit 40 sets the “left node” item value in order from the highest node shown in FIGS. 34 and 41, that is, the node whose “No” item value is “0” shown in FIGS. And while tracing the pointer stored in the item value of “right node”, the item value of “operator” is “logical product (∧)” and the item value of “operator” is “logical sum (∨)”. ”Is searched for subtrees in which the node“ ”is continuous.

  Next, in step S <b> 702, the test data generation unit 40 obtains a node whose item value of “operator” is “logical product (∧)” as a result of the search in step S <b> 701, and the item value of “operator” is “logical”. It is determined whether or not a subtree in which nodes that are “sum (∨)” are continuous can be searched.

  If the test data generation unit 40 determines in S702 that the search has been completed, the item value of the upper node of the searched subtree, that is, the “operator” stored in the RAM 16 in S703 is “logical product (７０)”. The item value of “operator” of the node “” is updated from “logical product (∧)” to “logical sum (∨)”.

  Next, in step S704, the test data generation unit 40 uses the left node item value save area and the right node (not shown) of the RAM 16 as the item values of the “left node” and “right node” of the upper nodes of the searched subtree. Store in the item value save area.

  Next, in step S <b> 705, the test data generation unit 40 updates the item values of “left node” and “right node” of the upper nodes of the searched subtree to “new numbers”, respectively. For example, the test data generation unit 40 adds 1 to the maximum value of the No item in the RAM 16 as the “new number” of the “left node”, and sets the “left node” as the “new number” of the “right node”. The value obtained by adding 1 to the “new number” of “” is stored. In addition, you may make it store the arbitrary numbers which are not yet stored in the item value of No of RAM16, respectively.

  Next, in step S706, the test data generation unit 40 selects the “left node” and “right node” items of the nodes under the searched subtree, that is, the nodes whose “operator” item value is “logical sum”. Get the value.

  In step S707, the test data generation unit 40 determines whether the No item value of the lower node of the retrieved subtree matches the value of the left node item value save area.

  If the test data generation unit 40 determines in S707 that they match, the item “No” stored in the “left node” of the upper node in S705 is replaced with the item “Operator” in S708. Is “logical product (∧)”, the item “left node” is the item value of “left node” of the lower node acquired in S706, and the item “right node” is the left node item value saved in the RAM 16. Data of new nodes storing the values of the areas is generated and additionally stored in the RAM 16.

  Further, in S709, the test data generation unit 40 stores “new number” stored in the “right node” of the upper node in S705 for the “No” item, and “logical product (∧) for the“ operator ”item. ””, The “left node” item value of the “right node” of the subordinate node acquired in S706, and the “right node” item store the value of the left node item value save area of the RAM 16, respectively. The new node data is generated and additionally stored in the RAM 16.

  On the other hand, if the test data generation unit 40 determines in S707 that they do not match, in S710, the item “No” is replaced with the “new number” stored in the “left node” of the upper node in S705 as the “operator”. "Logical product (∧)" for the item "", the value of the left node item value saving area of the RAM 16 for the item "left node", and "lower node" obtained in S706 for the item "right node". Data of new nodes each storing the item value of “left node” are generated and additionally stored in the RAM 16.

  Further, in S711, the test data generation unit 40 stores “new number” stored in the “right node” of the upper node in S705 for the “No” item, and “logical product (∧) for the“ operator ”item. ) ", The value of the left node item value saving area of the RAM 16 is stored in the item of" left node ", and the item value of" right node "of the lower node acquired in S706 is stored in the item of" right node ", respectively. The new node data is generated and additionally stored in the RAM 16.

  Thereafter, the negative standard form conversion unit 34 proceeds to the process of S701.

  Then, as a result of the search in S701, the negative standard form conversion unit 34 determines that the item value of the “operator” is “logical product (∧)” and the item value of the “operator” is “logical sum (∨ When it is determined that the subtrees in which the node “)” is continuous cannot be searched, the conversion to the disjunctive standard form is terminated, and the process proceeds to S126 shown in FIG.

  Through the processing in S122 (FIG. 53), the negative standard form logical expression represented by the logical structure data in the tree structure format is converted into the disjunctive standard form logical expression.

  42 and 44 show examples of logical formula data after the processing of S703 to S709 is executed once for the logical formula data shown in FIGS. As shown in this figure, a subtree in which a logical product (∧) and a logical sum (∨) included in the logical data of a tree structure are obtained by subtracting a logical sum (∨) from two lower nodes of the logical product (∧). ) And a process of converting into a subtree represented by the logical sum of two logical products (∧) of the node not focused on as a logical sum and the lower-order nodes of the node focused on as a logical sum. By repeating until the subtree in which the logical product (∧) and the logical sum (連 続) are continuous from the data is eliminated, it can be converted into a disjunctive standard logical expression.

  Returning to the description of FIG. 47, in S126 of FIG. 47, the information processing apparatus 10 converts the logical expression data in the tree structure format representing the logical expression of the disjunctive standard form into the partial tree data for each clause of the disjunctive normal form. To divide. In step S128, the information processing apparatus 10 converts the partial tree data of each section into character string data indicating the logical expression of each section, and stores the character string data in the data generation property storage unit 41.

  In next S130, the information processing apparatus 10 acquires character string data indicating a logical expression of one section from the data generation property storage unit 41. In S132, the information processing apparatus 10 acquires the acquired one section. Character string data indicating a logical expression is output to the satisfiability determination unit 42. At this time, the satisfiability determination unit 42 determines the satisfiability of the logical expression (constraint condition) indicated by the input character string data, and obtains and outputs satisfaction solution data.

  In step S134, the information processing apparatus 10 acquires the satisfaction solution data output from the satisfaction possibility determination unit 42, and stores the satisfaction solution data in the test data table of the test data storage unit 44 as a set of test data. To do.

  In next step S136, the information processing apparatus 10 determines whether or not the processing of S130 to S134 has been executed for all clauses of the disjunctive standard logical expression. If it is determined that there is a clause for which the processing of S130 to S134 has not been performed, the information processing apparatus 10 returns to S130 and executes the processing of S130 to S134 for the unprocessed clause. On the other hand, when it is determined that the processing of S130 to S134 has been executed for all the sections, the information processing apparatus 10 ends the test data generation processing routine.

  Then, using the test data table stored in the test data storage unit 44, the operator causes the information processing apparatus 10 or another apparatus to execute an inspection program for the inspection target software, thereby inspecting the inspection target software. To do.

  As described above, the information processing apparatus 10 according to the present embodiment uses a logical expression of equality with an equal sign as a logical expression using an equal sign in the logical expression data indicating the constraint condition regarding the input value of the software to be inspected. Convert to an expression. Then, this logical expression is converted into the disjunctive standard form, and each clause of the logical expression converted into the disjunctive standard form is output as a logical expression that is input to the SMT solver. Then, the information processing apparatus 10 can generate test data in consideration of the boundary value test regarding the input value by obtaining the satisfiability solution data of the logical expression of each clause.

  In addition, the information processing apparatus 10 according to the present embodiment can automatically generate test data that satisfies business specifications and can be subjected to a boundary value test.

  The information processing apparatus 10 according to the present embodiment can generate a plurality of sets of test data in consideration of all combinations of variations of boundary values related to input values and variations of constraint conditions related to input values. Further, the information processing apparatus 10 can generate more realistic test data from a business specification description that is not conscious of the test.

  In addition, when the boundary value constraint generating unit 38 finds an inequality operator with an equal sign in a logical expression indicating a constraint condition related to an input value, the boundary value constraint generation unit 38 uses the logical expression for an empirical boundary value test in a software test. And a logical expression for testing a representative value of the input value. Thereby, the information processing apparatus 10 can generate test data for testing the representative value and also generate test data for testing the upper boundary value or the lower boundary value.

  In the above-described embodiment, the case where the process of generating test data and the determination process of satisfiability are performed by one information processing apparatus is described as an example, but the present invention is not limited to this. For example, an information processing apparatus different from the information processing apparatus 10 that performs the process of generating test data may perform the satisfiability determination process. In this case, the information processing apparatus 10 performs, for each section of the converted disjunctive standard form logical expression data, other information processing that performs a sufficiency determination process on character string data indicating the logical expression of the section. It outputs to an apparatus and acquires sufficiency solution data from the said other information processing apparatus.

  Further, although the information processing apparatus 10 has been described with respect to an example in which the satisfiability determination process is executed by a program different from the program for executing the test data generation process routine, the information processing apparatus 10 is not limited thereto. Absent. The information processing apparatus 10 may be configured to perform test data generation processing and satisfiability determination processing by a program for executing a test data generation processing routine.

  In addition, the information processing apparatus 10 exemplifies a case where a conversion law for removing an implication operator, a conversion law for removing double negation, and a conversion law based on De Morgan's law are sequentially applied to logical formula data. Although described, the present invention is not limited to this. The information processing apparatus 10 performs other orders on the logical formula data (for example, a conversion law for removing double negation, a conversion law for removing implication operators, and a conversion law based on De Morgan's law). In order), the above conversion law may be applied. In this case, the information processing apparatus 10 may apply the above conversion rule repeatedly until the logical formula data is converted into negative standard logical formula data.

  Further, although the information processing apparatus 10 has been described by way of example of generating test data based on logical expression data indicating the constraint condition regarding the input value of the software to be inspected, the present invention is not limited to this. For example, the information processing apparatus 10 sets the module part of the software as the inspection target, and generates test data related to the input value of the module part based on the logical expression data indicating the constraint condition regarding the input value of the module part to be inspected. It may be.

  The information processing apparatus 10 is not particularly limited with respect to the hardware mechanism. In the above description, the mode in which the program for executing the test data generation processing routine is stored in the HDD 18 has been described. However, the program is stored in a portable recording medium such as a CD-ROM, a DVD-ROM, or a USB memory. It is also possible to provide it in a stored form. For example, as shown in FIG. 54, a recording medium 52 such as a CD-ROM, DVD-ROM, or USB memory storing a program for executing a test data generation processing routine is stored in the drive device 50 of the information processing apparatus 10. Set. Then, a program for executing the test data generation processing routine is installed in the HDD 18 from the recording medium 52 via the drive device 50.

10 Information processing device 12 CPU
14 ROM
16 RAM
18 HDD
30 Property storage unit 32 Logical expression tree structure generation unit 34 Negative normal form conversion unit 36 Inequality sign removal conversion unit 38 Boundary value constraint generation unit 40 Test data generation unit 41 Data generation property storage unit 42 Satisfiability determination unit 44 Test data storage Part

Claims (10)

On the computer,
With reference to the storage unit in which the data of the logical expression indicating the constraint condition regarding the input value of the software to be inspected is stored, it is determined whether the logical expression data includes an inequality sign with an equal sign,
A logical expression conversion program that causes a process of converting the inequalities with an equal sign stored in the storage unit into equal signs when it is determined to be included in the determination. When it is determined that the computer is included in the determination, the logical expression indicated by the inequality with equal sign stored in the storage unit, the logical expression obtained by converting the inequality with equal sign to the equal sign, and the like The logical expression conversion program according to claim 1, wherein the logical expression conversion program executes a process of converting an inequality with a sign into data of a logical expression represented by a logical sum with a logical expression converted to an inequality sign. Further determine whether the logical expression includes an inequality sign that negates,
When it is determined in the determination that the inequality sign that the negation is included is included, the logical expression indicated by the inequality sign that is negative and stored in the storage unit is the data of the logical expression indicated by the inequality sign contrary to the inequality sign The logical expression conversion program according to claim 1, wherein the computer is caused to execute a process of converting into a logical expression. Determine whether the logical expression includes a logical product related to negation,
When it is determined that the logical product related to the negation is included in the determination, the logical formula data indicated by the logical product related to the negation stored in the storage unit is expressed by logical formulas on the left side and the right side of the logical product. Each of which is converted into data of a logical expression represented by a logical sum having one of the logical expressions related to negation and the logical expression related to the negation as the left side and the other as the right side. The logical expression conversion program according to claim 1. Determining whether the logical expression includes a logical sum related to negation;
When it is determined in the determination that the logical sum related to the negation is included, the data of the logical expression indicated by the logical sum related to the negation stored in the storage unit is stored in the left side and the right side of the logical sum operator. Each of the logical expressions is negated, and the computer is caused to execute a process of converting into data of a logical expression represented by a logical product having one of the logical expressions related to the negation as the left side and the other as the right side. The logical expression conversion program according to any one of claims 1 to 4. Determining whether an implication is included in the logical expression;
When it is determined that the implication is included in the determination, the logical expression data indicated by the implication stored in the storage unit is a first logical expression in which the logical expression on the left side of the implication is negated. And causing the computer to execute a process of converting the first logical expression and a logical expression represented by a logical product having one of the right sides of the implication as a left side and the other as a right side. The logical expression conversion program according to any one of 1 to 5. Determining whether the logical expression includes a logical sum related to the logical product;
When it is determined that the logical product related to the logical product is included in the determination, the logical expression data indicated by the logical product related to the logical product stored in the storage unit is set to the left side of the logical product. A first logical sum having a second side as the second side that is a side that is not related to the logical product of the logical sum and the second side, and a right side of the logical product as the first side. The data is converted into data of a logical expression represented by a second logical sum of two sides and a logical product of the first logical sum as the first side and the second logical sum as the second side. The logical expression conversion program according to claim 1, which causes the computer to execute processing. If it is determined in the determination that the logical product does not include the logical sum, the logical expression data stored in the storage unit does not include the logical sum and is combined with the logical product. Divide each sub-expression of the expression,
The logical expression according to claim 7, further comprising: causing the computer to execute a process of storing the data of each of the divided partial logical expressions in the storage unit as logical expression data to be determined for satisfiability. Conversion program. A storage unit that stores data of logical expressions indicating constraints on input values of software to be inspected;
A determination unit that determines whether or not an inequality sign with an equal sign is included in the logical expression stored in the storage unit;
When it is determined that the determination unit is included, a logical expression conversion unit that converts the inequalities with equal sign stored in the storage unit into equal signs,
A logical expression conversion device comprising: Computer
With reference to the storage unit in which the logical expression data indicating the constraint condition regarding the input value of the software to be inspected is stored, it is determined whether or not the logical expression includes an inequality sign with an equal sign,
A logical expression conversion method, comprising: executing a process of converting the inequalities with equal signs stored in the storage unit into equal signs when it is determined that they are included in the determination.

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