JP2012190936A - Device mounting structure of semiconductor device - Google Patents

Device mounting structure of semiconductor device Download PDF

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JP2012190936A
JP2012190936A JP2011052083A JP2011052083A JP2012190936A JP 2012190936 A JP2012190936 A JP 2012190936A JP 2011052083 A JP2011052083 A JP 2011052083A JP 2011052083 A JP2011052083 A JP 2011052083A JP 2012190936 A JP2012190936 A JP 2012190936A
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lead
source
gate
drain
terminal
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Makoto Ijiri
良 井尻
Akiteru Rai
明照 頼
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Sharp Corp
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Sharp Corp
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Priority to JP2011052083A priority Critical patent/JP2012190936A/en
Priority to CN2012800122915A priority patent/CN103415924A/en
Priority to PCT/JP2012/051405 priority patent/WO2012120930A1/en
Publication of JP2012190936A publication Critical patent/JP2012190936A/en
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Abstract

PROBLEM TO BE SOLVED: To achieve a device mounting structure that can take advantage of the merits of low power consumption and high-speed response characteristics of a semiconductor device using GaN.SOLUTION: A GaN device 10 is mounted on a die pad 14 by using a lead frame in which a source lead 15 and die pad 14 are integrally formed. Then, a source terminal 11 of the GaN device is wire-bonded to the die pad 14. This structure reduces leakage current from the rear surface of the chip, reduces on-resistance, reduces loop current between a gate and a source, and reduces parasitic inductance at a source wiring side, thereby preventing oscillation of a gate voltage via parasitic capacitance between the gate and the source.

Description

本発明は、半導体装置に関し、特に、ＧａＮを用いるパワーデバイスチップをフレームに搭載する場合のデバイスの実装構造に関する。   The present invention relates to a semiconductor device, and more particularly to a device mounting structure when a power device chip using GaN is mounted on a frame.

ＧａＮ（窒化ガリウム）に代表される、バンドギャップが２ｅＶを超えるワイドギャップ半導体を用いたデバイスは、従来のＳｉを用いるデバイスと比較して、低消費電力であり、高速スイッチングが可能という利点を備えている。これは、デバイスの絶縁破壊電界が大きいという理由による。   Devices using wide gap semiconductors with a band gap exceeding 2 eV, represented by GaN (gallium nitride), have the advantages of low power consumption and high-speed switching compared with devices using conventional Si. ing. This is because the breakdown electric field of the device is large.

一般に、デバイスの耐圧はドリフト層の長さ（ＷＤ）と絶縁破壊電界（Ｅｃ）の積により表される。従って、耐圧を同じとした場合、絶縁破壊電界が大きい方がドリフト層の長さを短くできる。ここで、ワイドギャップ半導体において、絶縁破壊電界はＳｉよりも１０倍程度高いため、ドリフト層の長さをおよそ１／１０にすることができる。また、不純物濃度は絶縁破壊電界の２乗に比例するため、Ｓｉと比べて１００倍に高くすることができる。以上より、耐圧を同じとした場合、ワイドギャップ半導体を用いたデバイスのオン抵抗（Ｒｏｎ）は、Ｓｉを用いるデバイスと比較して約１／１０００に低抵抗化が可能となる。   In general, the breakdown voltage of a device is represented by the product of the drift layer length (WD) and the breakdown electric field (Ec). Therefore, when the breakdown voltage is the same, the length of the drift layer can be shortened when the breakdown electric field is large. Here, in the wide gap semiconductor, since the dielectric breakdown electric field is about 10 times higher than Si, the length of the drift layer can be reduced to about 1/10. Further, since the impurity concentration is proportional to the square of the dielectric breakdown electric field, it can be made 100 times higher than Si. As described above, when the breakdown voltage is the same, the on-resistance (Ron) of the device using the wide gap semiconductor can be reduced to about 1/1000 compared to the device using Si.

一方、デバイスの高速応答性を表す指標として、遮断周波数（ｆＴ）という指標がある。当該遮断周波数はデバイスの電流利得が１となる周波数であり、ドリフト層の長さＷＤに反比例する。従って、ワイドギャップ半導体を用いるデバイスでは、ドリフト層の長さをＳｉと比べて１／１０に設定できることにより、Ｓｉよりも一桁高い周波数で使用することが可能となる。   On the other hand, there is an index called cutoff frequency (fT) as an index representing the high-speed response of the device. The cutoff frequency is a frequency at which the current gain of the device is 1, and is inversely proportional to the length WD of the drift layer. Therefore, in a device using a wide gap semiconductor, since the length of the drift layer can be set to 1/10 compared to Si, it can be used at a frequency one digit higher than Si.

このように、ワイドギャップ半導体を用いることで、Ｓｉと比較してオン抵抗が低く、結果低消費電力で、且つ、高速性に優れたデバイスが可能である。   As described above, by using a wide gap semiconductor, a device having a low on-resistance as compared with Si, resulting in low power consumption and excellent high-speed performance is possible.

上記のワイドギャップ半導体を用いるデバイスの実装方法として、下記特許文献１および２に示すように、ドレインリードとダイパッドを接続したリードフレームのダイパッド上にデバイスを固定し、デバイスとドレインリード、ソースリード、及び、ゲートリードとの接続をワイヤボンディングにより行う方法が、従来より用いられてきた。   As a device mounting method using the above wide gap semiconductor, as shown in Patent Documents 1 and 2, the device is fixed on the die pad of the lead frame in which the drain lead and the die pad are connected, and the device and the drain lead, the source lead, A method of connecting to the gate lead by wire bonding has been conventionally used.

特開２００８−６６５５３号公報JP 2008-66553 A 特開２０１０−１６１０３号公報JP 2010-16103 A

従来のＳｉパワーデバイスでは、ゲート注入電荷量Ｑｇが大きいため、寄生発振が起こるような大きなインダクタンスは回路側で対応が可能であり、デバイス実装において、回路の寄生インダクタンスについて特別の注意を払う必要がなかった。   In the conventional Si power device, since the gate injection charge amount Qg is large, a large inductance that causes parasitic oscillation can be dealt with on the circuit side, and it is necessary to pay special attention to the parasitic inductance of the circuit when mounting the device. There wasn't.

ところが、ＧａＮを用いたデバイスでは、ゲート注入電荷量Ｑｇが非常に小さいため、単なる配線の寄生インダクタンスであってもゲート電圧が発振することがわかった。   However, in the device using GaN, it was found that the gate voltage oscillates even if the parasitic inductance of the wiring is simple because the gate injection charge amount Qg is very small.

これに対し、ゲート抵抗として大きなものをゲート端子に接続することで発振は抑制できるが、ＧａＮの低消費電力、高速応答性の長所を生かすことができない結果となる。   On the other hand, oscillation can be suppressed by connecting a large gate resistance to the gate terminal, but the advantages of low power consumption and high-speed response of GaN cannot be utilized.

本発明は、上記の状況に鑑み、ＧａＮを用いたデバイスにおいて、大きなゲート抵抗を付加することなく寄生発振を抑制できるように、デバイス実装構造の面から寄生インダクタンスの低減を実現するものであり、これにより、ＧａＮの特徴である低消費電力、高速応答特性を生かしたパワーデバイスを実現することを目的とする。   In view of the above situation, the present invention realizes a reduction in parasitic inductance from the surface of a device mounting structure so that parasitic oscillation can be suppressed without adding a large gate resistance in a device using GaN. Accordingly, it is an object to realize a power device that takes advantage of the low power consumption and high-speed response characteristics that are characteristic of GaN.

上記目的を達成するための本発明に係る半導体装置は、
ソース端子、ドレイン端子、ゲート端子の少なくとも三端子が基板表面側に設けられた、ＧａＮを用いるパワーデバイスが、ソースリード部とダイパッド部とが一体成形されたリードフレームの前記ダイパッド部に搭載され、
前記パワーデバイスの前記ソース端子が前記ダイパッド部とワイヤ接続され、
前記パワーデバイスの前記ドレイン端子がドレインリードと、前記パワーデバイスの前記ゲート端子がゲートリードとワイヤ接続されてなるデバイス実装構造を有することを特徴とする。 In order to achieve the above object, a semiconductor device according to the present invention provides:
A power device using GaN in which at least three terminals of a source terminal, a drain terminal, and a gate terminal are provided on the substrate surface side is mounted on the die pad portion of a lead frame in which a source lead portion and a die pad portion are integrally formed,
The source terminal of the power device is wire-connected to the die pad portion;
The power device has a device mounting structure in which the drain terminal of the power device is connected to a drain lead, and the gate terminal of the power device is connected to the gate lead by wire.

上記特徴の半導体装置は、更に、前記ドレインリードが、前記ゲートリードと前記リードフレームの前記ソースリード部との間に配置されることが好ましい。   In the semiconductor device having the above characteristics, the drain lead is preferably disposed between the gate lead and the source lead portion of the lead frame.

上記特徴の半導体装置は、更に、前記パワーデバイスを構成するトランジスタが、
前記ソース端子と接続するソース電極、前記ドレイン端子と接続するドレイン電極、及び、前記ゲート端子と接続するゲート電極を備え、前記ゲート電極が前記ドレイン電極よりも前記ソース電極側に片寄って配置される非対称構造を有することが好ましい。 In the semiconductor device having the above characteristics, the transistor constituting the power device further includes:
A source electrode connected to the source terminal; a drain electrode connected to the drain terminal; and a gate electrode connected to the gate terminal, wherein the gate electrode is disposed closer to the source electrode side than the drain electrode. It preferably has an asymmetric structure.

上記特徴の半導体装置は、更に、前記ドレインリード内の樹脂封止されるインナーリード部分の面積が、前記ゲートリード内の樹脂封止されるインナーリード部分の面積よりも大きいことが好ましい。   In the semiconductor device having the above characteristics, it is preferable that the area of the inner lead portion to be resin-sealed in the drain lead is larger than the area of the inner lead portion to be resin-sealed in the gate lead.

上記特徴の半導体装置は、更に、前記リードフレームの前記ソースリードには、前記ドレインリードよりも低電圧が供給されることが好ましい。   In the semiconductor device having the above characteristics, it is preferable that a lower voltage is supplied to the source lead of the lead frame than to the drain lead.

本発明者等は、鋭意研究により、ソース側配線の寄生インダクタンスを小さくすることで、発振が抑制され、ゲート電圧のオンオフに対して安定なスイッチングが可能になることを見出した。   The inventors of the present invention have intensively researched and found that by reducing the parasitic inductance of the source-side wiring, oscillation is suppressed and stable switching can be performed with respect to on / off of the gate voltage.

図５にシミュレーションに用いた回路の構成を示す。Ｌｄ、Ｌｓ１、Ｌｓ２、Ｌｇｓは夫々配線の寄生インダクタンスであり、Ｃｇｄ，Ｃｇｓ，Ｃｄｓは夫々ＧａＮ−ＦＥＴの寄生容量である。図５において、ＦＥＴがオンからオフに、オフからオンに切り替わると、ＬｄからＣｏｓｓ、Ｌｓ１、及びＬｓ２を介したＬＣ直列回路が共振する。結果、Ｌｓ１の両端電圧が振動する。当該Ｌｓ１の両端電圧の振動は、ゲートドライバにとって電圧ノイズ源となる。   FIG. 5 shows the configuration of the circuit used for the simulation. Ld, Ls1, Ls2, and Lgs are parasitic inductances of wirings, respectively, and Cgd, Cgs, and Cds are parasitic capacitances of GaN-FETs. In FIG. 5, when the FET is switched from on to off and from off to on, the LC series circuit from Ld to Coss, Ls1, and Ls2 resonates. As a result, the voltage across Ls1 vibrates. The vibration of the voltage across Ls1 becomes a voltage noise source for the gate driver.

更に、Ｌｓ１の両端電圧が振動することにより、ＣｇｓとＬｓ１を介したＬＣ直列回路が共振し、ゲート電圧Ｖｇが振動する。この結果、ＦＥＴの意図しないオンオフが繰り返され、これが更にＬｄからＣｏｓｓ、Ｌｓ１、及びＬｓ２を介したＬＣ直列回路の共振を引き起こす。   Furthermore, when the voltage across Ls1 vibrates, the LC series circuit via Cgs and Ls1 resonates, and the gate voltage Vg vibrates. As a result, unintended ON / OFF of the FET is repeated, which further causes resonance of the LC series circuit from Ld to Coss, Ls1, and Ls2.

このように、ＬｄからＣｏｓｓ、Ｌｓ１、及びＬｓ２を介したＬＣ直列回路の共振と、ＣｇｓとＬｓ１を介したＬＣ直列回路の共振が相互に誘起される結果、ゲート電圧Ｖｇの振動が増幅され、スイッチングノイズが増加し、最悪の場合ＦＥＴが発振して回路が破壊される虞がある。   As described above, the resonance of the LC series circuit via Loss and Coss, Ls1, and Ls2 and the resonance of the LC series circuit via Cgs and Ls1 are mutually induced. As a result, the oscillation of the gate voltage Vg is amplified. The switching noise increases, and in the worst case, the FET may oscillate and the circuit may be destroyed.

上記のＬＣ回路による共振を防ぐには、ＬｄとＬｓ１（及び、Ｌｓ２）をできる限り小さくすればよいことが推察される。   It can be inferred that Ld and Ls1 (and Ls2) should be as small as possible in order to prevent resonance by the LC circuit.

図６は、ソース側配線の寄生インダクタンスＬｓ１、及び、ドレイン側配線の寄生インダクタンスＬｄを変えた場合の、スイッチング時のゲート電圧の立ち上がり、立ち下がりの電圧変化をシミュレーションした結果である。図６より、ドレイン側配線の寄生インダクタンスＬｄを小さくする（図６（ｂ））よりも、むしろソース側配線の寄生インダクタンスＬｓ１を小さくした（図６（ａ））方が、ゲート電圧の振動防止に著しい効果があることが分かる。   FIG. 6 shows the result of simulating the rise and fall of the gate voltage during switching when the parasitic inductance Ls1 of the source side wiring and the parasitic inductance Ld of the drain side wiring are changed. From FIG. 6, the gate voltage oscillation is prevented by reducing the parasitic inductance Ls1 of the source side wiring (FIG. 6A) rather than reducing the parasitic inductance Ld of the drain side wiring (FIG. 6B). It can be seen that there is a remarkable effect.

図７は、図６においてＦＥＴに生じる電力損失（＝Ｉｆｅｔ＊Ｖｄ）を示す図であり、図７より、ドレイン側配線の寄生インダクタンスＬｄを小さくする（図７（ｂ））よりも、ソース側配線の寄生インダクタンスＬｓ１を小さくした（図７（ａ））方が、損失も少ないことが分かる。   FIG. 7 is a diagram showing the power loss (= Ifet * Vd) generated in the FET in FIG. 6. Compared to FIG. 7, the parasitic inductance Ld of the drain side wiring is made smaller (FIG. 7B) than the source side. It can be seen that the loss is reduced when the parasitic inductance Ls1 of the wiring is reduced (FIG. 7A).

上記の知見に基づき、本発明では、デバイスの実装方法を変更し、従来のＳｉＭＯＳＦＥＴにおいてはドレインリードと接続していたダイパッドを、ソースリードと接続することとし、当該ダイパッドとデバイスのソース端子との接続をワイヤボンディングにより行うこととした。これにより、従来のダイパッドとドレインリードを一体成形した構造と比較して、ＧａＮチップのソース端子とチップ裏面の電位差を小さくできるため、チップ裏面からのリーク電流を減らし、オン抵抗を小さくすることができる。また、ゲート−ソース間のループ電流が小さくなることでソース配線の寄生インダクタンスが抑制され、Ｃｇｓを介したＬＣ直列回路の発振を抑えることができる。   Based on the above knowledge, in the present invention, the device mounting method is changed, and the die pad connected to the drain lead in the conventional SiMOSFET is connected to the source lead, and the die pad and the source terminal of the device are connected. The connection was made by wire bonding. As a result, the potential difference between the source terminal of the GaN chip and the back surface of the chip can be reduced as compared with the conventional structure in which the die pad and the drain lead are integrally formed. it can. In addition, since the gate-source loop current is reduced, the parasitic inductance of the source wiring is suppressed, and the oscillation of the LC series circuit via Cgs can be suppressed.

従って、本発明に依れば、ＧａＮを用いたデバイスにおいて、大きなゲート抵抗を付加することなく寄生発振を抑制でき、ＧａＮの特徴である低消費電力、高速応答特性を生かしたパワーデバイスを実現することができる。   Therefore, according to the present invention, in a device using GaN, parasitic oscillation can be suppressed without adding a large gate resistance, and a power device utilizing the low power consumption and high-speed response characteristics of GaN is realized. be able to.

本発明に係る半導体装置のチップ実装例Chip mounting example of semiconductor device according to the present invention 従来技術に係る半導体装置のチップ実装例Example of chip mounting of a semiconductor device according to the prior art ＧａＮを用いるパワーデバイスのデバイス構造を示す断面図。Sectional drawing which shows the device structure of the power device using GaN. 本発明に係る半導体装置の他のチップ実装例Other chip mounting examples of the semiconductor device according to the present invention 本発明の課題を説明するための回路図The circuit diagram for explaining the subject of the present invention 本発明の効果を説明するためのグラフであり、スイッチング時のゲート電圧の立ち上がり及び立ち下がりの、ゲート電圧の変化を示すグラフIt is a graph for demonstrating the effect of this invention, and is a graph which shows the change of the gate voltage of the rise and fall of the gate voltage at the time of switching 本発明の効果を説明するためのグラフであり、スイッチング時においてＦＥＴに生じる電力損失の時間変化を示すグラフIt is a graph for demonstrating the effect of this invention, and is a graph which shows the time change of the power loss which arises in FET at the time of switching

〈第１実施形態〉
本発明のチップ実装構造を有する半導体装置１０の構成例を図１に示す。図１は、半導体装置１０の実装後の形態の模式図である。尚、比較のため、従来の方法で半導体装置１０をチップ実装した場合の実装後の形態の模式図を、図２に示す。尚、以降の実施形態の説明に用いる図面では、同一の構成要素には同一の符号を付すこととし、また、名称及び機能も同一であるので、同様の説明を繰り返すことはしない。 <First Embodiment>
A configuration example of a semiconductor device 10 having a chip mounting structure of the present invention is shown in FIG. FIG. 1 is a schematic diagram of a form after the semiconductor device 10 is mounted. For comparison, FIG. 2 shows a schematic diagram of a form after mounting when the semiconductor device 10 is mounted on a chip by a conventional method. In the drawings used for the description of the following embodiments, the same components are denoted by the same reference numerals, and the names and functions are also the same, so the same description will not be repeated.

半導体装置１０は、ＧａＮを用いて構成されるパワーデバイスであり、基板表面側に、ソース端子１１、ドレイン端子１２、ゲート端子１３が形成されている。そして、ダイパッド１４上に半導体装置１０が搭載され、固定されている。   The semiconductor device 10 is a power device configured using GaN, and a source terminal 11, a drain terminal 12, and a gate terminal 13 are formed on the substrate surface side. The semiconductor device 10 is mounted and fixed on the die pad 14.

ＧａＮを用いる当該パワーデバイスのデバイス構造の模式的な断面図を図３に示す。図３に示すデバイスは、ＨＥＭＴ(High Electron Mobility Transistor)構造のＦＥＴであり、Ｓｉ基板２０上に、ＡｌとＧａの組成比が異なるＡｌＧａＮの多層膜からなるバッファ層２１を介してＧａＮ層２２が積層され、ＧａＮ層２２の上にＡｌＧａＮの層２３が積層されている。ＧａＮ層２２上の所定の領域には、ＡｌＧａＮ層２３を貫通するようにソース電極２４とドレイン電極２５が形成され、ゲート電極２６が、ＡｌＧａＮ層２３上の所定の領域に、ソース電極２４とドレイン電極２５がゲート電極２６を挟んで互いに対向するように形成されている。ドレイン電極２５は、絶縁膜２７上に形成されたドレイン端子１２と、コンタクトホール２８を介して電気的に接続される。同様に、図示しないが、ソース電極２４は、別の断面において、絶縁膜２７上に形成されたソース端子１１と電気的に接続され、ゲート電極２５は、更に別の断面において、絶縁膜２７上に形成されたゲート端子１３と電気的に接続される。   FIG. 3 shows a schematic cross-sectional view of the device structure of the power device using GaN. The device shown in FIG. 3 is an FET having a HEMT (High Electron Mobility Transistor) structure, and a GaN layer 22 is formed on a Si substrate 20 via a buffer layer 21 made of an AlGaN multilayer film having different composition ratios of Al and Ga. The AlGaN layer 23 is laminated on the GaN layer 22. A source electrode 24 and a drain electrode 25 are formed in a predetermined region on the GaN layer 22 so as to penetrate the AlGaN layer 23, and a gate electrode 26 is formed in the predetermined region on the AlGaN layer 23. The electrodes 25 are formed so as to face each other with the gate electrode 26 interposed therebetween. The drain electrode 25 is electrically connected to the drain terminal 12 formed on the insulating film 27 through the contact hole 28. Similarly, although not shown, the source electrode 24 is electrically connected to the source terminal 11 formed on the insulating film 27 in another cross section, and the gate electrode 25 is formed on the insulating film 27 in another cross section. Are electrically connected to the gate terminal 13 formed in the circuit.

ＡｌＧａＮ層２３とＧａＮ層２２とのヘテロ接合界面近傍において、２次元電子ガス層２９が形成され、ゲート電極２６に電圧（ゲート電圧）を印加することで、当該ゲート電極２６の下方の当該２次元電子ガス層の濃度が変調され、ソース電極２４とドレイン電極２５間に流れる電流が制御される。尚、図３に示すデバイスは、ドレイン電極２５に印加される電圧とゲート電圧との差が高電圧となるため、放電しないようにゲート電極２６とドレイン電極２５との距離を、ゲート電極２６とソース電極２４との距離よりも大きくとり、ゲート電極２６がドレイン電極２５よりもソース電極２４側に片寄って配置された非対称なデバイス構造を有している。   In the vicinity of the heterojunction interface between the AlGaN layer 23 and the GaN layer 22, a two-dimensional electron gas layer 29 is formed, and by applying a voltage (gate voltage) to the gate electrode 26, the two-dimensional electron gas layer 29 below the gate electrode 26. The concentration of the electron gas layer is modulated, and the current flowing between the source electrode 24 and the drain electrode 25 is controlled. In the device shown in FIG. 3, since the difference between the voltage applied to the drain electrode 25 and the gate voltage becomes a high voltage, the distance between the gate electrode 26 and the drain electrode 25 is set so as not to discharge. The device has an asymmetric device structure in which the gate electrode 26 is arranged closer to the source electrode 24 side than the drain electrode 25 with a distance greater than the distance from the source electrode 24.

図１及び図２に戻ると、半導体装置１０に隣接して、ソースリード１５、ドレインリード１６、ゲートリード１７がこの順で形成されている。即ち、ドレインリード１６が、ゲートリード１７とソースリード１５の間に挟まれて配置されている。これらのリード端子１５，１６，１７は夫々、半導体装置１のソース端子１１、ドレイン端子１２、ゲート端子１３とワイヤ接続（ワイヤボンディング）される。更に、図１又は図２の点線で示す領域１８内において、ワイヤ接続される部分を覆うように樹脂封止がされ、半導体装置１０がパッケージされる。   Returning to FIG. 1 and FIG. 2, a source lead 15, a drain lead 16, and a gate lead 17 are formed in this order adjacent to the semiconductor device 10. That is, the drain lead 16 is disposed between the gate lead 17 and the source lead 15. These lead terminals 15, 16, and 17 are respectively connected to the source terminal 11, the drain terminal 12, and the gate terminal 13 of the semiconductor device 1 by wire connection (wire bonding). Further, resin sealing is performed so as to cover the wire-connected portion in the region 18 indicated by the dotted line in FIG. 1 or FIG. 2, and the semiconductor device 10 is packaged.

本発明では、図１に示すように、ソースリード１５とダイパッド１４は、両者が一体成形されてリードフレームを構成しており、ソース端子１１とソースリード１５の接続が、ソース端子１１とダイパッド１４をワイヤボンディングすることによりなされている。一方、ドレインリード１６及びゲートリード１７は、夫々、ダイパッド１４と分離形成され、ドレインリード１６とドレイン端子１２、ゲートリード１７とゲート端子１３との接続が、ワイヤボンディングによりなされている。   In the present invention, as shown in FIG. 1, the source lead 15 and the die pad 14 are integrally formed to form a lead frame, and the connection between the source terminal 11 and the source lead 15 is connected to the source terminal 11 and the die pad 14. Are made by wire bonding. On the other hand, the drain lead 16 and the gate lead 17 are formed separately from the die pad 14, and the drain lead 16 and the drain terminal 12, and the gate lead 17 and the gate terminal 13 are connected by wire bonding.

これに対し、従来例では、図２に示すように、ドレインリード１６とダイパッド１４が一体成形されてリードフレームを構成しており、ドレイン端子１２とドレインリード１６の接続が、ドレイン端子１２とダイパッド１４をワイヤボンディングすることによりなされている。一方、ソースリード１５及びゲートリード１７は、夫々、ダイパッド１４と分離形成され、ソースリード１５とソース端子１１、ゲートリード１７とゲート端子１３との接続が、ワイヤボンディングによりなされている。   On the other hand, in the conventional example, as shown in FIG. 2, the drain lead 16 and the die pad 14 are integrally formed to constitute a lead frame, and the connection between the drain terminal 12 and the drain lead 16 is connected to the drain terminal 12 and the die pad. 14 is formed by wire bonding. On the other hand, the source lead 15 and the gate lead 17 are formed separately from the die pad 14, and the source lead 15 and the source terminal 11 and the gate lead 17 and the gate terminal 13 are connected by wire bonding.

上述の通り、本発明では、ソースリード１５とダイパッド１４が一体成形され、ソース端子１１とダイパッド１４がワイヤボンディングされて接続されているため、チップ裏面の電位を介して基板の電位がソース電圧に固定され、基板を経由してチップ裏面に流れるリーク電流を減らし、結果、オン抵抗を小さくすることができる。また、ソース配線の寄生インダクタンスが抑制され、ゲート電圧の発振を抑えることができる。   As described above, in the present invention, since the source lead 15 and the die pad 14 are integrally formed and the source terminal 11 and the die pad 14 are connected by wire bonding, the potential of the substrate becomes the source voltage via the potential on the back surface of the chip. The leakage current that is fixed and flows to the back surface of the chip via the substrate can be reduced, and as a result, the on-resistance can be reduced. Further, the parasitic inductance of the source wiring is suppressed, and the oscillation of the gate voltage can be suppressed.

尚、本発明では、ドレインリード１６はドレイン端子１２とワイヤボンディングされるが、このため、ドレインリード１６とダイパッド１４が一体成形され、ドレイン端子１２とダイパッド１４をワイヤボンディングされる従来の構成（図２）と比較すると、ドレイン配線の寄生インダクタンスはかえって増加することとなる。しかしながら、図６より、ソース配線側の寄生インダクタンス（図５のＬｓ１）を低減することが、ドレイン配線側の寄生インダクタンス（図５のＬｄ）を低減することよりも、ゲート電圧の発振を抑制するという点において重要であることが示されている。別の言い方をすると、図６は、ゲート電圧の発振を抑制するという点において、ソース配線側の寄生インダクタンスを低減することで、ドレイン配線の寄生インダクタンスが増加することによるデメリットをはるかに上回るメリットが得られることを示すものである。そして、本発明は、これを積極的に利用するものである。   In the present invention, the drain lead 16 is wire-bonded to the drain terminal 12. For this reason, the drain lead 16 and the die pad 14 are integrally formed, and the drain terminal 12 and the die pad 14 are wire-bonded in a conventional configuration (FIG. Compared with 2), the parasitic inductance of the drain wiring increases on the contrary. However, from FIG. 6, reducing the parasitic inductance on the source wiring side (Ls1 in FIG. 5) suppresses the oscillation of the gate voltage than reducing the parasitic inductance on the drain wiring side (Ld in FIG. 5). In that respect. In other words, FIG. 6 has the advantage that the parasitic inductance on the source wiring side is reduced and the disadvantage due to the increase in the parasitic inductance of the drain wiring is much reduced in that the oscillation of the gate voltage is suppressed. It shows that it is obtained. And this invention utilizes this positively.

更に、半導体装置１０の他の実装例を図４に示す。図４では、ドレインリード１６の領域１８との重なり部分、即ちドレインリード１６内の樹脂封止される部分（インナーリード）の面積を、ゲートリード１７の領域１８との重なり部分、即ちゲートリード１７内の樹脂封止される部分の面積よりも大きくしている。上記ドレインリード１６（ゲートリード１７）の樹脂封止される部分は、ワイヤボンディングが可能な部分の面積に相当する。ドレインリード１６のワイヤボンディング可能な部分の面積を大きくすることで、ドレインリード１６とドレイン端子１２との接続を、複数のワイヤを介して行うことが可能になるため、ソース配線側の寄生インダクタンスと併せて、ドレイン配線側の寄生インダクタンスを低減することが可能になる。これにより、ゲート電圧の発振を防止できるとともに、オン抵抗を削減することができる。   Furthermore, another mounting example of the semiconductor device 10 is shown in FIG. In FIG. 4, the area of the portion of the drain lead 16 overlapping the region 18, that is, the area of the resin lead-sealed portion (inner lead) in the drain lead 16 is the same as the portion of the gate lead 17 overlapping the region 18, that is, the gate lead 17. The area is larger than the area of the resin-sealed portion. The resin-sealed portion of the drain lead 16 (gate lead 17) corresponds to the area of the portion where wire bonding is possible. By increasing the area of the portion of the drain lead 16 that can be wire bonded, the drain lead 16 and the drain terminal 12 can be connected via a plurality of wires. In addition, the parasitic inductance on the drain wiring side can be reduced. As a result, oscillation of the gate voltage can be prevented and on-resistance can be reduced.

本発明は、ＧａＮをスイッチング素子として用いるパワーデバイスの実装に利用可能である。   The present invention can be used for mounting a power device using GaN as a switching element.

１０： 半導体装置（ＧａＮデバイス）
１１： ソース端子
１２： ドレイン端子
１３： ゲート端子
１４： ダイパッド
１５： ソースリード
１６： ドレインリード
１７： ゲートリード
１８： 樹脂封止される領域
２０： 基板
２１： バッファ層
２２： ＧａＮ層
２３： ＡｌＧａＮ層
２４： ソース電極
２５： ドレイン電極
２６： ゲート電極
２７： 絶縁膜
２８： コンタクトホール
２９： ２次元電子ガス 10: Semiconductor device (GaN device)
11: Source terminal 12: Drain terminal 13: Gate terminal 14: Die pad 15: Source lead 16: Drain lead 17: Gate lead 18: Resin-sealed region 20: Substrate 21: Buffer layer 22: GaN layer 23: AlGaN layer 24: Source electrode 25: Drain electrode 26: Gate electrode 27: Insulating film 28: Contact hole 29: Two-dimensional electron gas

Claims (5)

ソース端子、ドレイン端子、ゲート端子の少なくとも三端子が基板表面側に設けられた、ＧａＮを用いるパワーデバイスが、
ソースリード部とダイパッド部とが一体成形されたリードフレームの前記ダイパッド部に搭載され、
前記パワーデバイスの前記ソース端子が前記ダイパッド部とワイヤ接続され、
前記パワーデバイスの前記ドレイン端子がドレインリードと、前記パワーデバイスの前記ゲート端子がゲートリードとワイヤ接続されてなるデバイス実装構造を有する半導体装置。 A power device using GaN, in which at least three terminals of a source terminal, a drain terminal, and a gate terminal are provided on the substrate surface side,
Mounted on the die pad portion of the lead frame in which the source lead portion and the die pad portion are integrally molded,
The source terminal of the power device is wire-connected to the die pad portion;
A semiconductor device having a device mounting structure in which the drain terminal of the power device is connected to a drain lead, and the gate terminal of the power device is connected to a gate lead by wire. 前記ドレインリードが、前記ゲートリードと前記リードフレームの前記ソースリード部との間に配置されることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the drain lead is disposed between the gate lead and the source lead portion of the lead frame. 前記パワーデバイスを構成するトランジスタが、
前記ソース端子と接続するソース電極、前記ドレイン端子と接続するドレイン電極、及び、前記ゲート端子と接続するゲート電極を備え、
前記ゲート電極が前記ドレイン電極よりも前記ソース電極側に片寄って配置される非対称構造を有することを特徴とする請求項１または２に記載の半導体装置。 Transistors constituting the power device are
A source electrode connected to the source terminal; a drain electrode connected to the drain terminal; and a gate electrode connected to the gate terminal;
The semiconductor device according to claim 1, wherein the gate electrode has an asymmetric structure in which the gate electrode is arranged closer to the source electrode side than the drain electrode. 前記ドレインリード内の樹脂封止されるインナーリード部分の面積が、前記ゲートリード内の樹脂封止されるインナーリード部分の面積よりも大きいことを特徴とする請求項１〜３の何れか１項に記載の半導体装置。   The area of the inner lead portion to be resin-sealed in the drain lead is larger than the area of the inner lead portion to be resin-sealed in the gate lead. A semiconductor device according to 1. 前記リードフレームの前記ソースリードには、前記ドレインリードよりも低電圧が供給されることを特徴とする請求項１〜４の何れか一項に記載の半導体装置。
The semiconductor device according to claim 1, wherein a voltage lower than that of the drain lead is supplied to the source lead of the lead frame.
JP2011052083A 2011-03-09 2011-03-09 Device mounting structure of semiconductor device Pending JP2012190936A (en)

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