JP2012185803A - Reconfiguration device, processing arrangement method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit configuration modification period while avoiding the dependence on processing content, without increasing a circuit scale by mechanism addition, in the circuit configuration modification of a reconfiguration device.SOLUTION: An external memory 101 holds therein circuit configuration information 106. The circuit configuration information 106 is a setting group for operating elements constituting a reconfiguration device 105. A configuration controller 102 acquires the circuit configuration information 106 from the memory 101 through a connecting wire 104. The acquired circuit configuration information 106 is transmitted to the reconfiguration device 105 through a connecting wire 103.

Description

  The present invention relates to a reconfigurable device capable of changing a circuit configuration, a processing arrangement method thereof, and the like.

  Conventionally, there has been proposed a reconfigurable device capable of changing the processing content performed by the above circuit by changing the internal circuit configuration even in an LSI circuit device after manufacture. Since the processing can be changed even in the manufactured LSI circuit device, it is not necessary to recreate the LSI in accordance with the specification change or the like. Currently, reconfigurable devices are used in various fields in that the manufacturing cost can be reduced and the development period can be shortened.

  As a configuration of the reconfigurable device, a type in which a large number of LUTs (Look-Up-Tables) are mounted and a type in which a large number of processing elements are mounted are typical. Each element is connected to a switching element such as a multiplexer. Here, settings for operating each component such as the LUT, processing element, and switching element are collectively referred to as circuit configuration information. There are various methods for generating circuit configuration information. Generally, (1) logical processing called technology mapping, (2) physical allocation to each component, (3) route determination of each component, These processes are often performed in order. The circuit configuration information is finally generated through the above three steps.

  (1) In the logical process assignment step, the process is assigned to a component. Specifically, each process is assigned to a logical component without specifying a physical component. As an index for order change, the viewpoint of circuit area, operation speed, and power consumption is generally used. (2) In the placement step, physical assignment of which process is performed with which component in the reconfigurable device is determined. Since the number of switching elements related to data communication differs depending on the distance between processing elements in which processing related to data input / output is arranged, the delay time (maximum operating frequency) varies greatly. For this reason, it is usually important to arrange the processing having an input / output relationship on the processing elements as close as possible to shorten the delay time. (3) In the route determination step, a route by the switching element is determined for data communication between processing elements in an input / output relationship of data communication. In order to determine a specific path as compared with the arrangement process, it is important to determine a path with a reduced delay time between processing elements.

  In recent years, the scale of processing that can be executed in the reconfigurable device is increasing with the improvement in the degree of integration. However, recently, the demand for processing itself has become more complicated and sophisticated than that, and it may be difficult to perform all processing at once with one reconfigurable device. In contrast, there is a method in which processing is sequentially performed in a time-division manner in one reconfigurable device. More specifically, first, a desired process is divided, and circuit configuration information corresponding to the divided process is generated. Thereafter, the circuit configuration of the reconfigurable device is changed and processed based on the circuit configuration information. This makes it possible to perform large-scale processing with the reconfigurable device. However, if all the circuit configurations are changed every time, the entire processing time becomes long, and the speed performance deteriorates. Similarly, when the number of processing divisions is large, the processing speed is deteriorated.

  As a method for solving this problem, there is a multi-context reconfiguration device. The context is circuit configuration information, and the multi-context reconfiguration device is a device in which a memory for storing a plurality of circuit configuration information is mounted in the reconfiguration device. When the circuit configuration is changed, the device can be reconfigured by switching the memory, and the circuit reconfiguration time can be greatly reduced by switching at high speed. However, since it is necessary to additionally install a memory for circuit configuration information, there is a problem that the circuit scale increases.

  On the other hand, Patent Document 1 proposes a method based on a skeleton circuit technique as a method for shortening the reconstruction time. In this method, circuit configuration information called a preceding base circuit is configured in advance in a reconfigurable device. Here, the preceding base circuit is a common circuit portion that is common to all of the plurality of circuit configuration information, and a non-exclusive independent circuit that is not common to the plurality of circuits and that does not share the circuit configuration information on the reconfigurable device. This is circuit configuration information consisting of parts. By partially reconfiguring only the circuit differences on the reconfigurable device, a circuit necessary for processing is configured. Compared with the multi-context type, this method does not require an additional configuration memory, so that the circuit scale does not increase.

Japanese Patent No. 3558119

  However, in general, the reconstruction device may execute various applications, and the number of common parts is reduced depending on the application. Further, the number of circuit configuration information to be reconfigured varies depending on the application. In the generation of the preceding base circuit unit described in Patent Document 1, when there are few common parts or the number of circuit configuration information is large and greatly exceeds the circuit scale of the reconfigurable device, the circuit configuration is changed. It is difficult to reduce the period efficiently. Further, in the processing arrangement process described above, in addition to reducing the change period of the circuit configuration, the distance between the processing elements in the data input / output relationship needs to be short. When the communication distance between the processing elements related to input / output is long, the delay time of data communication is increased, and as a result, the entire processing period is increased.

  The present invention has been made in view of the above-described problems, and by considering the order of circuit configuration change, the circuit change period can be efficiently performed without increasing the circuit scale while suppressing the data communication delay between the processing elements. The purpose is to reduce.

  The processing leaf position method of the present invention is a processing arrangement method for determining a constituent element that performs each processing of a data flow for a reconfigurable device composed of a plurality of constituent elements, and is at least two different data flows And an input step for inputting the processing order of the data flow, a constraint step for inputting constraints on the components of the reconfigurable device, the number of setting changes necessary for the reconfiguration according to the data flow, and the data flow Using a distance between components based on data input / output dependency, and determining a component to execute a required process by determining the arrangement of the components, To do.

  According to the present invention, the circuit configuration information is created so as to reduce the number of settings required for reconfiguration while suppressing the delay time of data communication, thereby reducing the reconfiguration period of the reconfiguration device without increasing the circuit scale. It is possible.

It is a figure which shows the structural example of the processing apparatus containing a reconstruction device. It is a figure which shows the structural example of a reconstruction device. It is a figure which shows the example of a procedure of the data communication between the elements of a reconstruction device. It is a figure which shows the structural example of a processing element. It is a figure which shows the example of a format of a configuration command. It is a figure which shows the example of an outline | summary of the setting stored in the configuration memory of a processing element. It is a flowchart which shows the procedure which reads / writes a setting. It is a figure which shows the structural example of a switching element. It is a figure which shows the example of an outline | summary of the setting stored in the configuration memory of a switching element. It is a figure which shows the example of arrangement | positioning to the processing element of the process in a data flow. It is a time chart which processes a some data flow sequentially. It is a figure which shows the example of a model of the processing element array toward process arrangement | positioning. It is a figure which shows the example of an outline for performing the process arrangement | positioning of the some data flow in 1st Embodiment. It is a flowchart for performing processing arrangement in the first embodiment. It is a figure which shows the example of an outline for performing the process arrangement | positioning of the data flow in 2nd Embodiment. It is a figure which shows the example of an outline for performing the process arrangement | positioning of the data flow in 3rd Embodiment. It is a figure which shows the example of an outline for performing the process arrangement | positioning of the data flow in 4th Embodiment. It is a figure which shows the example of an outline for performing the processing arrangement range limitation of the data flow in 5th Embodiment. It is a block diagram which shows an example of a structure of the apparatus which produces circuit structure information.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments to which the invention is applied will be described in detail with reference to the accompanying drawings.

  First, a first embodiment of the present invention will be described. An example of the overall configuration of a system having a reconfigurable device according to the first embodiment is shown in FIG. The external memory 101 holds circuit configuration information 106 therein. The circuit configuration information 106 is a group of settings for operating elements constituting the reconfigurable device 105. The configuration controller 102 acquires circuit configuration information 106 from the memory 101 through the connection 104. The acquired circuit configuration information 106 is sent to the reconfiguration device 105 through the connection 103. Here, a processing element array is used as an example of the reconstruction device 105. In the following description, the processing element array will be specifically described. However, the present invention is not limited to the configuration of each processing element and the path configuration described below.

  FIG. 2 shows a schematic diagram of a processing element array which is a reconstruction device in the present embodiment. In the reconstruction device, switching elements 201 which are input / output processing means with 8 inputs and 8 outputs are arranged in a two-dimensional lattice pattern. A processing element 202 having 4 inputs and 4 outputs, which is an arithmetic processing means, is arranged in the lattice of the switching element 201. The eight inputs and eight outputs of the switching elements 201a to i are connected to the other four switching elements 201 in the direction of east, west, south, and north (upper right and lower left), respectively, as a set, with one input and one output as a set. .

  Furthermore, it has a configuration in which it is bidirectionally connected to four different processing elements 202 in the northeast, southeast, southwest and northwest directions via connection lines 204a and 204b. The switching elements 201a to 201i and the processing elements 202a to 202d are connected in a daisy chain in one direction by a connection 205.

  Connections 203 a and 203 b and connection lines 204 a and 204 b are connections that are connected to communicate processing target data between the switching element 201 and the processing element 202. A connection 205 is a connection for supplying settings to the switching element 201 and the processing element 202.

  With the above settings, the switching element 201 determines the input / output destination of the processing target data, and the processing element 202 determines the input / output destination and processing content of the processing target data. In addition, the direction of the arrow of each connection 203a, 203b, 204a, 204b, 205 of FIG. 2 has shown the direction of data. The switching elements 201a to 201i have the same configuration, and the processing elements 202a to 202d have the same configuration.

  Here, as an example of a communication protocol for each of the connections 203a, 203b, 204a, 204b, and 205, a two-wire handshake using a Valid signal and a Ready signal is shown in FIG. In FIG. 3, a data signal line 303, a valid signal line 304, and a ready signal line 305 are connected between the module A301 on the transmission side and the module B302 on the reception side. The Valid signal is a signal indicating that the transmitting side can transmit to the receiving side through the Valid signal line 304. The Ready signal is a signal indicating that the receiving side can receive data to the transmitting side through the Ready signal line 305. In this protocol, the data on the data signal line 303 is transmitted from the module A301 to the module B302 at the clock rising timing when both the valid signal line 304 from the module A301 and the ready signal line 305 of the module B302 are valid. In the waveform of FIG. 3, data A is transferred from module A301 to module B302 at timing 306a, data B at timing 306b, data C at timing 306c, and data D at timing 306d.

  The configuration of the processing element 202 is shown in FIG. The processing element 202 includes a configuration unit 401, an input unit 402, a computational unit 403, an output unit 404, and a temporary buffer 405. The configuration unit 401 manages settings for determining the operation content of the processing element 202. The input unit 402 performs input processing based on the setting of the configuration unit 401. The computational unit 403 performs arithmetic processing based on the setting of the configuration unit 401. In addition, the computational unit 403 can hold the processed result in the temporary buffer 405 for input to the computational unit 403 again. The output unit 404 performs output processing based on the setting of the configuration unit 401.

  The operation of the processing element 202 will be described more specifically. The input unit 402 acquires setting information for determining an input destination from the configuration unit 401 through the connection 406. The acquired setting information specifies which input port is used to communicate with the externally connected module. Based on the information, data to be processed is acquired through the connections 204a-ne, 204a-se, 204a-sw, and 204a-nw. Here, reference numerals ne, se, sw, and nw indicate directions, respectively, and the connection line 204a-ne is connected to a switching element arranged in the northeast. 204a-se is connected to a switching element arranged in the southeast. 204a-sw is connected to a switching element arranged in the southwest. 204a-nw is connected to a switching element arranged in the northwest. The acquired data is sent to the computer unit 403 through the connection 409.

  The computational unit 403 acquires setting information for determining the processing content from the configuration unit 401 through the connection 407. Based on the acquired setting information, data sent from the input unit 402 is acquired and processed. The processed data is sent to the output unit 404 through the connection 410.

  The computational unit 403 holds at least one computing unit. The arithmetic unit is, for example, an arithmetic unit such as an adder / subtracter, a comparator, a multiplier, a divider, a logical arithmetic unit, or an arithmetic unit composed of a combination thereof, or an arithmetic operation composed of a combination of these and other arithmetic units. Such as a vessel. In the following, as a specific example, the above-described computational unit 403 will be described assuming that product-sum operation and comparison operation processing can be performed, and one of them can be selectively performed in one operation. In the product-sum operation, the process of a · b + c · d is performed, and in the comparison operation, c is output if a> b, and d is output otherwise. In addition, the computational unit 403 is configured to be able to repeatedly use the arithmetic unit for one input. In the case of repeated use, the processing results once used by the computing unit are stored in a temporary buffer through the connection 412 and then input to the computer unit 403 again through the connection 411. A new process is performed on the data inputted again by the above computing unit. As will be described in detail later, the setting refers to the type of operation and the iterative process, and the values of the variables a, b, c, and d required for each process are referred to. Means to specify.

  The output unit 404 acquires setting information indicating the output destination of the processed data through the connection 408. The acquired setting information specifies through which output port communication with the switching element is performed. Based on the information, the data is output to the switching element through connection lines 204b-ne, 204b-se, 204b-sw, and 204b-nw. Here, the connection line 204b-ne is connected to a switching element arranged in the northeast. 204b-se is connected to a switching element arranged in the southeast. 204b-sw is connected to a switching element arranged in the southwest. 204b-nw is connected to a switching element arranged in the northwest.

  Next, the operation of the configuration unit 401 will be described. The configuration unit 401 holds a unique ID for each processing element 202. The configuration unit acquires the setting information sent from the input side connection 205, processes it in the configuration unit, and outputs the setting through the output side connection 205. The configuration unit 401 has a configuration memory 413 for storing settings corresponding to its own ID.

  FIG. 5 shows a configuration command 501 for setting that is transmitted to and received from the configuration unit. The configuration command 501 includes a read / write mode 502, an ID 503, a configuration address 504, and a setting value 505. The read / write mode 502 is a signal that determines the read / write processing of the configuration command. The ID 503 is a signal that determines the processing element 202 to be processed. The configuration address 504 is a signal for designating an address in the memory where the setting in the configuration unit 401 is held. A set value 505 is a signal representing an actual set value. In FIG. 5, M, N, O, and P indicating the bit width are values determined by the actually configured architecture. Hereinafter, the setting based on the above-described configuration will be described more specifically.

  Reference numeral 601 in FIG. 6 denotes an address of the configuration memory 413, which corresponds to an address designated by the configuration address 504 in FIG. Reference numeral 602 denotes an actual set value, which corresponds to the set value 505 in FIG. In the present embodiment, each of these is read as setting, but the present invention is not limited to the above-mentioned unit. In the figure, an example in which settings relating to the input unit 402, the computational unit 403, and the output unit 404 are held in the configuration memory 413 is shown.

  A setting value indicated by an address 0x0000 — 0000 (“0x” indicates a hexadecimal number) is setting information for determining an input destination in the input unit 402, and a predetermined input destination is determined according to this value. The iteration number indicated by the address 0x0000 — 0004 is setting information for determining the number of repetitions of calculation in the computational unit 403, and the number of repetitions of calculation is determined according to the value. In the present embodiment, up to four calculations are assumed.

  The operation setting indicated by the address 0x0000 — 0008 is a setting for determining the type of calculation performed in the first calculation, and the product-sum calculation or the comparison calculation is determined according to the value. The variable setting indicated by the address 0x0000 — 000c is a setting for determining the reference destination of the value of the variable a in the first calculation. The reference destination includes an input value from the input port, a fixed value held in the configuration memory 413, and a temporary buffer value holding a previous calculation result. Depending on this value, one of the above values is input to this variable a. Similarly to 0x0000_000c, variable settings indicated by 0x0000_0010, 0x0000_0014, and 0x0000_0018 are settings for determining reference destinations of the values of variables b, c, and d in the first calculation.

  Next, the parameter indicated by 0x0000 — 001c is a fixed value for the variable a when the reference destination specified by 0x0000 — 000c in the first calculation is a fixed value. Similar to 0x0000 — 001c, the fixed values indicated by 0x0000 — 0020, 0x0000 — 0024, and 0x0000 — 0028 are values used in the variables b, c, and d in the first calculation.

  Subsequent 0x0000 — 002c to 0x0000 — 0094 indicate setting values for the second, third, and fourth times, respectively, similarly to the settings related to the first calculation indicated by the above 0x0000 — 0008 to 0x0000 — 0028. Finally, an output select value indicated by 0x0000 — 0098 is a setting value for determining an output destination in the output unit 404, and a predetermined output destination is determined according to the value.

  Next, FIG. 7 shows a processing flow performed in the configuration unit. In step S701, a configuration command 501 is input. In step S <b> 702, it is determined whether the ID 503 specified by the input configuration command 501 matches the own ID of the configuration unit 401. If it is determined in step S702 that the ID is different from its own ID, in step S711 and 712, the input configuration command 501 is output without being processed. If it coincides with its own ID, it is next determined in step S703 whether the value of the read / write mode 502 is the read mode. If it is not the read mode, it is determined in step S707 whether or not it is the write mode. If it is not in any mode, the data is output as it is without being processed in steps S711 and 712. If the read mode is determined, the data designated by the configuration address 504 is read from the configuration memory 413 in step S704. Thereafter, the read data is written in the set value 505 of the input configuration command 501 in step S705, and the configuration command 501 is output in step S706. If the write mode is determined, the setting value 505 of the configuration command 501 input in step S708 is written into the configuration memory 413 designated by the configuration address 504. Next, in step S709, the value of the input configuration command 501 is not changed and is output as it is in step S710. One setting value 505 can be changed by a single configuration command, and a desired process is realized by sequentially transmitting configuration commands and changing all necessary setting values. In other words, this set number determines the processing content switching time.

  The configuration of the switching element 201 is shown in FIG. The switching element 201 includes a configuration unit 801 and a crossbar switch 802. The configuration unit 801 manages setting values for determining a connection destination to which data is transferred. The crossbar switch 802 connects the input and output one to one based on the setting of the configuration unit 801. Similar to the configuration unit 401 of the processing element 202, the configuration unit 801 holds a unique ID for each switching element 201. The configuration unit acquires setting information sent from the input side connection 205, performs processing in the configuration unit, and outputs a setting value through the output side connection 205. The configuration unit holds the acquired setting in the configuration memory 804. The configuration command of the configuration unit and its processing flow are the same as the format shown in FIG. 5 and the processing flow shown in FIG. The crossbar switch 802 acquires setting information for determining an input / output destination of data from the configuration unit 801 through the connection 803. The switching element 201 acquires data through the connections 203a-w, -s, 203b-e, -n, and the connections 204b-ne, -se, -sw, -nw based on the acquired set values. The acquired data is passed through the connected connections 203a-e, -n, 203b-w, -s, and the connections 204a-ne, -se, -sw, -nw.

  Here, the connections 203a-w and -s mean that they are connected to the switching elements arranged in the west and south, respectively. 203b-e and -n mean that the switching elements are connected to the east and north, respectively.

  Connections 203a-e and -n mean that they are connected to switching elements arranged east and north, respectively. 203b-w and -s mean that they are connected to switching elements arranged in the west and south, respectively.

  Connections 204a-ne, -se, -sw, and -nw mean that they are connected to switching elements arranged in the northeast, southeast, southwest, and northwest, respectively. Connections 204b-ne, -se, -sw, and -nw mean that they are connected to switching elements arranged in the northeast, southeast, southwest, and northwest, respectively.

  FIG. 9 shows a setting example related to the input / output connection of the crossbar switch 802 in the switching element 201, which is held in the configuration memory 804. Reference numeral 901 denotes a memory address, which corresponds to the address specified by the configuration address 504 in FIG. Reference numeral 902 denotes a set value, which is the set value 505 in FIG. The connection setting indicated by the address 0x0000_0000 determines whether the input from the connection line 203a-w is output to 203a-e, n, 203b-w, -s, 204a-ne, -se, -sw, or -nw. Is a set value for Subsequently, 0x0000_0004 is a setting value that determines which connection the input from the connection 203a-s is to be output in the same way as 0x0000_0000. 0x0000_0008 is a setting value that determines which connection the input from the connection 203b-e is to be output in the same way as 0x0000_0000. 0x0000 — 000c is a setting value that determines which connection the input from the connection 203b-n is to be output in the same way as 0x0000 — 0000. 0x0000 — 0010 is a setting value that determines to which connection the input from the connection 204b-ne is output as in the case of 0x0000 — 0000. 0x0000 — 0014 is a setting value that determines to which connection the input from the connection 204b-se is output as in the case of 0x0000 — 0000. 0x0000 — 0018 is a setting value that determines which connection the input from the connection 204b-sw is output in the same way as 0x0000 — 0000. 0x0000 — 001c is a setting value that determines to which connection the input from the connection 204b-nw is output as in the case of 0x0000 — 0000.

  Next, the outline of the arrangement of the data flow in the components will be described with reference to FIG. Here, the arrangement means to determine whether or not to execute the data flow process by a processing element defined by a predetermined arrangement. In FIG. 10, the nodes 1002, 1003, 1004, and 1005 of the data flow 1001 are processes performed by one processing element. In the example, the processes corresponding to the nodes 1002, 1003, 1004, and 1005 are arranged in the processing elements 202-1, -2, -3, and -4 of the reconfigurable device 105. The settings 1006, 1007, 1008, and 1009 are configured with an address 601 and a setting value 602 corresponding to the processing contents of 1002, 1003, 1004, and 1005, respectively. Note that the processing contents to be performed in each node have already been assigned, and the settings 1006, 1007, 1008, and 1009 are determined in advance. By determining the arrangement, it is possible to determine the ID 503 corresponding to the processing element to which each setting is written.

  FIG. 11 shows an example of a time chart for realizing a desired process by changing a plurality of types of the configuration of the reconfigurable device described above. FIG. 11 shows a time chart in which a plurality of different data flows A to Z are sequentially executed by the same reconstruction device. The data flow handled in the present embodiment is a data flow configured in units that can be arranged in the processing element of the reconfigurable device. Settings for processing each data flow are generated in advance. A series of processes in which a reconfigurable device is reconfigured based on settings generated in advance for the reconfigurable device and processing is performed based on the configuration is sequentially performed in a predetermined order.

  In the following description, it is assumed that the data flow A is already arranged and the data flow B is an arrangement target. Specifically, the processing arrangement of the data flow B is determined with reference to a setting value for executing the arranged data flow A. After determining the processing arrangement of the data flow B with reference to the processing arrangement of the data flow A, the data flow B is already arranged and the data flow C is set as an arrangement target. Specifically, the processing arrangement of the data flow C is determined with reference to the setting value for executing the data flow B that has already been arranged in the same manner as when the processing arrangement of the data flow B is determined. By repeating the above procedure in sequence, the data flow from A to Z can be arranged.

  In general, the placement problem has a wide solution space just by determining only the placement. Therefore, if detailed wiring determination is performed at the same time, not only a good solution cannot be calculated, but also the solution itself may not be calculated. For this reason, in this arrangement method, detailed wiring information is not determined, and the arrangement is determined using the approximate distance based on the arrangement model shown in FIG. In the present embodiment, a processing element array is used as an arrangement model, and a Manhattan model based on the position of the processing element is used. The solution is calculated using the Manhattan distance between processing elements as an index. However, in the present invention, the approximate distance is not limited to the Manhattan distance. As an index, detailed wiring can be performed simultaneously. In the present embodiment, an arrangement model based on the Manhattan model is used as the arrangement model, but the arrangement model is not limited thereto. It may be an architecture-dependent model or a model based on Euclidean space.

  As illustrated in FIG. 12, an arrangement model 1201 is defined for the reconfiguration device 105 including the switching element 201 and the processing element 202. The arrangement model 1201 includes only the processing element 202, and the distance as an index is represented by a distance 1202 between the processing elements in the horizontal direction and a distance 1203 in the vertical direction. In the present embodiment, the vertical and horizontal distances are equal, but may be different. Further, the distance handled in the present invention may be a physical length or a length of time required for communication between elements, and is not limited thereto.

  Next, with reference to the arrangement model shown in FIG. 12, a method for arranging processing focused on processing elements shown in the time chart of FIG. 11 on processing elements will be described.

  FIG. 13 shows an outline of the arrangement in the present embodiment. The data flow A includes processes represented as nodes 1301, 1302, 1303, and 1304, and settings 1305, 1306, 1307, and 1308 are settings of processes performed in the respective nodes. A flow 1309 represents a data input / output relationship between the nodes 1301 and 1302. A flow 1310 represents a data input / output relationship between the nodes 1301 and 1303. A flow 1311 represents a data input / output relationship between the nodes 1302 and 1304. A flow 1312 represents a data input / output relationship between the nodes 1303 and 1304.

  Data flow B is composed of processes represented as nodes 1313, 1314, 1315, and 1316, and settings 1317, 1318, 1319, and 1320 are settings of processes performed in the respective nodes. A flow 1321 represents a data input / output relationship between the nodes 1313 and 1315. A flow 1322 represents a data input / output relationship between the nodes 1314 and 1315. A flow 1323 represents a data input / output relationship between the nodes 1315 and 1316.

  Here, it is assumed that the processing of the above-described data flows A and B is arranged in the area 1324 in the processing element array arrangement model 1201. In the present embodiment, the arrangement in a part of the processing element array will be described. However, the arrangement is not limited thereto, and the arrangement may be in a plurality of parts or in the whole. Reference numeral 1325 denotes a processing arrangement example for the data flow A in the area 1324 described above. Reference numeral 1326 denotes a processing arrangement example for the data flow B in the area 1326. The processing elements 1327, 1328, 1329, 1330 in each processing arrangement 1325, 1326 each represent physically the same processing element. In the processing arrangement 1325, the processing of the node 1301 is arranged in the processing element 1327 in the data flow A. The processing of the node 1302 is arranged in the processing element 1329. The processing of the node 1303 is arranged in the processing element 1328. The processing of the node 1304 is arranged in the processing element 1330. The distance of data communication between processing elements is represented as a distance 1331 in the flow 1309, a distance 1332 in the flow 1310, a distance 1333 in the flow 1311, and a distance 1334 in the flow 1312.

  Subsequently, for the data flow B, the processing of the node 1313 is arranged in the processing element 1327. The processing of the node 1314 is arranged in the processing element 1328. The processing of the node 1315 is arranged in the processing element 1329. The processing of the node 1316 is arranged in the processing element 1330. The distance of data communication between the processing elements is represented as a distance 1335 in the flow 1321, distances 1336 and 1337 in the flow 1322, and a distance 1338 in the flow 1323.

  When processing is switched from data flow A to data flow B, the processing element 1327 changes the setting from setting 1305 to setting 1317 as indicated by setting change 1339. In the processing element 1328, the setting is changed from the setting 1307 to the setting 1318 as indicated by a setting change 1341. In the processing element 1329, the setting is changed from the setting 1306 to the setting 1319 as indicated by a setting change 1339. In the processing element 1330, the setting is changed from the setting 1308 to the setting 1320 as indicated by a setting change 1339.

  In the present embodiment, attention is paid to two elements, that is, the number of setting changes when processing is switched and the distance between components based on the dependency relationship of the data flow when performing the arrangement.

  In the example of FIG. 13 used in the present embodiment, the data flow A has already been processed and arranged, and the setting value in each memory of each processing element related to the data flow A is given as a fixed value. Data flow B is a processing arrangement target. That is, it is assumed that the processing order of the data flow is determined, and the arrangement of the data flow to be processed next is determined based on the already arranged arrangement information.

  FIG. 19 shows a block configuration diagram of an apparatus for generating circuit configuration information 106 for switching processing from a data flow to a data flow. In FIG. 19, reference numeral 2501 denotes a CPU that controls the entire apparatus. A ROM 2502 stores a boot program and BIOS. A RAM 2503 is used as a work area of the CPU 2501 and stores an OS (operating system) and applications. Reference numeral 2504 denotes an OS, an application for creating the circuit configuration information 106, and a hard disk drive (HDD) for storing various data. A keyboard 2505 and a mouse 2506 function as a user interface. Reference numeral 2507 denotes a display control unit incorporating a video memory and a display controller therein. Reference numeral 2508 denotes a display device for receiving and displaying a video signal from the display control unit 2507. An interface 2509 communicates with various external devices. For example, when the external memory 101 shown in FIG. 1 is connected, the circuit configuration information 106 created by this apparatus is written into the external memory 101.

  In the above configuration, when the apparatus is turned on, the CPU 2501 executes the boot program stored in the ROM 2502, loads the OS stored in the HDD 2504 into the RAM, and then creates an application for creating the circuit configuration information 106. By starting, this apparatus functions as a circuit configuration information creation apparatus.

  Hereinafter, the processing of this apparatus that functions as a circuit configuration information creation apparatus for carrying out the present invention will be described with reference to the flowchart of FIG. Although this procedure shows an example of a processing arrangement method based on simulated annealing, the present invention is not limited to the above method, and numerical values such as various approximate solutions such as genetic algorithms, linear programming, and nonlinear programming are used. An optimization method may be used. Further, the method may be changed according to the scale of the problem to be arranged.

The index representing each data flow shown in FIG. 13 is i, the node index is j, and the configuration address of the memory held in the element corresponding to the address 601 in FIG. 6 or the address 901 shown in FIG. 9 is k. To do. Also, let l be an index related to the flow between the nodes j. From the above, the set value in each memory can be expressed as u _{i, j, k} . In the i-th data flow, the starting node of flow l is S _{i, l} and the arriving node is d _{i, l} .

Also, as shown in FIG. 12, an index representing each processing element is r. The location of each node j in each data flow i can be expressed as x _{i, j} and y _{i, j} . In this embodiment, since different processes in the same data flow are not arranged in the same processing element, x _{i, j} and y _{i, j} are always different for each node j. That is, different processes are not arranged in the same processing element.

Here, it is assumed that the data flow that has undergone processing arrangement is i0, and the data flow to be processed is i1. First, in step S1401, a plurality of data flows and their order relationship (i order) are input. For the data flow that has been processed and arranged, the arrangement information x _{i0, j} and y _{i0, j} are also input together with the set value u _{i0, j, k} .

  Next, in step S1402, the requirement specification and hardware constraint conditions are input. Here, the hardware restriction condition can be a restriction on the hardware configuration such as the configuration information that each processing element associated with the hetero configuration individually has and the amount of heat generated by the processing. The required specifications are items that should be restricted in terms of hardware use, such as the distance restriction between processing elements and the ratio of the number of setting changes and the priority of the distance element described later in step S1406. However, the present invention is not limited only to the above-described restrictions.

  In step S1403, the processing arrangement of the target data flow is performed. In the initial process arrangement, there is a method of arranging the process randomly or by linking the depth direction of the data flow and the input / output direction of the processing element array. However, the method is not limited to these methods. Absent. If it is not the initial arrangement, the arrangement of the process is changed based on simulated annealing. In the present embodiment, the initial processing arrangement or the processing arrangement change is performed for the target data flow B that is the processing arrangement. For data flow A that has already been processed, the processing layout is not changed based on the constraints.

In step S1404, it is determined whether the processing arrangement result satisfies the requirement specification input in step S1403. As shown in the following equation, if the constraint is satisfied, the penalty variable p _{0 is set} to 0, and if it is violated, the penalty variable p ₀ is set to the penalty value C _p0 .

Here, in this embodiment, when there is a violation, the uniform C _p0 is treated as a constant value, but it may be a variable value according to the violation item. In step S1405, it is determined whether the processing arrangement result satisfies the hardware constraint condition input in step S1302.

As shown in the following equation, if the constraint is satisfied, the penalty variable p _{1 is set} to 0, and if it is violated, the penalty variable p ₁ is set to the penalty value C _p1 .

Here, in this embodiment, when there is a violation, the uniform C _p1 is treated as a constant value, but it may be a variable value according to the violation item. In step S1406, the distance based on the number of setting changes and the arrangement between data flow changes to be processed is calculated, and an evaluation value is calculated. First, calculation of the number of setting changes will be described. This is the number of settings that need to be changed in the case of setting changes 1339, 1340, 1341, and 1342, which will be described with reference to the example of FIG.

More specifically, the set value u _{i0, j, k} in the data flow i0 that has been processed and the set value u _i1 of the same type of processing elements that are arranged at the same position in the data flow i1 to be processed. _If the values of _{, j, k} do not match, α ₁ is added to the setting change number. If the above values match, nothing is added.

Here, the node j0 of the data flow i0 arranged in the processing element r is represented as j0 _r, and the node j1 of the data flow i1 is represented as j1 _r . Here, r is an index representing each processing element as described above. The number of setting changes necessary for changing the processing contents of the nodes arranged at the same position when the data flow is switched can be obtained by the following expression.

Here, α ₁ is normally 1, but it is also possible to change the weight for each address where each setting is stored according to the structure of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow. As shown in FIG. 7, one setting value can be changed by a single configuration command. Therefore, if this number is reduced, the process switching time can be reduced.

  Next, distance calculation will be described. The distance is the total amount of the distances 1335, 1336, 1337, and 1338 in the data flow B that is the arrangement target. Based on the data input / output relationship of the arrangement and data flow in step S1403, the distance can be expressed by the following equation.

Here, κ _1l and λ _1l are the weights of the distances between the nodes for each x and y, and the weights can be changed uniformly or separately depending on the architecture such as the distance between the nodes. The formula for calculating the evaluation value in this step is defined as follows from the above formula.

  Here, δ is an index representing the ratio of the priority of the number of setting changes and distance given in step S1402. In other words, the evaluation value decreases as the required specifications and hardware constraints are satisfied, the distance is shorter, and the number of setting changes required for reconfiguration is smaller.

  Finally, in step S1407, it is determined whether the target has been achieved based on simulated annealing. If the target has been achieved, the process ends. If the target has not been reached, the process returns to step S1403, and steps S1403 to S1407 are repeated. Here, the target value is repeated until a sufficiently good result is obtained or a predetermined calculation time is reached.

  As a result, the circuit configuration information 106 is generated in the HDD 2504. After that, it can be written to the external memory 101 to be used via the interface 2509 and mounted in the actual product.

  In the embodiment described above, the example in which the circuit configuration information 106 is created by an external device (FIG. 17) has been shown. This is the same in all embodiments described below. Further, the configuration controller 102 may create the circuit configuration information 106 by executing the processing of FIG. 13 instead of the external device. For example, if the external memory 101 stores settings for each of a plurality of data flows (required number of processors and processing parameters for each processor) and the configuration controller 102 creates the circuit configuration 106 based on the settings of the plurality of data flows. Good. This point is also applicable to all embodiments described below.

  In the processing arrangement method of the data flow to the processing element in a general reconfigurable device, since the number of setting changes is not conscious, it is necessary to change all the settings between the data flow processing changes.

  In the present embodiment, it is possible to reduce the number of setting changes effectively by paying attention to the processing order of the data flow and reducing the total number of setting changes in addition to the distance.

  Next, a second embodiment of the present invention will be described. FIG. 15 shows a time chart of processing according to the second embodiment and an outline of processing arrangement. In this embodiment, when changing the setting of the reconfigurable device, the processing content itself of each data flow is determined, but in the embodiment related to processing arrangement when the change order is indefinite and changes depending on the situation, input data, etc. is there.

  In the period 1502 in the time chart 1501, processing related to the data flow A is performed, processing related to the data flow C is performed in the periods 1504 and 1508, and processing related to the data flow B is performed in the period 1506. In the period 1503, the setting change of the data flow A to the data flow C is performed. In the period 1505, the setting change of the data flow C to the data flow B is performed. In a period 1507, the setting change of the data flow C from the data flow B is performed. In the present embodiment, since the order of processing changes of the data flows A, B, and C is not constant, it is necessary to arrange the processing in consideration of all setting changes between the respective data flows.

  In the figure, reference numerals 1509, 1522, and 1431 show examples of the arrangement of processing elements in the data flows A, B, and C, respectively. Here, the arrangement of the processing of all these data flows is performed at once. Note that the processing elements 1510, 1511, 1512, and 1513 in the arrangement examples 1509, 1522, and 1531 indicate physically the same processing elements.

  Settings 1514, 1515, 1516, and 1517 represent settings for the processing elements 1510, 1511, 1512, and 1513 in the arrangement of the data flow A, respectively. Settings 1523, 1524, 1525, and 1526 represent settings for the processing elements 1510, 1511, 1512, and 1513 in the arrangement of the data flow B, respectively. Settings 1532, 1533, 1534, and 1535 represent settings for the processing elements 1510, 1511, 1512, and 1513 in the arrangement of the data flow C, respectively. Here, the above setting is the setting described with reference to FIG. 6 as in the first embodiment. In the present embodiment, the total number of setting changes necessary for data flow change in the processing elements 1510, 1511, 1512, and 1513 between the data flows A and B, between B and C, and between C and A, and the connection between the processing elements. Pay attention to the total distance.

  By calculating the setting change number that the total number and the distance number add to the evaluation value shown in the flowchart 1406 shown in FIG. 14 as an evaluation value to be described later, the number of setting changes at the time of reconfiguring the reconfigurable device in consideration of the distance Reduce.

  Note that the setting change of the processing elements 1510, 1511, 1512, and 1513 between the data flows A and B is represented by 1539. A change in the setting of the processing elements 1510, 1511, 1512, and 1513 between the data flows B and C is represented by 1540. The setting change of the processing elements 1510, 1511, 1512, and 1513 between the data flows C and A is represented by 1541.

  The difference between this embodiment and the first embodiment is that processing arrangement of a plurality of data flows is performed at the same time. In step S1401 of FIG. 14, a plurality of data flows are input, and at the same time, the processing order is arbitrary. In the processing placement performed in step S1404 in FIG. 14, processing placement is performed for all the data flows A, B, and C that are processing placement targets. In step S1406 of FIG. 14, there are the following differences from the first embodiment.

The value of the setting value u _{io, j, k} in the data flow i0 to be processed and the setting value u _{i1, j, k} of the same type of processing elements arranged at the same position in the data flow i1 to be processed If does not match, α ₂ is added to the number of setting changes. Also, the setting value u _{i1, j, k} in the data flow i1 to be processed and the setting value u _{i2, j, k} of the same type of processing elements arranged at the same position in the data flow i2 to be processed. If the values do not match, β ₂ is added to the number of setting changes. Further, the setting value u _{i2, j, k} in the data flow i2 to be processed and the setting value u _{i0, j, k} of the same type of processing elements arranged at the same position in the data flow i0 to be processed. If the values do not match, γ ₂ is added to the number of setting changes. Other than the above, nothing is added if the set values match.

Here, the node j0 of the data flow i0 arranged in the processing element r is represented as j0 _r , the node j1 of the data flow i1 is represented as j1 _r, and the node j2 of the data flow i2 is represented as j2 _r . Here, r is an index representing each processing element as described above.

  When the data flow is switched, the number of setting changes necessary for changing the processing contents of the nodes arranged at the same position can be obtained by the following equation.

Here, α ₂ , β ₂ , and γ ₂ are each normally 1, but the weight can be changed for each address in which each setting is stored according to the configuration of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow.

  There are the following differences in distance. In the example illustrated in FIG. 15, the distance is expressed as a total amount of the distances 1518, 1519, 1520, 1521, 1527, 1528, 1529, 1530, 1536, 1537, and 1538. The arrangement of the processing elements in the drawing is only an example, and the total amount of these distances is changed by changing the arrangement. The distance can be expressed by the following expression based on the arrangement and the data input / output of the data flow after the arrangement.

Here, the weights of κ2 _{i, l} and λ2 _{i, l} can be changed uniformly or separately depending on the architecture such as the distance between nodes for each data flow. According to the present embodiment, by considering all the data flows, even if the execution order of processing is indefinite, an effect of reducing the number of setting changes can be obtained on average taking the distance into consideration.

  Next, a third embodiment of the present invention will be described. FIG. 16 shows a time chart of processing according to the third embodiment and an outline of processing arrangement. In the present embodiment, it is assumed that the processing order of a plurality of data flows and the processing arrangement of each are already determined. This embodiment relates to a processing arrangement for inserting a process corresponding to a new data flow without changing the processing arrangement before and after the insertion between processes of an arbitrary data flow in the above-described processing order.

  A time chart 1601 in FIG. 16 is a time chart in which the processing order to be performed by the reconfigurable device is already determined and the processing arrangement is also determined. In the time chart 1601, after the processing 1603 of the data flow A, the processing 1605 of the data flow C is performed after a period 1604 of changing from the setting of the data flow A to the setting of the data flow C. The time chart 1602 is a time chart in which the data flow B is newly inserted between the data flow A and the data flow C of the time chart 1601. After the process 1603 of the data flow A, the process 1607 of the newly inserted data flow B is performed after a period 1606 of changing from the setting of the data flow A to the setting of the data flow B. Thereafter, the processing 1605 of the data flow B is performed after a period 1608 of changing from the setting of the data flow B to the setting of the data flow C. At this time, in order to determine the processing arrangement of the data flow B without changing the processing arrangement of the data flows A and C, the setting change amount between the data flows that have already been arranged before and after the insertion is considered.

  Reference numerals 1609, 1622, and 1631 in the figure indicate examples of arrangement of processing elements in the data flows A, B, and C, respectively. In this embodiment, the data flows A and C have already been processed and the data flow B is processed. The processing elements 1610, 1611, 1612, and 1613 in the arrangement examples 1609, 1622, and 1631 indicate the same processing element.

  Settings 1614, 1615, 1616, and 1617 represent settings for the processing elements 1610, 1611, 1612, and 1613 in the arrangement of the data flow A, respectively. Settings 1623, 1624, 1625, and 1626 represent settings for the processing elements 1610, 1611, 1612, and 1613 in the arrangement of the data flow B, respectively. Settings 1632, 1633, 1634, and 1635 represent settings for the processing elements 1610, 1611, 1612, and 1613 in the arrangement of the data flow C, respectively. Here, the above setting is the setting described with reference to FIG. 6 as in the first embodiment. In the present embodiment, the total number of setting changes necessary for data flow change in the processing elements 1610, 1611, 1612, and 1613 between the data flows A and B, between B and C, and between C and A, and the connection between the processing elements. Pay attention to the total distance.

  The setting change of the processing elements 1610, 1611, 1612, and 1613 between the data flows A and B accompanying the newly inserted data flow B is represented by 1639. A change in the settings of the processing elements 1610, 1611, 1612, and 1613 between the data flows B and C is represented by 1640.

  The difference between the present embodiment and the first embodiment is that the processing arrangement of the target data flow is performed with reference to a plurality of data flows that have already been arranged.

  The processing arrangement performed in step S1403 in FIG. 14 is only for the data flow B. Data flows A and C are already processed and are not changed. In step S1406 of FIG. 14, there are the following differences from the first embodiment.

The set value u _{i0, j, k} in the data flow i0 that has already been processed matches the set value u _{i1, j, k} of the processing element that is placed at the same position in the data flow i1 to be processed. If not, add α ₃ to the number of setting changes. Further, the setting value u _{i1, j, k} in the data flow i1 to be processed and the setting value u _{i2, j, k} of the processing element arranged at the same position in the data flow i2 that has been processed are If they do not match, β ₃ is added to the number of setting changes. If the above values do not match, nothing is added.

Here, the node j0 of the data flow i0 arranged in a certain processing element r is represented as j0 _r , the node j1 of the data flow i1 is represented as j1 _r, and the node j2 of the data flow i2 is represented as j2 _r . Here, r is an index representing each processing element as described above.

  The number of setting changes necessary for changing the processing contents of the nodes arranged at the same position when the data flow is switched can be obtained by the following expression.

Α ₃ and β ₃ are normally 1 respectively, but the weight can be changed for each address where each setting is stored according to the configuration of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow.

  There are the following differences in distance. In the example illustrated in FIG. 16, the distance is expressed as a total amount of the distances 1618, 1619, 1620, 1621, 1627, 1628, 1629, 1630, 1636, 1637, and 1638. The arrangement of the processing elements in the drawing is only an example, and the total amount of these distances is changed by changing the arrangement. The distance can be expressed by the following expression based on the arrangement and the data input / output of the data flow after the arrangement.

Here, the weights of κ3 _l and λ3 _l can be changed uniformly or separately depending on the architecture such as the distance between nodes for each data flow. When a new data flow is inserted, the effect of reducing the number of setting changes with the data flow before and after the insertion can be obtained.

  Next, a fourth embodiment of the present invention will be described. FIG. 17 shows a time chart of processing according to the fourth embodiment and an outline of processing arrangement. In the present embodiment, after processing a certain standard data flow, an embodiment relating to processing arrangement in the case where the data flow to be performed next differs depending on the result.

  In the time chart 1701 of FIG. 17, the processing of the reference data flow X is performed in the period 1702, and the setting change from the data flow X to the data flow A, B, or C is performed in the period 1703 according to the result. After the setting is completed, the data flow A, B, or C is processed in the period 1704, and the setting is changed from the data flow A, B, or C to the data flow X in the period 1705 in order to perform the reference data flow X again. I do. The above sequence is repeated, and whether data flow A, B, or C is performed varies depending on the result of data flow X.

  In the figure, reference numerals 1706, 1719, 1728, and 1737 indicate arrangement examples in the data flows X, A, B, and C, respectively. In this embodiment, processing arrangement of all data flows X, A, B, and C is performed. The processing elements 1707, 1708, 1709, and 1710 in the arrangement examples 1706, 1719, 1728, and 1737 indicate the same processing elements.

  Settings 1711, 1712, 1713, and 1714 represent settings for the processing elements 1707, 1708, 1709, and 1710 in the arrangement of the data flow X, respectively. Settings 1720, 1721, 1722, and 1723 represent settings for the processing elements 1707, 1708, 1709, and 1710 in the arrangement of the data flow A, respectively. Settings 1729, 1730, 1731, and 1732 represent settings for the processing elements 1707, 1708, 1709, and 1710 in the arrangement of the data flow B, respectively. Settings 1738, 1739, 1740, and 1741 represent settings for the processing elements 1707, 1708, 1709, and 1710 in the arrangement of the data flow C, respectively. Here, the above setting is the setting described with reference to FIG. 6 as in the first embodiment.

  Specifically, in this embodiment, processing arrangement of the data flows X, A, B, and C is performed. At the time of processing arrangement, the total number of setting changes required for the data flow change in the processing elements 1707, 1708, 1709, and 1710 between the data flows X and A, between X and B, and between X and C and the connection between the processing elements Pay attention to the total distance.

  Note that the setting change of the processing elements 1707, 1708, 1709, and 1710 between the data flows X and A is represented by 1745. A setting change of the processing elements 1707, 1708, 1709, and 1710 between the data flows X and B is represented by 1746.

  A setting change of the processing elements 1707, 1708, 1709, and 1710 between the data flows X and C is represented by 1747.

  The difference between this embodiment and the first embodiment is that there is a branch in the processing order, and processing is arranged for the data flow between the branch destination and the branch source.

  In step S1301 in FIG. 13, a plurality of data flows are input and a processing order partially including an arbitrary order relation is input. Here, “partial arbitrary” means that there is a branch in the execution order in this embodiment, and only the execution order of the branch source and the branch destination is arbitrary.

  The processing placement performed in step S1403 in FIG. 14 performs processing placement for all of the data flows X, A, B, and C that are the processing placement targets. In the present embodiment, an example is shown in which all data flows are handled as processing arrangement targets, but the present invention is not limited to this. In this embodiment, attention is paid to the processing order. When at least one data flow has already been processed and arranged, the processing arrangement of other data flows is performed.

In step S1406 of FIG. 14, there are the following differences from the first embodiment. The value of the setting value u _{i0, j, k} in the data flow i0 to be processed and the setting value u _{i1, j, k} of the same type of processing element arranged at the same position in the data flow i1 to be processed If does not match, add α ₄ to the number of setting changes. In addition, the setting value u _{i0, j, k} in the data flow i0 to be processed and the setting value u _{i2, j, k} of the same type of processing elements arranged at the same position in the data flow i2 to be processed. If the values do not match, β ₄ is added to the setting change number. Further, the setting value u _{i0, j, k} in the data flow i0 to be processed and the setting value u _{i3, j, k} of the same type of processing elements arranged at the same position in the data flow i3 to be processed. If the values do not match, γ ₄ is added to the number of setting changes. Other than the above, nothing is added when the set values match.

Here, the node j0 of the data flow i0 arranged in a certain processing element r is represented as j0 _r , the node j1 of the data flow i1 is represented as j1 _r , the node j2 of the data flow i2 is represented as j2 _r, and the data flow. The node j3 of i3 is represented as j3 _r . Here, r is an index representing each processing element as described above.

  The number of setting changes necessary for changing the processing contents of the nodes arranged at the same position when the data flow is switched can be obtained by the following expression.

Here, α ₄ , β ₄ , and γ ₄ are normally 1 respectively, but the weight can be changed for each address in which each setting is stored according to the configuration of the configuration memory of the processing element. In addition, in order to give priority to the switching time for each data flow, it is possible to weight each data flow.

  There are the following differences in distance. In the example shown in FIG. 17, the distance is expressed as a total amount of the distances 1715, 1716, 1717, 1718, 1724, 1725, 1726, 1727, 1733, 1734, 1735, 1736, 1742, 1743, 1744. The arrangement of the processing elements in the drawing is only an example, and the total amount of these distances is changed by changing the arrangement. The distance can be expressed by the following expression based on the arrangement and the data input / output of the data flow after the arrangement.

Here, the weights of κ4 _{i, l} and λ4 _{i, l} can be changed uniformly or separately depending on the architecture such as the distance between nodes for each data flow. According to this embodiment, when performing a plurality of data flows in order, even if there is a branch in the execution order, by considering a data flow that is a branch source and a plurality of other data flows that are a branch destination, The effect of reducing the number of setting changes can be obtained.

  Next, a fifth embodiment of the present invention will be described. FIG. 18 shows an outline of the data flow and the processing arrangement restriction method according to the fifth embodiment. The processing placement problem is generally difficult and often takes a long time to calculate a solution. The problem is further increased when a plurality of data flows are arranged simultaneously as in the present invention. Therefore, in this embodiment, the solution calculation time is effectively shortened by limiting the range in which processing can be arranged.

  The data flow 1819 includes nodes 1801 to 1818 corresponding to a plurality of processes. Reference numeral 1826 denotes an input device 1820 and an output device 1821 for the processing element array, and the processing element array is between them.

  In this embodiment, when the processing of the data flow 1819 is arranged in the arrangement model 1201, the solution space is effectively narrowed by associating the depth direction of the data flow with the input / output positions to the processing element array. Specifically, the nodes 1801 to 1804 are set so that only the range indicated by 1821 can be arranged. Further, 1805 to 1810 are set such that only the range indicated by 1822 can be arranged. 1811 to 1814 are set so that only the range indicated by 1822 can be arranged. 1815 to 1818 are set such that only the range indicated by 1823 can be arranged.

  These restrictions are assumed to be input in step S1402 of FIG. In this embodiment, the possible arrangement range is associated with the depth of the data flow and the input / output direction of the processing element array, but is not limited thereto.

  In the above-described embodiment, each processing arrangement method is described for each use case, but the present invention may be a combination of these methods. Further, although the processing element has been described as a component of the reconfigurable device, the present invention is not limited to this, and an LUT or a combination thereof may be used. Further, the setting is not limited to the setting shown in the embodiment, and may be a setting used in an LUT-based reconfiguration device. In the embodiment, the processing arrangement target is set for all the input data flows. However, the processing arrangement may be performed for only a part of the data flow by specifying the processing arrangement target range of the data flow. In the embodiment, the number of processing elements is the same between data flows, but the number of processing elements in which processing is arranged may be different. Further, although the description is made so that the total distance value shown in the embodiment is small, the arrangement may be determined so that the maximum value of each distance is small. Further, the arrangement may be determined so that the average value of each distance is reduced.

  In the above-described embodiment, the processing elements are uniformly arranged in a lattice shape, and the connection distance between the processing elements is described as being constant. However, the present invention is not limited to this. When processing elements are connected in a manner such as a tree structure, the distances may be weighted according to the tree structure. That is, each distance may be weighted according to the connection form of the processing elements.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (6)

A processing arrangement method for determining a component that performs each process of data flow for a reconfigurable device composed of a plurality of components,
An input step for inputting at least two different data flows and a processing order of the data flows;
A constraint step for entering constraints on the components of the reconfigurable device;
Required by determining the arrangement of the components using the number of setting changes necessary for the reconfiguration according to the data flow and the distance between the components based on the data input / output dependency of the data flow. And a determination step for determining which component causes the process to be executed.   The processing arrangement method according to claim 1, wherein the restriction includes a restriction that limits an arrangement possible range for each process in the data flow in accordance with a data flow configuration and a reconfiguration device configuration.   2. The processing arrangement method according to claim 1, wherein the setting change number is weighted by a setting for determining a processing content of each constituent element or each data flow.   The processing arrangement method according to claim 1, wherein a distance of connection between the components is weighted to the components. A program for causing a computer to execute a processing arrangement method for determining a component for performing each process of data flow for a reconfigurable device including a plurality of components,
An input step for inputting at least two different data flows and a processing order of the data flows;
A constraint step for entering constraints on the components of the reconfigurable device;
Required by determining the arrangement of the components using the number of setting changes necessary for the reconfiguration according to the data flow and the distance between the components based on the data input / output dependency of the data flow. A program for causing a computer to execute a determination step for determining which component causes a process to be executed.   A reconfigurable device that operates based on setting information generated by the processing arrangement method according to claim 1.

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