JP2012181577A - File system for managing non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend a product life of a non-volatile memory by eliminating the necessity of deleting excessive data in a FCB area for preventing the FCB area from being damaged.SOLUTION: A CPU 2 controlling a flash ROM 1 rewrites values of predetermined addresses possessed by a data area 10 that are to be assigned to respective addresses possessed by a first FCB area 11 of a first block B1 among a plurality of blocks B1 to B100 configuring the flash ROM 1, and values of predetermined addresses possessed by a second FCB area 12 of the first block B1 that are to be assigned to each of the plurality of blocks, by representing the values in four values "8","C","E", and "F" among the 16 types of values "0 to F" representing 4 bits in hexadecimal notation, and putting the values in order of "F" → "E" → "C" → "8". Also, at least the first FCB area between the first and second FCB areas is arranged by dividing the first FCB area into a plurality of blocks.

Description

  The present invention relates to a management file system for managing data write information to a nonvolatile memory such as a flash ROM, and more particularly to a nonvolatile memory management file system in which excessive data erasure is prevented.

  Conventionally, when the call button is operated on the entrance cordless handset, the video of the entrance from the camera is recorded in the non-volatile memory of the recording unit by operating the go-out button of the recording unit, and recorded on the recording unit by operating the playback button of the recording unit. There has been disclosed a television door phone device that reproduces a recorded video of an entrance on a monitor of a master unit (see, for example, Patent Document 1). According to this apparatus, it is possible to reliably record the image of the visitor who has operated the call button, and to easily identify the visitor.

  For example, data writing or data erasing to the flash ROM that constitutes such a nonvolatile memory can be performed by program control by using hardware such as a CPU, but normally, the number of data erasing is limited. The manufacturer guaranteed value is, for example, 100,000 times.

JP 2001-94977 A

  However, the writing status for each data area of the flash ROM must be managed using a special data area, FCB (File Control Block) area, and this FCB area is located at a specific location in the flash ROM. Since only the FCB area is erased or written every time data is written to the data area, the FCB area may be destroyed due to the limitation on the number of erasures as described above. There was a problem that the entire flash ROM could not be used.

  The present invention has been made in order to solve this problem, and is a nonvolatile memory management capable of preventing the destruction of the FCB area by eliminating excessive data erasure in the FCB area and extending the product life of the nonvolatile memory. It aims to provide a file system for use.

  To achieve the above object, a nonvolatile memory management file system according to a first aspect of the present invention includes a nonvolatile memory having a plurality of blocks having a predetermined data capacity, and a CPU for controlling the nonvolatile memory. In the file system for non-volatile memory management comprising the CPU, the CPU has a predetermined address value of a data area allocated to a predetermined address of the first FCB area of the first block among the plurality of blocks. The value of the predetermined address included in the second FCB area of the first block allocated to each of the plurality of blocks is expressed as “8” among the 16 types “0 to F” of four types expressed in hexadecimal. ”,“ C ”,“ E ”, and“ F ”, which are rewritten in the order of“ F ”→“ E ”→“ C ”→“ 8 ”.

  The nonvolatile memory management file system according to the second aspect of the present invention provides the values of “8”, “C”, “E”, and “F” in the first aspect of the present invention, “The specified address in the data area is unusable”, “The specified address in the data area is full”, “Data is already written in the specified address in the data area”, “The specified address in the data area The data is assigned to “no data written to the address”.

  A non-volatile memory management file system according to a third aspect of the present invention includes a non-volatile memory having a plurality of blocks having a predetermined data capacity, and a CPU for controlling the non-volatile memory. In the management file system, the nonvolatile memory includes a data area having a predetermined range of addresses for each block, and a first FCB area for allocating and managing the write status of the data area to the predetermined range of addresses. And a second FCB area for managing the write status of each block by assigning it to a predetermined range of addresses, and at least the first FCB area of the first and second FCB areas is for each of a plurality of blocks. It is divided and arranged.

  According to the nonvolatile memory management file system of the present invention, when the nonvolatile memory is controlled by the control of the CPU, the data area and the first and second FCB areas are divided into a plurality of blocks constituting the nonvolatile memory. At least the first FCB area is divided and the value of the predetermined address included in the data area respectively assigned to the predetermined address included in the first FCB area of the first block, the first The value of the predetermined address of the second FCB area of the th block is “8: The predetermined address of the data area is unusable among 16 types of values“ 0 to F ”in which 4 bits are expressed in hexadecimal. "C: The predetermined address in the data area is full", "E: Data is already written in the predetermined address in the data area", "F: In the predetermined address in the data area" Expressed in four values over data is not written, "it can be rewritten in the order of" F (1111) "→" E (1110) "→" C (1100) "→" 8 (1000) ". Further, as a characteristic of the nonvolatile memory, when each internal bit is changed from “0” to “1”, data erasure occurs and there is a concern about the above-mentioned number of times limitation. However, each internal bit is changed from “1” to “1”. When changing to “0”, the above-mentioned number of times is not limited. This eliminates the need for excessive data erasure in the FCB area, so that the destruction of the FCB area can be prevented, and therefore the product life of the nonvolatile memory can be extended.

FIG. 1 is a system explanatory diagram showing the configuration of a file system for nonvolatile memory management according to an embodiment of the present invention.

  Embodiments to which a file system for managing nonvolatile memory according to the present invention is applied will be described below with reference to the drawings.

  FIG. 1 is a system explanatory diagram showing the configuration of a file system for nonvolatile memory management according to an embodiment of the present invention. This system has a plurality of blocks having a predetermined data capacity, and here, a non-volatile memory having 100 blocks of 150,000 bytes (hereinafter referred to as the first block B1 to the 100th block B100). A flash ROM 1 is provided, and a CPU 2 is provided for controlling the flash ROM 1, for example, for writing and erasing data.

  The flash ROM 1 includes a data area 10 having a predetermined range of addresses for each of a plurality of 100 blocks from the first block B1 to the 100th block B100, in this case, “1000-50999”. The first FCB area 11 for allocating and managing the write status of the data area 10 for each block in a predetermined range of addresses, here, addresses “0 to 499”, and In the first block B1, the write status for each of the first block B1 to the 100th block B100, which is a plurality of blocks, is assigned to a predetermined range of addresses, in this case, addresses "700 to 800" for management. The second FCB area 12 is provided.

  In the nonvolatile memory management file system having such a configuration, the CPU 2 includes the first FCB of the first block B1 among the first block B1 to the 100th block B100 constituting the flash ROM 1. The address “0” in the area 11 is associated with the addresses “1000 to 1099” in the data area 10 of the same block B 1, and the value of the address “0” is 16 types of “4” expressed in hexadecimal. Using only the values of “8”, “C”, “E”, “F” among the values of “0 to F”, recording is performed in the order of “F” → “E” → “C” → “8”. To do.

  Here, the 16 types of “0 to F” values in which 4 bits are expressed in hexadecimal are 2 values such as two numbers “1” and “0” respectively indicating data writing and data erasing described above. Notation in hexadecimal notation is expressed in hexadecimal notation, and “8” represented by “1000” in binary notation is the same as “predetermined address of data area 10 is unusable” “C” represented by “1100” in the binary notation indicates that “the predetermined address of the data area 10 is full”, and “1110” represented by “1110” in the similar binary notation. “E” indicates that “data has already been written at a predetermined address in the data area 10”, and “F” represented by “1111” in “same binary notation” indicates “a predetermined address in the data area 10 No data has been written to It shall be assigned respectively.

  Therefore, as described above, the CPU 2 has the “0” address included in the first FCB area 11 of the first block B1 constituting the flash ROM 1 and the “1000-1099” addresses included in the data area 10 of the block B1. When the value of the address “0” is “F”, it can be determined that “data is not written” at addresses “1000 to 1099”, and the value of the address “0” is If it is “E”, “data is already written” at addresses “1000 to 1099”, and if the value of “0” is “C”, addresses “1000 to 1099” have “free space”. If the value of the address "0" is "8", the value of the address "0" can be searched such that the addresses "1000 to 1099" are "unusable".

  By repeating the search operation as described above, the CPU 2 has “1, 2, 3,... 498, 499” included in the first FCB area 11 of the first block B1 constituting the flash ROM 1. The addresses “1100 to 1199, 1200 to 1299, 1300 to 1399,... 50800 to 50899, 50900 to 50999” included in the data area 10 of the same block B 1 are associated with each other, “1, 2, 3,. ... 498, 499 ”by searching for the value, 500 values of“ 0-499 ”in the same block B1 can be searched.

  Further, the CPU 2 is the first of the addresses “700 to 800” included in the second FCB area 12 of the first block B1 among the first block B1 to the 100th block B100 constituting the flash ROM 1. The address “700” is assigned to the first block B1, the second address “701” is assigned to the second block B2, and the third address “702” is assigned to the third block B1. Like block B3,..., “700 to 799” in the second FCB area 12 can correspond to a total of 100 blocks B1 to B100, respectively. As for the address value, the same retrieval means as described above is used. If the address value is “F”, “data has not been written”, and if “E”, “data has already been written. “F” → “E” → “C”, such as “Filled in”, “C”, “Full with no free space”, “8”, “Unusable”. By recording in the order of “→” 8, a total of 100 blocks from the first block B1 to the 100th block B100 can be used.

  Next, for example, writing data whose data length is fixed at 100 bytes to the flash ROM 1 in which a total of 100 blocks from the first block B1 to the 100th block B100 can be used or its A specific operation when erasing is performed under the control of the CPU 2 will be described.

  For example, when data is written at the first activation or reset activation, the CPU 2 performs the first (first) data writing operation in the first block B1 of the first block B1 constituting the flash ROM 1. For the values of addresses “700 to 799” in the FCB area 12, those in which “F” or “E” is recorded are searched in order from the top. Here, since the value at address “700” is determined to be “F” because all the data has been erased, the value is rewritten to “E”, and the first block B 1 ( The data area 10) to be set is set during data writing.

  Thereafter, the CPU 2 records “F” or “E” for the value of the address “0 to 499” included in the first FCB area 11 of the first block B1 constituting the flash ROM 1. Search in order from the top. Here, the value of the address “0” is determined as “F” because all the data has been erased, and the size of the area of “1000 to 1099” included in the data area 10 is also written. Since the data length matches the data length that is about to be written, the value can be rewritten to “C”, and data (data length fixed at 100 bytes) can be written in addresses “1000 to 1099” of the data area 10.

  Next, as the second data writing operation, the CPU 2 sets “F” or “E” for the value of the addresses “700 to 799” included in the second FCB area 12 of the first block B1 constituting the flash ROM 1. Search the recorded items in order from the top. Here, the value of address “700” is determined as “E” due to the first writing operation described above.

  Further, the CPU 2 records “F” or “E” for the value of the addresses “0 to 499” included in the second FCB area 12 of the first block B1 constituting the flash ROM 1. Search from the top in order. Here, the value of the address “0” is “C” due to the first writing operation described above, and the value of the address “1” is “F” because all the data has been erased. Therefore, the value can be rewritten to “C”, and data (data length is fixed at 100 bytes) can be written in addresses “1100 to 1199” of the data area 10, respectively.

  Note that the CPU 2 can repeatedly perform the above-described data writing operation on the first block B1 constituting the flash ROM 1, and when performing the 500th data writing operation, the second FCB. With respect to the values of addresses “700 to 799” in the area 12, the ones in which “F” or “E” is recorded are searched in order from the top. Here, the value of “700” is determined as “E” due to the 499th writing operation.

  Further, the CPU 2 records “F” or “E” for the value of the addresses “0 to 499” included in the second FCB area 12 of the first block B1 constituting the flash ROM 1. Search from the top in order. Here, the value of the “498” address is “C” due to the 499th writing operation, and the value of the “499” address is “F” because all the data has been erased. Therefore, the value can be rewritten to “C”, and data (data length is fixed at 100 bytes) can be written in addresses “50900 to 50999” of the data area 10, respectively.

  Furthermore, after completing the first to 500th data writing operations as described above, the CPU 2 is full because the first block B1 has no free space due to the 500th writing operation. Since additional writing cannot be performed, the value “700” in the second FCB area 12 of the first block B1 constituting the flash ROM 1 is rewritten to “C” as an instruction to that effect, and “ The value of the address “701” is set to “E”, and all data in the second block B2 are erased and set to “F”.

  Next, as the data write operation for the first time, the CPU 2 sets “F” or “E” for the value of the addresses “700 to 799” in the second FCB area 12 of the first block B1 constituting the flash ROM 1. Search the recorded items in order from the top. Here, the value of the address “701” is determined as “E” due to the 500th writing operation described above.

  Thereafter, the CPU 2 records “F” or “E” for the value of the address “0 to 499” included in the first FCB area 11 of the second block B 2 constituting the flash ROM 1. Search in order from the top. Here, since the value of the address “0” is determined as “F” because all the data is erased, the value is rewritten to “C”, and “1000 to 1099” that the data area 10 has. The data (the data length is fixed at 100 bytes) can be written in each address.

  The CPU 2 performs the data writing operation as described above for the second block B2 constituting the flash ROM 1 from the 501st to the 1000th operation, and for the third block B3, 1001. From the first operation to the 1500th operation, it can be repeated for the 100th block B100, such as from the 49501th operation to the 50000th operation.

  As a result, when 50000 pieces of data (with a data length fixed at 100 bytes) are written in the data area 10 of the first block B1 to the 100th block B100 constituting the flash ROM 1, all of them are written. Blocks B1 to B100 become full. The CPU 2 that has detected this writes “0” to the “800” address of the second FCB area 12 of the block B1, so that the data writing operation is performed from the first block B1 to the 100th block B100. It can be shown that it has made a round.

  Thereafter, as the data write operation for the 50001th time, the CPU 2 sets “F” or “E” for the value of the address “700 to 799” in the second FCB area 12 of the first block B1 constituting the flash ROM 1. Search the recorded items in order from the top. Here, since all the values of the addresses “700 to 799” are “C”, the value of the address “800” is searched. If it is determined that the value of “800” is “0”, the past data needs to be overwritten. Therefore, after all the data in the first block B1 is erased and rewritten to “F” , The value of the address “700” is rewritten to “E”, and the first block B1 (the data area 10 constituting the first block B1) is set during data writing.

  In addition, the CPU 2 records “F” or “E” for the value of the addresses “0 to 499” included in the first FCB area 11 of the first block B1 constituting the flash ROM 1. Search from the top in order. Here, since the value of the address “0” is determined as “F” because all the data is erased, the value is rewritten to “E”, and “1000 to 1099” that the data area 10 has. The data (the data length is fixed at 100 bytes) can be written in each address.

  Note that the data writing operation after the 5000th time is performed in the same process as the first to 499th times described above under the control of the CPU 2, and a specific description thereof will be omitted.

  Further, when a write error occurs in the data when the data write operation is performed, for example, when an error occurs at the address “1100 to 1199” which is the second write of the first block B1, The value of the address “1” in the first FCB area 11 of the first block B1 corresponding to the address “1100 to 1199” is rewritten to “8”, and the data abnormality at the address is recorded. As for the value of the address 499, the addresses where “F” or “E” are recorded can be searched again in order from the top, and the address where data is newly written can be searched.

  As is clear from the above description, the erasing operation related to the block among the first block B1 to the 100th block B100 constituting the flash ROM 1 is performed only once out of 50000 data writing operations. Since excessive data erasure in the first and second FCB areas 11 and 12 (at least the first FCB area 11) is not necessary, the destruction of the FCB area can be prevented. The product life of the flash ROM 1 can be extended.

  The non-volatile memory management file system of the present invention has been described with a specific embodiment. However, the present invention is not limited to this embodiment, and any configuration known so far as long as the effect of the present invention is achieved. It goes without saying that this system, for example, a system to which a nonvolatile memory other than the flash ROM 1 is applied can also be adopted.

  Further, when a nonvolatile memory other than the flash ROM 1 of the present invention is applied, the number of blocks having a predetermined data capacity constituting the memory, the data area 10 for each block, the first and second FCB areas 11, 12 Each of the predetermined addresses that can be changed can be changed as appropriate in accordance with the standard of the memory, and the number of times data can be written (the number of operations) varies.

  Further, in the present invention, only the first FCB area 11 among the first and second FCB areas 11 and 12 is arranged as the arrangement of the first block B1 to the 100th block B100 constituting the flash ROM 1. However, the present invention is not limited to this mode. For example, the first and second FCB areas 11 and 12 can be divided and arranged for each block.

1. Flash ROM (nonvolatile memory)
B1 to B100 ... 1st block to 100th block (plural blocks)
10 ... Data area 11 ... First FCB area 12 ... Second FCB area 2 ... CPU

Claims (3)

In a nonvolatile memory management file system comprising a nonvolatile memory having a plurality of blocks of a predetermined data capacity, and a CPU for controlling the nonvolatile memory,
The CPU allocates a value of a predetermined address included in the data area allocated to a predetermined address included in a first FCB area of a first block of the plurality of blocks, and is allocated to the plurality of blocks, respectively. The value of the predetermined address included in the second FCB area of the first block is set to “8”, “C”, “E” among 16 types of “0 to F” values represented by 4 bits in hexadecimal notation. ”And“ F ”, and a file system for nonvolatile memory management, wherein the file system is rewritten in the order of“ F ”→“ E ”→“ C ”→“ 8 ”.   The values of “8”, “C”, “E”, and “F” are set to “a predetermined address in the data area is unusable”, “a predetermined address in the data area is full”, 2. The nonvolatile memory management according to claim 1, wherein the data is assigned to “data is already written at a predetermined address in the data area” and “data is not written at a predetermined address in the data area”. File system. In a nonvolatile memory management file system comprising a nonvolatile memory having a plurality of blocks of a predetermined data capacity, and a CPU for controlling the nonvolatile memory,
The nonvolatile memory includes a data area having a predetermined range of addresses for each block, a first FCB area for allocating and managing a write status of the data area to a predetermined range of addresses, and the block And a second FCB area for managing the write status of addresses in a predetermined range of addresses,
A file system for nonvolatile memory management, wherein at least a first FCB area of the first and second FCB areas is divided and arranged for each of the plurality of blocks.

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