JP2012178754A - Electric power combiner - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent characteristic deterioration accompanying to reduction of a lateral dimension while reducing the lateral dimension of an electric power combiner.SOLUTION: An electric power combiner includes: a first impedance transformer which constitutes a serial circuit about which, from an input side, a first line, return line, second line, and straight line are connected, and about which its input side is connected to an input terminal; a second impedance transformer having the same structure as the first impedance transformer; an isolation circuit making up a loop with the first and second impedance transformers; and an output impedance transformers disposed between an output contact point shared by the first and second impedance transformers and an output terminal. The first line and the second line are arranged in parallel to each other, an aspect ratio of lateral and longitudinal length of the loop is less than 1, the phase of an input signal is turned 90 degrees by narrowing the line width of the first line than the line width of a first return line, the isolation circuit matches to input impedance, and the output impedance transformer matches to output impedance.

Description

  The present invention relates to a power amplifier, and more particularly to a power amplifier suitable for amplification of a signal in a microwave band or a millimeter wave band.

  As an example, the parallel amplifier includes amplifiers 5a to 5d arranged in parallel as shown in FIG. 14, a power distribution circuit 3 that distributes inputs, and a power combiner circuit 4 that combines the outputs of the amplifiers. The RF signal input from the input terminal 1 is distributed by the power distribution circuit 3 into signals having the same homologous amplitude. In FIG. 14, the power distribution circuit 3 has a two-stage configuration, and is divided into two by the power distributor 3a, and further divided into two by the power distributor 3b and the power distributor 3c, respectively. The power combining circuit 4 that combines the amplified signals is symmetrical with the power distribution circuit 3.

The outputs of the amplifiers 5a and 5b are combined by the power combiner 4a, the outputs of the amplifiers 5c and 5d are combined by the power combiner 4c, and the outputs of the power combiners 4a and 4c are combined by the power combiner 4b. Output from the output terminal 2. In a two-branch structure such as the power combining circuit 4, ^2N parallel signals can be combined into one signal in N stages. Furthermore, if a Wilkinson power combiner is used for a node having a two-branch structure, high isolation can be ensured between branches (for example, see Patent Document 1).

  Before describing the problem to be solved by the present invention, the basic configuration and operation of the Wilkinson power combiner will be described. In the basic circuit configuration shown in FIG. 15, 21 and 22 are input terminals, 23 is an output terminal, 204a and 204b are impedance transformers that connect between 21 and 23, and between 22 and 23, respectively. It is a transmission line having a quarter wavelength (λ / 4) with respect to the frequency. Reference numeral 205 denotes an isolation resistor that connects between 21 and 22. When the input impedance is designed to be Zi (= Ri) and the output impedance is set to Zo (= Ro) so that the reflection loss is minimized, the resistance value Rs of 205 is set as Expression (1).

Impedance transformer 204a, the characteristic impedance _{Z b} of 204b is set as Equation (2).

When the amplitude and phase of the input are the same, the isolation resistor 205 is equal to the absence of the terminal because the terminal has the same potential and no current flows. In that case, the input impedance Ri seen from the output side of the impedance transformers 204a and 204b is transformed to 2 * Ro (from the equations (2) and (3)). Since the transformed impedance is connected in parallel, it is equivalently Ro and matched with the output impedance Ro.

The basic principle of isolation between inputs will be described next. When the signal is input from only one of the inputs, for example, from the input terminal 21, the signal component having a phase rotation of 0 degrees flowing out through the isolation resistor 205 cancels with the signal component having a phase rotated by 180 degrees through the impedance transformers 204a and 204b. As a result, the backward signal flowing out from the terminal 22 is greatly reduced. In order to maximize the isolation, the circuit parameters may be set so that the amplitudes of the two components are equal at the required frequency.

  In order to make the phase rotation of the signal passing through the isolation resistor 205 approach 0 degrees, it is necessary to narrow the interval between the input terminals 21 and 22. Further, since the impedance transformers 204a and 204b and the isolation resistor 205 are topologically connected to the loop, it is desirable to have a structure that is not spatially close so that parasitic coupling hardly occurs. In the case of an n-sided regular polygon having a constant peripheral length L, the lateral width d is obtained by the equation (4).

However, n is an even number. The value of equation (4) monotonically increases with respect to n and becomes maximum when n is infinite. That is, d (= L / π) is maximized in the case of a circle. For example, when the ¼ wavelength is 400 μm, L = 800 μm and d≈255 μm.

  As a result, it is preferable that the impedance transformers 204a and 204b have a semicircular layout as shown in the two-dimensional structural diagram of FIG. If S0 and Y0 are a loop horizontal dimension and a loop vertical dimension, respectively, the aspect ratio is S0 / Y0 = 1. In FIG. 16, reference numerals 201 and 202 denote circuits upstream of the power combiner, and reference numeral 203 denotes a 50Ω line for connection to a circuit subsequent to the power combiner.

  FIG. 17 shows the ideal characteristics of a conventional Wilkinson power combiner. The characteristic curve portion corresponding to the required frequency (indicated by ▼) is located at the center of the Smith chart so that the input reflection (FIG. 17a) and the output reflection (FIG. 17d) are minimized. The input separation (FIG. 17b) is preferably -20 dB or less. The characteristic indicating the pass gain (FIG. 17c) is represented by the output contribution of each input, and is equal to −3.01 dB in the required frequency band when there is no loss, but is lower if there is a loss.

JP 11-330813 A

“Analysis and Design of Compact Two-way Wilkinson Power Dividers Using Coupled Lines,” APMC 2009, pp. 1319-1322 “Characteristics of Coupled Microstriplines,” IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-27, No. 7, July 1979, pp. 700-705

  The power distribution circuit is structurally similar to the power combining circuit, only the input / output relationship is reversed. In the following description of the power combiner, it is clear that if “combining” is replaced with “distribution” by reversing the input / output relationship, the contents also apply to the power distribution circuit. The same applies to the description of the power distributor.

  Also, in this specification, the description and figure display are unified so that signals are input from the left and output to the right, and “horizontal” on the left and right and “vertical” on the top and bottom.

  When the impedance transformers 204a and 204b are semicircular as shown in FIG. 16, there is a problem that the circuit area is large. In order to solve this, in the Wilkinson power divider disclosed in Non-Patent Document 1, the loop area is reduced by arranging impedance transformers 214a and 214b in parallel as shown in FIG.

  In this case, the horizontal / vertical aspect ratio S3 / Y3 is several times larger than 1. However, when the outputs of the parallel amplifiers are synthesized by a circuit with a built-in chip, to reduce the area, a small horizontal dimension, that is, a positive fraction whose horizontal / vertical aspect ratio is as small as possible is required. This is because the vertical dimension of the chip is determined by the parallel amplifying unit, and the horizontal dimension becomes smaller as the output terminal of the power combiner approaches the input terminal, and an increase in chip area can be suppressed. However, when the lateral dimension is reduced, the characteristic impedance changes due to the self-coupling of the lines, and the input separation and input / output matching deteriorate. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to prevent characteristic deterioration caused by a reduction in the horizontal dimension of the power combiner while reducing the horizontal dimension of the power combiner.

  Of the inventions disclosed in this application, typical ones will be briefly described as follows.

  A first series circuit in which the first line, the first return line, the second line, and the first straight line are connected in order from the input side is configured, and the input side of the first series circuit is connected to the first input terminal. 1 impedance transformer and the 2nd series circuit where the 3rd line, the 2nd turnback line, the 4th line, and the 2nd straight line are connected in order from the input side are constituted, and the input side of the 2nd series circuit is the 2nd input A second impedance transformer connected to the terminal, an isolation circuit disposed between the first input terminal and the second input terminal and constituting a loop with the first impedance transformer and the second impedance transformer; An output impedance transformer disposed between an output contact and an output terminal shared by the impedance transformer and the second impedance transformer, the first line and the second line, and the third line and the fourth line, respectively. Flat to each other The ratio of the width of the loop in the input / output direction to the width of the loop in the direction orthogonal to the input / output direction is smaller than 1, and the line width of the first line is narrower than the line width of the first folded line. Since the width is narrower than the line width of the second folded line, the input signal phase is rotated by 90 degrees in each of the first impedance transformer and the second impedance transformer, and the input impedance is matched by the isolation circuit, and the output impedance transformer is used. A power combiner that matches the output impedance.

  ADVANTAGE OF THE INVENTION According to this invention, the characteristic deterioration accompanying a horizontal dimension reduction can be prevented, making the horizontal dimension of a power combiner small.

1 is an example of a circuit diagram of a power combiner according to a first embodiment. It is an example of the schematic sectional drawing which shows the capacity | capacitance component of the even number (Even) mode and odd number (Odd) mode in parallel MSL. 10 is an example of a layout diagram showing a two-dimensional structure of a power combiner according to Embodiment 2. FIG. 6 is an example of an equivalent circuit diagram showing a power combiner according to Embodiment 2. FIG. 10 is an example of a graph illustrating characteristics of a power combiner according to the second embodiment. 10 is an example of a layout diagram illustrating a two-dimensional structure of a power combiner according to a third embodiment. FIG. 10 is an example of an equivalent circuit diagram illustrating a power combiner according to a third embodiment. FIG. FIG. 9 is an example of a schematic diagram illustrating a trajectory on a complex plane representing impedance transformation of a multi-stage MSL according to the third embodiment. 12 is an example of a graph showing characteristics of a power combiner according to a third embodiment. 6 is an example of an equivalent circuit diagram showing a power combiner according to Embodiment 2. FIG. 10 is an example of an equivalent circuit diagram illustrating a power combiner according to a third embodiment. FIG. FIG. 10 is an example of a circuit diagram illustrating a power combining circuit according to a fourth embodiment. FIG. 10 is an example of a circuit diagram illustrating a parallel amplifier according to a fifth embodiment. It is a circuit diagram which shows the block configuration of the conventional parallel type amplifier. It is a circuit diagram which shows the conventional Wilkinson system power combiner. FIG. 6 is a layout diagram showing a two-dimensional structure of a conventional Wilkinson power combiner. It is a graph which shows the characteristic of the conventional Wilkinson system power combiner. It is a layout figure which shows the two-dimensional structure of the conventional Wilkinson-type power divider | distributor.

  1 is a circuit diagram of a power combiner according to Embodiment 1 of the present invention. The impedance transformer 120a has a series circuit including a line 121a, a return line 122a, a line 123a, and a straight line 124a connected in order from the input side. The line 121a and the line 123a are arranged in parallel with each other, and the input side of the series circuit is connected to the input terminal 11.

  The impedance transformer 120b has the same structure as the impedance transformer 120a. That is, it has a series circuit composed of a line 121b, a folded line 122b, a line 123b, and a straight line 124b connected in order from the input side. The line 121 b and the line 123 b are arranged in parallel to each other, and the input side is connected to the input terminal 12.

  The isolation circuit 125 is connected between the input terminal 11 and the input terminal 12, and forms a loop with the impedance transformer 120a and the impedance transformer 120a.

  The output impedance transformer 126 is connected between the output contact 14 and the output terminal 13 shared by the impedance transformer 120a and the impedance transformer 120b.

  When the line is formed on the surface of the dielectric substrate on the backside ground, it can be modeled by a microstrip line (MSL). In the following, the case where the line is MSL will be described, but it is considered that the line is qualitatively applied to transmission lines other than MSL.

  Lines arranged in parallel have different characteristic impedances from lines of the same line width isolated by mutual coupling. First, the characteristic impedance of the parallel MSL will be described. According to Non-Patent Document 2, as shown in FIG. 2, in the parallel MSL of the line width W, the line interval S, and the substrate thickness H, the unit line length capacities of the even mode and the odd mode are expressed by the equations (5) and (6), respectively. Given in.

However, ε ₀ is the vacuum dielectric constant, ε _r is the relative dielectric constant of the substrate, ε _re is the equivalent dielectric constant, and c is the speed of light, and Equations (7) to (15) are established.

When the index i indicates the even mode or the odd mode, and the capacity in the air is C _i ^a , the characteristic impedance and the equivalent relative dielectric constant are obtained by the equations (16) and (17).

Although the above description applies to the case of symmetric parallel MSL, it is assumed that even-numbered and odd-numbered modes exist in the same way in asymmetric parallel MSL and operate in the same manner qualitatively.

  When there is a parallel MSL portion due to folding, the odd-mode characteristic impedance is effective. The line-to-line capacitance of the parallel MSL portion has an effect, and the characteristic impedance is reduced. As a result, the phase rotation is equivalently reduced in the line 121a. It can be understood by rewriting equation (3) as equation (18).

When the absolute value of tan (βl) is small, the denominator can be approximated by 1. Since the second term of the numerator proportional to Z _b, Z _b is the equivalent to tan (βl) is reduced smaller, the phase rotation is reduced.

  That is, if the horizontal dimension of the power combiner is reduced by using the line width W0 of the isolated straight line MSL corresponding to the characteristic impedance determined by the equation (2) as in the Wilkinson type power combiner of the prior art, it exists due to folding. In the parallel MSL portion, the characteristic impedance is reduced. For this reason, phase rotation becomes insufficient, and an error is also generated in impedance transformation, so that the characteristics of input separation and input / output matching deteriorate.

  Therefore, in this embodiment, paying attention to the change in the characteristic impedance of the parallel MSL portion, the phase rotation is increased by changing the line width of the parallel MSL portion. Specifically, the capacitance is reduced and the characteristic impedance is increased by reducing the line width of the parallel MSL portions 121a and 121b. As a result, the phase rotation increases, and the input signal phase can be rotated by 90 degrees in the impedance transformers 120a and 120b with respect to the center frequency of the required frequency band, whereby the input separation can be improved. In general, since the deviation of impedance transformation remains, in this embodiment, the output impedance transformer 126 improves the matching with the output impedance, and the isolation circuit 125 improves the matching with the input impedance. Input / output matching can be improved at the same time.

  Also, the line width of the parallel MSL portion can be changed asymmetrically. Specifically, the phase rotation can be increased by making the line width of the line 123a wider than the line width of the straight line 124a and making the line 123b wider than the line width of the straight line 124b. In this case, it is also possible to realize 90-degree phase rotation by changing the line length of the impedance transformers 120a and 120b according to the change of the line width depending on the design conditions. Thereby, unlike the Wilkinson-type power combiner of the prior art, the total line length of each of the impedance transformers 120a and 120b can be made smaller than ¼ wavelength.

  In the first embodiment of the present invention, when the horizontal dimension of the loop of the power combiner is narrowed and the horizontal / vertical aspect ratio of the loop is smaller than 1, the input separation and the input / output matching are achieved without significantly increasing the loop length. Can achieve good performance.

  FIG. 3 is a layout diagram showing a two-dimensional structure of the power combiner according to the second embodiment of the present invention.

  The impedance transformer 100a is configured by a series circuit of an MSL 101a, a semicircular MSL 102a, an MSL 103a, and a straight MSL 104a, and is connected to the input terminal 11. The impedance transformer 100b is configured by a series circuit of an MSL 101b, a semicircular MSL 102b, an MSL 103b, and a straight MSL 104b, and is connected to the input terminal 12. An isolation resistor 105 is connected between the input terminals 11 and 12, and forms a loop with the impedance transformer 100a and the impedance transformer 100b.

  An output impedance transformer 106 is connected between the output contact 14 and the output terminal 13 shared by the impedance transformer 100a and the impedance transformer 100b.

  In this embodiment, the MSL 101a and the MSL 103a are arranged in parallel, the MSL 101b and the MSL 103b are arranged in parallel, the line width of the MSL 101a and the MSL 101b is W5, and the line width of the MSL 103a and the MSL 103b is W6. Furthermore, the line widths of the semicircular MSL 102a, the semicircular MSL 102b, the straight MSL 104a, and the straight MSL 104b are equal, and are set to W7.

  The impedance transformer 100a and the impedance transformer 100b are asymmetrical, and the length of the straight line MSL 104a and the straight line MSL 104b is determined by the length of the isolation resistor 105. S1 and Y1 are a loop horizontal dimension and a loop vertical dimension, respectively. The aspect ratio S1 / Y1 is smaller than 1.

FIG. 4 is an equivalent circuit diagram of FIG. However, the microwave connection element that accurately models the discontinuous joint of the microwave circuit is omitted. W7 is equal to the line width of the linear MSL orphaned having a characteristic impedance Z _b obtained from equation (2). Even if the line width dimension is optimized in accordance with restrictions on layout design or manufacturing, it is considered to be within the scope of the present invention. The resistance value of the isolation resistor 105 is equal to Rs in Expression (1).

  As in the first embodiment, the odd-mode characteristic impedance is effective in the parallel MSL portion formed by the MSL 101a and the MSL 103a. If the line widths of the parallel MSL portions 101a and 101b are narrower than W7, the reduction in phase rotation can be corrected and the separation between inputs can be improved. Furthermore, input matching can be ensured by the isolation resistor 105, and output matching can be ensured by the output impedance transformer 106.

  Furthermore, it is also possible to change the line length of the impedance transformers 100a and 100b in accordance with the change of the line width according to the design condition and realize 90 degree phase rotation. Thereby, unlike the Wilkinson power combiner of the prior art, the total line length of the impedance transformers 100a and 100b can be made smaller than ¼ wavelength.

  In FIGS. 3 and 4, although depicted as semi-circular MSL 102a and semi-circular MSL 102b, there are shapes including octagons or rectangles due to process limitations in implementation. Furthermore, it is possible to intentionally change the line width of the rectangular bend to suppress the deterioration of the microwave performance.

  The output impedance transformer 106 can be realized by MSL, but may be configured by a matching circuit including a lumped constant element. As shown in FIG. 10, the output matching circuit 130 can be configured by a series capacitor 131 and a grounded inductance 132 between the output contact 14 and the output terminal 13.

  FIG. 5 shows characteristics obtained from the simulation of the power combining circuit of FIG. 4 designed when the lateral dimension is 70 μm by the above method. It was assumed that the substrate thickness was 100 μm, the relative dielectric constant was 12.9, and the required frequency band was 58 GHz to 67 GHz. The input / output impedance is designed to be 50Ω so as to minimize the input / output reflection within the required frequency band delimited by the marker (▼) (FIGS. 5A and 5D). The isolation resistance is 100Ω. As shown in FIG. 5B, the isolation is −25 dB or less. The pass gain (FIG. 5C) is expressed as an output contribution to the input, and is about 0.1 dB lower than -3.01 dB (in the case of no loss).

  From the simulation results, the power combiner of the second embodiment can realize performance suitable for output combining in the parallel type high power amplifier. Furthermore, compared with a power combiner of the prior art as shown in FIG. 16, the present invention can realize a lateral width reduction of 70% or more, which is suitable for chip incorporation.

  FIG. 6 is a layout diagram showing a two-dimensional structure of the power combiner according to the third embodiment of the present invention.

  The impedance transformer 110a is composed of a series circuit of an MSL 111a, a semicircular MSL 112a, an MSL 113a, and a straight MSL 114a, and is connected to the input terminal 15. The impedance transformer 110b is configured by a series circuit of an MSL 111b, a semicircular MSL 112b, an MSL 113b, and a straight MSL 114b, and is connected to the input terminal 16. A series circuit of the capacitor 118a, the isolation resistor 115, and the capacitor 118b is connected between the input terminals 15 and 16, and forms a loop with the impedance transformer 110a and the impedance transformer 110b.

  An output impedance transformer 116 is connected between the output contact 18 and the output terminal 17 shared by the impedance transformer 110a and the impedance transformer 110b.

  In this embodiment, MSL 111a and MSL 113a are arranged in parallel to each other, MSL 111b and MSL 113b are arranged in parallel to each other, the line width of MSL 111a and MSL 111b is W8, and the line width of MSL 113a and MSL 113b is W9. Further, the line width of the semicircular MSL 112a and the semicircular MSL 112b is W10, and the line width of the straight MSL 114a and the straight MSL 114b is W11.

  The impedance transformer 110a and the impedance transformer 110b are asymmetrical, and the length of the straight line MSL 114a and the straight line MSL 114b is determined by the length of the series circuit of the capacitor 118a, the isolation resistor 115, and the capacitor 118b.

  S2 and Y2 are a loop horizontal dimension and a loop vertical dimension, respectively. The aspect ratio S2 / Y2 is smaller than 1.

FIG. 7 is an equivalent circuit diagram of FIG. However, the microwave connection element that accurately models the discontinuous joint of the microwave circuit is omitted. When the line width of the isolated linear MSL having a characteristic impedance Z _b obtained from the equation (2) and W0, W10 and narrower than W0, it is a feature of the present embodiment to set the W11 wider than W0. That is, the relationship of Formula (19) is established.

Further, if the characteristic impedance of the straight line MSL with the line width W10 is Z _M1 and the characteristic impedance of the straight line MSL with the line width W11 is Z _M2 , the relationship of Expression (20) is established. mag () means an absolute value.

Figure 8 is MSL and characteristic impedance _{Z M1,} 2-stage MSL due to impedance changes the impedance of the complex plane of the _{Z M2} (real _{Z r} is the horizontal axis of the characteristic impedance _{Z b} for a fixed frequency, the imaginary _{Z im} the vertical axis ). Assuming that Z ₁ = Zi (= Ri) and Z ₂ = 2Zo = (2Ro), the relationship of Expression (21) and Expression (22) is established.

In Equation (21), β ₂ and l ₂ are the wave number and line length of the straight line MSL whose line width is W11, and in Equation (22), β ₁ and l ₁ are the wave number and line of the straight line MSL whose line width is W10. It is long. Z ₃ is the output-side termination impedance (= Z ₂ ) viewed from the discontinuous interface of the two-stage MSL.

On the complex plane of impedance, the impedance transformed by MSL has a circular trajectory with respect to the MSL length. Trajectory corresponding to a quarter wavelength MSL characteristic impedance _{Z b} is a circumferential angle of 180 degrees. However, since the trajectory corresponding to the two-stage MSL of the characteristic impedances Z _M1 and Z _M2 has a longer radius than that of the characteristic impedance Z _b , the circumferential angle of the trajectory corresponding to each stage is smaller than 90 degrees. Accordingly, in the two-stage MSL, even if the total line length is shorter than ¼ wavelength, the phase rotation can be equivalently realized by 90 degrees. Therefore, when applied to a power combiner, the area can be reduced.

  In the third embodiment, as in the description of the first embodiment, the odd-mode characteristic impedance is effective in the parallel MSL portion constituted by the MSL 111a and the MSL 113a. The line width of the parallel MSL portion is set so that Expression (23) is established. Or it sets so that Formula (23) and Formula (24) may be materialized simultaneously.

As a result, the reduction of phase rotation due to the coupling of parallel MSL portions is corrected, and the separation between inputs is improved. Furthermore, output matching is ensured by the output impedance transformer 106, and input matching is ensured by optimizing the capacitance 118a, the isolation resistor 115, and the capacitance 118b having the same capacitance value as the capacitance 118a.

  Furthermore, it is possible to change the line length of the impedance transformer 100a and the impedance transformer 100b according to the change of the line width according to the design condition, and realize the 90 degree phase rotation together with the change of the line width.

  FIG. 9 shows characteristics obtained from the simulation of the power combiner of the third embodiment. The substrate and frequency conditions are the same as in FIG. The input / output impedance is designed to be close to 50Ω so that the input / output reflection is minimized within the required frequency band delimited by the marker (▼) (FIGS. 9A and 9D). The isolation resistance is 70Ω and the capacitance is 0.12 pF. As shown in FIG. 9B, the isolation is −25 dB or less. The pass gain (FIG. 9 (c)) is expressed as an output contribution to the input, and is about 0.1 dB lower than -3.01 dB (in the case of lossless).

  From the simulation results, the power combiner of the third embodiment can realize performance suitable for output combination in the parallel type high power amplifier. Furthermore, compared with a conventional power combiner as shown in FIG. 16, the present invention can realize a reduction in lateral width of 70% or more in lateral dimension. Further, since the relationship of Expression (19) is established, the vertical dimension can be reduced by 45% or more compared to the example of the second embodiment, which is suitable for incorporating a chip.

  As in the second embodiment, the output impedance transformer 116 can be realized by MSL, but may be configured by a matching circuit including a lumped constant element. As shown in FIG. 11, the output matching circuit 140 can be configured by a series capacitor 141 and a grounded inductance 142 between the output contact 18 and the output terminal 17.

  FIG. 12 is a circuit diagram showing a power combining circuit according to the fourth embodiment of the present invention. Signals input from the terminals 61 and 62 are combined by the power combiner 6a via the 50Ω lines 601 and 602, and signals input from the terminals 63 and 64 are combined by the power combiner 6b via the 50Ω lines 603 and 604. Is done. The outputs of the power combiners 6a and 6b are combined by the power combiner 6c via the 50Ω lines 605 and 606. The power combiners described in the first to third embodiments are applied to the power combiners 6a to 6c.

FIG. 12 shows a two-stage two-branch structure, but it is clear that the number of input signals can be increased by increasing the number of stages by the same method. The N-stage power combining circuit can combine 2 ^N parallel signals into one signal.

  In the power combiner 6a or 6b that is not the power combiner 6c connected to the output terminal 62, each output impedance transformer 616a or 616b is an MSL bent in an L shape. In the power combining circuit of this embodiment, the parallel distance S3 between the vertical portion of the L-shaped MSL and the power combiner 6a or 6b is wider than the parallel distance S4 between the vertical portion of the L-shaped MSL and the subsequent power combiner 6c. As described above, an L-shaped MSL is arranged. Thereby, the characteristic change by the parasitic coupling of the L-shaped MSL and the power combiner can be suppressed.

  If the final stage power combiner 6c is implemented by the matching circuit 36 composed of lumped constant elements for matching with the output impedance, the area can be further reduced.

  FIG. 13 is a circuit diagram showing a parallel system amplifier according to the fifth embodiment of the present invention. The parallel amplifier includes a power combining circuit including parallel power amplifiers 5a to 5d and power combiners 6a to 6c, and a power distribution circuit that is used for power distribution by inverting the input / output of the power combiners 6a to 6c. . The power combiners 7a to 7c used for power distribution are hereinafter referred to as power distributors. The power combining circuit described in the fourth embodiment is applied to the power combining circuit.

  The input is divided into two by the power distributor 7c, further divided into four signals of the same homologous amplitude to the power distributors 7a and 7b, and input to the parallel power amplifiers 5a to 5d. The signals amplified by the power amplifier are combined by the power combiners 6a and 6b, and further combined by the power combiner 6c to become one signal.

  In the parallel amplifier, the chip vertical dimension is determined by the power amplifier, and the chip area can be reduced by reducing the horizontal dimensions of the power distribution circuit and the power combining circuit.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made. Those skilled in the art can appropriately combine the above-described embodiments. Will be understood.

1, 11, 12, 15, 16, 21, 22, 61-64, 66 ... input terminals 2, 13, 17, 23, 65, 67 ... output terminals 14, 18 ... output contacts 100a, 100b, 110a, 110b, 120a, 120b, 204a, 204b, 214a, 214b ... impedance transformers 101a, 103a, 101b, 103b, 111a, 113a, 111b, 113b ... (parallel) MSL
102a, 102b, 112a, 112b ... semicircular MSL
104a, 104b, 114a, 114b ... straight MSL
105, 115, 205, 215 ... isolation resistors 106, 116, 126, 36, 37 ... output impedance transformers 118a, 118b ... capacitors 121a, 123a, 121b, 123b ... (parallel) lines 122a, 122b ... folded lines 124a, 124b ... straight line 125 ... isolation circuit 130, 140 ... output matching circuit 131, 141 ... capacitance 132, 142 ... inductance 201, 202, 203, 601-606 ... 50 ohm line 3 ... power distribution circuits 3a-3c, 7a-7c ... Power distributor 4 ... Power combiners 4a to 4c, 6a to 6c ... Power combiners 5a to 5d ... Amplifiers 616a and 616b ... L-shaped MSL

Claims (5)

A first series circuit in which the first line, the first return line, the second line, and the first straight line are connected in order from the input side is configured, and the input side of the first series circuit is connected to the first input terminal. A first impedance transformer;
A second series circuit is configured in which the third line, the second folded line, the fourth line, and the second straight line are connected in order from the input side, and the input side of the second series circuit is connected to the second input terminal. A second impedance transformer;
An isolation circuit disposed between the first input terminal and the second input terminal and forming a loop with the first impedance transformer and the second impedance transformer;
An output impedance transformer disposed between an output contact and an output terminal shared by the first impedance transformer and the second impedance transformer;
The first line and the second line, the third line and the fourth line, each arranged in parallel with each other,
The ratio of the width of the loop in the input / output direction to the width of the loop in the direction orthogonal to the input / output direction is less than 1,
The line width of the first line is narrower than the line width of the first folded line, and the line width of the third line is narrower than the line width of the second folded line, so that the first impedance transformer and the second line Each input signal phase is rotated 90 degrees with an impedance transformer,
Match the input impedance with the isolation circuit,
A power combiner that matches the output impedance with the output impedance transformer. The power combiner according to claim 1, wherein
The input impedance is Ri, the output impedance is Ro,
Z _b = √ (2 * Ri * Ro)
If the W0 the line width of an isolated straight line having a determined characteristic impedance Z _b by,
The line width of the first folded line, the line width of the first straight line, the line width of the second folded line, the second straight line is equal to W0,
The isolation circuit is a first resistor having a resistance value of 2 * Ri;
The power combiner, wherein the output impedance transformer is a transmission line or a matching circuit including a lumped constant capacitance and a lumped constant inductance. The power combiner according to claim 1, wherein
The input impedance is Ri, the output impedance is Ro, and Ri <2 * Ro
age,
Z _b = √ (2 * Ri * Ro)
If the W0 the line width of an isolated straight line having a determined characteristic impedance Z _b by,
The line width of the first folded line and the line width of the second folded line are narrower than W0,
The line width of the first straight line and the line width of the second straight line are wider than W0,
The isolation circuit is a series circuit including a first capacitor, a second resistor, and a second capacitor having the same capacitance value as the first capacitor;
The power combiner, wherein the output impedance transformer is a transmission line or a matching circuit including a lumped constant capacitance and a lumped constant inductance. A power combining circuit having a two-branch structure with N inputs (N ≧ 4) and one output using at least one power combiner according to claim 1,
The output impedance transformer of each of the second power combiner and the third power combiner connected to the input terminal of the first power combiner connected to the output terminal is an L-shaped transmission line,
A power combining circuit in which a distance between the L-shaped vertical line portion and the first power amplifier is smaller than a distance between the L-shaped vertical line portion and the second power combiner or the third power combiner. A power combining circuit according to claim 4;
A parallel amplifier having a plurality of amplifiers arranged in parallel,
A parallel-type amplifier that synthesizes outputs of the plurality of amplifying units using the power combining circuit.