JP2012175319A - Clock generation device, dll (digital locked loop) circuit and clock generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DLL circuit that generates a high precision clock in a small circuit scale and simple design configuration.SOLUTION: The DLL circuit includes: a clock generation section 100 for generating, from an externally input operating clock clks, an input clock having a different or same frequency from or as the operating clock and a set value k indicating a desired frequency, a generated clock clkc having a frequency that is the operating clock frequency divided by the set value k; a phase comparison section 200 for comparing the generated clock clkc with an externally input reference clock clkr in phase and outputting a phase difference; and a correction section 300 for generating a correction value for correcting the set value k to bring the phase difference to "0" in accordance with the phase difference output from the phase comparison section 200, and adding the correction value to the set value k.

Description

  The present invention relates to a technique for generating a clock having an arbitrary frequency based on an operation clock.

As a technique related to the present invention, for example, there is a timing signal generation circuit disclosed in Patent Document 1.
The timing signal generating circuit disclosed in Patent Document 1 adds a variable delay to an input clock and generates an arbitrary frequency by dividing it.
The variable delay is, for example, a tap type delay stage such as a delay line. Adding a delay selects one output of each tap of the tap type delay stage, and division means selecting the selected tap output. 1 / (2 ^ n).
However, the above-described configuration has a problem that the resolution (accuracy) of the generated frequency depends on the minimum delay amount of the variable delay used and becomes rough.
Patent Document 1 also discloses a method of configuring a variable delay with a four-phase clock generation circuit (assuming a DLL (Digital Locked Loop) configuration) and a phase interpolator (see FIG. 26).
In this configuration, since an arbitrary delay (phase shift) can be generated by the phase interpolator, the problem that the resolution (accuracy) of the generated frequency becomes rough is solved.
However, in this configuration, since a four-phase clock generation circuit and a phase interpolator are used, there are problems that the circuit scale is large and the design is complicated.

JP 2000-196418 A

From the above, in the conventional technology, it is possible to generate a wide range of frequencies (wide frequency range), but when the circuit scale is small and the design is easy, the resolution (accuracy) of the generation frequency deteriorates. When the accuracy is improved, the circuit scale is large and the design is complicated.
In other words, in the conventional technology, it is impossible to achieve both the accuracy of the generation frequency, the circuit scale, and the ease of design.

  One of the main objects of the present invention is to solve such problems, and it is a main object of the present invention to generate a highly accurate clock with a configuration that is small in circuit scale and easy to design. .

A clock generation device according to the present invention includes:
An operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a reference for phase adjustment is obtained from the accumulated result. An accumulation unit for generating a clock, a first control signal for controlling a delay amount, and a second control signal for controlling timing of phase adjustment;
A clock having a predetermined frequency is input from the outside as an input clock, the first control signal generated by the accumulator is input, and a delay amount controlled by the first control signal is given to the input clock. A variable delay unit for generating a delay clock of the input clock;
The reference clock generated by the accumulation unit and the second control signal are input, the delay clock generated by the variable delay unit is input, the phase of the reference clock is enabled by enabling the second control signal And a phase adjustment unit that generates a clock having a frequency obtained by dividing the frequency of the operation clock by (twice the set value).

  According to the present invention, a highly accurate clock can be generated with a configuration with a small circuit scale and easy design.

FIG. 3 is a block diagram for explaining a DLL circuit configuration according to the first embodiment. 3 is a block diagram for illustrating a configuration of an accumulation unit 110 according to Embodiment 1. FIG. 6 is a diagram for explaining an operation of an accumulator 111 in an accumulator 110 according to Embodiment 1. FIG. 6 is a diagram for explaining a relationship between an operation of an accumulator 111 in an accumulator 110 and a set value k in the first embodiment. FIG. 6 is a diagram for explaining an operation of a reference clock clka generation unit 113 in an accumulation unit 110 in the first embodiment. FIG. 3 is a block diagram for illustrating a configuration of a variable delay unit 120 according to Embodiment 1. FIG. 6 is a diagram for explaining a relationship between an input and an output to delay element 121 in the first embodiment. FIG. 3 is a block diagram for explaining a configuration of a phase adjustment unit 130 according to Embodiment 1. FIG. 6 is a diagram for explaining an operation of a phase adjustment unit 130 according to Embodiment 1. FIG. FIG. 6 is a diagram for illustrating the accuracy of a generated clock clkc in the DLL circuit according to the first embodiment. FIG. 6 is a block diagram for explaining a DLL circuit configuration according to a second embodiment. FIG. 10 is a block diagram for illustrating a configuration of an accumulating unit 110 in a second embodiment. FIG. 11 is a diagram for explaining the operation of an accumulator 111 in an accumulator 110 in the second embodiment. 6 is a block diagram for explaining a configuration of a pulse generation unit 140 in Embodiment 2. FIG. FIG. 6 is a block diagram for explaining a configuration of a phase adjustment unit 130 in a second embodiment. FIG. 10 is a diagram for explaining the operation of a phase adjustment unit 130 in the second embodiment. FIG. 10 is a block diagram for illustrating a configuration of a frequency comparison unit 400 in the second embodiment. 6 is a block diagram for illustrating a configuration of a correction unit 300 according to Embodiment 2. FIG. FIG. 10 is a block diagram for explaining a DLL circuit configuration according to a third embodiment. FIG. 10 is a block diagram for illustrating a configuration of an accumulating unit 110 in a third embodiment. FIG. 10 is a block diagram for illustrating a configuration of a clock selection unit 150 in a third embodiment. FIG. 10 is a diagram for explaining the operation of the DLL circuit according to the third embodiment. FIG. 10 is a block diagram for illustrating a configuration of a fourth embodiment. FIG. 10 is a block diagram for illustrating a configuration of a fifth embodiment. FIG. 10 is a block diagram for illustrating a configuration of a sixth embodiment. Schematic of prior art.

In the first to third embodiments, a DLL (Digital Locked Loop) circuit for solving the above problem will be described.
The DLL circuit according to the first to third embodiments includes a clock generation unit, a phase comparison unit, and a correction unit.
The clock generator
An accumulation unit that operates with an operation clock, accumulates a set value, and generates a first clock;
A variable delay unit that delays an input clock or pulse by a delay amount controlled by an accumulation unit, and generates a second clock;
A phase correction unit that corrects the phase of the first clock with the second clock at a timing controlled by the accumulation unit;
A generated clock having a frequency that is one time the operating clock frequency (twice the set value) is generated.
The phase comparison unit compares the phase difference between the generated clock and a reference clock input from the outside, and outputs the phase difference.
The correction unit generates a correction value for correcting the set value so that the phase difference is set to “0” from the phase difference output from the phase comparison unit, and adds the correction value to the set value. .

Since the DLL circuit according to the first to third embodiments having the above configuration performs clock generation in the accumulation unit, it can generate a wide range of frequencies corresponding to the number of bits of the accumulation unit with the upper limit being ½ of the operation clock frequency. In addition, since the phase of the generated clock is adjusted using the clock generated by the variable delay unit, the generated clock can be generated with high accuracy.
Furthermore, since the clock generation unit is configured by an accumulation unit, a variable delay unit, and a phase adjustment unit that can be logically designed, it is easy to design and can be configured by one multi-bit counter, and thus has a small circuit scale.

  In the fourth to sixth embodiments, a DLL circuit configured by a single clock generator described in the first to third embodiments will be described.

Embodiment 1 FIG.
FIG. 1 shows a configuration example of a DLL circuit according to the first embodiment.
The DLL circuit of FIG. 1 includes a clock generation unit 100, a phase comparison unit 200, and a correction unit 300. The input is a set value k (real number), an operation clock clks, a reference clock clkr, and a double-speed clock clks2 of the operation clock. (The frequency is double) and the output is the generated clock clkc.
Furthermore, the clock generation unit 100 includes an accumulation unit 110, a variable delay unit 120, and a phase adjustment unit 130.
The set value k in FIG. 1 is a real value, and is obtained by dividing the operation clock frequency by twice the generated clock frequency.
For example, when the operation clock frequency is 500 MHz and the generated clock frequency is 160 MHz, the setting value k is 500 MHz / (160 MHz × 2) = 1.5625. By this calculation, the set value k represents how many operating clocks the half cycle of the generated clock is. In the above calculation, the half cycle of the generated clock frequency of 160 MHz is 1.5625 cycles of the operation clock of 500 MHz.
The clock generation unit 100 is an example of a clock generation device.

FIG. 2 shows a configuration example of the accumulation unit 110 according to the first embodiment.
2 includes an accumulator 111, a detection unit 112, a reference clock clka generation unit 113, and a control signal C1 generation unit 114.
The control signal C1 generation unit 114 corresponds to a first control signal generation unit, and the detection unit 112 corresponds to a second control signal generation unit.

The accumulator 111 is operated by the operation clock clks and accumulates the set value k as an input.
FIG. 3 shows an operation timing chart of the accumulator 111.
Since the accumulator 111 accumulates the set value k by the operation clock clks, the result of the accumulator 111 changes linearly within the bit width of the accumulator 111, and when the bit width is exceeded, “0” The process of returning to "" is repeated.
Therefore, if this operation is continuously performed, the result of the accumulator 111 changes like a sawtooth wave as shown in FIG.
Further, the linear change of the accumulator 111 changes in slope when the value of the set value k is changed. As shown in FIG. 4, the slope changes gradually when the set value k is small and becomes steep when the set value k is large.

Each time the detection unit 112 in FIG. 2 detects that the result of the accumulator 111 exceeds the bit width of the accumulator 111 (that is, the maximum bit value that can be displayed by the bit width of the accumulator 111), A pulse signal indicating the detection is output as the control signal C2 (corresponding to the second control signal) (the control signal C2 is asserted).
The control signal C2 is a signal for controlling the timing of phase adjustment.
The detection of the bit width exceeding the result of the accumulator 111 is performed by, for example, comparing the carry of the most significant bit of the accumulator 111 or the result of the accumulator 111 with the maximum value of the bit width of the accumulator 111. Detect with

The reference clock clka generator 113 in FIG. 2 inverts the current reference clock clka value according to the input timing of the control signal C2, and outputs the inverted signal as the next reference clock clka.
The reference clock clka holds the value until the next input timing of the control signal C2.
The reference clock clka is a clock subject to phase adjustment.
FIG. 5 shows operation waveforms of the reference clock clka and the control signal C2.
For example, when the current reference clock clka is “1”, “1” is inverted to “0” at the timing of detection of exceeding the bit width to be the next reference clock clka.
The value is held until the next bit width excess detection timing.
As described above, the reference clock clka generation unit 113 generates the reference clock clka whose edge interval is the interval between the assert timings of the control signal C2.
The reference clock clka may use a change in MSB (Most Significant Bit) of the accumulator 111 as it is.

2 acquires the decimal part of the accumulator 111 according to the input timing of the control signal C2, and outputs the acquired decimal part as the control signal C1 (corresponding to the first control signal). .
The control signal C1 holds the value until the next control signal C2 input timing.
The control signal C1 is a signal for controlling the delay amount in the variable delay unit 120.
The reason why the result of the accumulator 111 has a fractional part when the bit width is exceeded is that the set value k is a real value (K = 1.5625 in the above example).
As described above, the control signal C1 generation unit 114 specifies the decimal value of the set value when the control signal C2 is asserted by the detection unit 112, and generates and outputs the control signal C1 that notifies the specified decimal value. .
In order to obtain the decimal part, the decimal value of the accumulator 111 when the bit width is exceeded can be obtained by masking the decimal value of the accumulator 111 with the control signal C2.

FIG. 6 shows the configuration of the variable delay unit 120 of the first embodiment.
The variable delay unit 120 of FIG. 6 includes a plurality of delay elements 121, a selector 122, and a conversion unit 123.
The delay elements 121 add a delay to the double-speed clock clks2 of the operation clock input from the outside. A plurality of delay elements 121 are connected in series, and each delay element 121 has an output terminal.
This can be substituted by a common delay line or the like.

FIG. 7 shows an operation timing chart of the delay elements 121 connected in series.
Each time the signal passes through the delay element 121, the input clock is delayed by a delay amount corresponding to one delay element 121.
6 generates a select value for the selector 122 to select the output terminal of the delay element 121 from the control signal C1 output from the accumulator 110.
The select value is generated by the following method. The delay amount delayed by one cycle of the operation clock clks is set as an upper limit value, and the number of stages of the delay elements 121 necessary for delaying by that amount is held as a code value.
Since the control signal C1 is a decimal value that cannot be counted by the operation clock clks, it represents a necessary delay amount when one cycle of the operation clock clks is set to the delay amount “1”.
For example, if the control signal C1 is “0.5”, the necessary delay amount is a half cycle of one cycle of the operation clock clks, and if “0.2”, 0. Two cycles.
The number of stages of the delay elements 121 that can obtain a delay amount corresponding to the necessary delay amount indicated by the control signal C1 is selected from the code values.
This may be selected from a look-up table or the like using the control signal C1 as a reference value, or it may be obtained by multiplying the control signal C1 by the code value that is the upper limit value of the delay amount.
The code value obtained as described above is output as a select value.
This operation is performed every time the control signal C1 is input, and the select value is held until the next timing when the control signal C1 is input.
The selector 122 in FIG. 6 selects one of the serially connected output terminals of the delay element 121 according to the select value of the converter 123 output, and outputs a signal output from the selected output terminal as the delay clock clkd. .
As described above, the variable delay unit 120 receives a clock having a predetermined frequency as an input clock from the outside, inputs the control signal C1 generated by the accumulation unit 110, and inputs a delay amount controlled by the control signal C1. This is applied to the clock, and a delay clock clkd of the input clock is generated and output.

FIG. 8 shows the configuration of the phase adjustment unit 130 of the first embodiment.
The phase adjustment unit 130 shown in FIG. 8 includes a logical product of the delay clock clkd and the control signal C2, an exclusive OR of the logical product output and the reference clock clka, and generates an output of the exclusive OR. Output as.
FIG. 9 shows an operation timing chart of the phase adjustment unit 130 shown in FIG.
As shown in FIG. 9, the phase adjustment unit 130 calculates the logical product of the control signal C2 and the delay clock clkd that is selected by the variable delay unit 120 and changes at every control signal C2 assert timing.
The generated clock clkc is generated by taking the exclusive OR of the result of the logical product and the reference clock clka.
As described above, the phase adjustment unit 130 receives the reference clock clka generated by the accumulation unit 110 and the control signal C2, receives the delay clock clkd generated by the variable delay unit 120, and enables the control signal C2. The phase of the reference clock clka is adjusted by the delay clock clkd, a clock having a frequency obtained by dividing the frequency of the operation clock clks by twice the set value k is generated, and the generated clock is output as the generated clock clkc.

The phase comparison unit 200 of the first embodiment shown in FIG. 1 detects the phase difference between the generated clock clkc generated by the clock generation unit 100 having the configuration and operation described so far and the reference clock clkr input from the outside.
As described above, the phase comparison unit 200 compares the phase of the generated clock clkc generated by the clock generation unit 100 with the phase of the reference clock clkr input from the outside, and the phase difference between the generated clock clkc and the reference clock clkr. Is output.

The correction unit 300 according to the first embodiment shown in FIG. 1 refers to the generated clock clkc from the phase difference detected by the phase comparison unit 200 and the set value k used by the clock generation unit 100 to generate the generated clock clkc. A correction value for correcting the set value k is generated so that the phase difference of the clock clkr is “0”.
Then, the correction unit 300 adds the generated correction value to the setting value k used for generating the correction value, and calculates a new setting value k.
The clock generation unit 100 generates the generated clock clkc with the new set value k calculated as described above.

As described above, the DLL circuit according to the first embodiment shown in FIG. 1 generates the generated clock clkc that is phase-synchronized with the reference clock clkr by the loop processing of the clock generation unit 100, the phase comparison unit 200, and the correction unit 300.
With this configuration, the generation frequency width of the generated clock clkc is the bit width of the accumulator 111 in the accumulator 110 in the clock generator 100, with an upper limit of ½ of the frequency of the operation clock clks. A wide range can be realized.
Further, the frequency accuracy of the generated clock clkc can be set to 50% because the phase of the reference clock clka generated by the accumulator 111 is corrected by the delay clock clkd generated by the variable delay unit 120. And high accuracy.
FIG. 10 shows the accuracy with respect to the setting of the generated clock clkc of the DLL circuit of FIG.
In FIG. 10, the generation frequency is a target frequency, and the output frequency is a frequency of a clock (corresponding to the generation clock clkc) generated by the clock generation unit 100 targeting the generation frequency, and is an actual measurement value. .
As shown in FIG. 10, in the DLL circuit according to the present embodiment, the error is 0 ppm in all cases and is highly accurate.
Further, the circuits shown in FIGS. 2, 6, and 8 can be configured by digital circuits, can be easily designed, and the constituent elements are counters and primitive logic circuits, and thus have a small circuit scale.

In the above description, the clock input to the variable delay unit 120 is the double-speed clock clks2 of the operation clock, but is not limited thereto.
That is, the clock input to the variable delay unit 120 may have the same cycle as the operation clock, may be a clock with a cycle faster than the operation clock, or may be a clock with a slow cycle.
In addition, when a clock having a period faster than the operation clock is input, the clock may not be an integer multiple of the operation clock.
In addition, when a clock having a cycle slower than the operation clock is input, the clock may not be a cycle of an integer of the operation clock.

Further, instead of the phase comparison unit 200, a frequency comparison unit that compares the frequency difference between the generated clock clkc and the reference clock clkr and outputs the frequency difference may be used.
Details of the frequency comparison unit will be described in the second embodiment.

Thus, in this embodiment,
An externally input operation clock, an input clock having a frequency different from or equal to that of the operation clock, and a generated clock having a frequency that is one half of the operation clock frequency (twice the set value) from a set value that represents a desired frequency. A clock generator for generating
A phase comparison unit that compares the phase difference between the generated clock and an externally input reference clock and outputs the phase difference;
A correction unit that generates a correction value that corrects the set value so that the phase difference is set to “0” from the phase difference that is output from the phase comparison unit, and that adds the correction value to the set value; A DLL circuit has been described.

In addition, the clock generation unit
A first control signal (control signal C1) for controlling a first clock (reference clock) and a delay amount is corrected by operating with an operation clock and accumulating set values input from the outside with an operation clock cycle. An accumulator for generating a second control signal (control signal C2) for controlling the timing;
A variable delay unit that receives an input clock having a frequency different from or equal to the operating clock from the outside, and generates a second clock by giving the input clock a delay amount controlled by the first control signal output from the accumulation unit When,
A phase adjustment unit that enables the second control signal and corrects the phase of the first clock with the second clock;
It has been explained that it is possible to generate a generated clock having a frequency that is one time the frequency of the operating clock (twice the set value).

  Further, it has been described that the set value input from the outside is a real number that is calculated from the division of the frequency of the operation clock and twice the desired frequency and can be expressed by an integer and a decimal.

In addition, the variable delay unit constituting the clock generation unit,
The double-speed clock to which the first control signal corresponding to the decimal part of the accumulation result of the set value of the accumulation unit is converted into a delay amount according to an internal conversion code, and a delay corresponding to the delay amount is input Alternatively, it has been described that the pulse is supplied to the pulse of the pulse generator and the second clock is output.

In addition, the phase adjustment unit constituting the clock generation unit,
By taking the logical sum, logical product, or exclusive logical sum of the first clock of the accumulating unit output and the second clock of the variable delay unit output or the delayed pulse at the timing of the second control signal. The adjustment of the phase of the first clock has been described.

  Further, it has been described that a frequency comparison unit that compares the frequency difference between the generated clock and the reference clock and outputs the frequency difference can be used instead of the phase comparison unit.

  Further, it has been described that the clock generation unit, the phase comparison unit, and the correction unit can be designed with a logic circuit.

  The operation of the clock generation unit 100 according to the present embodiment includes the operation of the accumulation unit 110 (accumulation step), the operation of the variable delay unit 120 (variable delay step), and the operation of the phase adjustment unit 130 (phase adjustment step). ).

Embodiment 2. FIG.
FIG. 11 shows a DLL circuit configuration according to the second embodiment.
In the DLL circuit of FIG. 11, a pulse generation unit 140 is added to the clock generation unit 100 from the configuration of the first embodiment, and there is no external clock input to the variable delay unit 120, and the pulse generation unit 140 generates the DLL circuit. It is configured to input a new pulse.
The phase comparison unit 200 is a frequency comparison unit 400.
The frequency comparison unit 400 compares the frequency of the generated clock clkc generated by the clock generation unit 100 with the frequency of the reference clock clkr input from the outside, and outputs a frequency difference between the generated clock clkc and the reference clock clkr.
Further, the correction unit 300 according to the present embodiment generates a correction value for the set value k with the frequency difference being 0 from the frequency difference output from the frequency comparison unit 400, and adds the correction value to the set value k. .
Further, the double-speed clock clks2 (frequency is double) of the operation clock is used as another operation clock for operating the DLL circuit.

FIG. 12 shows the configuration of the accumulating unit 110 according to the second embodiment.
12 includes an accumulator 111, a reference clock clka generator 113, a control signal C1 generator 114, a down counter 115/117, a comparator 116/118, and an adder 119.

The accumulator 111 is operated by the input operation clock clks, and accumulates only the decimal value of the set value k, and the FF (flip-flop) 1102 that holds only the integer part of the set value k. / 1103.
The decimal value accumulator 1101 accumulates the decimal value of the set value k with the period of the operation clock clks.
Accumulation execution in the accumulator 111 and update of the value are performed based on the result of the comparator 116 at the subsequent stage.

  The adder 119 in FIG. 12 carries the output of the FF 1102/1103 that holds only the integer part of the setting value k in the accumulator 111 and the carry of the decimal value accumulator 1101 that accumulates only the decimal value of the setting value k. Add.

  The down counter 115 (corresponding to the first down counter) in FIG. 12 operates with the operation clock clks, and counts down the addition result of the adder 119 at the cycle of the operation clock clks.

The comparator 116 (corresponding to the first comparator) of FIG. 12 operates with the operation clock clks, compares the output of the down counter 115 with “1”, and outputs a pulse when the output of the down counter 115 becomes “1”. Output.
The output of the comparator 116 is output as a control signal C3 (corresponding to a third control signal).
The control signal C3 is a signal for controlling the pulse generation timing in the pulse generator 140.
Further, the control signal C3 is fed back to the accumulator 111 and the down counter 115/117, and is used as an enable signal for updating the values of the decimal value accumulator 1101, FF 1102 1103 and the down counter 115/117 in the accumulator 111. Also used.

  The down counter 117 (corresponding to the second down counter) in FIG. 12 operates with the double speed clock clks2 of the operation clock, and holds only the integer part of the set value k of the accumulator 111 in the period of the double speed clock clks2. The output of the FF 1103 to be down-counted.

  The comparator 118 (corresponding to the second comparator) in FIG. 12 operates with the double-speed clock clks2 of the operation clock, compares the output of the down counter 117 with “1” at the cycle of the double-speed clock clks2, and When the output of the counter 117 becomes “1”, a pulse is output.

The control signal C1 generation unit 114 in FIG. 12 has a comparison result of “1” or less from the output of the decimal value accumulator 1101 that accumulates only the decimal value of the set value k of the accumulator 111 and the output of the comparator 116. The decimal value is output as the control signal C1 at the timing when.
That is, the control signal C1 generation unit 114 inputs a pulse from the comparator 116, specifies the accumulated value of the decimal value in the decimal value accumulator 1101 when the pulse is input from the comparator 116, and specifies the specified decimal value. A control signal C1 for notifying the accumulated value is generated and output.

The reference clock clka generator 113 shown in FIG. 12 operates with the double-speed clock clks2 of the operation clock, and generates and outputs the reference clock clka from the output of the comparator 116 and the output of the comparator 118.
The reference clock clka is generated by generating a positive edge of the reference clock clka with the output pulse of the comparator 116 and generating a negative edge of the reference clock clka with the output pulse of the comparator 118.
Note that the reference clock clka is a clock subject to phase adjustment, as in the first embodiment.

FIG. 13 shows the generation operation timing of the reference clock clka in the accumulator 111 in the accumulator 110 of FIG.
In FIG. 13, the set value k is assumed to be “3.4”.
The values of the FFs 1102/1103, the decimal value accumulator 1101, and the down counter 115/117 in the accumulator 111 are updated by the output pulse of the comparator 116, and the down counter 115/117 receives the respective operation clock clks and double speed. The value updated by the clock clks2 is counted down.
The comparator 116/118 outputs a pulse when the down counter value becomes "1" or less.
The reference clock clka generation unit 113 generates the reference clock clka by setting “1” at the timing of the output pulse of the comparator 116 and setting “0” at the timing of the output pulse of the comparator 118.
As described above, the reference clock clka generation unit 113 receives the pulse from the comparator 116 and the pulse from the comparator 118, rises at the timing when the pulse is input from the comparator 116, and receives the pulse from the comparator 118. A reference clock clka that falls at the timing is generated.
The control signal C1 generation unit 114 outputs the output of the decimal value accumulator 1101 in the accumulator 111 at the timing of the output pulse of the comparator 116 as the control signal C1.

FIG. 14 shows the configuration of the pulse generation unit 140 of the second embodiment.
The pulse generation unit 140 shown in FIG. 14 is operated by a double speed clock clks2, and includes an FF that holds a control signal C3, and an OR circuit of the control signal C3 and the FF.
14 generates a pulse for one cycle of the operation clock clks and outputs it as an input pulse pl.
Thus, the pulse generation unit 140 receives the pulse output from the comparator 116 as the control signal C3, enables the control signal C3, and generates a pulse for one cycle of the operation clock clks.

The variable delay unit 120 in FIG. 11 is the same in configuration and operation as in FIG. 6, and the input only changes from the double speed clock clks2 to the input pulse pl generated by the pulse generation unit 140.
That is, the variable delay unit 120 derives a delay amount corresponding to the decimal value notified by the control signal C1, and gives the derived delay amount to the pulse pl input from the pulse generation unit 140 to generate the delay pulse pld. And output.

11 includes a logical sum of a reference clock clka output from the accumulator 110 and a delay pulse pld output from the variable delay unit 120 (FIG. 15), and the output of the logical sum is the generated clock clkc. .
FIG. 16 shows the operation timing of the phase adjustment unit 130.
Since only the logical sum of the reference clock clka and the delay pulse pld is set, the phase of the reference clock clka is adjusted only when the delay pulse pld is input (only the positive edge).
As described above, the phase adjustment unit 130 receives the reference clock clka generated by the accumulation unit 110, receives the delay pulse pld generated by the variable delay unit 120, and sets the phase of the reference clock clka as the delay pulse pld. A clock having a frequency obtained by adjusting and dividing the frequency of the operation clock clks by twice the set value k is generated, and the generated clock is output as the generated clock clkc.

FIG. 17 shows the configuration of the frequency comparison unit 400 of the second embodiment.
17 includes a counter 411 and a counter 421, a comparison period counter 430, a count value acquisition unit 412/422, a selector 413/423, a count conversion unit 424, and a difference comparison unit 440.
The frequency comparison unit 400 detects and outputs a frequency difference between the generated clock clkc and the reference clock clkr.

The counter 411 in FIG. 17 is a counter that operates with the generated clock clkc and counts during the count period of the comparison period counter 430.
The count value of the counter 411 represents the number of toggles of the generated clock clkc within the comparison period.
The counter 421 in FIG. 17 is a counter that operates with the reference clock clkr and counts during the count period of the comparison period counter 430. The count value of the counter 411 represents the number of toggles of the reference clock clkr within the comparison period.
The comparison period counter 430 in FIG. 17 operates with the reference clock clkr and determines a period for comparing the count values of the counters 411 and 421.
Counting is performed by down-counting, and when the count value becomes "1" or less, enable is output.
The count may be counted up.
The counter set value for determining the comparison period can be arbitrarily set from the outside.
The count value acquisition unit 412 in FIG. 17 captures the count value of the counter 411 at the timing of enabling the comparison period counter 430 output.
The count value acquisition unit 422 in FIG. 17 captures the count value of the counter 421 at the timing of enabling the comparison period counter 430.
The selector 413 in FIG. 17 selects either the counter 411 output or a value obtained by subtracting the count value acquisition unit 412 output from the counter 411 output, and inputs the selected value to the counter 411.
The value is selected by enabling the comparison period counter 430 output.
The selector 423 in FIG. 17 selects either the counter 421 output or a value obtained by subtracting the count value acquisition unit 422 output from the counter 421 output, and inputs the selected value to the counter 421.
The value is selected by enabling the comparison period counter 430 output.
The count conversion unit 424 in FIG. 17 calculates the counter value x (generated clock clkc frequency / reference clock clkr frequency) with respect to the counter value acquired by the count value acquisition unit 422, and converts the counter value to the value of the counter 411. Convert.
The difference comparison unit 440 in FIG. 17 performs subtraction between the count value acquisition unit 412 output and the count conversion unit 424 output, and outputs the subtraction result as a frequency difference between the generated clock clkc and the reference clock clkr.

FIG. 18 shows a configuration of the correction unit 300 according to the second embodiment.
The correction unit 300 determines that the frequency difference between the generated clock clkc and the reference clock clkr is “0” from the frequency difference detected by the frequency comparison unit 400 and the set value k used by the clock generation unit 100 to generate the generated clock clkc. A correction value for correcting the set value k is generated as follows.

The bit shift 310 in FIG. 18 performs a right bit shift of the set value k.
The shift amount can be arbitrarily set from the outside. Here, the weight of the correction value for the frequency difference “1” is determined.
A multiplier 320 in FIG. 18 multiplies the frequency difference output from the frequency comparison unit 400 by the set value k shift result of the bit shift 310 output, and converts the frequency difference into a correction value.
The bit shift 330/340 in FIG. 18 right bit shifts the output of the multiplier 320.
In each case, the shift amount can be arbitrarily set from the outside. The correction amount of the correction value is adjusted by bit shifting.
The integrator 350 of FIG. 18 accumulates the bit shift 340 output.
The integrator 350 holds the correction value when the frequency difference becomes “0”.
The adder 360 in FIG. 18 adds the bit shift 330 output and the integrator 350 output.
The bit shift 370 in FIG. 18 right bit shifts the output of the adder 360.
The shift amount can be arbitrarily set from the outside.
By bit shifting, the correction amount of the correction value is adjusted and output as the final correction value.

As described above, the DLL circuit according to the second embodiment shown in FIG. 11 generates the generated clock clkc that is frequency-synchronized with the reference clock clkr by the loop processing of the clock generation unit 100, the frequency comparison unit 400, and the correction unit 300.
The generateable frequency width and accuracy of the generated clock clkc with this configuration are the same as in the first embodiment.
It is also the same that all circuits can be constituted by digital circuits.
Furthermore, since the frequency comparison is used instead of the phase comparison, the design is easier than using the phase comparison.
In addition, in the configuration of FIG. 11, the phase comparison unit 200 of FIG. 1 can be used.

In the above description, the clock input to the down counter 117, the comparator 118, and the reference clock clka generator 113 is the double speed clock clks2 of the operation clock, but is not limited thereto.
That is, the clock input to the down counter 117, the comparator 118, and the reference clock clka generation unit 113 may be the same cycle as the operation clock, may be a clock having a faster cycle than the operation clock, or may be slow. It may be a periodic clock.
In addition, when a clock having a period faster than the operation clock is input, the clock may not be an integer multiple of the operation clock.
In addition, when a clock having a cycle slower than the operation clock is input, the clock may not be a cycle of an integer of the operation clock.

Thus, in this embodiment,
An externally input operation clock, an input clock having a frequency different from or equal to that of the operation clock, and a generated clock having a frequency that is one half of the operation clock frequency (twice the set value) from a set value that represents a desired frequency. A clock generator for generating
A phase comparison unit that compares the phase difference between the generated clock and an externally input reference clock and outputs the phase difference;
A correction unit that generates a correction value that corrects the set value so that the phase difference is set to “0” from the phase difference that is output from the phase comparison unit, and that adds the correction value to the set value; A DLL circuit has been described.

In addition, the clock generation unit
A first control signal (control signal C1) for controlling a first clock (reference clock) and a delay amount by operating with an operation clock and accumulating set values input from the outside with an operation clock cycle; An accumulation unit for generating a third control signal (control signal C3) for controlling the pulse generation timing;
Enabling the third control signal of the output of the accumulator, and generating a pulse of one cycle period of the operation clock; and
A variable delay unit that generates a delay pulse by giving a delay amount controlled by the first control signal of the accumulation unit output to the pulse generated by the pulse generation unit;
A phase adjustment unit for correcting the phase of the first clock with the delay pulse;
It has been explained that it is possible to generate a generated clock having a frequency equal to the set value of the operating clock frequency.

  Further, it has been described that the set value input from the outside is a real number that is calculated from the division of the frequency of the operation clock and (twice the desired frequency) and can be expressed by an integer and a decimal.

In addition, the variable delay unit constituting the clock generation unit,
The double-speed clock to which the first control signal corresponding to the decimal part of the accumulation result of the set value of the accumulation unit is converted into a delay amount according to an internal conversion code, and a delay corresponding to the delay amount is input Alternatively, it has been described that the pulse is supplied to the pulse of the pulse generator and the second clock is output.

In addition, the phase adjustment unit constituting the clock generation unit,
By taking the logical sum, logical product, or exclusive logical sum of the first clock of the accumulating unit output and the second clock of the variable delay unit output or the delayed pulse at the timing of the second control signal. The adjustment of the phase of the first clock has been described.

  Further, it has been described that a frequency comparison unit that compares the frequency difference between the generated clock and the reference clock and outputs the frequency difference can be used instead of the phase comparison unit.

  Further, it has been described that the clock generation unit, the phase comparison unit, and the correction unit can be designed with a logic circuit.

  The operation of the clock generation unit 100 according to the present embodiment includes the operation of the accumulation unit 110 (accumulation step), the operation of the pulse generation unit 140 (pulse generation step), and the operation of the variable delay unit 120 (variable delay step). ) And a clock generation method including an operation (phase adjustment step) by the phase adjustment unit 130.

Embodiment 3 FIG.
FIG. 19 shows a DLL circuit configuration according to the third embodiment.
The DLL circuit of FIG. 19 includes a clock generation unit 100, a phase comparison unit 200, and a correction unit 300.
The input is the same as in the first embodiment, except that the operation clock divided by four clocks clksd is input to the clock generation unit 100.
The clock generation unit 100 includes an accumulation unit 110, a variable delay unit 120, and a clock selection unit 150 instead of the phase adjustment unit 130.
In the present embodiment, control signal C4 (corresponding to a fourth control signal) is output from accumulation section 110 to clock selection section 150.
The control signal C4 is a signal that notifies the clock selection unit 150 of the rising timing and falling timing of the delay clock clkd.
The clock selection unit 150 selects and outputs the delay clock clkd input at the assertion timing of the control signal C4, and maintains the output of the most recently selected delay clock clkd except for the assertion timing of the control signal C4. A clock having a frequency obtained by dividing the frequency of the operation clock clks by the set value k is output as the generated clock clkc.

FIG. 20 shows the configuration of the accumulating unit 110 of the third embodiment.
20 includes an accumulator 111, a counter 1112, an adder 1113, a comparator 1114, and a control signal C4 generation unit 1115. The accumulation unit 110 (corresponding to the first control signal generation unit) in FIG.
The accumulator 111 operates according to the operation clock clks, accumulates the set value k in the operation clock clks cycle, and outputs the accumulation result of the set value k according to the asserted timing of the control signal C4 fed back.
The integer value of the accumulation result of the accumulator 111 is input to the adder 1113, and the decimal value of the accumulation result is output as the control signal C1.
That is, the control signal C1 is a signal that notifies the decimal value of the cumulative value of the set value k at the assertion timing of the control signal C4.
The counter 1112 of FIG. 20 operates with the operation clock clks as in the accumulator 111, counts up by “1”, and outputs the counter value.
The adder 1113 in FIG. 20 subtracts the count value of the counter 1112 from the integer value of the accumulation result of the accumulator 111, and outputs the difference between the accumulation result and the counter value.
The comparator 1114 in FIG. 20 compares “1” with the difference between the output of the accumulator 111 and the output of the counter 1112, which is the output of the previous stage adder 1113, and outputs the comparison result.
The control signal C4 generation unit 1115 (corresponding to the fourth control signal generation unit) in FIG. 20 receives the LSB (Least Significant Bit) of the output of the adder 1113 and the output of the comparator 1114 as inputs, and receives the control signal C4 as the control signal C4. Generate.
The output control signal C4 is output to the outside and simultaneously fed back to the accumulator 111.

  The variable delay unit 120 in FIG. 19 has the same configuration and operation as those in the first and second embodiments except that the input clock is a divided clock of the operation clock.

FIG. 21 illustrates a configuration of the clock selection unit 150 according to the third embodiment.
The clock selection unit 150 in FIG. 21 includes an FF 151 that holds the current generated clock clkc by the operation clock clks, and a selector 152 that selects the output of the FF 151 or the delay clock clkd by the control signal C4.
Based on the control signal C4, the delay clock clkd is selected at the timing when the delay clock clkd is switched, and then the FF 151 is selected until the delay clock clkd is switched.

The phase comparison unit 200 and the correction unit 300 in FIG. 19 have the same configuration and operation as in the first embodiment.
Further, it is possible to convert the phase comparison unit 200 to the frequency comparison unit 400 of the second embodiment, and the correction unit in that case has the configuration of the second embodiment.

FIG. 22 shows an operation at the time of clock generation in the DLL circuit of FIG.
The upper waveform of FIG. 22 shows the counter value transition by the counter 1112.
When the counter value matches the integer value of the accumulated value accumulated by the accumulator 111, the delay clock clkd selected by the decimal value of the accumulated value is output as a generated clock.
The adder 1113 and the comparator 1114 determine whether the counter value matches the integer value of the accumulated value accumulated by the accumulator 111.
The output selection of the selected delayed clock clkd is performed by the clock selection unit 150 by the control signal C4 output from the control signal C4 generation unit 1115.
In FIG. 22, each set of two arrows from the top to the bottom (two arrows on the same line) corresponds to the assertion timing of the control signal C4.
The delay clock clkd indicated by the upper arrow in the set of two arrows is a delay clock selected by the decimal value of the accumulated value, and the position indicated by the lower arrow is the generated clock clkc. Is the switching timing of the delay clock clkd.
In this way, the clock selection unit 150 selects and outputs the delay clock clkd that is input at the assertion timing of the control signal C4, feeds back the output delay clock clkd, and holds it in the FF 151. The delayed clock clkd fed back is output during the period up to the assertion timing.

  As described above, also in the DLL circuit according to the third embodiment shown in FIG. 19, as in the first and second embodiments, the generation clock clkc with a very wide range and high accuracy can be generated, and the design is easy. Thus, a small circuit scale can be realized.

In the above description, the clock input to the variable delay unit 120 is the four-frequency clock clksd of the operation clock, but is not limited thereto.
That is, the clock input to the variable delay unit 120 may have the same cycle as the operation clock, may be a clock with a cycle faster than the operation clock, or may be a clock with a slow cycle.
In addition, when a clock having a period faster than the operation clock is input, the clock may not be an integer multiple of the operation clock.
In addition, when a clock having a cycle slower than the operation clock is input, the clock may not be a cycle of an integer of the operation clock.

Thus, in this embodiment,
An externally input operation clock, an input clock having a frequency different from or equal to that of the operation clock, and a generated clock having a frequency that is one half of the operation clock frequency (twice the set value) from a set value that represents a desired frequency. A clock generator for generating
A phase comparison unit that compares the phase difference between the generated clock and an externally input reference clock and outputs the phase difference;
A correction unit that generates a correction value that corrects the set value so that the phase difference is set to “0” from the phase difference that is output from the phase comparison unit, and that adds the correction value to the set value; A DLL circuit has been described.

In addition, the clock generation unit
A fourth value that determines the edge interval between the first control signal (control signal C1) for controlling the delay amount and the generated clock by operating with the operation clock and accumulating the set value input from the outside in the operation clock cycle. An accumulator for generating a control signal (control signal C4);
A variable delay unit that receives an input clock having a frequency different from or equal to an operation clock from the outside, and generates a delay clock by giving the input clock a delay amount controlled by the first control signal of the accumulation unit output;
A clock selection unit that determines whether to select the delayed clock or the generated clock that is fed back according to the fourth control signal;
It has been explained that it is possible to generate a generated clock having a frequency that is a fraction of the operating clock frequency (twice the set value).

  Further, it has been described that the set value input from the outside is a real number that is calculated from the division of the frequency of the operation clock and (twice the desired frequency) and can be expressed by an integer and a decimal.

In addition, the variable delay unit constituting the clock generation unit,
The double-speed clock to which the first control signal corresponding to the decimal part of the accumulation result of the set value of the accumulation unit is converted into a delay amount according to an internal conversion code, and a delay corresponding to the delay amount is input Alternatively, it has been described that the pulse is supplied to the pulse of the pulse generator and the second clock is output.

In addition, the phase adjustment unit constituting the clock generation unit,
By taking the logical sum, logical product, or exclusive logical sum of the first clock of the accumulating unit output and the second clock of the variable delay unit output or the delayed pulse at the timing of the second control signal. The adjustment of the phase of the first clock has been described.

  Further, it has been described that a frequency comparison unit that compares the frequency difference between the generated clock and the reference clock and outputs the frequency difference can be used instead of the phase comparison unit.

  Further, it has been described that the clock generation unit, the phase comparison unit, and the correction unit can be designed with a logic circuit.

  The operation of the clock generation unit 100 according to the present embodiment includes the operation of the accumulation unit 110 (accumulation step), the operation of the variable delay unit 120 (variable delay step), and the operation of the clock selection unit 150 (clock selection step). ).

Embodiment 4 FIG.
FIG. 23 shows a DLL circuit configuration according to the fourth embodiment.
The DLL circuit of FIG. 23 includes only the clock generation unit 100 of the first embodiment, and omits the phase comparison unit 200 and the correction unit 300.
With the above configuration, only the clock generation unit may be designed, so that the design is easier and the circuit scale is reduced.

Embodiment 5 FIG.
FIG. 24 shows a DLL circuit configuration according to the fifth embodiment.
The DLL circuit of FIG. 24 includes only the clock generation unit 100 of the second embodiment, and the frequency comparison unit 400 and the correction unit 300 are omitted.
With the above configuration, only the clock generation unit may be designed, so that the design is easier and the circuit scale is reduced.

Embodiment 6 FIG.
FIG. 25 shows a DLL circuit configuration according to the sixth embodiment. The DLL circuit of FIG. 25 includes only the clock generation unit 100 of the third embodiment, and the phase comparison unit 200 and the correction unit 300 are omitted.
With the above configuration, only the clock generation unit may be designed, so that the design is easier and the circuit scale is reduced.

  100 clock generator, 110 accumulator, 111 accumulator, 112 detector, 113 reference clock clka generator, 114 control signal C1 generator, 115 down counter, 116 comparator, 117 down counter, 118 comparator, 120 Variable delay unit, 121 delay element, 122 selector, 123 conversion unit, 130 phase adjustment unit, 140 pulse generation unit, 150 clock selection unit, 151 FF, 152 selector, 200 phase comparison unit, 300 correction unit, 310 bit shift, 320 Multiplier, 330 bit shift, 340 bit shift, 350 integrator, 360 adder, 370 bit shift, 400 frequency comparison unit, 411 counter, 412 count value acquisition unit, 413 selector, 421 counter, 422 count value acquisition unit, 4 3 selector, 424 count conversion unit, 430 comparison period counter, 440 difference comparison unit, 1101 decimal value accumulator, 1102 flip-flop, 1103 flip-flop, 1112 counter, 1113 adder, 1114 comparator, 1115 control signal C4 generation unit .

Claims (12)

An operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a reference for phase adjustment is obtained from the accumulated result. An accumulation unit for generating a clock, a first control signal for controlling a delay amount, and a second control signal for controlling timing of phase adjustment;
A clock having a predetermined frequency is input from the outside as an input clock, the first control signal generated by the accumulator is input, and a delay amount controlled by the first control signal is given to the input clock. A variable delay unit for generating a delay clock of the input clock;
The reference clock generated by the accumulation unit and the second control signal are input, the delay clock generated by the variable delay unit is input, the phase of the reference clock is enabled by enabling the second control signal And a phase adjustment unit that generates a clock having a frequency obtained by dividing the frequency of the operation clock by (twice the set value). The accumulation part is
Enter a setting value that is divided into an integer value and a decimal value,
The accumulation part is
A second control signal generator that asserts a second control signal each time it is detected that the number of bits of the accumulated value of the set value exceeds a predetermined number of bits;
First control signal generation for specifying a decimal value of the set value when the second control signal is asserted by the second control signal generation unit and generating a first control signal for notifying the specified decimal value And
A reference clock generation unit that generates a reference clock having an interval of an assert timing of the second control signal as an edge interval;
The variable delay unit is
Deriving a delay amount corresponding to the decimal value notified by the first control signal, giving the derived delay amount to the input clock, and generating a delay clock of the input clock,
The phase adjusting unit is
2. The clock generation according to claim 1, wherein an exclusive OR of the reference clock and the delay clock is calculated at an assert timing of the second control signal, and a phase of the reference clock is adjusted by the delay clock. apparatus. An operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a reference for phase adjustment is obtained from the accumulated result. An accumulation unit that generates a clock, a first control signal that controls a delay amount, and a third control signal that controls a pulse generation timing;
A pulse generation unit that inputs the third control signal generated by the accumulation unit, enables the third control signal, and generates a pulse for one cycle of the operation clock;
The first control signal generated by the accumulation unit is input, the pulse generated by the pulse generation unit is input, and a delay amount controlled by the first control signal is given to the pulse, A variable delay unit for generating a delay pulse;
The reference clock generated by the accumulation unit is input, the delay pulse generated by the variable delay unit is input, the phase of the reference clock is adjusted by the delay pulse, and the frequency of the operation clock is ( And a phase adjusting unit that generates a clock having a frequency obtained by dividing by twice the set value. The accumulation part is
Enter a setting value that is divided into an integer value and a decimal value,
The accumulation part is
A decimal accumulator for accumulating the decimal value of the set value in the period of the operation clock;
A first down counter for down-counting the integer value of the set value and the addition value of the carry of the decimal value accumulation result by the decimal accumulator and the integer value of the set value at the cycle of the operation clock When,
A first comparator that outputs a pulse when the count value in the first down counter becomes 1;
A second down counter that counts down the integer value of the set value with a clock having a predetermined frequency;
A second comparator that outputs a pulse when the count value in the second down counter becomes 1;
A pulse is input from the first comparator, a cumulative value of a decimal value in the decimal accumulator when a pulse is input from the first comparator is specified, and the specified cumulative value of the decimal value is A first control signal generation unit that generates a first control signal to be notified;
A timing at which a pulse is input from the first comparator, a pulse is input from the second comparator, a pulse is input from the first comparator, and a pulse is input from the second comparator. And a reference clock generation unit that generates a reference clock that falls at
The pulse generator is
The pulse output from the first comparator of the accumulation unit is input as the third control signal, the third control signal is enabled, and a pulse for one cycle of the operation clock is generated,
The variable delay unit is
Deriving a delay amount corresponding to the decimal value notified by the first control signal, giving the derived delay amount to the pulse input from the pulse generation unit, to generate a delay pulse,
The phase adjusting unit is
4. The clock generation apparatus according to claim 3, wherein a logical sum of the reference clock and the delay pulse is calculated and a phase of the reference clock is adjusted by the delay pulse. First, an operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a delay amount is controlled from the accumulated result. And an accumulator for generating a fourth control signal for notifying the rising timing and falling timing of the delay clock by asserting,
A clock having a predetermined frequency is input from the outside as an input clock, the first control signal generated by the accumulator is input, and a delay amount controlled by the first control signal is given to the input clock. A variable delay unit for generating a delay clock of the input clock;
The fourth control signal generated by the accumulation unit is input, the delay clock input at the assertion timing of the fourth control signal is selected and output, and except for the assertion timing of the fourth control signal, A clock selector that maintains the output of the most recently selected delay clock and outputs a clock having a frequency obtained by dividing the frequency of the operation clock by (twice the set value). Clock generator. The accumulation part is
Enter a setting value that is divided into an integer value and a decimal value,
The accumulation part is
The set value is accumulated at the cycle of the operation clock, and the fourth control signal output and fed back to the clock selection unit is input, and the set value at the assert timing of the input fourth control signal A first control signal generating unit for generating a first control signal for notifying a decimal value of the cumulative value of
A counter that counts up in a cycle of the operation clock;
A fourth control signal generation unit that asserts a fourth control signal when a difference between an integer value of the cumulative value of the set values by the first control signal generation unit and a count value of the counter becomes 1 or less; Have
The variable delay unit is
Deriving a delay amount corresponding to the decimal value notified by the first control signal, giving the derived delay amount to the input clock, and generating a delay clock of the input clock,
The clock selector is
The selected delay clock is selected and output at the assertion timing of the fourth control signal, and the output delay clock is fed back, and the period until the next assertion timing of the fourth control signal is the delayed delay. The clock generation apparatus according to claim 5, wherein a clock is output. The clock generation device includes:
The clock generation device according to claim 1, wherein the clock generation device is configured by a logic circuit. The clock generation device according to claim 1,
Furthermore,
A phase comparison unit that compares the phase of the generated clock generated by the clock generation device with the phase of a reference clock input from the outside, and outputs a phase difference between the generated clock and the reference clock;
A DLL (Digital), comprising: a correction unit that generates a correction value for the set value that sets the phase difference to 0 from a phase difference that is an output of the phase comparison unit, and adds the correction value to the set value. Locked Loop) circuit. The clock generation device according to claim 1,
Furthermore,
A frequency comparison unit that compares the frequency of the generated clock generated by the clock generation device with the frequency of a reference clock input from the outside, and outputs a frequency difference between the generated clock and the reference clock;
A DLL (Digital), comprising: a correction unit that generates a correction value for the set value with the frequency difference being 0 from the frequency difference output from the frequency comparison unit, and adds the correction value to the set value. Locked Loop) circuit. An operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a reference for phase adjustment is obtained from the accumulated result. An accumulation step for generating a clock, a first control signal for controlling a delay amount, and a second control signal for controlling timing of phase adjustment;
An external clock having a predetermined frequency is input as an input clock, the first control signal generated by the accumulation step is input, and a delay amount controlled by the first control signal is given to the input clock. A variable delay step for generating a delay clock of the input clock;
The reference clock and the second control signal generated by the accumulation step are input, the delay clock generated by the variable delay step is input, and the phase of the reference clock is enabled by enabling the second control signal. And a phase adjustment step of generating a clock having a frequency obtained by dividing the frequency of the operation clock by (twice the set value). An operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a reference for phase adjustment is obtained from the accumulated result. An accumulation step for generating a clock, a first control signal for controlling a delay amount, and a third control signal for controlling a pulse generation timing;
A pulse generation step of inputting the third control signal generated by the accumulation step, enabling the third control signal, and generating a pulse for one period of the operation clock;
The first control signal generated by the accumulation step is input, the pulse generated by the pulse generation step is input, and a delay amount controlled by the first control signal is given to the pulse, A variable delay step for generating a delay pulse;
The reference clock generated by the accumulation step is input, the delay pulse generated by the variable delay step is input, the phase of the reference clock is adjusted by the delay pulse, and the frequency of the operation clock is ( And a phase adjustment step of generating a clock having a frequency obtained by dividing by twice the set value. First, an operation clock having a predetermined frequency is input from the outside, a set value is input from the outside, the input set value is accumulated at the cycle of the operation clock, and a delay amount is controlled from the accumulated result. And an accumulation step for generating a fourth control signal for notifying the rising timing and falling timing of the delay clock by assertion,
An external clock having a predetermined frequency is input as an input clock, the first control signal generated by the accumulation step is input, and a delay amount controlled by the first control signal is given to the input clock. A variable delay step for generating a delay clock of the input clock;
The fourth control signal generated by the accumulation step is input, the delay clock input at the assertion timing of the fourth control signal is selected and output, and except for the assertion timing of the fourth control signal, A clock selection step of outputting a clock having a frequency obtained by dividing the frequency of the operation clock by (twice the set value) while maintaining the output of the delay clock selected most recently. Clock generation method.

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