JP2012174318A - Sense amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sense amplifier circuit capable of acceleration without increasing power consumption as much as possible.SOLUTION: In the sense amplifier circuit including a latch circuit formed by connecting two inverters, and two transistors for precharge inserted between a bit line and each output node of the latch circuit to perform precharge operation in response to a sense amplifier activation signal, precharge operation is accelerated by applying predetermined voltage between a substrate and a source of each transistor for precharge, using a substrate bias effect of the transistor and lowering threshold voltage. An inverter circuit for inverting a sense amplifier activation signal or the inversion signal thereof and applying the inverted signal to the substrate of each transistor for precharge is provided, an nMOSFET source terminal of each inverter circuit is connected to an output node of the latch circuit, and reuses substrate leak current caused to flow to the output node from the substrate of each transistor for precharge through an nMOSFET during precharging.

Description

  The present invention relates to a sense amplifier circuit for use in, for example, an SRAM (Static Random Access Memory).

  In recent years, the realization of ambient electronics is expected as a form of information society that adds further value to a ubiquitous society. In the ubiquitous society, a user can access a computer without being aware of the existence of the computer. In order to enjoy the benefits of a ubiquitous society, active access from users was essential. On the other hand, in ambient electronics, the computer itself selects information suitable for each user and provides it to the user. The realization of ambient electronics is expected to make the information society more accessible to us. In order to realize ambient electronics, development of next-generation CMOS LSI (Complementary Metal-Oxide-Semiconductor Large Scale Integration) applications such as environmental sensors and biological sensors is indispensable. It is assumed that many environmental sensors will be installed around us. For this reason, it is expensive to replace the battery frequently. Further, since the biosensor is directly embedded in the human body, battery replacement by surgery is a burden on the wearer. From the above, these sensor devices are required to operate for a long period of time with very limited power supplied from a micro battery or the surrounding environment. Therefore, in order to realize a next-generation CMOS LSI application, development of an ultra-low power consumption LSI is indispensable.

  Until now, the power consumption in LSI has been reduced by miniaturization based on the scaling law and the accompanying reduction in power supply voltage. However, in recent years, it is difficult to continue to reduce power consumption by these methods. This is due to an increase in leakage current in the LSI. Due to the thinning of the gate insulating film accompanying the miniaturization of the design process, the gate leakage current flowing between the gate and the source and between the gate and the drain through the gate insulating film increases. Further, since the threshold voltage needs to be reduced as the power supply voltage decreases, the subthreshold leakage current increases accordingly. The subthreshold leakage current increases exponentially as the threshold voltage decreases. Therefore, the subthreshold leakage current increases at an accelerated rate by continuing miniaturization based on the scaling law and reducing the power supply voltage. Such an increase in leakage current becomes an obstacle in reducing the power consumption of LSI. Therefore, there is a need for a method for reducing power consumption that is different from the conventional one. At present, the subthreshold region operation of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is drawing attention instead of the conventional low power consumption design method. The subthreshold region operation of the MOSFET is effective as a method for dramatically reducing power consumption. However, the characteristics of the MOSFET in the subthreshold region vary greatly due to variations in PVT (Process, Voltage, and Temperature). Therefore, there are problems in realizing a subthreshold LSI that stably operates in any environment.

A. Pavlov et al., "CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies", Springer, pp.13-30, 2009. C. Hsu et al., "New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.2, pp.377-384, 2006 . M. Sumita et al., "Mixed Body Bias Techniques With Fixed Vt and Ids Generation Circuits", IEEE Journal of Solid-state Circuits, Vol. 40, No.1, pp.60-66, 2005.

  An SRAM that is a storage element is an important element circuit in an LSI. Since SRAM occupies most of the chip area, it greatly affects the performance of the LSI. The sense amplifier circuit is an amplifier circuit used when reading data held in the SRAM cell. During the read operation of the SRAM, a potential difference is generated between the two bit lines (BL and BLB) connected to the SRAM cell. The sense amplifier circuit amplifies the potential difference between the bit lines, so that the data held in the SRAM cell can be read. In order to perform the amplification operation again after performing the amplification operation by the sense amplifier circuit, it is necessary to perform the precharge operation of the sense amplifier circuit.

There are two types of MOSFETs: p-channel MOSFETs (hereinafter referred to as pMOSFETs) in which holes are carriers responsible for current conduction, and n-channel MOSFETs (hereinafter referred to as nMOSFETs) in which electrons are carriers. The MOSFET controls the drain current _ID by changing the gate-source voltage _VGS .

FIG. 1 is a graph showing a voltage V _GS vs. current _ID characteristic (linear scale) of a MOSFET according to the prior art, and FIG. 2 shows a voltage V _GS vs. current _ID characteristic (logarithmic scale) of the MOSFET according to the prior art. It is a graph. As apparent from FIGS. 1 and 2, when the voltage V _GS exceeds the threshold voltage V _TH , the drain current _ID increases rapidly. The region of V _GS > V _TH is called a strong inversion region, and the region of V _GS <V _TH is called a subthreshold region. MOSFETs have different characteristics in the strong inversion region and the subthreshold region.

FIG. 3 is a graph showing voltage V _DS vs. current _ID characteristics in the strong inversion region of the MOSFET according to the prior art. The voltage _VDS is a drain-source voltage of the MOSFET. As is apparent from FIG. 3, the V _DS vs. _ID characteristics show different characteristics in the region of V _DS <V _GS −V _{TH and} the region of V _DS > V _GS −V _TH . The former is called a strong inversion linear region, and the latter is called a strong inversion saturation region. In general, when a circuit is designed in a strong inversion region, high-speed operation is possible, but power consumption is large.

FIG. 4 is a graph showing voltage V _DS vs. current _ID characteristics in a subthreshold region of a MOSFET according to the prior art. In general, a region where V _DS <0.1 V is called a subthreshold linear region, and a region where V _DS > 0.1 V is called a subthreshold saturation region. In general, in the sub-threshold region operation, the drain current is very small, so that low power consumption of the circuit can be expected. However, the operation is slow.

  The SRAM is a circuit element responsible for storing / holding data in the LSI, and the CMOS inverter is a logic circuit for inverting the input logic. The SRAM cell is constituted by a CMOS inverter.

  FIG. 5 is a circuit diagram showing a configuration of a CMOS inverter 11 according to the prior art. The CMOS inverter 11 includes a pMOSFET (P1) and an nMOSFET (N1). The source of the pMOSFET (P1) is connected to the power supply, and the source of the nMOSFET (N1) is grounded. The drain of the pMOSFET (P1) and the drain of the nMOSFET (N1) are connected and used as an output node. When a high level signal is input to the input of the inverter, the nMOSFET (N1) becomes conductive and a low level signal is output. When a low level signal is input, the pMOSFET (P1) becomes conductive and a high level signal is output.

  An inverter latch circuit is used as a circuit for holding data in the SRAM cell. FIG. 6 is a circuit diagram showing a configuration of an inverter latch circuit according to the prior art. The inverter latch circuit is composed of two CMOS inverters 11 and 12, of which one inverter is connected to the other input. In the inverter latch circuit, since the output voltage of one inverter is input to the other input terminal, one of the potentials of the nodes N and NB is at a high level and the other is at a low level. By maintaining this stable state, the inverter latch circuit can hold 1-bit information.

  FIG. 7 is a circuit diagram showing a configuration of an SRAM cell according to the prior art. The SRAM cell holds 1-bit information by using an inverter latch circuit. Access transistors N3 and N4 are nMOSFETs that conduct when data is read or written. When reading data held in the SRAM cell, first, the bit lines BL and BLB are raised to a high level, and then the word line WL is raised to a high level. When the word line WL is raised to the high level, the bit line connected to the node holding the low level among the two bit lines BL and BLB is discharged, and a minute potential difference is generated between the bit lines BL and BLB ( For example, refer nonpatent literature 2.).

  The sense amplifier circuit is a circuit used for a data read operation held in the SRAM cell. During the read operation of the SRAM, a potential difference is generated between the two bit lines BL and BLB connected to the SRAM cell. This potential difference is amplified by the sense amplifier circuit, and the data held in the SRAM cell is read out.

  FIG. 8 is a circuit diagram showing a configuration of a cross-coupled sense amplifier circuit (CCSA) according to the prior art. This is a cross-coupled sense amplifier circuit, which is a circuit generally used for reading data from a DRAM. The cross-couple type sense amplifier circuit includes an inverter latch circuit (N1, N2, P1, P2), a pMOSFET (P3, P4) for controlling the connection state between the inverter latch circuit and the bit line, and a sense amplifier activation signal (hereinafter referred to as “amplifier”). It is constituted by an nMOSFET (N3) for starting a sensing operation when the SAE signal becomes high level.

When a low level signal is input as the SAE signal, the sense amplifier circuit is in a standby state. At this time, the pMOSFETs P3 and P4 become conductive, and the potentials of the output nodes V _OUT and V _OUTB become equal to the bit lines BL and BLB, respectively. When reading the data held in the SRAM cell, a potential difference is generated between BL and BLB. In order to sense this potential difference, a high level is applied as the SAE signal.

When a high level signal is applied as the SAE signal, the positive feedback of the inverter latch circuit configuration operates. By the action of the positive feedback, the output node _{V OUT,} to a potential of _{V OUTB} is equal to the potential in the stable state of the inverter latch circuit, the output node _{V OUT,} the potential difference _{V OUTB} is amplified. Therefore, the potential of the output node connected to the bit line having a high potential is at a high level, and the potential of the output node connected to the bit line having a low potential is at a low level. At this time, the sensing operation time depends on the conductance of the transistors (N1, N2, N3) in the discharge portion and the capacitance of the transistors (N1, N2, P1, P2, P3, P4) constituting the output nodes V _OUT and V _OUTB. To do. As the conductance of the discharge portion is higher, that is, as the aspect ratio of the nMOSFETs N1, N2, and N3 is larger, the drain current of each transistor increases. Also, the smaller the capacitance of the transistors constituting the output nodes V _OUT and V _OUTB , that is, the smaller the transistor size of N1, N2, P1, P2, P3, and P4, the smaller the output capacitance, so the sensing operation time is shortened.

  Since the number of transistors constituting the cross-coupled sense amplifier circuit is small, it can be mounted with a small area. In addition, since the number of transistors connected in series is small, it is easy to secure the drain-source voltage of each transistor, and low voltage operation is possible. However, since the bit line is connected to the output node, the bit line capacitance increases, and the time and power consumption required for charging the bit line increase.

FIG. 9 is a circuit diagram showing a configuration of a current latch type sense amplifier circuit (CLSA) according to the prior art. The current latch type sense amplifier circuit has an inverter latch circuit (N1, N2, P1, P2), an nMOSFET (N3, N4) having the potentials of the bit lines BL, BLB as gate inputs, and a high level input as an SAE signal. An nMOSFET (N5) for performing a sensing operation and a precharge operation pMOSFET (P3, P4) for charging an output node are configured. When a low level signal is applied as the SAE signal, the pMOSFETs (P3, P4) are turned on. Further, the nMOSFET (N5) is turned off. Therefore, the output nodes V _OUT and V _OUTB are charged by the power supply voltage V _DD .

When a high level signal is applied as the SAE signal, the current latch type sense amplifier operates as a differential amplifier. At this time, the potential difference between the bit lines BL and BLB is propagated to the output nodes _VOUT and _VOUTB , respectively. When a minute potential difference is generated between the output nodes _VOUT and _VOUTB , the positive feedback of the inverter latch circuit configuration operates. At this time, the transistor of the inverter latch circuit configuration amplifies the potential difference between the output nodes _VOUT and _VOUTB until it fully swings to the power supply voltage _VDD or 0V. The number of transistors constituting the current latch type sense amplifier circuit is larger than that of the cross-couple type sense amplifier circuit. Furthermore, since the capacitance of the output node in the no-load state is larger than that of the cross-coupled sense amplifier circuit, the sensing operation is slower than that of the cross-coupled sense amplifier circuit. However, since the bit line is connected to the gate terminal of the nMOSFET (N3, N4), the bit line capacitance is smaller than that of the cross-coupled sense amplifier circuit in which the bit line and the output node are connected through the pMOSFET.

  FIG. 10 is a circuit diagram showing a configuration of a current-mirror sense amplifier circuit (CMSA) according to the prior art. Unlike the cross-coupled sense amplifier and current latch type sense amplifier that perform signal amplification by an inverter latch circuit, the current mirror type sense amplifier circuit performs signal amplification by current comparison. In the current mirror type sensor amplifier circuit, a bit line is connected to the gate terminal of an nMOSFET (N1, N2, N3, N4). The pMOSFETs (P1, P2, P3, P4) have a current mirror configuration. In the current mirror type sensor amplifier circuit, the input voltage is determined by comparing the magnitude of the current flowing through the circuit.

When the low level signal is applied as the SAE signal, the precharge operation pMOSFETs (P5, P6) are turned on. At this time, the nMOSFET (N5) is non-conductive. Therefore, the output nodes V _OUT and V _OUTB are charged by the power supply voltage V _DD . On the other hand, when a high level signal is applied as the SAE signal, a current corresponding to the potentials of the bit lines BL and BLB flows through the nMOSFETs (N1, N2, N3, N4). These currents are compared by pMOSFETs (P1, P2, P3, P4) having a current mirror configuration. The difference in the amount of current appears as the drain-source voltage between the nMOSFET and the pMOSFET, so that the potentials of the output nodes V _OUT and V _OUTB become high level or low level, respectively.

  In the current mirror type sensor amplifier circuit, when a high level signal is applied as the SAE signal, the current is continuously consumed. Therefore, power consumption is large. In the current mirror type sensor amplifier circuit, the current mirror section needs to operate in the saturation region. Therefore, it cannot operate normally at a low power supply voltage at which the current mirror circuit operates in the linear region.

  As described above, the subthreshold region operation of the MOSFET is effective as a method for reducing power consumption. However, the operation of the subthreshold region of the MOSFET is slow. Therefore, it can be used only for an application premised on low-speed operation. Therefore, when the conventional circuit is operated in the subthreshold region, there is a problem that applicable applications are limited.

  An object of the present invention is to provide a sense amplifier circuit capable of speeding up without increasing power consumption as much as possible in order to solve the above-described problems and make it applicable to more applications.

A sense amplifier circuit according to a first aspect of the present invention is a latch circuit formed by connecting two inverters in a cross couple, and is inserted between a bit line and each output node of the latch circuit and responds to a sense amplifier activation signal. In the cross-couple type sense amplifier circuit including two precharging transistors for precharging operation,
By applying a predetermined voltage between the substrate and the source of each of the precharge transistors, the threshold voltage is lowered using the substrate bias effect of the transistor, thereby speeding up the precharge operation. Features.

  The sense amplifier circuit further includes an inverter circuit that is provided for each of the precharge transistors and that inverts the sense amplifier activation signal or its inverted signal and applies the inverted signal to the substrate of each of the precharge transistors. Features.

  In the sense amplifier circuit, each inverter circuit includes a pMOSFET and an nMOSFET, and a source terminal of the nMOSFET is grounded.

  Further, in the sense amplifier circuit, each inverter circuit includes a pMOSFET and an nMOSFET, a source terminal of the nMOSFET is connected to an output node of the latch circuit, and a substrate of each precharging transistor at the time of precharging. The substrate leakage current flowing from the first through the nMOSFET to the output node is reused.

According to a second aspect of the present invention, there is provided a sense amplifier circuit comprising a latch circuit formed by connecting two inverters in a cross couple, and a sense amplifier activation signal inserted between a power supply voltage and each output node of the latch circuit. In a current latch type sense amplifier circuit including two precharging transistors for performing a precharging operation,
By applying a predetermined voltage between the substrate and the source of each of the precharge transistors, the threshold voltage is lowered using the substrate bias effect of the transistor, thereby speeding up the precharge operation. Features.

  The sense amplifier circuit further includes an inverter circuit that is provided for each of the precharge transistors and that inverts the sense amplifier activation signal or its inverted signal and applies the inverted signal to the substrate of each of the precharge transistors. Features.

  In the sense amplifier circuit, each inverter circuit includes a pMOSFET and an nMOSFET, and a source terminal of the nMOSFET is grounded.

  Further, in the sense amplifier circuit, each inverter circuit includes a pMOSFET and an nMOSFET, a source terminal of the nMOSFET is connected to an output node of the latch circuit, and a substrate of each precharging transistor at the time of precharging. The substrate leakage current flowing from the first through the nMOSFET to the output node is reused.

  According to the sense amplifier circuit of the present invention, by applying a predetermined voltage between the substrate and the source of each of the precharging transistors, the threshold voltage is lowered using the substrate bias effect of the transistor. Thus, the precharge operation can be speeded up. And an inverter circuit that is provided for each precharge transistor and that inverts the sense amplifier activation signal or its inverted signal and applies the inverted signal to the substrate of each precharge transistor. The source terminal is connected to the output node of the latch circuit, and by reusing the substrate leakage current flowing from the substrate of each precharging transistor to the output node via the nMOSFET at the time of precharging, the power consumption is greatly increased. Can be reduced.

It is a graph which shows the voltage _VGS vs. current _ID characteristic (linear scale) of MOSFET which concerns on a prior art. It is a graph which shows the voltage _VGS vs. current _ID characteristic (logarithmic scale) of MOSFET which concerns on a prior art. It is a graph which shows the voltage _VDS vs. current _ID characteristic of the strong inversion area | region of MOSFET which concerns on a prior art. It is a graph which shows the voltage _VDS versus current _ID characteristic of the subthreshold area | region of MOSFET which concerns on a prior art. It is a circuit diagram which shows the structure of the CMOS inverter which concerns on a prior art. It is a circuit diagram which shows the structure of the inverter latch circuit based on a prior art. It is a circuit diagram which shows the structure of the SRAM cell which concerns on a prior art. It is a circuit diagram which shows the structure of the cross couple type sense amplifier circuit based on a prior art. It is a circuit diagram which shows the structure of the current latch type | mold sense amplifier circuit based on a prior art. It is a circuit diagram which shows the structure of the current mirror type | mold sensor amplifier circuit based on a prior art. It is a circuit diagram which shows the structure of the cross couple type sense amplifier using the dynamic substrate bias which concerns on basic embodiment of this invention. It is a circuit diagram which shows the structure of the current latch type | mold sense amplifier using the dynamic substrate bias which concerns on basic embodiment of this invention. It is sectional drawing of pMOSFET at the time of a forward bias. It is a circuit diagram which shows the structure of the circuit which utilizes board | substrate leak current for charge of output capacity in this embodiment. 1 is a circuit diagram showing a configuration of a cross-coupled sense amplifier circuit using a dynamic substrate bias according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the current latch type | mold sense amplifier circuit using the dynamic substrate bias which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the cross couple type sense amplifier circuit which does not reuse the board | substrate leak current based on the 3rd Embodiment of this invention. FIG. 10 is a circuit diagram showing a configuration of a current latch type sense amplifier circuit that does not reuse a substrate leakage current according to a fourth embodiment of the present invention. 5 is a waveform diagram showing operation waveforms of the cross-coupled sense amplifier circuit according to the first embodiment. FIG. FIG. 3 is an operation waveform of the cross-coupled sense amplifier circuit according to the first embodiment, in particular, a waveform diagram showing an SAE signal and an SAEB signal. FIG. 6 is a waveform diagram showing operation waveforms of a current latch type sense amplifier circuit according to a second embodiment. FIG. 6 is a waveform diagram showing an operation waveform of the current latch type sense amplifier circuit according to the second embodiment, particularly showing an SAE signal and an SAEB signal. It is a table | surface which shows the precharge operation time and sensing operation time of the sense amplifier circuit which concerns on a prior art and each embodiment. 10 is a histogram showing variations in precharge operation time of a cross-coupled sense amplifier circuit according to the prior art. 6 is a histogram showing variations in precharge operation time of the cross-coupled sense amplifier circuit according to the first embodiment. 5 is a histogram showing variations in precharge operation time of a current latch type sense amplifier circuit according to the prior art. 10 is a histogram showing variations in precharge operation time of the current latch type sense amplifier circuit according to the second embodiment. It is a table | surface which shows the process variation dependence containing the average value and the maximum value of the precharge operation time of the sense amplifier circuit which concerns on a prior art and each embodiment. It is a table | surface which shows the average current consumption of the sense amplifier circuit which concerns on a prior art and each embodiment. It is a table | surface which shows PD product of the sense amplifier circuit which concerns on a prior art and each embodiment. It is a graph which shows the power supply voltage dependence of the precharge operation time of the sense amplifier circuit which concerns on a prior art and each embodiment. It is a graph which shows the power supply voltage dependence of the precharge operation time of the sense amplifier circuit which concerns on a prior art and each embodiment. It is a graph which shows the power supply voltage dependence of the power consumption of the sense amplifier circuit which concerns on a prior art and each embodiment. FIG. 32 is an enlarged view of FIG. 31.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  As described above, when the precharge operation is slow, there is a problem that it takes time before the amplification operation can be performed again. Therefore, speeding up the precharge operation leads to speeding up of the data read operation of the SRAM circuit. Therefore, in the embodiment according to the present invention, a sense amplifier circuit using substrate bias control is proposed in a sense amplifier circuit including a latch circuit formed by connecting two CMOS inverters in a cross couple. The sense amplifier circuit according to the embodiment is characterized in that the precharge operation time is improved by controlling the substrate potential of the MOSFET responsible for precharge during the precharge operation.

  First, the precharge operation speed-up method using the substrate bias effect of the MOSFET and its problems will be described below.

  When the data of the SRAM cell is amplified and read by the sense amplifier circuit, it is necessary to finish a series of operations from sensing to precharge within the timing required by the application. If the precharge is not completed within the required timing, the next sensing operation is not performed normally.

In the cross-coupled sense amplifier circuit, it is necessary to start the sensing operation in a state where the output node potential is equal to the bit line potential. However, if the sensing operation is performed before the precharge operation is completed, the potential difference generated at the output node becomes smaller than usual. In order to amplify this minute potential, more sensing operation time is required. In the current latch type sensor amplifier circuit, the output node potential needs to be charged to the power supply voltage V _DD before the sensing operation starts. However, if the sensing operation is started before the precharge operation is completed, the sensing operation may not be performed normally in the current latch type sensor amplifier circuit.

Thus, the operational stability of the sense amplifier circuit depends on the precharge operation speed. Therefore, in order to improve the read operation stability of the SRAM circuit, it is essential to increase the precharge operation speed of the sense amplifier circuit. In order to speed up the precharge operation, it is necessary to increase the driving force of the MOSFET responsible for the precharge operation. As a method for increasing the driving force of the MOSFET, there are methods such as increasing the voltages V _GS and V _DS or decreasing the threshold voltage. Since the MOSFET responsible for precharging is a pMOSFET, it is necessary to increase the source potential in order to increase the voltages V _GS and V _DS . Therefore, it is necessary to increase the power supply voltage, which is not suitable for subthreshold region operation. Therefore, as a method of reducing the threshold voltage, there is a method of controlling the threshold voltage using the substrate bias effect of the MOSFET. By reducing the threshold voltage of the MOSFET responsible for the precharge operation, the precharge operation can be speeded up.

A change amount ΔV _TH of the threshold voltage V _TH when the MOSFET substrate-source voltage V _BS is changed by ΔV _BS is expressed by the following equation.

Here, ε _si is the dielectric constant of silicon, q is the elementary charge, N _a is the acceptor concentration, and ψ _B is the difference between the Fermi potential and the intrinsic potential. From equation (1), a substrate - by controlling the voltage V _BS-source, it is possible to control the threshold voltage. In order to reduce the threshold voltage, a negative voltage may be applied between the substrate and the source. This bias method is called forward bias.

FIG. 11 is a circuit diagram showing the configuration of a cross-coupled sense amplifier using a dynamic substrate bias according to the basic embodiment of the present invention, and FIG. 12 uses the dynamic substrate bias according to the basic embodiment of the present invention. It is a circuit diagram showing a configuration of a current latch type sense amplifier. In these circuits, the threshold voltage can be lowered by controlling the substrate potential V _BODY of the pMOSFETs (P3, P4) that precharge the output node, and the precharge operation can be speeded up. 11 and 12, the substrate terminals of the pMOSFETs (P3, P4) are P3B and P4B, respectively.

  Next, problems when the substrate bias effect is used will be described below. When a forward bias voltage is applied between the substrate and the source, a substrate leakage current is generated.

FIG. 13 is a cross-sectional view of the pMOSFET during forward bias. As is apparent from FIG. 13, when a negative voltage is applied between the substrate and the source of the pMOSFET, the pn junction in the MOSFET is forward-biased. At this time, the pn junction operates as a diode element. As a result of the pn junction operating as a diode element, a substrate leakage current flows from the source terminal to the substrate. The substrate leakage current I _sub is expressed by the following equation.

Here, A _i and B _i are ionization constants, V _Dsat is the saturation voltage of the MOSFET, t _OX is the thickness of the oxide film, ε _OX is the dielectric constant of the oxide film, and X _j is the junction depth. The saturation voltage V _{Dsat of the} MOSFET is expressed by the following equation.

Substrate - by the source voltage _{V BS} increases, the threshold voltage _{V TH} decreases, the drain current _{I D} increases. Further, as the substrate-source voltage V _BS increases, the substrate leakage current I _sub increases exponentially. Therefore, by using the substrate bias control, the precharge operation of the sense amplifier circuit can be speeded up, but at the same time, the substrate leakage current is increased and the power consumption is increased.

  A sense amplifier circuit according to an embodiment for solving the above problems, that is, a sense amplifier circuit that speeds up the precharge operation without increasing power consumption will be described below.

  FIG. 14 is a circuit diagram showing a configuration of a circuit that utilizes the substrate leakage current for charging the output capacitance in the present embodiment. In FIG. 14, the output node of the CMOS inverter 11 (N1, P1) is connected to the substrate terminal of the transistor P3 responsible for precharging the output node. The source terminal of the nMOSFET (N1) of the CMOS inverter 11 is connected to the drain terminal of the pMOSFET (P3). Further, an SAEB signal that is an inverted signal of the SAE signal is input to the input terminal of the CMOS inverter 11.

During the sensing operation of the sense amplifier circuit, the SAE signal is at a high level. Therefore, a low level signal is input to the CMOS inverter 11. At this time, the pMOSFET (P1) constituting the CMOS inverter 11 becomes conductive. As a result, the substrate potential of the pMOSFET (P3) becomes the power supply voltage V _DD . In this state, since the substrate-source voltage _VBS is 0 V, the value of the threshold voltage _VTH does not change. On the other hand, during the precharge operation of the sense amplifier circuit, a low level signal is input as the SAE signal. At this time, the nMOSFET (N1) constituting the CMOS inverter 11 becomes conductive. As a result, the substrate potential of the pMOSFET (P3) is the same as that of the source terminal. In this state, the substrate - since the voltage _{V BS-source} is negative, the value of the threshold voltage of the pMOSFET (P3) is decreased. As the threshold voltage V _TH decreases, the output node is precharged.

In FIG. 14, an arrow indicates a current that flows during precharging. The precharge operation of the output capacitance by the sense amplifier circuit is performed by the drain current _Idp3 of the pMOSFET (P3). In the circuit according to the present embodiment, since the substrate bias effect is used, the substrate leakage current I _leak flows from the substrate (substrate terminal P3B) of the pMOSFET (P3). Since the substrate leakage current I _leak is used for charging the output node via the nMOSFET (N1), an increase in consumption current due to the substrate leakage current I _leak can be suppressed.

Next, a sense amplifier circuit using dynamic substrate bias control, that is, a sense amplifier circuit that speeds up the precharge operation without increasing power consumption will be described below. The circuit is characterized in that the power consumption is not increased by the substrate leakage current I _leak while using the substrate bias control of the MOSFET.

  FIG. 15 is a circuit diagram showing a configuration of a cross-coupled sense amplifier circuit using a dynamic substrate bias according to the first embodiment of the present invention. In FIG. 15, the sense amplifier circuit according to the first embodiment is characterized by further comprising CMOS inverters 13 and 14 as compared with the sense amplifier circuit of FIG. 8 according to the prior art. Here, the output nodes of the CMOS inverters 13 and 14 (N11, N12, P11, P12) are connected to the substrate terminals P3B and P4B of the pMOSFETs (P3 and P4) that are responsible for precharging the bit lines, respectively. The source terminals of the nMOSFETs (N11, N12) of the CMOS inverter are connected to the drain terminals of the pMOSFETs (P1, P2), respectively. An inverted signal SAEB (hereinafter also referred to as SAEB signal) of the SAE signal is input to the input terminals of the CMOS inverters 13 and 14.

When a high level signal is input as the SAE signal, the pMOSFETs (P11 and P12) constituting the CMOS inverters 13 and 14 are turned on. As a result, the substrate potential of the pMOSFETs (P3, P4) becomes the power supply voltage V _DD . In this state, since the substrate-source voltage _VBS is 0 V, the value of the threshold voltage _VTH does not change.

On the other hand, when a low level signal is input to the SAE signal, the nMOSFETs (N11 and N12) constituting the CMOS inverters 13 and 14 are turned on. As a result, the substrate potential of the pMOSFETs (P3, P4) is the same as that of the source terminal. In this state, the substrate - since the voltage _{V BS-source} is a negative voltage, the value of the threshold voltage _{V TH} of the pMOSFET (P3, P4) is reduced. As the threshold voltage V _TH decreases, the precharge operation of the cross-coupled sense amplifier circuit of FIG. 15 is accelerated. When a low level signal is input as the SAE signal and the nMOSFETs (N11, N12) are conductive, the substrate potential becomes equal to the potentials of the output nodes V _OUT , V _OUTB to be precharged. As the precharge operation proceeds, the gate-source voltage of each nMOSFET (N11, N12) decreases. As the gate-source voltage of each nMOSFET (N11, N12) decreases, the nMOSFET (N11, N12) becomes non-conductive. When the nMOSFETs (N11, N12) are turned off, the substrate terminals P3B, P4B of the pMOSFETs (P3, P4) responsible for the precharge operation are in a floating state. With this effect, the precharge operation can be performed in a state where the forward bias with respect to the substrate terminals P3B and P4B of the pMOSFETs (P3 and P4) is maintained.

  As described above, according to the present embodiment, it is possible to improve the precharge operation speed. In a cross-coupled sense amplifier circuit using dynamic substrate bias control, a substrate leakage current flows from a bit line and is used for charging an output capacitance. As a result, the potential of the bit line is lowered, and charging of the output capacitor is delayed.

  FIG. 16 is a circuit diagram showing a configuration of a current latch type sense amplifier circuit using a dynamic substrate bias according to the second embodiment of the present invention. 16, the sense amplifier circuit according to the second embodiment is characterized by further including CMOS inverters 13 and 14 as compared with the sense amplifier circuit of FIG. 9 according to the prior art. Here, as in FIG. 15, the output nodes of the CMOS inverters 13 and 14 (N11, N12, P11, P12) are connected to the substrate terminals P3B and P4B of the pMOSFETs (P3 and P4) responsible for precharging, respectively. ing. The source terminals of the nMOSFETs (N11, N12) of the CMOS inverters 13, 14 are connected to the drain terminals of the pMOSFETs (P3, P4), respectively. An inverted signal SAEB of the SAE signal is input to the input terminals of the CMOS inverters 13 and 14.

When a high level signal is input as the SAE signal, the pMOSFETs (P11 and P12) constituting the CMOS inverters 13 and 14 are turned on. As a result, the substrate potential of the pMOSFETs (P3, P4) becomes the power supply voltage V _DD . In this state, since the substrate-source voltage _VBS is 0 V, the value of the threshold voltage _VTH does not change. On the other hand, when a low level signal is input as the SAE signal, the nMOSFETs (N11, N12) constituting the CMOS inverters 13, 14 are turned on. As a result, the substrate potential of the pMOSFETs (P3, P4) is the same as that of the source terminal. In this state, the substrate - since the voltage _{V BS-source} is a negative voltage, the value of the threshold voltage _{V TH} of the pMOSFET (P3, P4) is reduced. As the threshold voltage V _TH decreases, the precharge operation of the current latch type sense amplifier circuit of FIG. 16 is speeded up. When a low level signal is input as the SAE signal and the nMOSFETs (N11, N12) are conductive, the substrate potential becomes equal to the potentials of the output nodes V _OUT , V _OUTB to be precharged. As the precharge operation proceeds, the gate-source voltage of the nMOSFETs (N11, N12) decreases. As the gate-source voltage of the nMOSFET (N11, N12) decreases, the nMOSFET (N11, N12) becomes non-conductive. When the nMOSFETs (N11, N12) are turned off, the substrate terminals P3B, P4B of the pMOSFETs (P3, P4) responsible for the precharge operation are in a floating state. With this effect, the precharge operation can be performed in a state where the forward bias with respect to the substrate terminals P3B and P4B of the pMOSFETs (P3 and P4) is maintained.

  As described above, according to the present embodiment, it is possible to improve the precharge operation speed. Unlike a cross-coupled sense amplifier circuit using dynamic substrate bias control, a current latch type sense amplifier circuit using dynamic substrate bias control flows from a power supply and is used to charge an output capacitance. Therefore, there is no adverse effect on the precharge operation time.

  When the substrate bias effect is applied to the sense amplifier circuit according to the prior art, the power consumption increases due to the substrate leakage current. However, in the sense amplifier circuits according to the first and second embodiments, since the substrate leakage current is used for charging the output node through the nMOSFET constituting the CMOS inverter, an increase in consumption current due to the substrate leakage current is suppressed. Is possible.

Furthermore, the operating characteristics of the sense amplifier circuits according to the first and second embodiments were evaluated by SPICE simulation. In addition to the following four sense amplifier circuits, the evaluation circuit
(A) A cross-coupled sense amplifier circuit according to the prior art (FIG. 8),
(B) a current latch type sense amplifier circuit according to the prior art (FIG. 9);
(C) Cross-coupled sense amplifier circuit according to the first embodiment (FIG. 15)
(D) Current latch type sense amplifier circuit according to the second embodiment (FIG. 16)
A cross-coupled sense amplifier circuit that does not reuse the substrate leakage current shown in FIGS. 17 and 18 in order to confirm the effect of reducing the consumption current by using the substrate leakage current for charging the output capacitance (third embodiment). The simulation was also performed for the current latch type sense amplifier circuit (fourth embodiment).

  FIG. 17 is a circuit diagram showing the configuration of a cross-coupled sense amplifier circuit that does not reuse the substrate leakage current according to the third embodiment of the present invention. FIG. 18 shows the substrate leakage according to the fourth embodiment of the present invention. It is a circuit diagram showing a configuration of a current latch type sense amplifier circuit that does not reuse current. The sense amplifier circuit according to the third embodiment of FIG. 17 is characterized in that the source terminals of the nMOSFETs (N11, N12) of the CMOS inverters 13 and 14 are grounded as they are, as compared with the sense amplifier circuit of FIG. Yes. Further, in the sense amplifier circuit according to the fourth embodiment of FIG. 18, the source terminals of the nMOSFETs (N11, N12) of the CMOS inverters 13 and 14 are grounded as they are, as compared with the sense amplifier circuit of FIG. It is a feature. The sense amplifier circuits according to the third and fourth embodiments are characterized in that the precharge can be speeded up, although the consumption current is less reduced.

The process for using the prototype sense amplifier circuit used for the simulation is a standard CMOS process of 0.35 μm. The power supply voltage V _DD was 0.5 V, and the bit line capacitance was 150 fF. The element size is only the nMOSFETs (N11, N12) of the sense amplifier circuits according to the first to fourth embodiments (gate width W, gate length L) = (0.4 μm, 5 μm), and all other MOSFETs are (gates). Width W, gate length L) = (5 μm, 5 μm).

  FIG. 19A is a waveform diagram showing operation waveforms of the cross-coupled sense amplifier circuit according to the first embodiment, and FIG. 19B is a waveform diagram showing its SAE signal and SAEB signal. FIG. 20A is a waveform diagram showing operation waveforms of the current latch type sense amplifier circuit according to the second embodiment, and FIG. 20B is a waveform diagram showing the SAE signal and the SAEB signal. The discharge operation of the bit line was evaluated by connecting a 6-transistor type SRAM cell in order to simulate an actual device.

As is clear from FIGS. 19A, 19B, 20A, and 20B, when a low level signal is input as the SAE signal, the substrate potential changes from the power supply voltage V _DD to 0V. From this, it can be confirmed that a forward bias is applied to the pMOSFETs (P3, P4) for precharge operation. Further, it can be confirmed that the substrate potential is stabilized around _0.25 V when the output nodes V _OUT and V _{OUTB of} the sense amplifier circuit are charged. This is because the substrate of the pMOSFET (P3, P4) is in a floating state. As described above, when the high level signal is obtained as the SAEB signal, the substrate potential becomes the power supply voltage V _DD again. Therefore, the substrate bias is not applied to the pMOSFETs (P3 and P4) that perform precharging during the next sensing operation, and the sensing operation is not affected.

FIG. 21 is a table showing the precharge operation time and the sensing operation time of the sense amplifier circuit according to the related art and each embodiment. The sensing operation time is the time from when the SAE signal increases to 10% of the power supply voltage V _DD to when the output node potential of the sense amplifier circuit decreases to 10% of the power supply voltage V _DD . The precharge operation time is the time from when the SAE signal decreases to 90% of the power supply voltage V _DD to when the output node potential of the sense amplifier circuit increases to 90% of the power supply voltage V _DD . As a subsequent load, one CMOS inverter was connected to the output node of the sense amplifier circuit.

  There was no significant difference in sensing operation time between the sense amplifier circuits according to the first and second embodiments and the sense amplifier circuit according to the related art. This is because the sense amplifier circuit according to the first and second embodiments is a method for improving only the precharge operation time. In the sense amplifier circuits according to the first and second embodiments and the sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current, precharging is performed by applying dynamic substrate bias control. During operation, the threshold voltage of the transistor decreases. As a result, the precharge operation time of the sense amplifier is reduced. By applying the dynamic substrate bias control, the sense amplifier circuit according to the first and second embodiments has a longer operation time than the sense amplifier circuit according to the related art, and the cross-coupled sense amplifier circuit has 79.9%. In the current latch type sense amplifier circuit, the reduction was 86.9%. In addition, the sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current reduce the precharge operation time by 82.9% and 90.4%, respectively, as compared with the sense amplifier circuit according to the related art. .

  The operating time reduction rate in the cross-coupled sense amplifier circuit is smaller than the operating time reduction rate in the current latch type sense amplifier circuit. This is due to the difference in the supply method of the charge necessary for the precharge operation in the two sense amplifier circuits. In the current latch type sense amplifier circuit, the power supply supplies the charge necessary for the precharge operation of the output node. On the other hand, in the cross-coupled sense amplifier circuit, the bit line supplies charges necessary for the precharge operation of the output node. Therefore, a substrate leak current is generated from the substrate terminal to the output node, thereby lowering the bit line potential. As the bit line potential decreases, the precharge operation time increases.

Also, the sense amplifier circuits according to the first and second embodiments have a smaller precharge operation time reduction rate than the sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current. This substrate potential of the pMOSFET responsible for precharging the sense amplifier circuit according to the first and second embodiments, higher than 0V, the substrate - the third and source voltage V _BS does not reuse the substrate leakage current This is because it is smaller than the sense amplifier circuit according to the fourth embodiment.

）とグローバルバラツキ（一様分布：０．１Ｖ＜ΔＶ_ＴＨ＜０．１Ｖ）双方を考慮した。なお、ＳＲＡＭセルにおける読み出し動作のプロセスバラツキ依存性を無視するため、ビット線の充電は理想電圧源によって行った。 Next, in order to evaluate the process variation dependency of the precharge operation time of the sense amplifier circuit according to the first and second embodiments and the sense amplifier circuit according to the related art, a Monte Carlo simulation was performed 250 times. At that time, random variation (Gaussian distribution:

) And global variation (uniform distribution: 0.1 V <ΔV _TH <0.1 V). In order to ignore the process variation dependency of the read operation in the SRAM cell, the bit line was charged by an ideal voltage source.

  FIG. 22 is a histogram showing variations in precharge operation time of the cross-coupled sense amplifier circuit according to the prior art, and FIG. 23 shows variations in precharge operation time of the cross-coupled sense amplifier circuit according to the first embodiment. It is a histogram to show. FIG. 24 is a histogram showing variations in the precharge operation time of the current latch type sense amplifier circuit according to the prior art. FIG. 25 shows the precharge operation time of the current latch type sense amplifier circuit according to the second embodiment. It is a histogram which shows variation. FIG. 26 is a table showing the process variation dependency including the average value and the maximum value of the precharge operation time of the sense amplifier circuit according to the related art and each embodiment. As apparent from FIGS. 22 to 26, by applying the dynamic substrate bias control, the maximum value of the precharge operation time is 86.9% in the cross-coupled sense amplifier circuit and in the current latch type sense amplifier circuit. It was reduced by 85.6%.

Next, simulation evaluation was performed in order to evaluate the power supply voltage dependency of the precharge operation time. The precharge operation time of each sense amplifier when the power supply voltage V _DD was changed from 0.5 V to 1.0 V was evaluated.

  FIG. 29 is a graph showing the power supply voltage dependency of the precharge operation time of the sense amplifier circuit according to the conventional technology and each embodiment, and FIG. 30 is a graph showing the precharge operation time of the sense amplifier circuit according to the conventional technology and each embodiment. It is a graph which shows power supply voltage dependence. 29 is a graph in which the power supply voltage is changed from 0.5 V to 0.75 V, and FIG. 30 is a graph in which the power supply voltage is changed from 0.75 V to 1.0 V.

As is apparent from FIGS. 29 and 30, the current latch type sense amplifier circuit according to the prior art has a longer precharge operation time than the cross couple type sense amplifier circuit according to the prior art, regardless of the value of the power supply voltage V _DD . However, in the section where the power supply voltage V _DD is 0.5 V to 0.7 V, the current latch type sense amplifier circuit according to the second embodiment has a precharge operation time longer than the cross-couple type sense amplifier circuit according to the first embodiment. Is short. This is because, as described above, the bit line supplies the charge necessary for the precharge operation of the output node, so that the substrate leakage current is generated from the substrate terminal to the output node, thereby lowering the bit line potential. . In the section where the power supply voltage V _DD is 0.7V or higher, the first cross-coupled sense amplifier circuit is faster than the current latch type sense amplifier circuit according to the second embodiment.

  As described above, the drain current of the MOSFET in the subthreshold region changes exponentially with respect to the gate-source voltage. For this reason, the drain current flowing through the pMOSFET responsible for precharging rapidly decreases due to the decrease in the bit line potential. Further, the drain current of the MOSFET in the strong inversion region does not change exponentially with respect to the gate-source voltage. Therefore, in the strong inversion region, the decrease in the drain current flowing through the pMOSFET responsible for precharging due to the decrease in the bit line potential is smaller than that in the subthreshold region. Therefore, the current latch type sense amplifier circuit according to the second embodiment in which the voltage between the gate and the source of the pMOSFET responsible for precharging does not decrease in the subthreshold region becomes high speed, and the sense amplifier with high speed precharge operation in the strong inversion region. The cross-coupled sense amplifier circuit according to the first embodiment based on the cross-coupled sense amplifier circuit, which is a circuit, becomes faster.

  Next, the current consumption in each sense amplifier circuit was evaluated. The bit line was charged by an ideal voltage source. As the speed at which the current latch type sense amplifier circuit according to the prior art, which is the slowest, can operate sufficiently, the sensing operation and the precharging operation of the sense amplifier are performed at a precharge operation of 300 μsec, a sensing operation of 50 μsec, and an operating frequency of 2.85 kHz The current consumption was evaluated.

  FIG. 27 is a table showing the average current consumption of the sense amplifier circuits according to the related art and each embodiment. The cross-couple type sense amplifier circuit and the current latch type sense amplifier circuit have an inverter latch circuit structure. Therefore, the current consumption during the operation of these sense amplifier circuits is mainly a through current that flows during sensing and precharging. By applying the dynamic substrate bias control, the through current of the CMOS inverters 13 and 14 for controlling the substrate potential flows at the timing of switching of the SAE signal. For this reason, the current path through which the through current flows during the transition of the SAE signal increases. However, the current flowing through each current path decreases as the output signal transitions earlier. As a result, the current consumption decreases by 6.06% in the cross-coupled sense amplifier circuit according to the first embodiment, and the current consumption decreases by 1.55% in the current latch type sense amplifier circuit according to the second embodiment. Increased.

In the sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current, the substrate leakage current constantly flows during precharge. Therefore, the cross-coupled sense amplifier circuit according to the third embodiment is 8.71 times that of the sense amplifier circuit according to the prior art, and the current latch type sense amplifier circuit according to the fourth embodiment is 13.1 times as much. The current consumption increased. The current consumption increase rate of the cross-coupled sense amplifier circuit according to the third embodiment is lower than that of the current latch type sense amplifier circuit according to the fourth embodiment. This is because, in the current latch type sense amplifier circuit according to the fourth embodiment, the output nodes V _OUT and V _OUTB are charged to the power supply voltage V _DD at the time of precharging, whereas the cross coupled type according to the third embodiment is used. This is because in the sense amplifier circuit, one of the output nodes V _OUT and V _OUTB is charged to a potential that is lower than the power supply voltage V _DD and the other is lower than the power supply voltage V _DD by a voltage ΔV.

  Next, the power supply voltage was changed from 0.5 V to 1.0 V, and the power supply voltage dependency of power consumption was evaluated. The simulation conditions are the same when comparing current consumption. FIG. 31 is a graph showing the power supply voltage dependency of the power consumption of the sense amplifier circuit according to the related art and each embodiment, and FIG. 32 is an enlarged view of FIG.

  Since the sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current constantly flow during the precharge operation, the power consumption increases as compared with the sense amplifier circuit according to the related art. The sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current have a cross-couple type sense amplifier circuit that is up to 87.2 times the current latch type sense compared to the sense amplifier circuit according to the prior art. The power consumption of the amplifier circuit increased 227 times. The sense amplifier circuits according to the first and second embodiments can suppress an increase in power consumption in both the cross-coupled sense amplifier circuit and the current latch type sense amplifier circuit by reusing the substrate leakage current. The sense amplifier circuit according to the first and second embodiments has a maximum of 7.41% for the cross-coupled sense amplifier circuit and a maximum of 8.24 for the current latch type sense amplifier circuit as compared with the sense amplifier circuit according to the related art. The power consumption according to the third and fourth embodiments has increased. In the sense amplifier circuits according to the first and second embodiments, it has been confirmed that the reduction in power consumption by reusing the substrate leakage current is effective even when the power supply voltage is increased.

  Further, a comparison of PD products was simulated for the prior art and the sense amplifier circuits according to the embodiments. The PD product is a product of power (Power) and delay time (Delay). The PD product is a value representing the operating energy of the circuit. FIG. 28 is a table showing the PD product of the conventional technology and the sense amplifier circuit according to each embodiment. As is apparent from FIG. 28, as a result of the improvement of the precharge operation time, the sense amplifier circuit according to the first and second embodiments is a cross-coupled sense amplifier circuit as compared with the sense amplifier circuit according to the prior art. The PD product was reduced by 74.3%, and the current latch type sense amplifier circuit was 77.3%. In the sense amplifier circuits according to the third and fourth embodiments that do not reuse the substrate leakage current, the precharge operation time is improved, but the current consumption increases due to the substrate leakage current. As a result, the PD product increased by 2.08 times for the cross-coupled sense amplifier circuit and 2.29 times for the current latch type sense amplifier circuit compared to the sense amplifier circuit according to the prior art.

  As described above, according to this embodiment, a sense amplifier circuit in which the precharge operation speed is improved by dynamically changing the substrate potential has been devised. In the sense amplifier circuits according to the first and second embodiments, an increase in power consumption can be suppressed by reusing the substrate leakage current generated when the substrate bias effect is used for output precharging. Here, in the cross-coupled sense amplifier circuit, the potential of the bit line is lowered due to the substrate leakage current. Therefore, the effect of reducing the precharge operation time by applying the dynamic substrate bias control is more than that of the cross-coupled sense amplifier circuit. The current latch type sense amplifier circuit is higher.

  In the above embodiments, the pMOSFETs P3 and P4 that operate in response to the SAE signal are used as the precharge operation transistors. However, the present invention is not limited to this, and the transistor operates in response to the inverted signal SAEB of the SAE signal. NMOSFET may be used.

  As described above in detail, according to the sense amplifier circuit of the present invention, by applying a predetermined voltage between the substrate and the source of each precharging transistor, the substrate bias effect of the transistor is used. By reducing the threshold voltage, the precharge operation can be speeded up. And an inverter circuit that is provided for each precharge transistor and that inverts the sense amplifier activation signal or its inverted signal and applies the inverted signal to the substrate of each precharge transistor. The source terminal is connected to the output node of the latch circuit, and by reusing the substrate leakage current flowing from the substrate of each precharging transistor to the output node via the nMOSFET at the time of precharging, the power consumption is greatly increased. Can be reduced.

11-14 ... CMOS inverter,
P1-P12 ... pMOSFET,
N1-N12 ... nMOSFET,
P3B, P4B ... Board terminal,
V _OUT , V _OUTB ... Output nodes.

Claims (8)

A latch circuit in which two inverters are connected in a cross couple, and two latch circuits inserted between a bit line and each output node of the latch circuit for performing a precharge operation in response to a sense amplifier activation signal. In a cross-coupled sense amplifier circuit including a precharging transistor,
By applying a predetermined voltage between the substrate and the source of each of the precharge transistors, the threshold voltage is lowered using the substrate bias effect of the transistor, thereby speeding up the precharge operation. A characteristic sense amplifier circuit.   2. An inverter circuit provided for each of the precharging transistors, further comprising an inverter circuit that inverts the sense amplifier activation signal or its inverted signal and applies the inverted signal to the substrate of the precharging transistor. The sense amplifier circuit described. Each inverter circuit includes a pMOSFET and an nMOSFET,
3. The sense amplifier circuit according to claim 2, wherein the source terminal of the nMOSFET is grounded. Each inverter circuit includes a pMOSFET and an nMOSFET,
A source terminal of the nMOSFET is connected to an output node of the latch circuit, and a substrate leakage current flowing from the substrate of each precharging transistor to the output node via the nMOSFET at the time of precharging is reused. The sense amplifier circuit according to claim 2. A latch circuit formed by connecting two inverters in a cross-coupled manner, and two latch circuits inserted between a power supply voltage and each output node of the latch circuit for performing a precharge operation in response to a sense amplifier activation signal In a current latch type sense amplifier circuit including a precharging transistor,
By applying a predetermined voltage between the substrate and the source of each of the precharge transistors, the threshold voltage is lowered using the substrate bias effect of the transistor, thereby speeding up the precharge operation. A characteristic sense amplifier circuit.   6. An inverter circuit which is provided for each of the precharging transistors and which inverts the sense amplifier activation signal or its inverted signal and applies the inverted signal to the substrate of each of the precharging transistors. The sense amplifier circuit described. Each inverter circuit includes a pMOSFET and an nMOSFET,
7. The sense amplifier circuit according to claim 6, wherein the source terminal of the nMOSFET is grounded. Each inverter circuit includes a pMOSFET and an nMOSFET,
A source terminal of the nMOSFET is connected to an output node of the latch circuit, and a substrate leakage current flowing from the substrate of each precharging transistor to the output node via the nMOSFET at the time of precharging is reused. The sense amplifier circuit according to claim 6.

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