JP2012173196A - Detection circuit, and physical quantity measuring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection circuit capable of switching detection sensitivity and a detection range without increasing a layout area and power consumption.SOLUTION: A detection circuit 10 for detecting physical quantity applied to a sensor element on the basis of differential input signals 290 and 292 from the sensor element, includes: a differential amplifying circuit 30 for amplifying the difference between the differential input signals 290 and 292 and outputting that as a first signal 114; a non-reversed amplifying circuit 50 for amplifying a signal 116 based on the first signal and outputting that as a second signal 118; and a rear stage circuit 14 for converting the second signal 118 into a direct-current signal, and producing one output signal 294 according to the physical quantity. At least one of the differential amplifying circuit 30 and the non-reversed amplifying circuit 50 changes an amplification factor, on the basis of an inputted selection signal 210.

Description

  The present invention relates to a detection circuit, a physical quantity measurement device, and the like.

  A sensor circuit in an apparatus for measuring a physical quantity such as an angular velocity is required to be reduced in size as the equipment to be mounted is reduced in size and weight. On the other hand, the sensor circuit is required to have high sensitivity even if it is small.

  In the invention of Patent Document 1, even when the phase difference at which high sensitivity is obtained differs depending on the type of vibration gyro and the like, it is possible to increase the detection sensitivity by generating the timing signal adjusted by the phase shift circuit.

JP 2006-105896 A

  Here, the sensor circuit is mounted on, for example, a vehicle or an electronic device, and is used for applications such as dead reckoning (DR) navigation and camera shake correction. For example, there is a need for a sensor circuit that can be used even in different applications, although the required sensitivity and the like are greatly different between DR and camera shake correction. However, in the invention of Patent Document 1, the sensitivity of detection cannot be adjusted when the usage is different.

  For example, a sensor circuit that outputs signals having different detection sensitivities from two LPFs (low-pass filters) set with different gains satisfies such a requirement. At this time, if the two LPFs are configured by RC circuits, the characteristics are likely to vary due to manufacturing variations. Therefore, if a switched capacitor circuit is used, characteristic fluctuations due to manufacturing variations can be suppressed. However, at this time, the area occupied by the switched capacitor circuit increases, and the demand for downsizing the sensor circuit cannot be satisfied. Furthermore, since the gain distribution according to the sensitivity cannot be optimized, the noise characteristic at the time of high sensitivity is deteriorated.

  The present invention has been made in view of such problems. According to some embodiments of the present invention, it is possible to provide a detection circuit capable of switching detection sensitivity and detection range with low noise without increasing layout area and power consumption.

(1) The present invention is a detection circuit that detects a physical quantity applied to the sensor element based on a differential input signal from the sensor element, and amplifies the difference between the differential input signals, A differential amplifier circuit that outputs a signal, a non-inverting amplifier circuit that amplifies a signal based on the first signal and outputs the second signal, converts the second signal into a DC signal, and A post-stage circuit that outputs one signal corresponding to a physical quantity, and at least one of the differential amplifier circuit and the non-inverting amplifier circuit changes an amplification factor based on an input selection signal.

(2) In this detection circuit, the differential amplifier circuit and the non-inverting amplifier circuit may change the amplification factor in conjunction with each other based on one selection signal.

  According to these inventions, at least one amplification factor of the differential amplifier circuit and the non-inverting amplifier circuit is changed based on the input selection signal without preparing a plurality of output terminals / output circuits. Thereby, it is possible to realize sensitivity / detection range setting according to the application without increasing the layout area and power consumption.

  At this time, the differential amplifier circuit and the non-inverting amplifier circuit may change the amplification factor in conjunction with each other based on one selection signal. Since the amplification factors of the two circuits can be switched with one selection signal, the control becomes easy and the number of terminals is not greatly increased.

(3) In this detection circuit, the differential amplifier circuit changes a resistance value of an input resistor, a feedback resistor, and a resistor provided between the non-inverting input terminal and the ground potential based on the selection signal. Thus, the amplification factor may be changed.

(4) In this detection circuit, the differential amplifier circuit may include an input resistor, a feedback resistor, and a resistor provided between the non-inverting input terminal and the ground potential as a circuit combining unit resistors. Good.

  According to these inventions, the differential amplifier circuit has the input resistance on the inverting input terminal side and the non-inverting input terminal side, the feedback resistance, and the resistance value of the resistor provided between the non-inverting input terminal and the ground potential. By changing it, the amplification factor can be changed. At this time, the amplification factor may change in accordance with, for example, the level (“0” on the low potential side or “1” on the high potential side) of the selection signal.

  Here, the resistor may be configured by a circuit in which unit resistors having one resistance value are combined. For example, when the unit resistance is one cell or a macro, it is possible to obtain a desired amplification factor while suppressing the influence of manufacturing variations.

(5) In this detection circuit, the non-inverting amplifier circuit changes the resistance value of the feedback resistor and the resistor provided between the inverting input terminal and the ground potential based on the selection signal, thereby increasing the amplification factor. May be changed.

(6) In this detection circuit, the non-inverting amplifier circuit may be configured by combining a feedback resistor and a resistor provided between the inverting input terminal and the ground potential with a unit resistor.

  According to these inventions, the non-inverting amplifier circuit can change the amplification factor by changing the resistance value of the feedback resistor and the resistor provided between the inverting input terminal and the ground potential. At this time, the amplification factor may change according to, for example, the level (“0” or “1”) of the selection signal.

  Here, the resistor may be configured by a circuit in which unit resistors having one resistance value are combined. For example, when the unit resistance is one cell or a macro, it is possible to obtain a desired amplification factor while suppressing the influence of manufacturing variations.

(7) In this detection circuit, the post-stage circuit may include an offset adjustment circuit that adjusts a level of the second signal, and the offset adjustment circuit may change an adjustment range based on the selection signal. .

(8) In this detection circuit, the offset adjustment circuit may be arranged immediately after the non-inverting amplifier circuit.

(9) In this detection circuit, the offset adjustment circuit may include a resistor, and the adjustment range may be changed by changing a resistance value of the resistor based on the selection signal.

  According to these inventions, adjustment can be performed inside the offset adjustment circuit in response to a variation caused by a change in at least one amplification factor of the differential amplifier circuit and the non-inverting amplifier circuit. Since the offset adjustment circuit changes the adjustment range based on the selection signal, for example, appropriate offset adjustment can be performed without changing the code signal set at the time of shipment.

  At this time, the offset adjustment circuit may be arranged immediately after the non-inverting amplifier circuit. By sharing part of the circuit, the circuit area can be further reduced.

  Further, the offset adjustment circuit may include, for example, a variable resistor or a resistor combination circuit having a switch for controlling electrical connection. Then, based on the selection signal, the resistance value of the variable resistor may be changed, or the switch of the resistor combination circuit may be switched on and off.

(10) The present invention is a physical quantity measuring device including any of the detection circuits described above.

  According to the present invention, since the detection sensitivity and the detection range can be switched without increasing the layout area and power consumption of the detection circuit, a small physical quantity measuring device that can be used for various purposes can be realized.

The block diagram of the detection circuit of 1st Embodiment. The figure of the signal output part which the detection circuit of a comparative example contains. The figure which shows the example of the circuit in the front | former circuit of the detection circuit of 1st Embodiment. The figure which shows the differential amplifier circuit of 1st Embodiment. The figure which shows the non-inverting amplifier circuit of 1st Embodiment. The figure which shows the example of the circuit in the back | latter stage circuit of the detection circuit of 1st Embodiment. The figure which shows the circuit example of DAC of 1st Embodiment. The block diagram of the detection circuit of a modification. The figure which shows the example of the circuit in the back | latter stage circuit of a modification. The figure which shows a physical quantity measuring apparatus. The block diagram of a drive circuit.

1. First Embodiment A first embodiment of the present invention will be described with reference to FIGS. 2 is a diagram of a signal output unit of a comparative example, and the signal output unit of the present embodiment is shown in FIG.

1.1. Configuration of Detection Circuit According to this Embodiment FIG. 1 is a block diagram of a detection circuit 10 according to this embodiment. The detection circuit 10 receives differential input signals 290 and 292 from the sensor elements. In this embodiment, noise-resistant differential input is performed, but single-ended input may be used.

  The differential input signals 290 and 292 are signals representing physical quantities applied to the sensor elements. The detection circuit 10 performs necessary processing on the analog signal based on the differential input signals 290 and 292 in the pre-stage circuit 12 and converts it into a DC signal in the post-stage circuit 14 including the synchronous detection circuit 60 to perform necessary processing. . Then, an output signal 294 corresponding to the physical quantity is generated.

  Here, the front circuit 12 corresponds to an AC stage that handles AC signals, and the rear circuit 14 corresponds to a DC stage that handles DC signals.

  The pre-stage circuit 12 of the detection circuit 10 includes charge amplifiers 20-1 and 20-2, a differential amplifier circuit (differential amplifier) 30, a high-pass filter (HPF) 40, and a non-inverting amplifier circuit (AC amplifier) 50.

  The subsequent circuit 14 of the detection circuit 10 includes a synchronous detection circuit 60, a signal output unit 70, and an offset adjustment circuit 90.

  The selection signal 210 is input to the differential amplifier circuit 30 and the non-inverting amplifier circuit 50 and is used for selecting a gain (amplification factor). In the present embodiment, one selection signal 210 is input to the differential amplifier circuit 30 and the non-inverting amplifier circuit 50, but two different selection signals 210 may be input respectively. The selection signal 210 is input to the offset adjustment circuit 90 to change the adjustment range. The adjustment width refers to the amount of change in the offset signal 126 when the code signal 212 changes by one.

  The code signal 212 is input to the offset adjustment circuit 90 to determine the offset signal 126. The code signal is, for example, a 3-bit digital signal.

  The charge amplifiers 20-1 and 20-2 convert the charges of the differential input signals 290 and 292 to voltages, respectively. The charge amplifier 20-1 and the charge amplifier 20-2 have the same configuration. The charge amplifiers 20-1 and 20-2 may be omitted.

  The differential amplifier circuit 30 receives both the signals 110 and 112 output from the charge amplifiers 20-1 and 20-2, amplifies the difference between these signals, and outputs the amplified signal as the first signal 114. As will be described later, the gain of the differential amplifier circuit 30 is selected by the selection signal 210.

  The high pass filter 40 transmits the high frequency component of the first signal 114 and outputs it as the signal 116.

  Then, the non-inverting amplifier circuit 50 amplifies the signal 116 and outputs the second signal 118 to the subsequent circuit 14. Note that the gain of the non-inverting amplifier circuit 50 is also selected by the selection signal 210 as described later.

  The synchronous detection circuit 60 receives the second signal 118 and performs synchronous detection. At this time, an offset signal 126 is input from the offset adjustment circuit 90 to the synchronous detection circuit 60 in order to accurately measure the physical quantity applied to the sensor element. The offset signal 126 corresponds to the code signal 212, and the adjustment width is changed by the selection signal 210.

  The signal output unit 70 receives the signal (DC signal) 120 output from the synchronous detection circuit 60, and generates or amplifies a signal converted into a DC voltage by a smoothing process such as a low-pass filter. Then, an output signal 294 corresponding to the physical quantity is generated.

1.2. Signal Output Unit of Comparative Example Before showing an example of a circuit diagram of the detection circuit 10 of the present embodiment, a signal output unit 170 included in the detection circuit of the comparative example will be described with reference to FIG. The configuration of the detection circuit of the comparative example is the same as that in which the selection signal 210, the code signal 212, the offset adjustment circuit 90, and the offset signal 126 are omitted from the detection circuit 10 of the present embodiment except for the signal output unit 170. Therefore, explanation is omitted.

  FIG. 2 is a circuit diagram of the signal output unit 170 of the comparative example. The signal output unit 170 of the comparative example corresponds to the signal output unit 70 of the detection circuit 10 of the present embodiment in FIG. The signal output unit 170 receives the signal 220 output from the synchronous detection circuit, and performs processing by a low-pass filter configured by combining resistors 171 and 173 and capacitors 172 and 174, respectively. These low-pass filters function as a pre-filter for the synchronous detection smoothing process and the subsequent process.

  The signal output unit 170 includes a variable gain amplifier including variable resistors 176 and 177 and an operational amplifier 175. This variable gain amplifier is used as a digital gain. The output signals from the variable gain amplifier are input to two switched capacitor filters 178A and 178B having different gains, and the outputs of these filters become output signals 394A and 394B, respectively.

  In the detection circuit of the comparative example, for example, each of the output signals 394A and 394B is applied to a motion application (for example, sensitivity 0.3 mV / dps, detection range −2000 dps to +2000 dps) and a DR application (for example, sensitivity 2 mV / dps, detection range − (200 dps to +200 dps). By using the two switched capacitor filters 178A and 178B, a detection circuit that can be used even in different applications is realized.

  However, it is difficult to reduce the area because two switched capacitor filters having a large area in the entire detection circuit are included in order to suppress characteristic fluctuations due to manufacturing variations.

  On the other hand, in the detection circuit of this embodiment, the area can be significantly reduced by using only one switched capacitor filter as will be described later, compared to the detection circuit of the comparative example. Hereinafter, an example of a circuit diagram of the detection circuit of the present embodiment will be described.

1.3. Details of detection circuit of this embodiment 1.3.1. Pre-Circuit Circuit FIGS. 3 to 5 are diagrams illustrating examples of circuits in the pre-stage circuit 12 of the detection circuit of the present embodiment. The same elements as those in FIG.

1.3.1.1. Charge Amplifier The charge amplifiers 20-1 and 20-2 have the same configuration, and may be configured by an operational amplifier 26, a resistor (feedback resistor) 24, and a capacitor (feedback capacitor) 22, for example. At this time, the phase adjustment may be performed by performing conversion into a voltage signal and appropriately setting the resistance value of the resistor 24 and the capacitance of the capacitor 22.

1.3.1.2. Differential Amplifier Circuit The differential amplifier circuit 30 may be composed of variable resistors 32, 33, 34, and 35 and an operational amplifier 36, for example. The differential amplifier circuit 30 receives the signals 110 and 112 from the charge amplifiers 20-1 and 20-2, respectively, and outputs a first signal 114. The selection signal 210 determines the resistance values of the variable resistors 32, 33, 34, and 35.

FIG. 4 is a diagram showing details of the differential amplifier circuit 30 of the present embodiment. Variable resistor of the present embodiment 32, 33, 34, 35 (see FIG. 3), the unit resistance 37A~37F a resistance value _{R A,} is composed of 38A-38F. The same elements as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

For example, when the selection signal 210 is “0”, SW1 and SW3 are turned on, and SW2 and SW4 are turned off. At this time, the resistance value of the variable resistor 32 is 2R _A (corresponding to the unit resistors 37A to 37B), and the resistance value of the variable resistor 33 is also 2R _A (corresponding to the unit resistors 38A to 38B). The resistance value of the variable resistor 34 is 4R _A (corresponding to the unit resistors 37C to 37F), and the resistance value of the variable resistor 35 is also 4R _A (corresponding to the unit resistors 38C to 38F).

For example, when the selection signal 210 is “1”, SW1 and SW3 are turned off, and SW2 and SW4 are turned on. At this time, the resistance value of the variable resistor 32 is 4R _A (unit resistors 37A to 37D correspond), and the resistance value of the variable resistor 33 is also 4R _A (unit resistors 38A to 38D correspond). The resistance value of the variable resistor 34 is 2R _A (corresponding to the unit resistors 37E to 37F), and the resistance value of the variable resistor 35 is also 2R _A (corresponding to the unit resistors 38E to 38F).

The gain K _DIF of the differential amplifier circuit 30 of the present embodiment varies greatly as shown in the following expression (1) according to the level of the selection signal 210 (hereinafter, expressed as SEL in the expression). The detection circuit of this embodiment can select an appropriate gain K _DIF by setting the selection signal 210 according to the application (for example, camera shake correction).

１．３．１．３．ハイパスフィルター
ハイパスフィルター４０は、例えばキャパシタ４２と抵抗４４で構成されてもよい。このとき、不要な低周波成分を取り除くとともに、キャパシタ４２の容量と抵抗４４の抵抗値を適当に設定することで位相調整を行ってもよい。

1.3.1.3. High-pass filter The high-pass filter 40 may be composed of, for example, a capacitor 42 and a resistor 44. At this time, unnecessary low frequency components may be removed, and the phase adjustment may be performed by appropriately setting the capacitance of the capacitor 42 and the resistance value of the resistor 44.

1.3.1.4. Non-inverting Amplifier Circuit The non-inverting amplifier circuit 50 may be composed of variable resistors 54 and 56 and an operational amplifier 52, for example. The non-inverting amplifier circuit 50 receives the signal 116 from the high pass filter 40 and outputs the second signal 118. The selection signal 210 determines the resistance values of the variable resistors 54 and 56.

FIG. 5 is a diagram showing details of the non-inverting amplifier circuit 50 of the present embodiment. Variable resistor 54 and 56 of the present embodiment (see FIG. 3) is composed of a unit resistance 55A~55E a resistance value _{R B.} The same elements as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

For example, when the selection signal 210 is “0”, SW5 is turned on and SW6 is turned off. At this time, the resistance value of the variable resistor 54 is 2R _B (corresponding to the unit resistors 55A to 55B), and the resistance value of the variable resistor 56 is 3R _B (corresponding to the unit resistors 55C to 55E).

For example, when the selection signal 210 is “1”, SW5 is turned off and SW6 is turned on. At this time, the resistance value of the variable resistor 54 is 3R _B (corresponding to the unit resistors 55A to 55C), and the resistance value of the variable resistor 56 is 2R _B (corresponding to the unit resistors 55D to 55E).

Gain K _AC of the non-inverting amplifier circuit 50 of the present embodiment is changed as equation (2) below according to the level of the selection signal 210. Detection circuit of this embodiment, by setting in response to a selection signal 210 applications (e.g. image stabilization), it is possible to select the appropriate gain K _AC.

ここで、本実施形態の前段回路１２の例では、１つの選択信号２１０によって連動してＫ_ＤＩＦおよびＫ_ＡＣが変化する。そのため、選択信号２１０の設定の違いによって、下記の式（３）に示すような大きなゲインの差が生じる。

Here, in the example of the pre-stage circuit 12 of the present embodiment, K _DIF and K _AC change in conjunction with one selection signal 210. Therefore, a large gain difference as shown in the following equation (3) occurs due to the difference in the setting of the selection signal 210.

式（３）のように、この例では６倍ものゲインの違いが生じる。そのため、例えばＤＲと手振れ補正といった異なる用途に、本実施形態の１つの検出回路で対応することが可能になる。このとき、比較例（図２参照）のような２つの出力を設ける必要はない。また、前段回路１２でゲイン設定を変更することで、低ノイズ特性、すなわちノイズ成分までは増幅されない特性を保持することもできる。

As in equation (3), a gain difference of 6 times occurs in this example. Therefore, for example, it is possible to cope with different uses such as DR and camera shake correction with one detection circuit of the present embodiment. At this time, it is not necessary to provide two outputs as in the comparative example (see FIG. 2). Further, by changing the gain setting in the pre-stage circuit 12, it is possible to maintain a low noise characteristic, that is, a characteristic that does not amplify the noise component.

1.3.2. Subsequent Circuit FIGS. 6 to 7 are diagrams illustrating examples of circuits in the subsequent circuit 14 of the detection circuit of the present embodiment. The same elements as those in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 6, in the detection circuit of this embodiment, by using only one switched capacitor filter 78, the area and power consumption can be greatly reduced compared to the detection circuit of the comparative example (see FIG. 2). Is possible. The detection circuit according to the present embodiment can cope with applications that require different detection sensitivities and detection ranges by selecting the gains K _DIF and K _AC using the selection signal 210.

On the other hand, when the offset adjustment is performed in the post-stage circuit 14, it is necessary to change the adjustment range in consideration of the gains K _DIF and K _AC in the pre-stage circuit 12. For example, if the adjustment step width is fixed in accordance with the case of a high gain, if the low gain is used, the step width is too large to perform appropriate adjustment. In the detection circuit of this embodiment, the offset adjustment circuit 90 performs adjustment according to the gain setting in the pre-stage circuit 12. Hereinafter, each functional block of the post-stage circuit 14 will be described in order.

1.3.2.1. Synchronous detection circuit The synchronous detection circuit 60 receives the second signal 118 and performs synchronous detection. The synchronous detection circuit 60 may generate an inverted signal of the second signal 118 using an inverting amplifier circuit including resistors 62 and 64 and an operational amplifier 66, for example. Then, for example, the forward or inverted signal may be selected by the switches 68 and 69 that are exclusively turned on. The selection signal SDET of the switches 68 and 69 may be a pulse signal given from the outside of the synchronous detection circuit 60, for example.

  The synchronous detection circuit 60 of the present embodiment receives the offset signal 126 from the offset adjustment circuit 90 and adjusts the signal level. At this time, the circuit area can be reduced by using the inverting amplifier circuit included in the synchronous detection circuit 60 for offset adjustment.

1.3.2.2. Offset Adjustment Circuit The offset adjustment circuit 90 outputs an offset signal 126 for removing unnecessary components included in the signal in order to accurately measure the physical quantity applied to the sensor element. The offset adjustment circuit 90 may adjust an analog signal obtained by converting the input code signal 212 by the DAC 92 with the resistors 94 and 96 and output the analog signal as the offset signal 126. At this time, on / off of the switch 98 that bypasses the resistor 96 may be changed by the selection signal 210.

  Here, the code signal 212 is a fixed value determined according to the individual difference of the detection circuit at the time of shipment, for example, and is stored in a flash memory or the like. Therefore, an analog signal obtained by converting the code signal 212 by the DAC 92 is also a signal having a specific level.

As described above, when the offset adjustment is performed in the post-stage circuit 14, it is necessary to change the adjustment range in consideration of the gains K _DIF and K _AC in the pre-stage circuit 12. The offset adjustment circuit 90 can perform adjustments corresponding to the gains K _DIF and K _AC by changing the adjustment range by turning on and off the switch 98.

As shown in FIG. 6, the resistance value of the _DAC 92 is R _DAC , the resistance value of the resistor 94 is R ₁ , the resistance value of the resistor 96 is R ₂ , and the resistance values of the resistor 62 and the resistor 64 are R ₀ . At this time, when 1 LSB of the _DAC 92 is expressed as V _DAC , for example, when the selection signal 210 is “0”, the adjustment width V _step 0 in the signal 120 is _expressed by the following formula (4). At this time, the switch 98 is on.

一方、例えば選択信号２１０が‘１’の場合には、信号１２０における調整幅Ｖ_{ｓｔｅｐ１}は下記の式（５）となる。なお、このときには、スイッチ９８はオフ状態となっている。

On the other hand, for example, when the selection signal 210 is “1”, the adjustment width V _step1 in the signal 120 is expressed by the following equation (5). At this time, the switch 98 is in an OFF state.

ここで、式（３）のように、選択信号２１０が‘０’の場合の差動増幅回路３０のゲインをＫ_ＤＩＦ０、非反転増幅回路５０のゲインをＫ_ＡＣ０とする。また、選択信号２１０が‘１’の場合の差動増幅回路３０のゲインをＫ_ＤＩＦ１、非反転増幅回路５０のゲインをＫ_ＡＣ１とする。

Here, as shown in Expression (3), when the selection signal 210 is “0”, the gain of the differential amplifier circuit 30 is K _DIF0 , and the gain of the non-inverting amplifier circuit 50 is K _AC0 . When the selection signal 210 is “1”, the gain of the differential amplifier circuit 30 is K _DIF1 , and the gain of the non-inverting amplifier circuit 50 is K _AC1 .

At this time, the resistance value _{R 1} of the resistor 94, the resistance value _{R 2} of the resistor 96, if selected to satisfy the equation (6) below, corresponding to the selection signal 210 (i.e., the gain _{K DIF,} the _{K AC} Appropriate adjustment range (corresponding to change) can be given.

例えば、選択信号２１０が‘０’の場合には、モーション用途（例えば、感度０．３ｍＶ／ｄｐｓ、検出範囲−２０００ｄｐｓ〜＋２０００ｄｐｓ）に適したゲイン設定であるとする。このとき、オフセット調整回路９０は、選択信号２１０の値に基づいて、例えば０．３ｍＶ／ｓｔｅｐのオフセット調整幅を選択してもよい。

For example, when the selection signal 210 is “0”, it is assumed that the gain setting is suitable for motion applications (for example, sensitivity 0.3 mV / dps, detection range −2000 dps to +2000 dps). At this time, the offset adjustment circuit 90 may select an offset adjustment width of, for example, 0.3 mV / step based on the value of the selection signal 210.

  For example, when the selection signal 210 is “1”, it is assumed that the gain setting is suitable for a DR application (for example, sensitivity 2 mV / dps, detection range −200 dps to +200 dps). At this time, the offset adjustment circuit 90 may select an offset adjustment width of 2 mV / step based on the value of the selection signal 210, for example.

  Although the configuration of the DAC 92 is not limited to a specific one, the present embodiment takes the circuit structure of FIG. The DAC 92 in FIG. 7 receives a digital value of n + 1 bits as the code signal 212. At this time, n is an integer greater than or equal to 0, and the code signal 212-i (i = 0, 1,... N) in FIG. 7 represents the signal of each bit of the code signal 212.

For example, the code signal 212-i (i = 0,1, ... n) is "1" if the switch of FIG. 7 is connected to _{V R} side, are connected to the GND side if '0'. Here, _{V R} is the reference voltage that gives the maximum voltage of the DAC 92.

  The DAC 92 in FIG. 7 is configured by a circuit using a resistor having a resistance value R as a unit. For example, 2R means twice the resistance value R. The output signal 214 is given by the following equation (7).

ここで、式（７）のＶ_ｉ（i＝０、１、…ｎ）は図７のスイッチで決まる電位であり、数８のように表すことができる。なお、ＧＮＤは接地電位であり数８では０（ゼロ）で表している。また、コード信号２１２−iは、下記の式（８）ではＣ_ｉと表現している。

Here, V _i (i = 0, 1,..., N) in Expression (7) is a potential determined by the switch of FIG. Note that GND is a ground potential, and is represented by 0 (zero) in Equation 8. The code signal 212-i is expressed as C _{i in} the following equation (8).

本実施形態のＤＡＣ９２の抵抗値Ｒ_ＤＡＣは、下記の式（９）で与えられるので、式（６）に基づいて抵抗９４の抵抗値Ｒ_１、抵抗９６の抵抗値Ｒ_２を適切に設定することが可能である。

Resistance _{R DAC} of DAC92 of this embodiment, the given by the following equation (9), suitably setting the resistance value _{R 1,} the resistance value _{R 2} of the resistor 96 of the resistor 94 on the basis of the equation (6) It is possible.

なお、式（７）、式（９）の“ｒ”は係数であり、ＤＡＣ９２の出力の中央のレベルを定めるのに使用される。例えば、ｎ＝２の場合にコード信号２１２として“１００ｂ”が入力されたときに、出力信号が１．３５Ｖとなるように係数“ｒ”が定められてもよい。

Note that “r” in the equations (7) and (9) is a coefficient, and is used to determine the central level of the output of the DAC 92. For example, when “100b” is input as the code signal 212 when n = 2, the coefficient “r” may be determined so that the output signal is 1.35V.

1.3.2.3. Signal Output Unit The signal output unit 70 receives the signal (DC signal) 120 output from the synchronous detection circuit 60, and performs processing by a low-pass filter configured by combining resistors 71 and 73 and capacitors 72 and 74, for example. Also good. These low-pass filters function as a pre-filter for the synchronous detection smoothing process and the subsequent process.

  The signal output unit 70 may include a variable gain amplifier including variable resistors 76 and 77 and an operational amplifier 75. This variable gain amplifier can be used as a digital gain.

  Then, the signal from the variable gain amplifier may be output from the signal output unit 70 as the output signal 294 through one switched capacitor filter 78.

  As described above, since the detection circuit of this embodiment includes only one switched capacitor filter 78, the layout area and power consumption can be reduced. Further, it is possible to change the gains of the differential amplifier circuit 30 and the non-inverting amplifier circuit 50 by the selection signal 210 and switch the detection sensitivity and detection range according to the application. Further, since the offset adjustment circuit 90 changes the offset adjustment width in response to these gain changes, an accurate output signal 294 corresponding to the physical quantity can be obtained.

2. Modified Examples Modified examples of the present embodiment will be described with reference to FIGS. In the detection circuit 10 </ b> A according to the modification, the offset adjustment circuit 90 is disposed at a location closer to the output signal 294. In addition, the same code | symbol is attached | subjected to the same element as FIGS. 1-7, and description is abbreviate | omitted.

  FIG. 8 is a block diagram of the detection circuit 10A of this modification. Adjustment of the signal level by the offset signal 126 can be performed at a location closer to the output signal 294. Therefore, a change in the output signal 294 due to the offset signal 126 can be easily predicted.

  The detection circuit 10A of the modification is different from the block diagram (see FIG. 1) of the detection circuit 10 of the first embodiment only in the synchronous detection circuit 60A of the post-stage circuit 14A and the signal output unit 70A. The offset adjustment circuit 90 itself is the same as in the first embodiment.

  FIG. 9 is a circuit diagram of the post-stage circuit 14A of this modification. The synchronous detection circuit 60A is different only in that the offset signal 126 is not input, and the other configuration is the same as that of the first embodiment, and thus the description thereof is omitted.

  The signal output unit 70 </ b> A includes an inverting amplifier circuit including resistors 82 and 84 and an operational amplifier 86 immediately before the switched capacitor filter 78. The offset signal 126 from the offset adjustment circuit 90 is input to this inverting amplifier circuit.

At this time, the resistance value of the resistor 82 and the resistor 84 as _{R 0,} by selecting the resistance value _{R 2} of the resistance value _{R 1,} resistor 96 of the resistor 94 on the basis of the equation (6), suitably corresponding to the selection signal 210 Can provide a wide offset adjustment range.

  As this modification shows, there is a degree of freedom in the arrangement of the offset adjustment circuit 90 in the subsequent circuit. Therefore, not only the configuration of the first embodiment but also a flexible design is possible.

3. Application example (physical quantity measuring device)
3.1. Configuration of Physical Quantity Measuring Device FIG. 10 is a configuration example of the physical quantity measuring device 1 including the detection circuit 10 of the present embodiment. The detection circuit 10 of the present embodiment functions as a detection part of the physical quantity measuring device 1. Here, the same elements as those in FIGS. 1 to 9 are denoted by the same reference numerals, and description thereof is omitted. Note that a detection circuit 10A according to a modification may be applied instead of the detection circuit 10 according to the present embodiment.

  The physical quantity measuring device 1 includes a detection circuit 10, a drive circuit 410, and vibrators 2 and 3 that are sensor elements. Here, the vibrators 2 and 3 may be integrated. For example, when the physical quantity measuring device 1 is a gyro sensor, Coriolis force acts on the sensor element. The Coriolis force is a force acting in a direction perpendicular to the vibration direction of the object and the rotation axis when the vibrating object is rotated, and the angular velocity can be detected based on the Coriolis force. At this time, the vibrators 2 and 3 are integrated, and include a drive electrode that inputs and outputs the excitation current 200 and the drive signal 208 from the drive circuit 410, and a detection electrode that outputs differential input signals 290 and 292.

3.2. Drive Circuit FIG. 11 is an example of a block diagram of a drive circuit 410 included in the physical quantity measuring device 1 (see FIG. 10). The same elements as those in FIG. 10 are denoted by the same reference numerals, and description thereof is omitted. The drive circuit 410 includes, for example, a current-voltage conversion circuit 420, a full-wave rectification circuit 430, a comparison adjustment circuit 440, and a drive signal generation circuit 450.

  The current-voltage conversion circuit 420 converts the excitation current 200 from the vibrator 2 into a voltage and outputs an output voltage 202. The amplitude of the output voltage 202 is proportional to the amplitude of the excitation current 200. The full-wave rectifier circuit 430 performs full-wave rectification on the output voltage 202 from the current-voltage conversion circuit 420 to obtain a voltage close to direct current, and outputs the output voltage 204. The comparison adjustment circuit 440 compares the output voltage 204 from the full-wave rectification circuit 430 with the voltage from the comparison voltage supply circuit 442, and outputs an output voltage 206 that is a signal reflecting the comparison result to the drive signal generation circuit 450. The drive signal generation circuit 450 generates the drive signal 208 based on the output voltage 202 from the current-voltage conversion circuit 420, and adjusts the amplitude of the drive signal 208 based on the output voltage 206.

  The physical quantity measuring device 1 can be realized by using such a drive circuit 410 and the detection circuit 10 of the present embodiment. Since the physical quantity measuring device 1 can switch the detection sensitivity and the detection range without increasing the layout area and power consumption of the detection circuit, it is small and can be used for various applications.

  The present invention is not limited to these exemplifications, and includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 ... Physical quantity measuring device, 2, 3 ... Vibrator, 10 ... Detection circuit, 10A ... Detection circuit, 12 ... Pre-stage circuit, 14 ... Subsequent circuit, 14A ... Subsequent circuit, 20-1, 20-2 ... Charge amplifier, 22 42, 72, 74, 172, 174 ... Capacitor, 24, 37A-37F, 38A-38F, 55A-55E, 44, 62, 64, 71, 73, 82, 84, 94, 96, 171, 173 ... Resistance , 26, 36, 52, 66, 75, 86, 175... Operational amplifier, 30... Differential amplifier circuit (differential amplifier), 40... High-pass filter (HPF), 50. Synchronous detection circuit, 60A ... synchronous detection circuit, 68, 69, 98 ... switch, 70 ... signal output unit, 70A ... signal output unit, 170 ... signal output unit, 32, 33, 34, 35, 54, 56, 7 , 77, 176, 177 ... variable resistance, 78, 178A, 178B ... switched capacitor filter, 90 ... offset adjustment circuit, 92 ... DAC, 110, 112, 116, 120, 214, 220 ... signal, 114 ... first signal 118 ... second signal, 126 ... offset signal, 200 ... excitation current, 202, 204, 206 ... output voltage, 208 ... drive signal, 210 ... selection signal, 212 ... code signal, 212-i ... code signal, 290 292 ... Differential input signal, 294 ... Output signal, 394A, 394B ... Output signal, 410 ... Drive circuit, 420 ... Current-voltage conversion circuit, 430 ... Full wave rectification circuit, 440 ... Comparison adjustment circuit, 442 ... Comparison voltage supply Circuit, 450... Drive signal generation circuit

Claims (10)

A detection circuit for detecting a physical quantity applied to the sensor element based on a differential input signal from the sensor element;
A differential amplifying circuit for amplifying a difference between the differential input signals and outputting as a first signal;
A non-inverting amplifier circuit that amplifies a signal based on the first signal and outputs the amplified signal as a second signal;
A second-stage circuit that converts the second signal into a DC signal and generates one output signal corresponding to the physical quantity,
At least one of the differential amplifier circuit and the non-inverting amplifier circuit is:
A detection circuit that changes the amplification factor based on an input selection signal. The detection circuit according to claim 1,
The differential amplifier circuit and the non-inverting amplifier circuit are:
A detection circuit that changes the amplification factor in conjunction with each other based on the one selection signal. The detection circuit according to claim 1,
The differential amplifier circuit is:
A detection circuit that changes an amplification factor by changing a resistance value of a resistance provided between an input resistor, a feedback resistor, and a non-inverting input terminal and a ground potential based on the selection signal. The detection circuit according to claim 3, wherein
The differential amplifier circuit is:
A detection circuit configured by combining a unit resistor with a resistor provided between an input resistor, a feedback resistor, and a non-inverting input terminal and a ground potential. The detection circuit according to any one of claims 1 to 4,
The non-inverting amplifier circuit is
A detection circuit that changes an amplification factor by changing a resistance value of a feedback resistor and a resistor provided between an inverting input terminal and a ground potential based on the selection signal. The detection circuit according to claim 5, wherein
The non-inverting amplifier circuit is
A detection circuit comprising a feedback resistor and a resistor provided between the inverting input terminal and the ground potential, in a circuit combining unit resistors. The detection circuit according to claim 1,
The latter circuit is
An offset adjustment circuit for adjusting a level of the second signal;
The offset adjustment circuit includes:
A detection circuit that changes an adjustment width based on the selection signal. The detection circuit according to claim 7, wherein
The offset adjustment circuit includes:
A detection circuit disposed immediately after the non-inverting amplifier circuit; The detection circuit according to any one of claims 7 to 8,
The offset adjustment circuit includes:
Including resistance,
A detection circuit that changes an adjustment width by changing a resistance value of the resistor based on the selection signal.   A physical quantity measuring device including the detection circuit according to claim 1.

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