JP2012170304A - Dc/dc voltage converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC/DC voltage converter which can adjust a voltage between a primary side voltage and a secondary side voltage to step-up and step-down even upon power running operation and regeneration operation while efficiency is improved and output power capacity is increased compared to a conventional DC/DC voltage converter and which secures miniaturization and weight saving.SOLUTION: The DC/DC voltage converter includes: a conversion main circuit 2 having field effect transistors FET1 to FET4 consisting of semiconductor materials of a wid band gap, an inductor L, an energy moving capacitor C0 and smoothing capacitors C1 and C2; and a control unit transferring power in both direction between the primary side and the secondary side and converting the DC voltage of step-up/down by turning on/off the FET1 to FET4 by a switching frequency which is not less than an upper limit of an audible frequency and controlling on-duty of the respective FETs so that a pair of the FETs in respective groups have a complementary relation where ON/OFF become opposite with the FET1 and FET4, and the FET2 and FET3 as the groups.

Description

  The present invention relates to a DC / DC voltage converter that converts a DC voltage into a DC voltage that is stepped up or stepped down while power is being exchanged bidirectionally between a primary side and a secondary side.

Conventionally, by using the switch-on and switch-off operations of series-connected semiconductor switch elements, the operation of accumulating energy in the inductor, discharging and charging the energy transfer capacitor, and discharging is combined to produce a voltage from DC to DC. An apparatus that performs conversion is used (Patent Document 1, Non-Patent Document 1).
This is a semiconductor switch element and a power device in which a rectifier element is connected in anti-parallel to this, and at the same time, only half of the power devices are turned on (switch-on for semiconductor switch element, forward bias for rectifier element). Thus, the withstand voltage of each power device can be set low. For this reason, the handling voltage of the DC / DC voltage converter can be set to a high voltage while suppressing an increase in conduction loss of each power device due to the high withstand voltage.

Here, a DC / DC voltage converter for converting the voltage after rectifying a commercial AC power supply (AC100V, AC200V), or a DC having an output power capacity of about 4 kW or more for converting a voltage in the range of about 100V to 1,000V. / DC voltage converters, IGBTs (Insulated Gate Bipolar Transistors) made of Si (silicon) as a power device, mainly as semiconductor devices, and Si as materials for rectifiers PIN diodes are used.
Such a DC / DC voltage conversion device may be configured in combination with an inverter that converts direct current into alternating current. For example, an electric drive system for a hybrid vehicle or an electric vehicle shown in FIG. Examples include a power conversion system for photovoltaic power generation and a power conversion system such as an air conditioner.

The electric drive system shown in FIG. 31 includes a battery 41 serving as a DC power source such as a nickel metal hydride battery, a lithium ion battery, or a fuel cell at the primary side terminals P1 and N1 of the DC / DC voltage converter 1, and the secondary side terminals P2 and N2. Are connected to inverters 51a and 51b. Further, the rotary electric machine 52a is connected to the inverter 51a, and the rotary electric machine 52b is connected to the inverter 51b. The rotating electrical machines 52a and 52b serve as a driving force source for the vehicle.
The DC / DC voltage conversion apparatus 1 converts the voltage of the battery 41 on the primary side into a DC / DC voltage and supplies it to the inverters 51a and 51b on the secondary side. The inverter 51a exchanges AC power with the rotary electric machine 52a, and the inverter 51b exchanges AC power with the rotary electric machine 52b.

In the photovoltaic power generation power conversion system of FIG. 32, the solar cell 42 is connected to the primary side terminals P1, N1 of the DC / DC voltage converter 1, and the inverter 51c is connected to the secondary side terminals P2, N2. The inverter 51c is connected to the commercial AC power supply 7 through the filter 6, and the DC / DC voltage converter 1 converts the generated voltage of the primary solar cell 42 into a DC / DC voltage to convert it to a secondary inverter 51c. To supply. The inverter 51c converts the DC voltage into a predetermined commercial AC voltage amplitude and frequency, and supplies it to the commercial power system.
The DC / DC voltage converter used in these systems is a power supply state (for example, the amount of light irradiation of a solar cell of a solar power generation system) or a load state (for example, rotation of a rotating electric machine of an electric drive system of a hybrid vehicle). The ratio of the voltage to be converted is adjusted according to the speed), and the output voltage is controlled.

JP-A-62-53171

Mitsubishi Electric Technical Report Vol. 61 1987 No. 2

However, the above-described conventional DC / DC voltage converter has the following three problems.
First, during a power running operation that sends power from the primary side to the secondary side, the secondary side voltage is adjusted to be lower than the primary side voltage, although a boosting operation that adjusts the secondary side voltage higher than the primary side voltage can be performed. The step-down operation is not possible, and the step-up / step-down operation cannot be performed simultaneously. Also, during the regenerative operation that recovers power from the secondary side to the primary side, although the step-down operation (step-up operation as seen from the primary side) that adjusts the primary side voltage lower than the secondary side voltage is possible, the primary side voltage The step-up operation to adjust higher than the secondary side voltage is impossible, and the step-up / step-down operation cannot be performed simultaneously.
This is the case when, for example, a rechargeable battery is connected to the primary side, an electric device that performs power generation operation is connected to the secondary side, and power is sent from the secondary side to the primary side to charge the battery. If the power generation voltage of the secondary-side electric device is not relatively high, the loss in charging the primary-side battery is increased, resulting in a disadvantage that the energy use efficiency is lowered.

Secondly, if a high output power capacity is to be obtained, there is a problem that the apparatus becomes large and heavy due to the loss of each element and the cooling means. A power device is mentioned as an element with a large generation loss. The generated losses of the semiconductor switch element and the rectifying element, which are power devices, have the following components, respectively.
In the semiconductor switch element, a conduction loss and a switching loss due to an ON resistance at the time of current conduction when the switch is on are generated. Switching loss is the voltage and conduction current across the semiconductor switch element during transitional rise and fall when switching from switch-off to switch-on (turn-on) and switching from switch-on to switch-off (turn-off). Is the time integral of the product of

Further, the rectifier element has a conduction loss due to an ON resistance during forward conduction and a reverse recovery loss during reverse recovery. The reverse recovery loss is the time integration of the product of the voltage across the rectifier element and the reverse recovery current in transitional rising and falling changes in the reverse recovery operation.
As described above, the switching loss of the semiconductor switching element and the reverse recovery loss of the rectifying element are generated at the timing of switching, and are proportional to the switching frequency. The increase in the switching frequency leads to the increase in the loss of the power device and the cooling means. Increase in size.
If the switching frequency is constant, the switching speed can be reduced to reduce the switching loss. However, this increases the rate of change of the current conducted to the power device. A large surge voltage is generated by the inductance component Ls parasitic to the conductor, and there is a concern that a high voltage is applied to the power device and the capacitor, resulting in damage.

Thirdly, in the volume and weight of the entire DC / DC voltage conversion device, a cooling heat sink and an inductor using a metal material occupy a large amount, so that there is a problem that the device becomes large in weight.
If the DC / DC voltage converter attempts to obtain a high output power capacity, the cooling heat sink is enlarged in order to mitigate the rise in the semiconductor junction temperature of the power device as the power device loss increases. There is a need.
In addition, as the output power capacity increases, the conduction current of the inductor also increases.On the other hand, the core of the inductor does not saturate even at a large current, and the core is increased to increase the cross-sectional area of the magnetic path in order to obtain a desired inductance value. In order to increase the size and suppress the increase in heat generation of the inductor winding, it is necessary to increase the cross-sectional area of the winding and reduce the resistance of the winding.
Since these cooling heat sinks and inductors use a large amount of metal material, they have a relatively high specific gravity compared to the resin material and have a great influence on the weight.

  The present invention has been made to solve the above-described conventional problems at the same time, and achieves improved efficiency and increased output power capacity as compared with conventional DC / DC voltage converters, while powering. A DC / DC voltage converter that can adjust between the primary side voltage and the secondary side voltage for both step-up and step-down both during operation and during regenerative operation. The purpose is to provide.

A DC / DC voltage conversion apparatus according to the present invention includes a conversion main circuit and a control unit, and performs DC voltage conversion of a step-up / down voltage by bidirectionally transferring power between a primary side and a secondary side. A DC voltage converter,
The main converter circuit is connected between the primary side positive side terminal and the negative side terminal and is connected between the primary side smoothing capacitor for smoothing the primary side voltage and the secondary side positive side terminal and the negative side terminal. The secondary side smoothing capacitor for smoothing the secondary side voltage, the energy transfer capacitor and inductor for storing and releasing energy, and the semiconductor unit capable of on / off switching operation and reverse conduction operation are provided with 2n (n Is an integer greater than or equal to 2) power modules connected in series with each other and connected between the positive terminal on the primary side and the negative terminal on the secondary side,
The negative side terminal on the primary side is connected to the positive side terminal on the secondary side,
The control unit divides 2n semiconductor units into two pairs of n pairs, and has a complementary relationship in which the on / off of the pair of semiconductor units constituting each pair is opposite to each other, and the inductor Control so that the alternating current component of the current flowing through the semiconductor unit is n times the switching frequency for controlling the on / off of the semiconductor unit,
The energy transfer capacitor includes a pair of semiconductors in each set, except for a semiconductor unit directly connected to a primary positive electrode terminal and a semiconductor unit directly connected to a secondary negative electrode terminal. Connect between the terminal closest to the primary positive terminal on the unit and the terminal closest to the secondary negative terminal on the unit,
The inductor is a pair of semiconductor units that are directly connected to each other, and is connected between the connection point and the negative electrode terminal on the primary side.

In the DC / DC voltage converter according to the present invention, as described above, in particular, the control unit divides 2n semiconductor units into two pairs of n pairs, and each pair constitutes a pair of semiconductors. The unit is controlled so that the on / off of the unit has a complementary relationship opposite to each other, and the alternating current component of the current flowing through the inductor is n times the switching frequency for controlling the on / off of the semiconductor unit.
Therefore, the frequency of the current flowing through the inductor increases to more than twice the switching frequency, and the AC component (ripple component) can be reduced or the required inductance can be reduced. Loss reduction, downsizing, and accompanying cooling heatsink downsizing are realized.
Also, the voltage between the secondary side voltage and the primary side voltage is boosted in both the power running operation that supplies power from the primary side to the secondary side and the regenerative operation that supplies power from the secondary side to the primary side. It is possible to convert the DC voltage to both the step-down and the step-down.

1 is an overall configuration diagram of a system of a DC / DC voltage converter according to the present invention. It is explanatory drawing which shows the flow of the electric power of the DC / DC voltage converter by this invention. It is a figure which shows the connection structure of the conversion main circuit of Embodiment 1 by this invention. It is a wave form diagram explaining operation | movement at the time of the power running pressure | voltage fall of Embodiment 1 by this invention (less than on-duty 50%). It is a wave form diagram explaining the operation | movement at the time of the power running pressure | voltage rise (on-duty 50% or more) of Embodiment 1 by this invention. It is a wave form diagram explaining the operation | movement at the time of the regeneration pressure | voltage fall (less than 50% of on-duty) of Embodiment 1 by this invention. It is a wave form diagram explaining the operation | movement at the time of the regeneration pressure | voltage rise (on-duty 50% or more) of Embodiment 1 by this invention. It is a figure which shows the frequency characteristic of the impedance of the capacitor of Embodiment 1 by this invention. It is a block diagram which shows the structure of the control unit and conversion main circuit of Embodiment 1 by this invention. It is a characteristic view which shows the relationship between on-duty and DC / DC voltage conversion ratio by this invention. It is a figure which shows the connection structure different from FIG. 3 of the conversion main circuit of Embodiment 1 by this invention. It is a figure which shows the connection structure different from FIG. 3, FIG. 11 of the conversion main circuit of Embodiment 1 by this invention. It is a block diagram which shows the structure of the control unit and conversion main circuit of Embodiment 2 by this invention. It is a block diagram which shows the detailed structure of the gate drive circuit of Embodiment 2 by this invention. It is a figure explaining the selection method of the switch-off circuit of Embodiment 2 by this invention. It is a wave form diagram explaining the turn-off operation | movement of the field effect transistor of Embodiment 2 by this invention. It is a figure which shows the connection structure of the conversion main circuit of Embodiment 3 by this invention. It is a block diagram which shows the structure of the control unit of Embodiment 3 by this invention. It is explanatory drawing which shows the relationship between the switching frequency of Embodiment 3 by this invention, and the emitted-heat amount of an inductor, a capacitor, and a semiconductor unit. It is a block diagram which shows the detailed structure of the frequency regulator of Embodiment 3 by this invention. It is a flowchart explaining the process of the selection process means of Embodiment 3 by this invention. It is a figure which shows the connection structure of the conversion main circuit of Embodiment 4 by this invention. It is a wave form diagram explaining the operation | movement at the time of the power running pressure | voltage fall of Embodiment 4 by this invention (less than on-duty 100/3%). It is a wave form diagram explaining the operation | movement at the time of the power running pressure | voltage fall of Embodiment 4 by this invention (on-duty 100/3% or more and less than 50%). It is a wave form diagram explaining the operation | movement at the time of the power running boost of Embodiment 4 by this invention (on-duty 50% or more and less than 100x (2/3)%). It is a wave form diagram explaining the operation | movement at the time of power boosting of Embodiment 4 by this invention (on-duty 100x (2/3)% or more). It is a wave form diagram explaining the operation | movement at the time of the regeneration pressure | voltage fall of Embodiment 4 by this invention (less than on-duty 100/3%). It is a wave form diagram explaining the operation | movement at the time of the regeneration pressure | voltage fall (on-duty 100/3% or more and less than 50%) of Embodiment 4 by this invention. It is a wave form diagram explaining the operation | movement at the time of the regeneration pressure | voltage rise of Embodiment 4 by this invention (on-duty 50% or more and less than 100x (2/3)%). It is a wave form diagram explaining the operation | movement at the time of the regeneration pressure | voltage rise (on-duty 100x (2/3)% or more) of Embodiment 4 by this invention. It is a block diagram of the electric drive system for motor vehicles using a DC / DC voltage converter. It is a block diagram of the power conversion system for solar power generation using a DC / DC voltage converter.

Embodiment 1 FIG.
Hereinafter, the DC / DC voltage converting apparatus according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a block diagram showing the overall configuration of the system according to the present embodiment. The DC / DC voltage conversion apparatus 1 includes a conversion main circuit 2 and a control unit 3. The DC / DC voltage converter 1 includes a positive side terminal P1 and a negative side terminal N1 on the primary side of the conversion main circuit 2 as connection terminals of the power path, and a positive side terminal P2 and a negative side terminal N2 on the secondary side. .
FIG. 2 schematically illustrates voltage conversion and power flow between the primary side and the secondary side of the DC / DC voltage conversion apparatus 1 according to this embodiment. A DC power supply 4 is connected to terminals P1 and N1 on the primary side of the DC / DC voltage converter 1, and an electric device 5 is connected to terminals P2 and N2 on the secondary side.
In FIG. 2, the DC power supply 4 is assumed to be a combination of a secondary battery such as a lithium ion battery, a nickel metal hydride battery, or a lead battery, as well as a power source such as a solar battery or a fuel cell combined with an electric double layer capacitor or a secondary battery. Is done. The electrical device 5 is a device that includes an electrical load and is combined with a power generation device or a power storage device.

The DC / DC voltage conversion device 1 can conduct current bidirectionally regardless of whether the primary terminal voltage V1 and the secondary terminal voltage V2 are V1 ≦ V2 or V1> V2. The voltage is converted so that power is exchanged between them.
Here, when the DC power supply 4 is in a discharging operation and the electric device 5 is in a power consuming operation, the DC / DC voltage conversion device 1 boosts the voltage to perform secondary operation from the primary side as shown in FIG. There are a case where power is sent in the direction toward the side and a case where power is sent after stepping down the voltage as shown in FIG.
Further, when the DC power supply 4 is in a charging operation and the electric device 5 is in a power supply operation, the DC / DC voltage conversion device 1 boosts the voltage (based on the primary side voltage V1 as shown in FIG. 2C). When the secondary side voltage V2 is V1 ≦ V2) and the electric power is sent from the secondary side to the primary side, as shown in FIG. 2 (d), the voltage is stepped down (based on the primary side voltage V1). The secondary side voltage V2 may have a relationship of V1> V2).
At this time, voltage conversion is performed by controlling on / off of a semiconductor switch element in a semiconductor unit (described later) provided in the conversion main circuit 2 in accordance with the gate drive signal 8 output from the control unit 3.

Here, the operation content of the DC / DC voltage converter 1 will be described with reference to FIGS. FIG. 3 is a diagram showing the circuit wiring of the conversion main circuit 2. Four semiconductor units are connected in series, and the voltage is boosted or stepped down from the primary side to the secondary side to supply power. Power is supplied by stepping down or boosting the voltage from the side to the primary side.
The conversion main circuit 2 includes a primary-side smoothing capacitor C1 that smoothes the primary-side terminal voltage V1, a secondary-side smoothing capacitor C2 that smoothes the secondary-side terminal voltage V2, and an inductor L that stores and discharges energy. And an energy transfer capacitor C0 and four semiconductor units.

  In the example of FIG. 3, the first to fourth semiconductor units employ field effect transistors FET4, FET3, FET2, and FET1 that include a parasitic diode therein. Note that these field effect transistors are formed of a wide band gap semiconductor whose band gap is larger than that of silicon. This will be described in detail later.

Next, details of the connection of the conversion main circuit 2 will be described.
Both terminals of the smoothing capacitor C1 are connected to the positive side terminal P1 and the negative side terminal N1 on the primary side of the conversion main circuit 2, and the negative side terminal N1 is also the positive side terminal P2 on the secondary side of the conversion main circuit 2 It is connected.
The positive terminal P1 is connected to one terminal of the smoothing capacitor C1 and the drain terminal of the FET1, and the other terminal of the smoothing capacitor C1 is connected to the negative terminal N1.
Further, both terminals of the smoothing capacitor C2 are connected to the positive side terminal P2 and the negative side terminal N2 on the secondary side of the conversion main circuit 2.

The source terminal of the FET 4 is the secondary negative terminal N2 of the conversion main circuit 2, the drain terminal is the source terminal of the FET 3, the drain terminal of the FET 3 is the source terminal of the FET 2, and the drain terminal of the FET 2 is the source terminal of the FET 1. , Each connected.
The energy transfer capacitor C0 has one terminal connected to the connection point between the FET 4 and the FET 3, and the other terminal connected to the connection point between the FET 2 and the FET 1.

  In this example, as mentioned in the explanation of the operation at the later stage, FET1 and FET4 and FET2 and FET3 are each a pair, and the pair of FETs forming each pair is on / off controlled so as to have a so-called complementary relationship. The Therefore, the energy transfer capacitor C0 is the primary in the pair of FET2 and FET3 except for the FET1 directly connected to the primary positive terminal P1 and the FET4 directly connected to the secondary negative terminal N2. It can also be said that it is connected between the drain terminal of the FET 2 that is the terminal closest to the positive electrode terminal P1 on the side and the source terminal of the FET 3 that is the terminal closest to the secondary negative electrode side terminal N2.

  As shown in FIG. 3, the inductor L has one terminal connected to the primary negative electrode side terminal N1 of the conversion main circuit 2, and the other terminal directly connected to each other, which is the pair of FETs described above. It is connected to the connection point between FET3 and FET2.

  From the control unit 3 not shown in FIG. 3, signals for controlling on / off of the field effect transistor as the gate drive signal 8 correspond to FET4, FET3, FET2, and FET1, respectively, Gate4, Gate3, Gate2, and Gate1. A signal is connected from the FET 4 to the gate electrode (G) of the FET 1 as a signal. The FET 4 performs a switching operation according to a voltage change of the Gate 4 signal, the FET 3 of the Gate 3 signal, the FET 2 of the Gate 2 signal, and the FET 1 of the Gate 1 signal.

Next, the operation of the conversion main circuit 2 will be described.
As described above, the DC / DC voltage conversion device 1 boosts the secondary side with respect to the primary side while transferring power bidirectionally from the primary side to the secondary side or from the secondary side to the primary side. Voltage conversion is performed so that both the operation and the step-down operation are performed. The step-up operation and the step-down operation are controlled by adjusting the timing of the on / off operation of the field effect transistor using Gate 4, Gate 3, Gate 2, and Gate 1 which are gate drive signals 8.
The voltage conversion control by the gate drive signal 8 will be described separately for the power running operation and the regenerative operation.

During power running:
1) When the on-duty is less than 50% and step-down operation:
An operation with an on-duty of less than 50% for stepping down the secondary side voltage V <b> 2 <the primary side voltage V <b> 1 during powering operation for supplying power from the primary side to the secondary side will be described.
However, the on-duty is a value for the Gate1 signal and the Gate2 signal, and the Gate3 signal and the Gate4 signal are complementary to the Gate2 signal and the Gate1 signal, respectively. Signal, on-duty of the Gate1 signal).

FIG. 4 shows a waveform when the on-duty of the gate drive signal is less than 50% in the step-down operation during the power running operation. 4A shows the gate drive signal, FIG. 4B shows the inductor current IL, and FIG. 4C shows the switching mode and its switching timing.
The inductor current IL has a positive polarity that flows through the inductor L from the connection terminal on the FET2 side to the connection terminal on the negative terminal N1 side.
In FIG. 4A, FET1 is turned on when the Gate1 signal is high, and FET2 is turned on when the Gate2 signal is high, and a current flows from the drain to the source.

The FET3 is turned on when the Gate3 signal is high, and the FET4 is turned on when the Gate4 signal is high. However, during powering operation, current flows from the source to the drain instead of the parasitic diodes inherent in the FET3 and FET4.
As a result, there is an advantage that the voltage drop in the part is small, the loss generated is reduced correspondingly, and the efficiency is improved. This advantage is an effect obtained when the field effect transistor FET is employed in the semiconductor unit in the control system according to the present invention.

Here, the Gate1 signal and the Gate4 signal are complementary signals whose logics of high and low are opposite to each other. When the Gate1 signal is high, the Gate4 signal is low, and when the Gate1 signal is low, the Gate4 signal is high. However, when switching between high and low logic, a blocking time (dead time) is provided so that both are not turned on at the same time due to a response delay of the switching operation of the field effect transistor.
Similarly, the Gate2 signal and the Gate3 signal are complementary signals in which high and low logics are opposite to each other, and the Gate1 signal and the Gate2 signal have a phase difference of 180 degrees. That is, the gate drive signal 8 has two pairs of signals as complementary signals, and the phase difference between them is equal.

  At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 4 are classified into three switching modes B, C, and D, and are switched in the order of B → D → C → D → B.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
The current flows in the path of the positive terminal P1, the FET 1, the energy transfer capacitor C0, the FET 3, the inductor L, and the negative terminal N1, and the energy is stored in the inductor L and the energy transfer capacitor C0. The electric device 5 is applied with the voltage across the smoothing capacitor C2 stored in the operation described later, and is supplied with energy from the smoothing capacitor C2.
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is about V1, and the potential of the FET3 side connection terminal is about the voltage VL of the FET3 side connection terminal of the inductor L. . The other side of the inductor L is connected to the negative terminal N1, and the potential is 0 (reference potential).
Therefore, the voltage VL = V1−Vc0 at the FET3 side connection terminal of the inductor L. Vc0 is the voltage across the energy transfer capacitor C0.

In switching mode D, FET3 and FET4 are on, FET1 and FET2 are off,
A current flows through the path of the negative terminal N2 → FET4 → FET3 → inductor L → positive terminal P2 → electric device 5 → negative terminal N2, and the energy accumulated in the inductor L is released.
Further, the negative electrode terminal N2 on the secondary side is −V2 with respect to the potential of the negative electrode terminal N1 on the primary side, which is the reference potential, and the current is conducted to the FET3 and FET4, and the voltage drop here is slight. Therefore, the voltage VL is approximately −V2. The difference between the voltage VL at the FET3 side connection terminal of the inductor L and the voltage at the positive side terminal P2 side connection terminal becomes negative at −V2, and the inductor current IL decreases in the direction of IL <0.

In switching mode C, FET2 and FET4 are on, FET1 and FET3 are off,
The current flows in the path of the negative terminal N2 → FET4 → energy transfer capacitor C0 → FET2 → inductor L → positive terminal P2 → electric device 5 → negative terminal N2, and the energy is stored in the inductor L. Released from the transfer capacitor C0. At the same time, a current also flows through the smoothing capacitor C2 to store energy.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is about VL, and the potential of the FET4 side connection terminal is about -V2. Therefore, the voltage VL at the FET3 side connection terminal of the inductor L becomes −V2 + Vc0.

  Here, since the on-duty of the Gate1 signal and the Gate2 signal is equal, the voltages VL in the switching modes B and C are equal in terms of time average, and a relationship of V1−Vc0 = −V2 + Vc0 is established. Therefore, the voltage Vc0 across the energy transfer capacitor C0 is (V1 + V2) / 2, which is ½ times the sum of the primary terminal voltage V1 and the secondary terminal voltage V2.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode B, VL = V1-Vc0 = (V1-V2) / 2,
In switching mode C, VL = −V2 + Vc0 = (V1−V2) / 2,
In switching mode D, VL = −V2
It becomes.
Accordingly, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1 and FET2 are expressed by the following relationship.

Switching mode B, C: L.ILrpl = ton. (V1-V2) / 2. (1a)
Switching mode D: L · ILrpl = −toff · (−V2) ·· (1b)
Here, L represents the inductance of the inductor L, and ILrpl represents the amplitude of the ripple current component (alternating current component) flowing through the inductor L.

  Since the left sides of Formula (1a) and Formula (1b) are equal, the following relationship is established.

  ton · (V1−V2) / 2 = toff · V2 (2)

  The above formula (2) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = ton / (ton + toff + toff) = (ton / T) / (1-ton / T) (3)
However, ton + toff = T / 2

In the above equation (3), the period T indicates a period in which the switching mode B → D → C → D → B is switched in order, and T / 2 = ton + toff.
Further, V2 / V1 on the left side of the expression (3) is a ratio between the primary side voltage V1 and the secondary side voltage V2 of the DC / DC voltage converter 1, and is a DC / DC voltage conversion ratio.
In the operation in which the on-duty of the gate drive signal shown in FIG. 4 is less than 50%, ton / T <0.5, and when applied to Expression (3), the DC / DC voltage conversion ratio is less than 1. . Therefore, the step-down operation is V2 <V1.

  From these, in switching modes B and C, the voltage VL = (V1−V2) / 2> 0 of the FET3 side connection terminal of the inductor L, and the voltage of the connection terminal of the inductor L on the negative side terminal N1 side is zero. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL increases in the positive direction.

As described above, in switching mode B → D → C → D → B,
In the switching modes B and C, the inductor current IL changes from the state of IL ≧ 0 further in the positive direction,
In the switching mode D, the inductor current IL changes toward the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

2) When the on-duty is 50% or more and the voltage is boosted:
Next, an operation with an on-duty of 50% or more for boosting the secondary side voltage V2 ≧ the primary side voltage V1 during the power running operation will be described.
FIG. 5 shows operation waveforms at that time, where (a) is a gate drive signal, (b) is an inductor current IL, and (c) is a switching mode and its switching timing.
5A, as in FIG. 4A, FET1 is turned on when the Gate1 signal is high, and FET2 is turned on when the Gate2 signal is high, and a current flows from the drain toward the source.
The FET3 is turned on when the Gate3 signal is high, and the FET4 is turned on when the Gate4 signal is high. However, during powering operation, current flows from the source to the drain instead of the parasitic diodes inherent in the FET3 and FET4.

  The Gate1 signal and the Gate4 signal, and the Gate2 signal and the Gate3 signal are complementary signals, respectively, and when the logic is switched between high and low, a blocking time (dead) is set so that both are not turned on simultaneously due to a response delay of the switching operation of the field effect transistor. Time). The phase difference between the Gate1 signal and the Gate2 signal is 180 degrees.

  At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 4 are classified into three types of switching modes A, B, and C, and are switched in the order of A → B → A → C → A.

First, in switching mode A, FET1 and FET2 are on, FET3 and FET4 are off,
The current flows in the path of the positive terminal P1, the FET1, the FET2, the inductor L, and the negative terminal N1, and energy is stored in the inductor L.
Since the voltage VL becomes approximately V1 when current flows between the FET1 and FET2, the difference between the voltage VL at the FET2 side connection terminal of the inductor L and the voltage at the connection terminal on the negative side terminal N1 side is (V1-0). ) And becomes positive, and the inductor current IL increases in the positive direction.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
The current flows through the path of the positive terminal P1, the FET 1, the energy transfer capacitor C0, the FET 3, the inductor L, and the negative terminal N1, and the energy is stored in the energy transfer capacitor C0. The electric device 5 is applied with the voltage across the smoothing capacitor C2 stored in the operation described later, and is supplied with energy from the smoothing capacitor C2.
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately V1, and the potential of the FET3 side connection terminal is approximately VL.
Accordingly, the voltage VL = V1−Vc0 at the FET3 side connection terminal of the inductor L

In switching mode C, FET2 and FET4 are on, FET1 and FET3 are off, and the current flows from the secondary negative terminal N2 → FET4 → energy transfer capacitor C0 → FET2 → inductor L → positive terminal P2 → electricity. The energy flows from the device 5 to the negative terminal N2 and is discharged from the inductor L and the energy transfer capacitor C0. At the same time, a current also flows through the smoothing capacitor C2 to store energy.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is approximately VL, and the potential of the FET4 side connection terminal is approximately -V2.
Therefore, the voltage VL at the FET3 side connection terminal of the inductor L becomes −V2 + Vc0.

  Similarly to the above-described operation in which the on-duty is less than 50%, since the on-duty of the Gate1 signal and the Gate2 signal is equal, the voltages VL in the switching modes B and C are equal in terms of time average V1−Vc0 = −V2 + Vc0 It becomes a relationship. Therefore, the voltage Vc0 across the energy transfer capacitor C0 is (V1 + V2) / 2, which is ½ times the sum of the primary terminal voltage V1 and the secondary terminal voltage V2.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode A, VL = V1,
In switching mode B, VL = V1-Vc0 = (V1-V2) / 2,
In the switching mode C, VL = −V2 + Vc0 = (V1−V2) / 2
It becomes.
Accordingly, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1 and FET2 are expressed by the following relationship.

Switching mode A: L.ILrpl = V1. (Ton-toff) / 2 .. (4a)
Switching modes B and C: L · ILrpl = −toff · (V1−V2) / 2
.. (4b)

  Since the left sides of the equations (4a) and (4b) are equal, the following relationship is established.

  V1 · (ton-toff) / 2 = −toff · (V1−V2) / 2 (5)

  The above equation (5) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = ton / toff = (ton / T) / (1-ton / T) (6)
However, ton + toff = T

In the above equation (6), the period T indicates a period in which the switching mode A → B → A → C → A is switched in order, and T = ton + toff.
Equation (6) is equivalent to Equation (3), that is, whether the on-duty is less than 50% or more than 50%, DC / DC continuously according to the change in on-duty. The voltage conversion ratio is adjusted.
In the operation in which the on-duty of the gate drive signal shown in FIG. 5 is 50% or more, ton / T ≧ 0.5, and when applied to Equation (6), the DC / DC voltage conversion ratio is 1 or more. Become. Therefore, the boosting operation is V2 ≧ V1.

  From these, in switching modes B and C, the voltage VL = (V1−V2) / 2 <0 of the FET3 side connection terminal of the inductor L, and the voltage of the negative side terminal N1 side connection terminal of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL decreases in the negative direction.

As described above, in the switching mode A → B → A → C → A,
In switching mode A, the inductor current IL changes so as to further increase in the positive direction from the state of IL ≧ 0,
In the switching modes B and C, the inductor current IL changes toward the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, even when the on-duty of the gate drive signal is 50% or more, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

During regenerative operation:
1) When the on-duty is less than 50% and step-down operation:
An operation with an on-duty of less than 50% for reducing the primary side voltage V1> the secondary side voltage V2 during the regenerative operation for supplying power from the secondary side to the primary side will be described. It should be noted that, based on the secondary side voltage V2, the boost is in the relationship of (V1 / V2)> 1.
In the step-down operation during the regenerative operation, as shown in FIG. 2 (d), the electric device 5 connected to the secondary side of the DC / DC voltage converter 1 is generated in the relationship of the secondary side voltage V2 <the primary side voltage V1. DC / DC voltage conversion from V2 to V1 is performed and the DC power supply 4 recovers the power to be generated.
FIG. 6 illustrates a waveform in which the on-duty of the gate drive signal is less than 50% during the step-down operation. 6A shows the gate drive signal, FIG. 6B shows the inductor current IL, and FIG. 6C shows the switching mode and the switching timing thereof.

6A, when the Gate3 signal is high, the FET3 is turned on, and when the Gate4 signal is high, the FET4 is turned on, and a current flows from the drain toward the source. The FET1 is turned on when the Gate1 signal is high, and the FET2 is turned on when the Gate2 signal is high. However, during the regenerative operation, a current flows from the source to the drain instead of the parasitic diodes inherent in the FET1 and FET2.
The gate drive signal of FIG. 6A, the switching mode of FIG. 6C, and the switching timing thereof are shown in FIG. 4A when the on-duty of the gate drive signal is less than 50% in the step-down operation during the power running operation. This is the same as FIG.
That is, the gate drive signal has the same waveform during the power running operation and the regenerative operation, and the combination of high and low logic of the gate drive signals from Gate 1 to Gate 4 is in the order of switching mode B → D → C → D → B. Switch.

In switching mode D, FET3 and FET4 are on, FET1 and FET2 are off,
The current flows through the path of the positive terminal P 2 → the inductor L → the FET 3 → the FET 4 → the negative terminal N 2, and energy is stored in the inductor L. From the direction of current conduction, the polarity of the inductor current IL is negative.
In addition, since FET3 and FET4 are turned on and current is conducted, the voltage VL is approximately -V2.
Therefore, the difference between the voltage at the FET3 side connection terminal of the inductor L and the voltage at the connection terminal on the positive side terminal P2 side becomes negative at (−V2-0), and the inductor current IL is negative from the state where IL <0. To increase.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
The current flows in the path of inductor L → FET 3 → energy transfer capacitor C 0 → FET 1 → positive terminal P 1 → DC power supply 4 → negative terminal N 1, and energy is discharged from inductor L and energy transfer capacitor C 0. Further, the power generation voltage V2 of the electric device 5 is applied to the smoothing capacitor C2, and energy is supplied to the smoothing capacitor C2.
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately V1, and the potential of the FET3 side connection terminal is approximately VL.
Accordingly, the voltage VL = V1−Vc0 at the FET3 side connection terminal of the inductor L

In switching mode C, FET2 and FET4 are on, FET1 and FET3 are off,
The current flows through the path of the positive terminal P2, the inductor L, the FET 2, the energy transfer capacitor C0, the FET 4, and the negative terminal N2, and the energy is discharged from the inductor L and stored in the energy transfer capacitor C0.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is approximately VL, and the potential of the FET4 side connection terminal is approximately -V2.
Therefore, the voltage VL at the FET3 side connection terminal of the inductor L becomes −V2 + Vc0.

Here, since the on-duties of the Gate3 signal and the Gate4 signal are equal, the voltages VL in the switching modes B and C are equal in terms of time average, and the relationship is V1−Vc0 = −V2 + Vc0.
Accordingly, the voltage Vc0 across the energy transfer capacitor C0 becomes (V1 + V2) / 2, which is ½ times the sum of the primary terminal voltage V1 and the secondary terminal voltage V2, as in the power running operation.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode B, VL = V1-Vc0 = (V1-V2) / 2,
In switching mode C, VL = −V2 + Vc0 = (V1−V2) / 2,
In switching mode D, VL = −V2
It becomes.
Accordingly, the potential difference between both ends of the inductor L and the switch-on time ton and the switch-off time toff of the FET1 and FET2 are expressed by a formula (1a) indicating a relationship when the on-duty of the gate drive signal is less than 50% in the step-down operation during the power running operation. , (1b).
For this reason, the relationship of Formula (2) and Formula (3) is similarly established.
That is, the voltage conversion ratio (V2 / V1) of the DC / DC voltage conversion apparatus 1 is expressed by Expression (3).

In the operation in which the on-duty of the gate drive signal in FIG. 6 is less than 50%, ton / T <0.5, and the DC / DC voltage conversion ratio is less than 1 when applied to Equation (3). Therefore, the step-down operation is V2 <V1.
That is, the primary side terminal voltage V1 is converted to a voltage higher than the secondary side terminal voltage V2.

  From these, in the switching modes B and C, the voltage VL = (V1−V2) / 2> 0 of the FET3 side connection terminal of the inductor L, and the voltage of the connection terminal of the inductor L on the negative side terminal N1 side is zero. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL decreases in the positive direction. That is, IL changes from the state where the inductor current IL <0 during the regenerative operation toward the state where IL ≧ 0.

As described above, when switching mode B → D → C → D → B,
In switching modes B and C, the inductor current IL changes toward a state where IL ≧ 0,
In the switching mode D, the inductor current IL changes so as to further increase in the negative direction from the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, as in the power running operation, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

2) When the on-duty is 50% or more and the voltage is boosted:
Next, an operation with an on-duty of 50% or more for boosting the primary side voltage V1 ≦ secondary side voltage V2 during the regenerative operation for supplying power from the secondary side to the primary side will be described. Note that, based on the secondary side voltage V2, the step-down is in the relationship of (V1 / V2) ≦ 1.
FIG. 7 shows operation waveforms at that time, where (a) is a gate drive signal, (b) is an inductor current IL, and (c) is a switching mode and its switching timing.
In FIG. 7A, the FET 3 is turned on when the Gate 3 signal is high, and the FET 4 is turned on when the Gate 4 signal is high, and a current flows from the drain to the source.
The FET1 is turned on when the Gate1 signal is high, and the FET2 is turned on when the Gate2 signal is high. However, during the regenerative operation, a current flows from the source to the drain instead of the parasitic diodes inherent in the FET1 and FET2.

The gate drive signal in FIG. 7A, the switching mode in FIG. 7C, and the switching timing thereof are shown in FIG. 5A when the on-duty of the gate drive signal is 50% or more in the boosting operation during the power running operation. This is the same as FIG.
That is, the gate drive signal has the same waveform during the power running operation and the regenerative operation, and the combination of high and low logic of the gate drive signals from Gate 1 to Gate 4 is in the order of switching modes A → B → A → C → A. Switch.

First, in switching mode C, FET2 and FET4 are on, FET1 and FET3 are off,
The current flows through the path of the positive terminal P2, the inductor L, the FET 2, the energy transfer capacitor C0, the FET 4, and the negative terminal N2, and the energy is stored in the inductor L and the energy transfer capacitor C0.
Since FET2 and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0 is approximately VL, and the potential of the FET4 side connection terminal is approximately -V2.
Therefore, the voltage VL of the inductor L on the FET2 side connection terminal is VL = −V2 + Vc0.

In switching mode B, FET1 and FET3 are on, FET2 and FET4 are off,
The current flows through the path of inductor L → FET 3 → energy transfer capacitor C 0 → FET 1 → positive terminal P 1 → DC power supply 4 → negative terminal N 1, energy is stored in inductor L, and discharged from energy transfer capacitor C 0. The
Since FET1 and FET3 are turned on and current is conducted, the potential of the FET1 side connection terminal of the energy transfer capacitor C0 is approximately V1, and the potential of the FET3 side connection terminal is approximately VL.
Accordingly, the voltage VL = V1−Vc0 at the FET3 side connection terminal of the inductor L

In switching mode A, FET1 and FET2 are on, FET3 and FET4 are off,
A current flows through a path of inductor L → FET 2 → FET 1 → positive terminal P 1 → DC power supply 4 → negative terminal N 1, and energy is discharged from the inductor L.
Since the voltage VL becomes approximately V1 when current flows between the FET1 and FET2, the difference between the voltage VL at the FET2 side connection terminal of the inductor L and the voltage at the connection terminal on the negative side terminal N1 side is (V1-0). ) = V1 and becomes positive, and the inductor current IL changes from the state of IL <0 toward the positive direction.

In addition, since the on-duty of the Gate3 signal and the Gate4 signal is the same as in the operation in which the on-duty is less than 50% during the regenerative operation described above, the voltages VL in the switching modes B and C are equal in time average. , V1−Vc0 = −V2 + Vc0.
Therefore, as in the step-down operation, the voltage Vc0 across the energy transfer capacitor C0 is (V1 + V2) / 2, which is ½ times the sum of the primary terminal voltage V1 and the secondary terminal voltage V2.

To summarize the above, the voltage VL at the FET3 side connection terminal of the inductor L is:
In switching mode A, VL = V1,
In switching mode B, VL = V1-Vc0 = (V1-V2) / 2,
In the switching mode C, VL = −V2 + Vc0 = (V1−V2) / 2
It becomes.
Accordingly, the relationship between the potential difference between both ends of the inductor L and the switch-on time ton and switch-off time toff of the FET1 and FET2 is an expression showing the relationship when the on-duty of the gate drive signal is 50% or more in the boosting operation during the power running operation. The same as (4a) and (4b). For this reason, the relationship of Formula (5) and Formula (6) is formed similarly.
That is, the voltage conversion ratio (V2 / V1) of the DC / DC voltage conversion apparatus 1 is expressed by Expression (6).

  In the operation in which the on-duty of the gate drive signal in FIG. 7 is 50% or more, ton / T ≧ 0.5, and the DC / DC voltage conversion ratio is 1 or more when applied to Equation (6). Therefore, V2 ≧ V1. That is, the secondary side terminal voltage V2 is boosted to a voltage higher than the primary side terminal voltage V1.

  From these, in switching modes B and C, the voltage VL = (V1−V2) / 2 <0 of the FET3 side connection terminal of the inductor L, and the voltage of the negative side terminal N1 side connection terminal of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL increases in the negative direction. That is, it changes so as to increase further in the negative direction from the state of the inductor current IL <0 during the regenerative operation.

As described above, when switching mode A → B → A → C → A,
In switching mode A, the inductor current IL changes toward a state where IL ≧ 0,
In the switching modes B and C, the inductor current IL changes so as to further increase in the negative direction from the state of IL <0.
From this, increase and decrease of the inductor current IL are repeated twice in the T / 2 period over the switching period T of the field effect transistor. That is, even when the on-duty of the gate drive signal is 50% or more, an alternating current having a frequency twice that of the switching frequency of the field effect transistor is conducted to the inductor L.

As described above, the AC current of twice the frequency is conducted to the inductor L with respect to the switching frequency of the field effect transistor in both the power running operation and the regenerative operation.
And the field effect transistor of the DC / DC voltage converter 1 of this invention operate | moves with the switching frequency of 20 kHz or more which is the upper limit of an audio frequency.
In this embodiment, the switching frequency is set to be higher than the upper limit of the audible frequency, as will be described in detail later. By adopting a so-called wide bandgap semiconductor for the switching element, this high switching frequency is set. This is because it is possible to obtain the advantages that it is possible to reliably prevent the generation of annoying noise from the inductor and capacitor, which has been a problem with this type of device.

  By the way, in the conventional DC / DC voltage converter, since the IGBT and PIN diode which used Si for the semiconductor unit are used, there exists a restriction | limiting that the upper limit of practical semiconductor junction temperature becomes about 175 degreeC. When this upper limit temperature is exceeded, the semiconductor unit made of Si is damaged due to changes in physical properties such as an increase in leakage current. Therefore, the output power capacity of the DC / DC voltage converter must be set so as to be less than the upper limit of 175 ° C. even if the semiconductor junction temperature of the semiconductor unit rises. Here, the semiconductor junction temperature of the semiconductor unit follows a balance between heat generation characteristics due to generation loss of the semiconductor unit and heat dissipation characteristics determined by the cooling structure for cooling the semiconductor unit and the temperature of the refrigerant.

On the other hand, since FET1, FET2, FET3, and FET4 in the DC / DC voltage converter of the present invention use field effect transistors made of a semiconductor material having a wide bandgap that is larger than that of Si, DC The output power capacity that can be handled by the DC / DC voltage converter 1 is much larger than that based on the prior art, and the power density is improved.
This is because the upper limit of the semiconductor junction temperature of the wide band gap material is raised above the upper limit of the semiconductor junction temperature of the Si material. The reason for this will be described.

  Si often used as a semiconductor material in the prior art has a band gap value of 1.12 eV. On the other hand, typical materials generally referred to as wide band gaps include silicon carbide 4H—SiC (band gap: 3.25 eV), gallium nitride GaN (band gap: 3.39 eV), diamond (band Gap: 5.47 eV).

  When comparing the Si material and the wide band gap material, the larger the band gap (the wider) the band structure representing the state of electrons in the crystal, the more the electrons transition from the valence band to the conduction band. Energy is required, but in the case of a wide band gap, electrons cannot jump to the conduction band unless they are excited by giving more thermal energy than Si. If this property is considered to apply to the leakage current of the PN junction of the power device, the wide band gap semiconductor material is much higher than the temperature at which the leakage current starts flowing in the Si material when the semiconductor unit is off. Finally, the leakage current starts to flow. In other words, the upper limit of the semiconductor junction temperature at which a semiconductor unit made of a wide band gap material operates normally as a semiconductor is higher than that of a semiconductor unit made of Si material. For example, if the band gap value is 2.0 eV or more, the band gap value is about 80% or more larger than the Si band gap value 1.12 eV, so that the difference in the upper limit of the semiconductor junction temperature appears significantly. .

When the power handled by the DC / DC voltage converter is increased, the loss generated in the semiconductor unit increases and the semiconductor junction temperature rises. However, by using a semiconductor unit made of a material having a band gap value of 2.0 eV or higher, Deterioration is suppressed to a small extent, and heat resistance is improved.
Therefore, the DC / DC voltage conversion apparatus 1 according to the present invention can be operated until the temperature of the semiconductor junction becomes higher than that in the case where a semiconductor unit made of a conventional Si material is used. Expands and power density is improved.

  On the other hand, the cooling performance required by the cooling heat sink can be lowered by utilizing the fact that the upper limit of the semiconductor junction temperature is increased. If the cooling performance is lowered, the cooling heat sink is also reduced in size, so that a small and lightweight DC / DC voltage converter can be realized even with a high output capacity.

  Further, in order to switch the field effect transistor, which is a semiconductor switching element, at an audible frequency upper limit of 20 kHz or more, an alternating current having a frequency of 40 kHz or more is conducted to the inductor L, and the volume and weight of the inductor L are further increased than the conventional one. Can be reduced. Hereinafter, this point will be described.

  As described above for the operation of the conversion main circuit 2, the ripple current component of the inductor L is generated by periodically switching the polarity of the potential difference between the terminals of the winding of the inductor L, and the polarity of the potential difference between the terminals. Is linked to the switching operation of the semiconductor switch element. That is, the polarity of the potential difference between the terminals of the winding is switched in a shorter cycle as the semiconductor switch element is switched at a higher frequency. This is because the increase / decrease → increase → decrease of the ripple current component of the inductor L is repeated in a short time, so that the increase amount and decrease amount of the inductor current IL in this repetition decrease. The amplitude of the ripple current component is reduced.

For this reason, the alternating current conducted to the inductor L is reduced, and the total amount of current in which the direct current and the alternating current are superimposed is also reduced.
Therefore, since the amplitude of the ripple current component changes depending on the inductance value of the inductor L, instead of reducing the amplitude of the alternating current as it is, the inductance value is lowered to reduce the cross-sectional area of the magnetic path of the inductor, and the inductor L Can be made smaller and lighter than before.
At this time, if the amplitude of the ripple current component is ILrpl, the inductance value is Lc, the potential difference between terminals of the inductor winding is ΔV, and the switching period of the semiconductor switch element is T, the period of the ripple current component is T / 2. Expressed in relationship.

  Lc · ILrpl = ΔV · (T / 4) (7)

Now, when the switching frequency of the semiconductor switch element is 5 kHz (T = 200 μs), the ripple current component frequency of the inductor L is 10 kHz, the terminal-to-terminal potential difference ΔV = 350 V, and the inductance value Lc = 350 μH, the ripple is obtained from the equation (7). The current component amplitude ILrpl = 50A.
Here, when the switching frequency is increased to 20 kHz (T = 50 μs), which is the upper limit of the audible frequency, when the ripple current component frequency of the inductor L is 40 kHz and the potential difference between terminals ΔV = 350 V, Lc · ILrpl = 4375 from Equation (7). × 10 ^ -6.

If the inductance value Lc = 350 μH is maintained, ILrpl = 12.5A, which is 25% lower than the above-mentioned 50A. However, if ILrpl = 50A is maintained, L = 87.5 μH and the inductance value Lc is Reduce to 25%.
Reducing the inductance value Lc leads to lowering the number of turns of the inductor winding and the effective cross-sectional area of the inductor core, and the volume of the winding part and the core part is reduced, that is, the volume of the inductor L is reduced.

  Copper is mainly used for the winding of the inductor, and an electromagnetic steel plate or soft magnetic material mainly composed of iron, ferrite, or an alloy of iron, aluminum, or nickel is used for the core. The specific gravity of these metals is 8.95 g / cc for copper and 7.87 g / cc for iron, which is several times higher than the specific gravity of resin (plastic). Among the constituent materials, the DC / DC voltage converter 1 of the present invention that makes the inductor L, which is a metal-based structure, small and light, can be realized with excellent light weight even with high output capacity.

By the way, the DC / DC voltage conversion apparatus 1 of the present invention handles voltages in the range of about 100 V to 1,000 V, switches at an audio frequency upper limit of 20 kHz or higher, and has high output power capacity, small size, and light weight. Required.
However, the DC / DC voltage converter of the prior art uses a semiconductor switch element made of Si material, and it is extremely difficult to perform a switching operation at an audio frequency upper limit of 20 kHz or more.
Even if the semiconductor switch element is made of a Si material, if it is a field effect transistor, it is a unipolar device and has a short operation reaction time, and switching operation at a frequency higher than the upper limit of the audible frequency becomes possible. . However, only a semiconductor switch element with a withstand voltage of about 100 V or less has been put to practical use in order to meet the high output power capacity required for a DC / DC voltage converter and to have a low loss. Therefore, the field effect transistor made of Si cannot be used for the application of the DC / DC voltage converter 1 of the present invention.

  In addition, when an IGBT is used as a semiconductor switch element made of Si as in the past, it is suitable as an element withstand voltage for handling a voltage range of 100 V to 1,000 V, but at a frequency higher than the upper limit of the audible frequency. It could not be used for switching operation. In an IGBT having an element withstand voltage that matches the above voltage range, the drift layer in the device structure becomes thick in order to obtain the withstand voltage. Since the IGBT is a bipolar device, it takes time to eliminate minority carriers in the thick drift layer during the turn-off operation, and has a disadvantage that the operation reaction time is long. Due to the length of this operation reaction time, it is difficult to apply to a switching operation at a high frequency above the upper limit of the audible frequency.

On the other hand, the DC / DC voltage converter 1 of the present invention uses a field effect transistor or a rectifier diode using a semiconductor material having a wide band gap of, for example, 2.0 eV or more as a semiconductor unit. It can handle voltages in the range of about 100 V to 1,000 V, and can perform switching operation at 20 kHz or more of the upper limit of the audible frequency, and can be realized in a small size and light weight with a high output power capacity.
This is based on the characteristics that a wide band gap semiconductor has a higher breakdown field strength and a higher saturation drift velocity than a semiconductor made of Si.
In a semiconductor made of Si, the dielectric breakdown strength is 0.3 MV / cm and the saturation drift velocity is 1 × 10 7 cm / s, whereas in a wide band gap semiconductor, the dielectric breakdown strength is 4H-SiC. Is 3 MV / cm, GaN is 3 MV / cm, diamond is 2 MV / cm, saturation drift velocity is 4 × 10 ^ 7 cm / s for 4H-SiC, 2.4 × 10 ^ 7 cm / s for GaN, diamond is 2.5 × 10 ^ 7 cm / s.

  As the dielectric breakdown strength is higher, the thickness of the layer applied to the drift region can be reduced in the structure of the semiconductor unit when obtaining a withstand voltage necessary for the semiconductor unit. In addition, since the saturation drift speed is high, electrons can move quickly in the drift region. That is, as a feature of the wide band gap semiconductor, it is possible to perform a switching operation at a high frequency higher than the upper limit of the audible frequency because the electrons move quickly through the thin drift layer and the operation reaction time is short.

  Further, the DC / DC voltage converter 1 of the present invention switches the semiconductor switch element at a frequency higher than the upper limit of the audible frequency, and the frequency of the ripple current component of the inductor L becomes twice the switching frequency. Further, it is possible to eliminate the generation of annoying audible noise, which is remarkable with the inductor L, the energy transfer capacitor C0, and the smoothing capacitors C1 and C2. Therefore, conventionally, there is no need to take measures to bring about adverse effects such as increasing the cost, increasing the volume, and increasing the weight, such as attaching a vibration absorbing member for suppressing noise propagation to the outside or adopting a low magnetostrictive core material for the inductor. May be.

In addition, since the DC / DC voltage converter 1 of the present invention switches the semiconductor switch element at a frequency higher than that of the conventional one, the capacitance required for the energy transfer capacitor C0 and the smoothing capacitors C1 and C2 is increased. In addition, it is possible to reduce the loss generated and to make the device compact and lightweight.
This will be described with reference to FIG. FIG. 8 is a diagram showing the impedance characteristics of a capacitor with the horizontal axis representing the logarithmic value of the frequency and the vertical axis representing the logarithmic value of the impedance.

  In the figure, the alternate long and short dash line indicates the characteristics of the capacitance Ca, and the solid line indicates the characteristics of the capacitance Cb. The capacitance relationship is Cb <Ca, and Ca has a larger capacitance. The impedance decreases as the frequency increases from a low frequency range. This is because the capacitance component of the capacitor element is a main component that determines the impedance in a low frequency range. As the frequency increases, the impedance becomes a minimum value at a certain frequency, and when the frequency further increases beyond the frequency that becomes the minimum value, the slope is inverted and the impedance increases. This is because at a high frequency, the inductive component of the lead portion that becomes the current path of the capacitor element becomes the main component that determines the impedance.

Here, in the low frequency range where the capacitance component of the capacitor element is the main component of the impedance, the capacitance of the capacitor Cb having a smaller capacitance is larger than the capacitance of the capacitor Ca. On the other hand, in a high frequency range where the inductive component is the main component of impedance, the capacitance Ca having a larger capacitance has a larger impedance than the capacitance Cb.
Now, let the impedance be ZaΩ when the semiconductor switch element is switched at 10 kHz in the conventional DC / DC voltage converter and the frequency of the alternating current flowing in the capacitor is the same frequency. In the DC / DC voltage converter according to the present invention, if the switching is performed within the range up to the frequency where the impedance characteristic of the capacitor becomes a minimum value and the upper limit of the audible frequency is 20 kHz, the impedance is higher than the case of switching at 10 kHz as in the past. To reduce.

Therefore, even if the capacitance is reduced from Ca to Cb, if Cb is selected so that the impedance Zb at 20 kHz satisfies Zb <Za, the capacitor can be reduced in size and weight by reducing the capacitance. Impedance can be reduced at the same time.
Further, since the impedance is reduced from Za to Zb, the loss that occurs when an alternating current flows through the capacitor is reduced, which is preferable because the temperature rise due to heat generation of the capacitor is mitigated. The temperature rise due to heat generation promotes the deterioration of the resin material used for the capacitor, and thus becomes a factor for shortening the durability of the DC / DC voltage converter using the capacitor. The DC / DC voltage converter according to the present invention can achieve the effect of facilitating the reduction in size and weight of the capacitor and the securing of durability reliability.

Next, the operation of the control unit 3 will be described with reference to FIG. FIG. 9 is a block diagram illustrating the configuration of the control unit 3 and the conversion main circuit 2.
The control unit 3 internally inputs the primary side terminal voltage V1, the secondary side terminal voltage V2, the inductor current IL, and the DC / DC voltage conversion ratio instruction from an external device (not shown) from the conversion main circuit 2. The control calculation is performed in this manner, and a gate drive signal 8 for controlling the switching operation of FET4, FET3, FET2, and FET1 in the conversion main circuit 2 is output.

  The primary side terminal voltage V 1, secondary side terminal voltage V 2, inductor current IL, and DC / DC voltage conversion ratio instruction that are input to the control unit 3 are input to the conversion control unit 10. The conversion control unit 10 calculates the voltage conversion ratio of the conversion main circuit 2 that is actually operating from the ratio of the secondary terminal voltage V2 and the primary terminal voltage V1, and converts the DC / DC voltage from an external device. A negative feedback control calculation using a known proportional integration (PI) calculation or the like is performed in comparison with the ratio instruction to calculate a target amount Lduty of the on-duty of FET1 and FET2. Lduty is a range in which the lower limit of the duty is 0% and the upper limit is 100%. For example, Lduty = 0.0 when 0% and Lduty = 1.0 when 100%. Represent.

The inductor current IL is used as an input amount of a negative feedback control calculation performed by matching the inductor current target amount IL_ref and the inductor current IL as a control calculation loop included in the negative feedback control calculation loop having the voltage conversion ratio. It is done.
By applying the negative feedback minor control calculation of the inductor current, the control band of the negative feedback control system of the DC / DC voltage conversion ratio on the outer periphery can be set to a high frequency, and a wide band gap semiconductor is applied to the semiconductor switch element. Combined with switching at a higher frequency than before, the follow-up response of the conversion ratio control to the DC / DC voltage conversion ratio instruction is improved.

  Next, Lduty is input to the gate PWM generator 11. The gate PWM generator 11 performs pulse width modulation (PWM) corresponding to the value of Lduty, and FIG. 4 (a), FIG. 5 (a), FIG. 6 (a), FIG. 7 (a). The rectangular gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4 that are the original signals of the gate drive signal 8 (Gate1, Gate2, Gate3, and Gate4) shown in FIG. This is generated, for example, by using a triangular wave comparison method to compare the magnitude of a triangular wave having a frequency of 1.0 and an amplitude of 1.0 with a switching frequency of the semiconductor switch element.

  The gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4 are input to the gate drive circuit 12. The gate drive circuit 12 outputs a gate drive signal 8 for turning on and off the semiconductor switch element according to the logic of the gate PWM signal. Since the gate drive circuit 12 needs to transfer the gate PWM signal to and from the gate PWM generation unit 11, the gate drive circuit 12 receives the signal after being insulated. This is because the source potentials of FET4, FET3, FET2, and FET1 have individual values, and in order to switch on / off of FET4, FET3, FET2, and FET1, the gate potential is set based on the source potential of each field effect transistor. This is because the gate PWM generator 11 generates and outputs a gate PWM signal at the same reference potential.

In addition, as described above, the gate drive circuit 12 includes the gate drive circuit (1) 121, the gate drive circuit (2) 122, and the gate drive circuit (3) so that each field effect transistor having an individual source potential is operated. 123 and the gate drive circuit (4) 124.
Each gate drive circuit is signal-connected to the source potential of the corresponding field effect transistor, and switching between switching on and switching off by switching the voltage of the gate driving signal 8 between the power supply voltage VD and the source potential. Control. Since the power supply voltage VD needs to be individually supplied according to each field effect transistor, four mutually isolated power supply voltages VD1, VD2, VD3, and VD4 are generated by the gate power supply circuit 13, and each of the gate drive circuits (1) 121, a gate drive circuit (2) 122, a gate drive circuit (3) 123, and a gate drive circuit (4) 124.

  The gate drive circuit (1) 121 outputs a Gate1 signal to output FET1, the gate drive circuit (2) 122 outputs a Gate2 signal to output FET2, and the gate drive circuit (3) 123 outputs a Gate3 signal to drive FET3 to gate drive. The circuit (4) 124 outputs a Gate4 signal and performs switching operation of each FET4.

The relationship between the on-duty of the FET1 and FET2 and the DC / DC voltage conversion ratio has the characteristics shown in FIG. 10 according to the equations (3) and (6). As described above, the DC / DC voltage conversion apparatus 1 performs an operation in the control unit 3 to follow a DC / DC voltage conversion ratio instruction from an external device (not shown) as described above. A gate drive signal 8 with an on-duty corresponding to the instructed DC / DC voltage conversion ratio is output to control switch-on and switch-off of the semiconductor switch element in the conversion main circuit 2.
When the on-duty is 50%, the primary terminal voltage V1 and the secondary terminal voltage V2 of the DC / DC voltage converter 1 are equal. When the on-duty is 50% or more, the boost operation is performed, and the voltage conversion ratio V2 / V1 increases as the on-duty increases.
When the on-duty is less than 50%, the step-down operation is performed, and the voltage conversion ratio V2 / V1 decreases as the on-duty decreases.

As described above, according to the first embodiment, the DC / DC voltage conversion device is formed using a field effect transistor made of a semiconductor material having a wide band gap larger than that of Si as the semiconductor unit. Since it is configured, switching operation is possible at an audio frequency upper limit of 20 kHz or higher, and the upper limit of the semiconductor junction temperature of the semiconductor unit is significantly increased as compared with the conventional Si material.
Further, by adopting the conversion main circuit configuration of the present invention, the ripple current component frequency of the inductor L can be doubled the switching frequency of the semiconductor switch element.
As a result, even if the output power capacity of the DC / DC voltage converter increases and the loss generated in the semiconductor unit increases, the heat resistance temperature of the semiconductor unit increases, so that the heat dissipation by the heat sink and the heat generation of the power device are balanced. The relationship does not become inconsistent. On the other hand, by reducing the cooling performance required for the cooling heat sink, the cooling heat sink can be made smaller and lighter. Along with the downsizing of the device, the transportation and the packaging during transportation become simple.

Furthermore, since the frequency of the ripple current component of the inductor L is increased, the inductance of the inductor L can be lowered, and the volume and weight of the inductor are significantly reduced compared to those based on the prior art.
Therefore, it is possible to realize a small and lightweight DC / DC voltage conversion device while expanding the output power capacity that can be handled and improving the power density.
In particular, the generation of annoying audible noise, which is remarkable with the inductor L, the energy transfer capacitor C0, and the smoothing capacitors C1 and C2, can be solved.

Within the scope of the present invention, the semiconductor unit of the conversion main circuit 2 as shown in FIG. 11 is made of Si material and operates at a frequency higher than the upper limit of the audible frequency instead of the field effect transistor made of a wide band gap semiconductor material. An IGBT to which characteristics are adjusted as possible, and a rectifying element made of a semiconductor material with a wide band gap connected in reverse parallel thereto may be used.
In FIG. 11, the semiconductor switch elements are IGBT1, IGBT2, IGBT3, and IGBT4. The rectifying elements made of the wide band gap material are Di1, Di2, Di3, and Di4. IGBT1 and Di1, IGBT2 and Di2, IGBT3 and Di3, and IGBT4 and Di4 are connected in antiparallel to form a semiconductor unit capable of conducting current bidirectionally.

With this configuration, the semiconductor junction temperature of the IGBT, which is a semiconductor switching element, must be kept below the upper limit of 175 ° C. However, since a wide band gap semiconductor material is applied as the rectifying element, the reverse recovery time is Short reverse recovery current can be achieved.
Therefore, even if an IGBT made of Si material is used, the switching response speed of the IGBT can be increased and the switching loss can be reduced. Therefore, there is a margin in the temperature rise of the IGBT, and the DC / DC voltage converter can be handled. The output power capacity is increased and the power density is improved.

Further, as shown in FIG. 12, a field effect transistor made of a wide bandgap semiconductor material and a rectifying element connected in reverse parallel thereto may be applied to the semiconductor unit of the conversion main circuit 2.
In FIG. 12, the semiconductor switch elements are FET1, FET2, FET3, and FET4. The rectifying elements are Di1, Di2, Di3, and Di4. A rectifying element made of a wide band gap semiconductor material is mainly mounted as a Schottky barrier diode.

  With this configuration, since the rectifying element having excellent characteristics is applied, it is possible to shorten the recovery operation time in which the current flows in the reverse direction for a while when the current flowing through the rectifying element is commutated. Therefore, the operation state for each switching is set in a short time. Therefore, it is possible to further improve the switching frequency, reduce the inductance value Lc, reduce the volume of the inductor L, and realize a small and lightweight DC / DC voltage converter.

In the above description, the switching frequency of the semiconductor unit is set to be equal to or higher than the upper limit of the audible frequency, but the condition that satisfies the condition that the frequency of the AC component flowing through the inductor that is twice the switching frequency is equal to or higher than the upper limit of the audible frequency. In particular, since the noise generated by the inductor, whose noise is a problem, exceeds the upper limit of the audible frequency, generation of annoying audible noise can be prevented in the same manner as described above.
Furthermore, when used in an environment where the noise of the inductor is not particularly problematic, the switching frequency is set to be the same level as the conventional one regardless of the condition that the frequency of the AC component flowing through the inductor is not less than the upper limit of the audible frequency. In this way, standard and relatively inexpensive switching elements can be used, the device can be realized at low cost, and powering operation to supply power from the primary side to the secondary side and from the secondary side to the primary side In any case of the regenerative operation for supplying power, it is possible to enjoy the effect peculiar to the present invention that DC voltage conversion between the secondary side voltage and the primary side voltage can be performed for both step-up and step-down. I can do it.

Embodiment 2. FIG.
Hereinafter, a DC / DC voltage converter according to Embodiment 2 of the present invention will be described with reference to FIGS.
The DC / DC voltage converter according to the present embodiment excludes the configuration and operation of the gate PWM generator 11 and the gate drive circuit 12 in the control unit 3 and the operation when the field effect transistor in the conversion main circuit 2 is turned off. This is the same as in the case of the DC / DC voltage conversion apparatus of the first embodiment, and the description of the same configuration, operation, and action as in the first embodiment will be omitted as appropriate.

First, a description will be given with reference to FIG. FIG. 13 is a block diagram illustrating the configuration of the control unit 3 and the conversion main circuit 2 according to this embodiment. The control unit 3 internally inputs the primary side terminal voltage V1, the secondary side terminal voltage V2, the inductor current IL, and a DC / DC voltage conversion ratio instruction from an external device (not shown). A control calculation is performed, and a gate drive signal 8 for controlling the switching elements in the conversion main circuit 2 is output. According to the timing and logic gate drive signal 8 shown in the first embodiment, the switching element in the conversion main circuit 2 is switched on and off to perform desired DC / DC voltage conversion.
The primary terminal voltage V1, the secondary terminal voltage V2, the inductor current IL, and the DC / DC voltage conversion ratio instruction that are input to the control unit 3 are input to the conversion control unit 10, and negative feedback control calculation of the voltage conversion ratio is performed. Then, the target amount Lduty of the on-duty of FET1 and FET2 is output.

Subsequently, the gate PWM generation unit 11a receives Lduty, generates gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4 corresponding to the value of Lduty and outputs them to the gate drive circuit 12a.
Further, a switching signal DCsel for selecting either the switch-off circuit (1) or the switch-off circuit (2) of the gate drive circuit 12a is output to the gate drive circuit 12a depending on the magnitude of Lduty.

The detailed configuration of the gate drive circuit 12a is shown in FIG. FIG. 14 shows one of four individual drive circuit blocks 121a, 122a, 123a, and 124a constituting the gate drive circuit 12a as a drive circuit block 12xa. The individual drive circuit blocks 121a, 122a, 123a, and 124a have the same configuration and operation. The drive circuit block 121a corresponds to FET1, 122a corresponds to FET2, 123a corresponds to FET3, and 124a corresponds to FET4.
The drive circuit block 12xa generates and outputs the gate drive signal 8 by operating any one of the switch-on circuit 24, the switch-off circuit (1) 25, and the switch-off circuit (2) 26. The switch-on circuit 24 includes a semiconductor switch 241 such as a small signal field effect transistor and a circuit resistor 242.

  Similarly, the switch-off circuit (1) 25 includes a semiconductor switch 251 and a circuit resistor 252, and the switch-off circuit (2) 26 includes a semiconductor switch 261 and a circuit resistor 262. Here, a relationship of (resistance value of circuit resistor 252) <(resistance value of circuit resistor 262) is given.

When the gate PWM signal Gpwm is input to the gate drive circuit 12a, it is transmitted to the signal buffers 21 and 22 internally. The signal buffer 21 is an amplifier circuit that controls the semiconductor switch 241 to be closed when the logic of the gate PWM signal Gpwm is switch-on logic and open when the logic is switch-off logic.
When Gpwm is switch-on logic, the semiconductor switch 241 is closed, and the voltage of the gate drive signal 8 (Gate) becomes the power supply voltage VD. Therefore, the field effect transistor in the corresponding conversion main circuit 2 is switched on.

The signal buffer 22 is an amplifier circuit that controls the semiconductor switches 251 and 261 so as to be opened when the logic of the gate PWM signal Gpwm is switch-on logic and closed when the logic is switch-off logic.
When Gpwm is switch-off logic, either the semiconductor switch 251 or the semiconductor switch 261 is closed, and the voltage of the gate drive signal 8 (Gate) becomes equal to the source potential. Therefore, the field effect transistor in the corresponding conversion main circuit 2 is switched off.

Here, which of the semiconductor switch 251 and the semiconductor switch 261 is to be closed is selected by a circuit switch 23 as an off signal adjusting means.
The output of the signal buffer 22 and the switching signal DCsel are input to the circuit switch 23 to select which one of the switch-off circuit (1) 25 and the switch-off circuit (2) 26 is operated, and the switch on the selected side A control signal is transmitted to close the semiconductor switch in the off circuit.

Selection of the switch-off circuit in the circuit switcher 23 is performed in the form shown in FIG.
FIG. 15 is an explanatory diagram schematically showing which of two types of switch-off circuits is selected corresponding to the on-duty. In FIG. 15, switching of the switch-off circuit is performed with a hysteresis of an on-duty width ΔD with respect to the on-duty.
That is, when the switch-off circuit (1) 25 is selected and the on-duty is equal to or higher than Da% (second threshold), the switch-off circuit (2) 26 is switched to be selected. Further, when the switch-off circuit (2) 26 is selected, if the on-duty is less than (Da-ΔD)% (first threshold), the switch-off circuit (1) 25 is switched to be selected.
That is, when the on-duty is high and Da% or more, the switch-off circuit is operated with a high circuit resistance value. When the on-duty is low and less than (Da−ΔD)%, the switch-off circuit with a low circuit resistance value is used. Operate with.
As described in the first embodiment, the boost operation is performed when the on-duty is 50% or more. The higher the on-duty, the larger the DC / DC voltage conversion ratio, and the higher the secondary side voltage V2 of the DC / DC voltage converter. Become.

  As will be described later, the circuit switch 23 turns off the semiconductor switch by lowering the gate signal 8 to the semiconductor switch based on the relationship of (resistance value of the circuit resistor 252) <(resistance value of the circuit resistor 262). When the switch-off circuit (1) 25 is selected as the falling steepness when the first setting value is selected as the falling steepness, and the switch-off circuit (2) 26 is selected. Switching to the case where the second set value smaller than the first set value is selected as the falling steepness is performed.

  If operated as described above, when the secondary side voltage of the DC / DC voltage converter 1 is high, the surge voltage generated when the field effect transistor is turned off is reduced. It is possible to prevent the maximum voltage including the surge voltage between the sources (DS) from becoming excessive. This will be described in more detail with reference to FIG.

FIG. 16 shows an operation waveform when the field effect transistor is turned off, and the horizontal axis represents the passage of time. FIG. 16A shows a case where the switch-off circuit has a low circuit resistance value, and FIG. 16B shows a case where the switch-off circuit has a high circuit resistance value.
Each symbol in the figure is
Vgs: gate-source (GS) voltage,
Ig: operating current of the gate drive signal 8;
Vds: drain-source (DS) voltage,
Id: current flowing into the drain,
Vth: threshold voltage,
Nfet: the number of series field effect transistors in the conversion main circuit.

The process of the turn-off operation is represented by a change from time ta1 to ta4 in FIG. 16A and a change from time tb1 to tb4 in FIG. 16B.
In FIG. 16A, first, the logic of the gate drive signal 8 is switched from switch-on to switch-off at time ta1. Vgs discharges the gate-source capacitance Cgs and reaches Vth at time ta2. Since the voltage Vds starts to increase from time ta2, the voltage across the drain-source capacitance Cds increases and is charged. At the same time, the gate-drain capacitance Cgd is also charged. From the time ta2 to the time ta3, the discharge of Cgs is temporarily stopped, the decrease of the voltage Vgs is stopped and becomes constant at Vth. During this time, the operating current Ig of the gate drive signal 8 increases and becomes Δigp1. At time ta3, the voltage Vds almost increases.

When the charging of Cgd is almost completed at time ta3, the discharging of Cgs resumes and the current Id decreases. At time ta4, Id completely decreases and the turn-off operation is completed.
Here, an induced voltage is generated from the product of the change rate dId / dt of the current Id and the parasitic inductance Ls of the wiring conductor portion, resulting in a surge voltage ΔVsg1. When the transient operation of the turn-off is finished, the voltage converges to Vds = (2 · V2) / Nfet. This is a state in which the portion to which the voltage V2 is applied is handled by half of the Nfet field effect transistors. The half is responsible because it operates as a combination in which the relationship between the switch-on and switch-off of the field effect transistor is complementary.
In a transient state of the turn-off operation, a surge voltage is superimposed on the voltage Vds, and the maximum value reaches Vds_max = (2 · V2) / Nfet + ΔVsg1. If this Vds_max is excessive, there is a greater concern that the withstand voltage of the power device or capacitor will be exceeded and damaged.

On the other hand, when operating with a switch-off circuit using a high circuit resistance value in which the falling steepness of the gate signal is small and gentle, the operation is as shown in FIG.
In FIG. 16B, the content of the operation over time tb1, tb2, tb3, tb4 is the same as that in FIG. 16A, and time tbx corresponds to time tax. However, due to the difference in circuit resistance value, the operating current Ig of the gate drive signal 8 from time tb2 to time tb3 becomes Δigp2 which is smaller than Δigp1 in FIG. This is because the operating current Ig flows with a circuit resistance value higher than the threshold voltage Vth.

  Therefore, the change rate dId / dt of the current Id when the discharge of Cgs is resumed from the time tb3 to the time tb4 and the current Id is decreased is slower than the waveform of FIG. . Accordingly, the surge voltage ΔVsg2 expressed by the product of the parasitic inductance Ls of the wiring conductor portion is lower than ΔVsg1 in FIG. 16A, and the maximum value Vds_max = (2 · V2) of the voltage Vds in the transient state. ) / NFET + ΔVsg2 also decreases.

  From the above, the DC / DC voltage conversion apparatus 1 according to the second embodiment switches the switch-off circuit in the gate drive circuit 12a according to the on-duty so that the secondary voltage V2 is high. The surge voltage superimposed between the drain and source of the field effect transistor is kept low. For this reason, the drain-source voltage can be excessively high, exceeding the withstand voltage of the semiconductor unit or capacitor, and can be operated so as not to be damaged.

Note that if the switch-off operation speed is increased, the surge voltage increases in a direction that is proportional to the change rate dId / dt of the current Id.
In the second embodiment, when the on-duty is high, the switch-off operation speed is slowed down, so that the concern is that the secondary side voltage V2 is high and exceeds the withstand voltage of the semiconductor unit or capacitor. The switch-off circuit is switched so that the surge voltage is reduced only in the operating range. Therefore, the switch-off operation speed can be increased in the operation range where the secondary terminal voltage V2 is not a high voltage, and there is an advantage that the switching loss is small and the efficiency is high.

Embodiment 3 FIG.
Hereinafter, a DC / DC voltage conversion apparatus according to Embodiment 3 of the present invention will be described with reference to FIGS.
The DC / DC voltage converter according to the present embodiment is configured to adjust the switching frequency of the field effect transistor based on the energy transfer capacitor C0, the inductor L, and the temperature of the field effect transistor that is the semiconductor unit. Is the same as that of the DC / DC voltage converter of the first embodiment. Hereinafter, the description of the same configuration, operation, and action as in the first embodiment will be omitted as appropriate.

First, FIG. 17 is a diagram showing a configuration of the conversion main circuit 2 according to the present embodiment. The FET 1 in the conversion main circuit 2 is provided with a temperature detection diode 271 in the vicinity of the semiconductor chip or on the component surface of the semiconductor chip, and detects the semiconductor chip temperature of the FET 1. Similarly, a temperature detection diode 273 is formed in the vicinity of the semiconductor chip of the FET 3 or on the constituent surface of the semiconductor chip, and detects the semiconductor chip temperature of the FET 3.
An inductor temperature detector 28 and a capacitor temperature detector 29 for detecting respective temperatures are attached to the inductor L and the energy transfer capacitor C0, and each temperature is detected.

  FIG. 18 is a block diagram showing the configuration of the control unit 3 according to this embodiment. The control unit 3 includes an external primary terminal voltage V1, a secondary terminal voltage V2, an inductor current IL, a DC / DC voltage conversion ratio instruction from an external device (not shown), and the conversion main circuit. 2, signals from the temperature detection diodes 271 and 273, the inductor temperature detector 28, and the capacitor temperature detector 29 are input.

Specifically, the signal of the inductor temperature detector 28 is input to the inductor temperature calculation circuit 31 and outputs the inductor temperature TmL. The signal of the capacitor temperature detector 29 is input to the capacitor temperature calculation circuit 32, and the capacitor temperature TmC is output.
The signals of the temperature detection diodes 271 and 273 are input to the semiconductor chip temperature calculation circuit 33, and the semiconductor chip temperature Tmj, which is the higher one of FET1 or FET3, is output.
The temperature detecting diode has a property that the voltage VF between the anode At and the cathode Kt varies depending on the temperature of the PN junction portion under the condition that a predetermined forward bias current is flowing. The semiconductor chip temperature calculation circuit 33 calculates the semiconductor chip temperatures of the FET1 and FET3 using this property.
For convenience, the semiconductor chip temperatures of FET2 and FET4 are not detected. However, this is not necessarily the case, and the semiconductor chip temperatures of all field effect transistors may be detected. Only one semiconductor chip temperature may be detected.

Subsequently, the temperatures TmL, TmC, and Tmj are input to the frequency adjuster 34 that is a switching frequency adjusting unit. The frequency adjuster 34 selects an appropriate value of the switching frequency of the field effect transistors FET1, FET2, FET3, and FET4 based on these input temperatures.
The appropriate value is selected by adjusting the switching frequency to be gradually increased when the temperature of the inductor L or the energy transfer capacitor C0 becomes high and approaches the upper limit of the specified operating temperature range.

  This will be described with reference to FIG. FIG. 19A is a schematic diagram illustrating the relationship between the switching frequency fc, the amount of heat generated by the inductor L, and the energy transfer capacitor C0. As shown in FIG. 19A, the lower the switching frequency fc, the greater the amount of heat generation, and the higher the switching frequency fc, the smaller the amount of heat generation. As described in the first embodiment, this is because the higher the switching frequency, the smaller the amplitude of the alternating current, which is the ripple current component, and the more the loss, that is, the heat generation amount. Similarly, the amount of heat generated by the energy transfer capacitor C0 is reduced because the amplitude of the alternating current is reduced. The reason why the heat generation amount of the inductor L and the energy transfer capacitor C0 decreases at the power root as the switching frequency fc increases is that the heat generation amount mainly depends on the power of the alternating current.

FIG. 19B is a schematic diagram illustrating the relationship between the switching frequency fc and the heat generation amount of the semiconductor unit. As shown in FIG. 19B, the lower the switching frequency fc, the smaller the heat generation amount, and the higher the switching frequency fc, the larger the heat generation amount. This is because, as the switching frequency is higher, the number of times of switching per predetermined time increases, so that the switching loss that occurs in the semiconductor switch element and the reverse recovery loss that occurs in the rectifier element increase. The field effect transistor is a bidirectional conduction device in which a semiconductor switching element and a rectifying element are integrated.
From the characteristics shown in FIGS. 19A and 19B, the lower the switching frequency fc, the higher the temperature of the inductor L and the energy transfer capacitor C0. The higher the switching frequency fc, the higher the temperature of the semiconductor switch element and the rectifying element. easy.

From this characteristic, the frequency adjuster 34 operates as follows. FIG. 20 is a block diagram showing a detailed configuration of the frequency adjuster 34. In the figure, 341 is a frequency adjustment table L, 342 is a frequency adjustment table C, and 343 is a frequency adjustment table j. Reference numeral 344 denotes selection processing means.
The inductor temperature TmL from the inductor temperature calculation circuit 31 is input to the frequency adjustment table L341, and the switching frequency candidate fcl suitable for TmL is output by referring to the table. In this table, the initial value fc0 is set when the temperature is lower than the threshold value Tl_F in the range of the operating temperature range Tl_min to Tl_max of the inductor L, and is gradually increased until fcl_max is reached corresponding to Tl_max when the temperature is higher than the threshold value Tl_F. Yes. This is intended to gradually increase the switching frequency at high temperatures in accordance with the characteristic that the amount of heat generated by the inductor L decreases when the switching frequency in FIG. 19A is high.
Here, the initial value fc0 is a frequency that is equal to or higher than the upper limit of the audible frequency, and none of the inductor L, the energy transfer capacitor C0, and the semiconductor unit is at a high temperature and performs a normal operation without fear of overheating. This is the basic setting value.

  Similarly, the capacitor temperature TmC from the capacitor temperature calculation circuit 32 is input to the frequency adjustment table C342, and a switching frequency candidate fcc suitable for TmC is output by referring to the table. In this table, the initial value fc0 is set when the temperature is lower than the threshold value Tc_F in the range of the operating temperature range Tc_min to Tc_max of the capacitor C, and gradually increases until fcc_max is reached corresponding to Tc_max when the temperature is higher than the threshold value Tc_F. Yes. Similarly to the case of the inductor L described above, it is desired to gradually increase the switching frequency at a high temperature in accordance with the characteristic that the calorific value of the energy transfer capacitor C0 decreases when the switching frequency is high.

Further, the semiconductor chip temperature Tmj that is the highest detected temperature from the semiconductor chip temperature calculation circuit 33 is input to the frequency adjustment table j343, and a switching frequency candidate fcj suitable for Tmj is output by referring to the table. In this table, the initial value fcj_max is set when the temperature is lower than the threshold value Tj_F in the operating temperature range Tj_min to Tj_max of the semiconductor unit, and is gradually decreased until reaching fcj_min corresponding to Tj_max when the temperature is higher than the threshold value Tj_F. Yes.
This is because when the switching frequency in FIG. 19B is low, it is desired to gradually decrease the switching frequency at a high temperature in accordance with the characteristic that the heat generation amount of the semiconductor unit decreases.

Subsequently, the selection processing unit 344 receives the switching frequency candidates fcl, fcc, and fcj, and selects and outputs the switching frequency instruction value fc_ref according to the processing flow shown in FIG.
In the processing flow of FIG. 21, first, in step S101, the larger one of fcl and fcc is set to the switching frequency provisional instruction value fc_tmp. Next, in step S102, the magnitude relationship between the switching frequency provisional instruction value fc_tmp and the switching frequency candidate fcj is compared. If fc_tmp ≦ fcj, the process proceeds to step S104. On the other hand, if fc_tmp> fcj, the process proceeds to step S103. In step S103, fcj is set to the switching frequency provisional instruction value fc_tmp.
Next, in step S104, the provisional instruction value fc_tmp is set to the switching frequency instruction value fc_ref. This fc_ref is output from the selection processing means 344.

  In these operations, the branching in step S102 and the setting of fcj to the switching frequency provisional instruction value fc_tmp in step S103 are performed even when the inductor L or the energy transfer capacitor C0 is at a high temperature and it is desired to gradually increase the switching frequency. If the semiconductor chip temperature of the semiconductor unit is also high and the switching frequency is to be gradually decreased, the latter is preferentially selected as the switching frequency instruction value.

Next, the switching frequency instruction value fc_ref from the selection processing unit 344 is input to the gate PWM generation unit 11 b as an output of the frequency adjuster 34. Similarly to the gate PWM generation unit 11 of the first embodiment shown in FIG. 9, the gate PWM generation unit 11b performs pulse width modulation corresponding to the value of Lduty, and gate drive signals 8 (Gate1, Gate2, Gate3, Gate4). And generate and output rectangular gate PWM signals Gpwm1, Gpwm2, Gpwm3, and Gpwm4.
At this time, the gate PWM signal is generated by setting the frequency of the carrier wave, that is, the switching frequency to the switching frequency instruction value fc_ref.
Since the configuration and operation of the control unit 3 excluding the contents described above are the same as those of the control unit 3 described in the first embodiment, description thereof will be omitted.

  As described above, according to the DC / DC voltage converting apparatus 1 of the third embodiment, the switching frequency of the semiconductor unit is adjusted based on the energy transfer capacitor, the inductor, and the temperature of the semiconductor unit of the conversion main circuit. For this reason, even if the energy transfer capacitor or inductor is configured using a resin material having relatively low heat resistance compared to the semiconductor unit, when the energy transfer capacitor or inductor becomes high temperature, It is possible to protect the capacitor and the inductor from being overheated and damaged by gradually increasing the switching frequency within a range where the rise in the semiconductor chip temperature does not cause a problem.

Embodiment 4 FIG.
Hereinafter, the DC / DC voltage converter in Embodiment 4 of this invention is demonstrated using FIGS. 22-30.
In this example, the DC / DC voltage converter is different from the one described in the first embodiment, and two sets of two switches in which the switch-on and off states at the same time have a complementary relationship form a pair. The conversion main circuit 2 includes three sets of semiconductor units capable of conducting current.
FIG. 22 shows a conversion main circuit 2 having three semiconductor units. The conversion main circuit 2 of FIG. 22 includes field effect transistors FET1, FET2, FET3, FET4, FET5, FET6, which are semiconductor units, a primary side smoothing capacitor C1, a secondary side smoothing capacitor C2, energy transfer capacitors C0a, C0b, and An inductor L is provided.
All the semiconductor units are connected in series. Here, the voltage at the FET4 side connection terminal of the inductor L is represented as VL.

Next, details of the connection of the conversion main circuit 2 will be described.
Both terminals of the smoothing capacitor C1 are connected to the positive side terminal P1 and the negative side terminal N1 on the primary side of the conversion main circuit 2, and the negative side terminal N1 is also the positive side terminal P2 on the secondary side of the conversion main circuit 2 It is connected.
The positive terminal P1 is connected to one terminal of the smoothing capacitor C1 and the drain terminal of the FET1, and the other terminal of the smoothing capacitor C1 is connected to the negative terminal N1.
Further, both terminals of the smoothing capacitor C2 are connected to the positive side terminal P2 and the negative side terminal N2 on the secondary side of the conversion main circuit 2.

The source terminal of the FET 6 is the secondary negative terminal N2 of the conversion main circuit 2, the drain terminal is the source terminal of the FET 5, the drain terminal of the FET 5 is the source terminal of the FET 4, and the drain terminal of the FET 4 is the source terminal of the FET 3. The drain terminal of FET3 is connected to the source terminal of FET2, and the drain terminal of FET2 is connected to the source terminal of FET1.
The energy transfer capacitor C0a has one terminal connected to the connection point between the FET 5 and the FET 4 and the other terminal connected to the connection point between the FET 3 and the FET 2. The energy transfer capacitor C0b has one terminal connected to the connection point between the FET 6 and the FET 5, and the other terminal connected to the connection point between the FET 2 and the FET 1.

  In this example, as mentioned in the explanation of the operation at the later stage, FET1 and FET6, FET2 and FET5, FET3 and FET4 are each a pair, and a pair of FETs forming each pair has a so-called complementary relationship. ON / OFF controlled.

  As shown in FIG. 22, the inductor L has one terminal connected to the primary negative terminal N1 on the primary side of the conversion main circuit 2, and the other terminal directly connected to each other as the pair of FETs described above. It is connected to the connection point between FET4 and FET3.

  From the control unit 3 not shown in FIG. 22, signals for controlling on / off of the field effect transistor as the gate drive signal 8 correspond to FET6, FET5, FET4, FET3, FET2, and FET1, respectively, Gate6, Gate5. , Gate4, Gate3, Gate2, and Gate1 signals are connected from FET6 to the gate electrode (G) of FET1. The FET 6 performs a switching operation according to the voltage change of the Gate 6 signal, the FET 5 of the Gate 5 signal, the FET 4 of the Gate 4 signal, the FET 3 of the Gate 3 signal, the FET 2 of the Gate 2 signal, and the FET 1 of the Gate 1 signal.

  The field effect transistor is controlled to be switched on and off in accordance with the gate drive signal 8 from the control unit 3. The control unit 3 is similar to FIG. 9 of the first embodiment, and the on-duty target amount Lduty calculated by the conversion control unit 10 is input to the gate PWM generation unit 11. The gate PWM generator 11 performs pulse width modulation corresponding to the value of Lduty, and FIG. 23 (a), FIG. 24 (a), FIG. 25 (a), FIG. 26 (a), FIG. The rectangular gate PWM signals Gpwm1 and Gpwm2 that are the original signals of the gate drive signals 8 (Gate1, Gate2, Gate3, Gate4, Gate5, and Gate6) shown in 28 (a), FIG. 29 (a), and FIG. 30 (a). , Gpwm3, Gpwm4, Gpwm5, and Gpwm6 are generated and output.

Here, FIG. 23 illustrates a waveform when the on-duty of the gate drive signal is less than 100/3% in the step-down operation during the power running operation. (A) shows the gate drive signal, (b) shows the inductor current IL, and (c) shows the switching mode and its switching timing.
Similarly, FIG. 24 shows a case where the on-duty of the gate drive signal is 100/3% or more and less than 50% in the step-down operation during the power running operation, and FIG. 26 is a waveform when the on-duty of the gate drive signal is 100 × (2/3)% or more in the step-up operation during the power running operation when the value is 50% or more and less than 100 × (2/3)%. To do. (A) shows the gate drive signal, (b) shows the inductor current IL, and (c) shows the switching mode and its switching timing.
The inductor current IL has a positive polarity in which the inductor L flows in the direction from the FET4 side connection terminal to the negative terminal N1 side connection terminal.

The gate PWM signals Gpwm1, Gpwm2, Gpwm3, Gpwm4, Gpwm5, and Gpwm6 are input to the gate drive circuit 12. The gate drive circuit 12 outputs a gate drive signal 8 for turning on and off the semiconductor switch element according to the logic of the gate PWM signal.
Gpwm1 corresponds to FET1, Gpwm2 corresponds to FET2, Gpwm3 corresponds to FET3, Gpwm4 corresponds to FET4, Gpwm5 corresponds to FET5, and Gpwm6 corresponds to FET6, and controls the switching operation of the field effect transistor.

Although not shown, the gate drive circuit 12 includes a gate drive circuit (1) 121, a gate drive circuit (2) 122, a gate drive circuit (3) 123, It is divided into a gate drive circuit (4) 124, a gate drive circuit (5) 125, and a gate drive circuit (6) 126.
The gate power supply circuit 13 generates six mutually isolated power supply voltages VD1, VD2, VD3, VD4, VD5, and VD6 and supplies them to the respective gate drive circuits 121 to 126.

Next, voltage conversion control by the gate drive signal 8 will be described separately for the power running operation and the regenerative operation.
During power running:
1) When the on-duty is less than 100/3% and step-down operation:
An operation in which the on-duty for stepping down the secondary side voltage V2 <the primary side voltage V1 during powering operation for supplying power from the primary side to the secondary side is less than 100/3% will be described.
In FIG. 23A, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high, and a current flows from the drain toward the source. Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

Here, the Gate 1 signal and the Gate 6 signal, the Gate 2 signal and the Gate 5 signal, and the Gate 3 signal and the Gate 4 signal are complementary signals in which logics of high and low are opposite to each other. As shown in FIG. 23A, the gate drive signal 8 has three pairs of complementary signals, and the phase difference between them is equal.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into four types of switching modes E, F, G, and H, and H → E → G → E → F → E → H It switches in order.

In switching mode F, FET1, FET4, FET5 are on, FET2, FET3, FET6 are off,
The current flows through the path of the positive terminal P1, the FET 1, the energy transfer capacitor C0b, the FET 5, the FET 4, the inductor L, and the negative terminal N1, and the energy is stored in the energy transfer capacitor C0b. A voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.
Since FET1, FET4, and FET5 are on and current is conducted, the potential of the FET5 side connection terminal of the energy transfer capacitor C0b is about VL, and the potential of the FET1 side connection terminal is about V1.
Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is VL = V1−Vc0b. Here, Vc0b is a voltage across the energy transfer capacitor C0b.

In switching mode H, FET3, FET5, FET6 are on, FET1, FET2, FET4 are off,
The current flows in the path of the negative electrode side terminal N2, FET6, FET5, energy transfer capacitor C0a, FET3, inductor L, positive electrode side terminal P2, electrical equipment 5, and negative electrode terminal N2, and energy is discharged from the energy transfer capacitor C0a. To do.
Further, since FET3, FET5, and FET6 are on and the current is conducted, the potential of the FET3 side connection terminal of the energy transfer capacitor C0a is about VL, and the potential of the FET5 side connection terminal is about -V2.
Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is VL = −V2 + Vc0a. Here, Vc0a is a voltage across the energy transfer capacitor C0a.

In switching mode E, FET4, FET5, FET6 are on, FET1, FET2, FET3 are off,
The current flows through the path of the negative terminal N2 → FET6 → FET5 → FET4 → inductor L → positive terminal P2 → electric device 5 → negative terminal N2, and the energy accumulated in the inductor L is released.
Further, since FET4, FET5, and FET6 are on and current is conducted, the voltage VL is approximately -V2. The difference between the voltage VL at the connection terminal on the FET4 side of the inductor L and the voltage at the connection terminal on the negative terminal N1 side is negative at (−V2-0), and the inductor current IL is negative when IL ≧ 0. Decrease in the direction.

In switching mode G, FET2, FET4, FET6 are on, FET1, FET3, FET5 are off,
The current flows through the path of the negative terminal N2 → FET6 → energy transfer capacitor C0b → FET2 → energy transfer capacitor C0a → FET4 → inductor L → positive terminal P2 → electric device 5 → negative terminal N2. It is stored in the transfer capacitor C0a and discharged from the energy transfer capacitor C0b.
Since the FET2, FET4, and FET6 are on and the current is conducted, the potential of the FET4 side connection terminal of the energy transfer capacitor C0a is approximately VL, and the potential of the FET2 side connection terminal is the FET2 side of the energy transfer capacitor C0b. It becomes almost equal to the potential of the connection terminal. In addition, the potential of the FET6 side connection terminal of the energy transfer capacitor C0b is approximately −V2.
Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is VL = (− V2 + Vc0b−Vc0a).

Here, the on-duty of the Gate 1 signal, the Gate 2 signal, and the Gate 3 signal is equal. From this operation, the voltages VL in the switching modes F, G, and H are equal in terms of time average, and the relationship is V1−Vc0b = −V2 + Vc0b−Vc0a = −V2 + Vc0a. Therefore, Vc0b = (2/3) · (V1 + V2) and Vc0a = (1/3) · (V1 + V2).
From this, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1, FET2, and FET3 are expressed by the following relationship.

Switching modes F, G, H: L · ILrpl = ton · (V1-2 · V2) / 3
.. (8a)
Switching mode E: L.ILrpl = -toff (-V2) (8b)

  Since the left sides of Expression (8a) and Expression (8b) are equal, the following relationship is established.

  ton. (V1-2.V2) / 3 = -toff. (-V2) (9)

The above formula (9) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = ton / (3 · toff + 2 · ton) = ton / ((2/3) · T + toff)
= (Ton / T) / (1-ton / T) (10)
However, ton + toff = T / 3

In the above equation (10), the period T indicates a period in which the switching mode is switched in the order of H → E → G → E → F → E → H and makes a round, and T / 3 = ton + toff. The left side (V2 / V1) of Expression (10) is a DC / DC voltage conversion ratio.
In an operation in which the on-duty of the gate drive signal shown in FIG. 23 is less than 100/3%, (ton / T) <(1/3), and when applied to Expression (10), the DC / DC voltage conversion ratio is , Less than 1/2. Therefore, V2 <(V1 / 2).

From these, in the switching modes F, G, and H, the voltage VL at the connection terminal on the FET4 side of the inductor L is VL = (V1-2 · V2) / 3> 0, and the voltage at the connection terminal on the negative terminal N1 side of the inductor L Is 0.
Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL increases in the positive direction. Further, as described above, in the switching mode E, the inductor current IL changes in the negative direction when IL ≧ 0.

As described above, in the switching mode H → E → G → E → F → E → H,
In the switching modes F, G, and H, the inductor current IL changes so as to increase further in the positive direction from the state of IL ≧ 0,
In the switching mode E, the inductor current IL changes toward the state where IL <0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor.
Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.

2) When the on-duty is 100/3% or more and less than 50% and the step-down operation is:
Next, a case where the on-duty of the gate drive signal is 100/3% or more and less than 50% and the step-down operation is performed will be described.
In FIG. 24A, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high, and a current flows from the drain toward the source.
Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

The Gate1 signal and Gate6 signal, the Gate2 signal and Gate5 signal, the Gate3 signal and Gate4 signal are complementary signals in which the logics of high and low are opposite to each other, and the gate drive signal 8 has three types of signals that form a pair as complementary signals. Thus, the mutual phase differences are equally spaced.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into six types of switching modes F, G, H, I, J, and K, and G → J → H → K → F. Switching in order of → I → G.

  The state of each field effect transistor in the switching modes F, G, and H, the current conduction path, and the voltage VL at the FET4 side connection terminal of the inductor L are the item 1) during the powering operation described above. The on-duty is less than 100/3% Since this is the same as the case of, the description is omitted.

In switching mode I, FET1, FET2, FET4 are on, FET3, FET5, FET6 are off,
The current flows in the path of the positive terminal P1, the FET1, the FET2, the energy transfer capacitor C0a, the FET4, the inductor L, and the negative terminal N1, and the energy is stored in the energy transfer capacitor C0a.
The voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.
Since FET1, FET2, and FET4 are turned on and current is conducted, the potential of the FET2 side connection terminal of the energy transfer capacitor C0a is approximately V1, and the potential of the FET4 side connection terminal is approximately VL. Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is VL = V1−Vc0a. The voltage at the negative terminal N1 side connecting terminal of the inductor L is 0, and the difference between the voltage VL at the FET4 side connecting terminal of the inductor L and the voltage at the negative terminal N1 side connecting terminal is (V1−Vc0a).

In switching mode J, FET2, FET3, FET6 are on, FET1, FET4, FET5 are off,
The current flows in the path of the negative terminal N2 → FET6 → energy transfer capacitor C0b → FET2 → FET3 → inductor L → positive electrode terminal P2 → electric device 5 → negative electrode terminal N2, and energy is transferred from the energy transfer capacitor C0b. Released. At the same time, a current also flows through the smoothing capacitor C2 to store energy.
Since FET2, FET3, and FET6 are turned on and current is conducted, the voltage VL at the FET4 side connection terminal of the inductor L becomes equal to the potential of the high potential side terminal connected to the FET2 of the energy transfer capacitor C0b. Further, the potential of the low potential side terminal connected to the FET 6 of the energy transfer capacitor C0b becomes equal to the voltage −V2 of the negative side terminal N2. Therefore, the voltage VL at the connection terminal on the FET 4 side of the inductor L is VL = −V2 + Vc0b, and the difference between the voltage VL of the inductor L and the voltage at the connection terminal on the negative terminal N1 side is (−V2 + Vc0b−0).

In switching mode K, FET1, FET3, FET5 are on, FET2, FET4, FET6 are off,
The current flows through the path of the positive terminal P1, the FET 1, the energy transfer capacitor C0b, the FET 5, the energy transfer capacitor C0a, the FET 3, the inductor L, and the negative terminal N1, and the energy is discharged from the energy transfer capacitor C0a. Stored in the transfer capacitor C0b. A voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.

Since FET1, FET3, and FET5 are turned on and current is conducted, the potential of the FET5 side connection terminal of the energy transfer capacitor C0a becomes equal to the potential of the FET5 side connection terminal of the energy transfer capacitor C0b.
Further, the potential of the FET3 side connection terminal of the energy transfer capacitor C0a is approximately VL. The potential of the FET1 side connection terminal of the energy transfer capacitor C0b is approximately V1.
Therefore, the voltage VL at the FET3 side connection terminal of the inductor L is VL = (V1−Vc0b + Vc0a).
Therefore, the difference between the voltage VL at the connection terminal on the FET3 side of the inductor L and the voltage at the connection terminal on the negative terminal N1 side is (V1−Vc0b + Vc0a).

Here, the on-duty of the Gate 1 signal, the Gate 2 signal, and the Gate 3 signal is equal. From this operation, the voltages VL in the switching modes F, G, and H are equal in terms of time average, and the relationship is V1−Vc0b = −V2 + Vc0b−Vc0a = −V2 + Vc0a. From this, Vc0b = 2 · Vc0a.
Further, the voltages VL in the switching modes I, J, and K are equal in terms of time average, and the relationship is V1−Vc0a = (− V2 + Vc0b) = (V1−Vc0b + Vc0a). Accordingly, Vc0b = (2/3) · (V1 + V2) and Vc0a = (1/3) · (V1 + V2), as in the case where the on-duty of the gate drive signal is less than 100/3%.
From this, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1, FET2, and FET3 are expressed by the following relationship.

Switching modes F, G, H:
L · ILrpl = (T / 3−ton + T / 3) · (V1-2 · V2) / 3
= (2 · T / 3-ton) · (V1-2 · V2) / 3 (11a)
Switching modes I, J, K:
L.ILrpl =-(ton-T / 3). (2.V1-V2) / 3 .. (11b)
However, ton + toff = T

  Since the left sides of Expression (11a) and Expression (11b) are equal, the following relationship is established.

(2 · T / 3-ton) · (V1-2 · V2) / 3
=-(Ton-T / 3). (2.V1-V2) / 3 .. (12)

  The above equation (12) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = ton / (T-ton) = (ton / T) / (1-ton / T)
(13)
However, ton + toff = T

In the above equation (13), the period T indicates a period in which the switching mode G → J → H → K → F → I → G makes a round, and T = ton + toff. The left side (V2 / V1) of Expression (13) is a DC / DC voltage conversion ratio.
In the operation in which the on-duty of the gate drive signal shown in FIG. 24 is 100/3% or more and less than 50%, (1/3) ≦ (ton / T) <(1/2). When applied, the DC / DC voltage conversion ratio is ½ or more and less than 1. Therefore, (V1 / 2) ≦ V2 <V1.

From these, in the switching modes F, G, and H, the voltage VL of the connection terminal on the FET4 side of the inductor L is in the range of 0 to (−V1 / 3), and the voltage of the connection terminal on the negative electrode side N1 side of the inductor L is 0. is there. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL changes in the negative direction in a state where IL ≧ 0.
In switching modes I, J, and K, the voltage VL at the connection terminal on the FET 4 side of the inductor L is in the range of V1 / 2 to V1 / 3, and the voltage at the connection terminal on the negative terminal N1 side of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL increases in the positive direction.

As described above, in the switching mode G → J → H → K → F → I → G,
In the switching modes F, G, and H, the inductor current IL changes from the state of IL ≧ 0 toward the state of IL <0,
In the switching modes I, J, and K, the inductor current IL further changes to increase in the positive direction.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor. Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.

3) When the on-duty is 50% or more and less than 100 × (2/3)% and the boost operation is performed
Next, the case where the on-duty of the gate drive signal is 50% or more and less than 100 × (2/3)% during the power running operation will be described.
In FIG. 25A, FET1 turns on when the Gate1 signal is high, FET2 turns on when the Gate2 signal is high, and FET3 turns on when the Gate3 signal is high, and a current flows from the drain toward the source.
Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

As in the case of the step-down operation when the on-duty is 100/3% or less and less than 50%,
The Gate1 signal and Gate6 signal, the Gate2 signal and Gate5 signal, the Gate3 signal and Gate4 signal are complementary signals in which the logics of high and low are opposite to each other, and the gate drive signal 8 has three types of signals that form a pair as complementary signals. Thus, the mutual phase differences are equally spaced.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into six types of switching modes F, G, H, I, J, and K, and G → J → H → K → F. Switching in order of → I → G.

The state of each field effect transistor in the switching modes F, G, H, I, J, and K, the current conduction path, and the voltage VL at the FET4 side connection terminal of the inductor L are the item 2) on-duty during the powering operation described above. Is 100/3% or more and less than 50%, which is the same as in the step-down operation, and the description thereof is omitted.
From these, the relationship between the potential difference between both ends of the inductor L, the switch-on time ton, and the switch-off time toff of the FET1, FET2, and FET3 is similarly expressed by Expression (11a), Expression (11b), and Expression (12). . Therefore, for the primary side terminal voltage V1 and the secondary side terminal voltage V2, the DC / DC voltage conversion ratio (V2 / V1) is expressed as in Expression (13).

In the above equation (13), the period T indicates a period in which the switching mode G → J → H → K → F → I → G makes a round, and T = ton + toff.
In the operation of 50% or more and less than 100 × (2/3)% of the gate drive signal shown in FIG. 25, (1/2) ≦ (ton / T) <(2/3), and Expression (13) Is applied, the DC / DC voltage conversion ratio is 1 or more and less than 2. Therefore, V1 ≦ V2 <(2 · V1).

From these, in the switching modes F, G, and H, the voltage VL of the connection terminal on the FET4 side of the inductor L is in the range of (−V1 / 3) to (−V1), and the voltage of the connection terminal on the negative terminal N1 side of the inductor L. Is 0. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL changes in the negative direction in a state where IL ≧ 0.
In the switching modes I, J, and K, the voltage VL at the connection terminal on the FET4 side of the inductor L is in the range from (V1 / 3) to 0, and the voltage at the connection terminal on the negative terminal N1 side of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL increases in the positive direction.

As described above, the same as in the case of the step-down operation when the on-duty is 100/3% or less and less than 50% and the switching mode G → J → H → K → F → I → G In switching,
In the switching modes F, G, and H, the inductor current IL changes from the state of IL ≧ 0 toward the state of IL <0,
In the switching modes I, J, and K, the inductor current IL further changes to increase in the positive direction.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor.
Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.

4) When the on-duty is 100 x (2/3)% or more and boosting operation:
Next, a case where the on-duty of the gate drive signal is 100 × (2/3)% or more during the power running operation will be described.
In FIG. 26A, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high, and a current flows from the drain toward the source.
Further, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high. Instead of the parasitic diode inherent in the FET 6, it flows through the transistor portion.

The Gate1 signal and Gate6 signal, the Gate2 signal and Gate5 signal, the Gate3 signal and Gate4 signal are complementary signals whose logics of high and low are opposite to each other, and the gate drive signal 8 has three types of signals that form a pair as complementary signals. Thus, the mutual phase difference is equally spaced.
At this time, the high and low logic combinations of the gate drive signals from Gate 1 to Gate 6 are classified into four types of switching modes I, J, K, and M. M → K → M → I → M → J → M It switches in order.

  The state of each field effect transistor in switching modes I, J, and K, the current conduction path, and the voltage VL at the FET4 side connection terminal of the inductor L are the item 2) during the powering operation described above. The on-duty is 100/3% or more Since it is the same as the step-down operation at less than 50%, the description is omitted.

In switching mode M, FET1, FET2, FET3 are on, FET4, FET5, FET6 are off,
The current flows through the path of the positive terminal P1, the FET 1, the FET 2, the FET 3, the inductor L, and the negative terminal N1, and energy is stored in the inductor L.
In addition, since the FET1, FET2, and FET3 are turned on to conduct current, the voltage VL becomes approximately V1. The difference between the voltage VL at the FET3 side connection terminal of the inductor L and the voltage at the connection terminal on the negative side terminal N1 side becomes positive at (V1-0), and the inductor current IL further increases in the positive direction.
A voltage across the smoothing capacitor C2 is applied to the electric device 5, and energy is supplied from the smoothing capacitor C2.

Here, the on-duty of the Gate 1 signal, the Gate 2 signal, and the Gate 3 signal is equal. Due to this operation, the voltages VL in the switching modes I, J, and K are equal in terms of time average, and the relationship is (V1−Vc0a) = (− V2 + Vc0b) = (V1−Vc0b + Vc0a).
Therefore, Vc0b = (2/3) · (V1 + V2), Vc0a = (1/3) · (V1 + V2), as in the case where the on-duty of the gate drive signal is 100% or more and less than 50%. .
From this, the potential difference between both ends of the inductor L, the switch-on time ton and the switch-off time toff of the FET1, FET2, and FET3 are expressed by the following relationship.

Switching mode M: L.ILrpl = (T / 3-toff) .V1 .. (14a)

Switching modes I, J, K: L · ILrpl = −toff · (2 · V1−V2) / 3 ·· (14b) where ton + toff = T

  Since the left sides of Expression (14a) and Expression (14b) are equal, the following relationship is established.

  (T / 3−toff) · V1 = −toff · (2 · V1−V2) / 3 (15)

  The above formula (15) can be summarized with respect to the primary terminal voltage V1 and the secondary terminal voltage V2 as follows.

(V2 / V1) = (T-toff) / toff = ton / (T-ton)
= (Ton / T) / (1-ton / T) (16)
However, ton + toff = T

In the above equation (16), the period T indicates a period in which the switching mode M → K → M → I → M → J → M is switched in order, and T = ton + toff. The left side (V2 / V1) of Expression (16) is a DC / DC voltage conversion ratio.
In the operation in which the on-duty of the gate drive signal shown in FIG. 26 is 100 × (2/3)% or more, (2/3) ≦ (ton / T), and when applied to the equation (16), DC / DC The voltage conversion ratio is 2 or more. Therefore, (2 · V1) ≦ V2.

From these, in the switching modes I, J, and K, the voltage VL at the FET4 side connection terminal of the inductor L is VL = (2 · V1−V2) / 3 <0. The voltage at the connection terminal on the negative electrode side N1 side of the inductor L is zero.
Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL changes in the negative direction in a state where IL ≧ 0.
As described above, in the switching mode M, the inductor current IL further increases in the positive direction.

As described above, in the switching mode M → K → M → I → M → J → M,
In switching modes I, J, and K, the inductor current IL changes from the state of IL ≧ 0 toward the state of IL <0,
In the switching mode M, the inductor current IL further increases in the positive direction from the state where IL ≧ 0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor.
Accordingly, an alternating current having a frequency three times that of the switching frequency of the field effect transistor is conducted to the inductor L.
In addition, the equations (10), (13), and (16) are equal, that is, the DC / DC voltage is continuously adjusted according to the change of the on-duty regardless of the on-duty. The conversion ratio is adjusted.

Next, the regenerative operation will be described.
During regenerative operation:
The present embodiment also has the symmetry of operation between powering and regeneration described in the first embodiment. The operation at the time of regeneration in the present embodiment is that the electric power generated by the electrical device 5 connected to the secondary side of the DC / DC voltage converter 1 is DC / DC voltage converted from V2 to V1 and recovered by the DC power supply 4. .
At this time, DC / DC voltage conversion is performed in a voltage V1> voltage V2 relationship in the step-down operation and in a relationship V1 ≦ voltage V2 in the voltage step-up operation.
The waveform of the gate drive signal 8 is shown in FIG. 27A, FIG. 28A, FIG. 29A, and FIG. 30A, and is the same as that during the power running operation. That is,
FIG. 27A shows that when the on-duty of the gate drive signal is less than 100/3%,
FIG. 28A shows a case where the on-duty of the gate drive signal is 100/3% or more and less than 50%.
FIG. 29A shows a case where the on-duty of the gate drive signal is 50% or more and less than 100 × (2/3)%.
FIG. 30A shows the waveform of the gate drive signal when the on-duty of the gate drive signal is 100 × (2/3)% or more.

1) When the on-duty is less than 100/3% and step-down operation:
An operation in which the on-duty for reducing the secondary side voltage V2 <the primary side voltage V1 during the regenerative operation for supplying power from the secondary side to the primary side is less than 100/3% will be described. Note that, based on the secondary side voltage V2, the voltage is boosted in a relationship of V1 / V2> 1.
In FIG. 27A, the FET 4 is turned on when the Gate 4 signal is high, the FET 5 is turned on when the Gate 5 signal is high, and the FET 6 is turned on when the Gate 6 signal is high, and a current flows from the drain toward the source.
In addition, FET1 is turned on when the Gate1 signal is high, FET2 is turned on when the Gate2 signal is high, and FET3 is turned on when the Gate3 signal is high. However, during the regenerative operation, the current flows from the source to the drain. Instead of the parasitic diode inherent in the FET 3, it flows through the transistor portion.

The combination of high and low logic of the gate drive signals from Gate 1 to Gate 6 is shown in FIG. 27C when the on-duty of the gate drive signal is less than 100/3%, and the on-duty of the gate drive signal is 100/3% or more. If it is less than 50%, the on-duty of the gate drive signal shown in FIG. 28C is 50 × or more and less than 100 × (2/3)%, and the on-duty of the gate drive signal shown in FIG. At 2/3)% or more, the result is as shown in FIG.
That is, there are eight switching modes: E, F, G, H, I, J, K, and M.

In switching mode E,
The current flows through the path of the positive terminal P2, the inductor L, the FET 4, the FET 5, the FET 6, the negative terminal N2, the electrical device 5, and the positive terminal P2, and energy is stored in the inductor L. Further, since FET4, FET5, and FET6 are turned on and current is conducted, the voltage VL is approximately -V2. Further, since the secondary side positive terminal P2 is connected to the primary side negative terminal N1, the difference between the voltage VL of the FET 4 side connection terminal of the inductor L and the voltage of the connection terminal on the positive side terminal P2 side is It becomes negative at (−V2-0), and the inductor current IL further increases in the negative direction when IL <0.

In switching mode F,
The current flows through the path of the negative terminal N1, the inductor L, the FET 4, the FET 5, the energy transfer capacitor C0b, the FET 1, the positive terminal P1, the DC power supply 4, the negative terminal N1, and the energy is discharged from the energy transfer capacitor C0b. Is done. The smoothing capacitor C <b> 2 is applied with the voltage across the electric device 5, and the generated energy from the electric device 5 is supplied.
Since FET1, FET4, and FET5 are on and current is conducted, the potential of the FET5 side connection terminal of the energy transfer capacitor C0b is about VL, and the potential of the FET1 side connection terminal is about V1.
Therefore, the voltage VL at the connection terminal of the inductor L on the FET 4 side is VL = V1−Vc0b.

In switching mode G,
Positive side terminal P2 → Inductor L → FET 4 → Energy transfer capacitor C0a → FET 2 → Energy transfer capacitor C0b → FET 6 → Negative side terminal N2 → Electrical device 5 → Positive side terminal P2 Released from C0a and stored in energy transfer capacitor C0b.
Further, since FET2, FET4, and FET6 are turned on and current is conducted, the voltage VL is approximately (−V2 + Vc0b−Vc0a).

In switching mode H,
The current flows in the path of the positive terminal P2, the inductor L, the FET 3, the energy transfer capacitor C0a, the FET 5, the FET 6, the negative terminal N2, the electrical device 5, and the positive terminal P2, and the energy is stored in the energy transfer capacitor C0a. It is done.
Further, since FET3, FET5, and FET6 are turned on and current is conducted, the voltage VL is approximately (−V2 + Vc0a).

In switching mode I,
The current flows in the path of inductor L → FET 4 → energy transfer capacitor C0a → FET 2 → FET 1 → positive terminal P1 → DC power supply 4 → negative terminal N1 → inductor L, and energy is released from the energy transfer capacitor C0a. .
Further, since FET1, FET2, and FET4 are turned on and current is conducted, the voltage VL is approximately (V1-Vc0a).

In switching mode J,
The current flows through the path of the positive terminal P2, the inductor L, the FET 3, the FET 2, the energy transfer capacitor C0b, the FET 6, the negative terminal N2, the electrical device 5, and the positive terminal P2, and the energy is stored in the energy transfer capacitor C0b. It is done.
Further, since FET2, FET3, and FET6 are turned on and current is conducted, the voltage VL is approximately (−V2 + Vc0b).

In switching mode K,
The current flows through the path of inductor L → FET 3 → energy transfer capacitor C0a → FET 5 → energy transfer capacitor C0b → FET 1 → positive terminal P1 → DC power supply 4 → negative terminal N1 → inductor L,
Energy is released from the energy transfer capacitor C0b and stored in the energy transfer capacitor C0a.
Further, since FET1, FET3, and FET5 are turned on to conduct current, the voltage VL is approximately (V1−Vc0b + Vc0a).

In switching mode M,
A current flows in a path of inductor L → FET 3 → FET 2 → FET 1 → positive terminal P 1 → DC power supply 4 → negative terminal N 1 → inductor L, and energy is released from the inductor L.
Further, since FET1, FET2, and FET3 are turned on and current is conducted, the voltage VL is approximately V1.
The difference between the voltage VL at the FET3 side connection terminal of the inductor L and the voltage at the connection terminal on the negative side terminal N1 side is positive at (V1-0), and the inductor current IL is directed in the positive direction when IL <0. Change.

Subsequently, each range of the on-duty of the gate drive signal and switching of the corresponding switching mode will be described.
1) When the on-duty is less than 100/3% and step-down operation:
When the on-duty of the gate drive signal is less than 100/3%, as shown in FIG. 27 (c), the switching mode is switched in the order of H → E → G → E → F → E → H, and makes a round with a period T. .
As in the power running operation, the voltages VL in the switching modes F, G, and H are equal in terms of time average, and the relationship is (V1−Vc0b) = (− V2 + Vc0b−Vc0a) = (− V2 + Vc0a). Therefore, Vc0b = (2/3) · (V1 + V2) and Vc0a = (1/3) · (V1 + V2).
The potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary terminal voltage V1, and the secondary terminal voltage V2 of the FET1, FET2, and FET3 are expressed by the following equations (8a), (8b), and ( 9) is established.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage conversion device 1 is represented by Expression (10).
In an operation in which the on-duty of the gate drive signal is less than 100/3%, (ton / T) <(1/3), and the DC / DC voltage conversion ratio is less than 1/2 when applied to the equation (10). . Therefore, V2 <(V1 / 2). That is, the secondary side terminal voltage V2 is stepped down to a voltage lower than ½ times the primary side terminal voltage V1.

From these, in the switching modes F, G, and H, the voltage VL = (V1-2 · V2) / 3> 0 of the FET4 side connection terminal of the inductor L, and the voltage of the negative terminal N1 side connection terminal of the inductor L is 0. is there. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL changes in the positive direction.
In the switching mode E, as described above, it further increases in the negative direction when IL <0.
As described above, in the switching mode H → E → G → E → F → E → H,
In the switching modes F, G, and H, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0,
In the switching mode E, the inductor current IL increases further in the negative direction from the state of IL <0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. An alternating current will be conducted.

2) When the on-duty is 100/3% or more and less than 50% and the step-down operation is:
Next, when the on-duty of the gate drive signal is 100/3% or more and less than 50%, as shown in FIG. 28C, the switching mode G → J → H → K → F → I → G In this order, and makes a round with a period T.
Similarly to the power running operation, the voltages VL in the switching modes F, G, and H are equal in time average, and (V1−Vc0b) = (− V2 + Vc0b−Vc0a) = (− V2 + Vc0a).
The voltages VL in the switching modes I, J, and K are also equal on a time average basis, and the relationship is (V1−Vc0a) = (− V2 + Vc0b) = (V1−Vc0b + Vc0a). Accordingly, as in the case where the on-duty of the gate drive signal is less than 100/3%, the voltages at both ends of the energy transfer capacitor are Vc0b = (2/3) · (V1 + V2) and Vc0a = (1/3). ) · (V1 + V2).
Thus, the potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary side connection terminal voltage V1, and the secondary side connection terminal voltage V2 of the FET1, FET2, and FET3 are expressed by the equations (11a) and (11b). ), The relationship of Expression (12) is established.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage converter 1 is represented by the equation (13).
In an operation in which the on-duty of the gate drive signal is 100/3% or more and less than 50%, (1/3) ≦ (ton / T) <(1/2), and DC / The DC voltage conversion ratio is ½ or more and less than 1. Therefore, (V1 / 2) ≦ V2 <V1. That is, the secondary side terminal voltage V2 is stepped down to a voltage that is (1/2) times or more and less than 1 time the primary side terminal voltage V1.

From these, in the switching modes F, G, and H, the voltage VL at the connection terminal on the FET4 side of the inductor L is in the range of 0 to (−V1 / 3), and the voltage at the connection terminal on the negative electrode side terminal N1 side of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL further increases in the negative direction.
In the switching modes I, J, and K, the voltage VL at the FET4 side connection terminal of the inductor L is in the range of (V1 / 2) to (V1 / 3), and the voltage at the connection terminal on the negative electrode side N1 side of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL changes in the positive direction when IL <0.

As described above, in the switching mode G → J → H → K → F → I → G,
In the switching modes F, G, and H, the inductor current IL increases from the state of IL <0 further in the negative direction,
In the switching modes I, J, and K, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. An alternating current will be conducted.

3) When the on-duty is 50% or more and less than 100 × (2/3)% and the boost operation is performed
Next, when the on-duty of the gate drive signal is 50% or more and less than 100 × (2/3)%, as shown in FIG. 29 (c), the switching mode G → J → H → K → F It changes in the order of → I → G, and makes a round with a period T.
Item 2) at the time of the regenerative operation As in the case of the step-down operation with the on-duty being 100% or more and less than 50%, the voltages VL in the switching modes F, G, and H are equal in time average, and (V1− Vc0b) = (− V2 + Vc0b−Vc0a) = (− V2 + Vc0a).
In addition, the voltages VL in the switching modes I, J, and K are also equal in time average, and the relationship is (V1−Vc0a) = (− V2 + Vc0b) = (V1−Vc0b + Vc0a). From these, as in the case where the on-duty of the gate drive signal is less than 100/3%, the voltage across the energy transfer capacitor is Vc0b = (2/3) · (V1 + V2),
Vc0a = (1/3) · (V1 + V2).
Accordingly, the potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary side connection terminal voltage V1, and the secondary side connection terminal voltage V2 of the FET1, FET2, and FET3 are similarly expressed by the equations (11a) and (11). The relationship of (11b) and Formula (12) is established.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage converter 1 is expressed by the equation (13),
In an operation in which the on-duty of the gate drive signal is 50% or more and less than 100 × (2/3)%, (1/2) ≦ (ton / T) <(2/3), and Expression (13) When applied, the DC / DC voltage conversion ratio is 1 or more and less than 2. Therefore, V1 ≦ V2 <(2 · V1). That is, the secondary terminal voltage V2 is boosted to a voltage that is higher than 1 time and lower than twice the primary side terminal voltage V1.

From these, in the switching modes F, G, and H, the voltage VL of the FET4 side connection terminal of the inductor L is in the range of (−V1 / 3) to (−V1), and the connection terminal of the inductor L on the negative electrode side terminal N1 side. Is 0. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL further increases in the negative direction.
In the switching modes I, J, and K, the voltage VL at the connection terminal on the FET4 side of the inductor L is in the range of 0 to (V1 / 3), and the voltage at the connection terminal on the negative electrode side terminal N1 side of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes positive, and the inductor current IL changes in the positive direction when IL <0.

As described above, the same as in the case of the step-down operation when the on-duty is 100/3% or less and less than 50% and the switching mode G → J → H → K → F → I → G In switching,
In the switching modes F, G, and H, the inductor current IL increases from the state of IL <0 further in the negative direction,
In the switching modes I, J, and K, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.
From this, the increase and decrease of the inductor current IL are repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. An alternating current will be conducted.

4) When the on-duty is 100 x (2/3)% or more and boosting operation:
Further, when the on-duty of the gate drive signal is 100 × (2/3)% or more, as shown in FIG. 30C, the switching mode M → K → M → I → M → J → M It switches in order and makes one round with the period T.
Similarly to the power running operation, the voltages VL in the switching modes I, J, and K are equal in terms of time average, and the relationship is (V1−Vc0a) = (− V2 + Vc0b) = (V1−Vc0b + Vc0a).
Therefore, Vc0b = (2/3) · (V1 + V2),
Vc0a = (1/3) · (V1 + V2).
The potential difference between both ends of the inductor L, the switch-on time ton, the switch-off time toff, the primary terminal voltage V1, and the secondary terminal voltage V2 of the FET1, FET2, and FET3 are expressed by the equation (14a), as in the powering operation. The relationship of Formula (14b) and Formula (15) is established.

Therefore, the voltage conversion ratio (V2 / V1) of the DC / DC voltage converter 1 is represented by the equation (16).
In an operation in which the on-duty of the gate drive signal is 100 × (2/3)% or more, (2/3) ≦ (ton / T), and the DC / DC voltage conversion ratio is 2 or more when applied to the equation (16). It becomes. Therefore, (2 × V1) ≦ V2. That is, the secondary terminal voltage V2 is boosted to a voltage higher than twice the primary terminal voltage V1.

Accordingly, in the switching modes I, J, and K, the voltage VL at the connection terminal on the FET4 side of the inductor L is VL ≦ 0, and the voltage at the connection terminal on the negative electrode side N1 side of the inductor L is 0. Therefore, the potential difference between both ends of the inductor L becomes negative, and the inductor current IL further increases in the negative direction.
In the switching mode M, as described above, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.

As described above, in the switching mode M → K → M → I → M → J → M,
In switching modes I, J, and K, the inductor current IL further increases in the negative direction,
In the switching mode M, the inductor current IL changes from the state of IL <0 toward the state of IL ≧ 0.
Therefore, the increase and decrease of the inductor current IL is repeated three times in the T / 3 period over the switching period T of the field effect transistor, and the inductor L has a frequency three times the switching frequency of the field effect transistor. AC current will be conducted.

As described above, the DC / DC voltage converter according to the fourth embodiment has the inductor L three times as large as the switching frequency of the field effect transistor in both the power running operation and the regenerative operation. AC current with a frequency of
Accordingly, since the frequency of the ripple current component of the inductor L is further increased as compared with the DC / DC voltage conversion device in the first embodiment, the inductance of the inductor L can be reduced, and the volume and weight of the inductor are reduced. Compared to the conventional technology, it is significantly reduced.

  As described as a modification of the first embodiment, the switching frequency of the field-effect transistor is the same as that of the first embodiment even when the frequency of the AC component flowing through the inductor L is set to be equal to or higher than the upper limit of the audible frequency. Since it may be set to a lower value, there is an advantage that the switching loss and the like can be reduced as compared with the case of the first embodiment.

In addition, the same effects as those of the first embodiment can be obtained. That is, since the field effect transistor is made of a wide band gap semiconductor material, even if the output power capacity of the DC / DC voltage converter increases and the loss generated in the semiconductor unit increases, Since the heat-resistant temperature becomes high, it is possible to realize a small and lightweight DC / DC voltage conversion device while expanding the output power capacity that can be handled and improving the power density.
Further, it is possible to eliminate or reduce the generation of annoying audible noise, which is remarkable with the inductor L, the energy transfer capacitors C0a and C0b, and the smoothing capacitors C1 and C2.

As mentioned above, although the Example regarding this invention was demonstrated by Embodiment 1-Embodiment 4, these are only what illustrated the preferable Example of this invention.
For example, although the upper limit of the audible frequency is 20 kHz, the upper limit of the audible frequency as an index can be set to another value for the purpose of solving the problem of audible noise of the DC / DC voltage converter. .
The present invention is not limited to the configurations and operations of these embodiments, and may be implemented with modifications to other configurations and operations as long as they are within the scope of the present invention.

1 DC / DC voltage converter, 2 conversion main circuit, 3 control unit, 4 DC power supply,
5 Electrical equipment, 8 Gate drive signal, 11, 11a, 11b Gate PWM generator,
12, 12a Gate drive circuit, 23 circuit switcher, 25, 26 switch-off circuit, 271, 273 temperature detection diode, 28 inductor temperature detector,
29 capacitor temperature detector, C1, C2 smoothing capacitor,
C0, C0a, C0b Energy transfer capacitors,
FET1-FET6 Field effect transistor, L inductor.

Claims (16)

A DC / DC voltage converter that includes a conversion main circuit and a control unit, and exchanges power in both directions between the primary side and the secondary side to perform DC voltage conversion of the step-up / down,
The main conversion circuit includes a primary side smoothing capacitor connected between the primary side positive side terminal and the negative side terminal and smoothing the primary side voltage; the secondary side positive side terminal and the negative side terminal; , A secondary side smoothing capacitor that smoothes the secondary side voltage, an energy transfer capacitor and inductor that stores and discharges energy, and a semiconductor that can perform on / off switching operation and reverse conduction operation 2n (n is an integer of 2 or more) units connected in series and connected between the primary side positive side terminal and the secondary side negative side terminal, and a power module,
The primary side negative side terminal is connected to the secondary side positive side terminal,
The control unit divides the 2n semiconductor units into two pairs of n pairs, and has a complementary relationship in which on / off of the pair of semiconductor units constituting each pair is opposite to each other. And controlling the alternating current component of the current flowing through the inductor to be n times the switching frequency for controlling the on / off of the semiconductor unit,
The energy transfer capacitor is the semiconductor unit except for the semiconductor unit directly connected to the primary-side positive terminal and the semiconductor unit directly connected to the secondary-side negative terminal. In a pair of semiconductor units, connected between a terminal closest to the primary positive terminal on the primary side and a terminal closest to the secondary negative terminal on the secondary side,
The inductor is a DC / DC voltage converter that is connected between the connection point of the pair of semiconductor units that are directly connected to each other and the negative terminal on the primary side. The power module is composed of four semiconductor units connected in series, first, second, third, and fourth, in order from the one connected to the positive terminal on the primary side,
The control unit controls the first and fourth semiconductor units, the second and third semiconductor units as the pair, respectively.
The energy transfer capacitor is connected between a connection point of the first and second semiconductor units and a connection point of the third and fourth semiconductor units,
2. The DC / DC voltage converter according to claim 1, wherein the inductor is connected between a connection point of the second and third semiconductor units and the negative terminal on the primary side. The control unit is configured such that when the primary side voltage is V1, and the secondary side voltage is V2,
When power is supplied from the primary side to the secondary side, the voltage conversion ratio (V2 / V1) is less than 1 by controlling on / off of the first and second semiconductor units with an on-duty of less than 50%. The step-down operation is performed and the voltage conversion ratio (V2 / V1) is increased to 1 or more by performing on-off control with an on-duty of 50% or more.
When power is supplied from the secondary side to the primary side, the voltage conversion ratio (V2 / V1) is less than 1 by controlling on / off of the first and second semiconductor units with an on-duty of less than 50%. The DC / DC converter according to claim 2, wherein the step-down operation is performed and the voltage conversion ratio (V2 / V1) is set to 1 or more by performing on-off control with an on-duty of 50% or more. DC voltage converter. The power module is composed of six semiconductor units connected in series, first, second, third, fourth, fifth, and sixth, in order from the one connected to the positive terminal on the primary side. And
The control unit controls the first and sixth semiconductor units, the second and fifth semiconductor units, and the third and fourth semiconductor units as the pair, respectively.
The energy transfer capacitor includes a first capacitor connected between a connection point of the second and third semiconductor units and a connection point of the fourth and fifth semiconductor units, and the first and second capacitors. And a second capacitor connected between the connection point of the semiconductor unit and the connection point of the fifth and sixth semiconductor units,
2. The DC / DC voltage converter according to claim 1, wherein the inductor is connected between a connection point of the third and fourth semiconductor units and the negative terminal on the primary side. The control unit is configured such that when the primary side voltage is V1, and the secondary side voltage is V2,
When power is supplied from the primary side to the secondary side, the first, second, and third semiconductor units are each turned on / off with an on-duty less than (100 × (1/3))%. The voltage conversion ratio (V2 / V1) is reduced by performing a step-down operation in which the conversion ratio (V2 / V1) is less than (1/2) and performing on / off control with an on-duty of (100 × (1/3))% or more and less than 50%. The voltage conversion ratio (V2 / V1) is reduced by performing a step-down operation in which V1) is (1/2) or more and less than 1 and ON / OFF control is performed with an on-duty of 50% or more (100 × (2/3))%. A boost operation is performed so that the voltage conversion ratio (V2 / V1) is 2 or more by performing on / off control with an on-duty of (100 × (2/3)) or more.
When power is supplied from the secondary side to the primary side, the first, second, and third semiconductor units are each turned on and off with an on-duty control less than (100 × (1/3))%. The voltage conversion ratio (V2 / V1) is reduced by performing a step-down operation in which the conversion ratio (V2 / V1) is less than (1/2) and performing on / off control with an on-duty of (100 × (1/3))% or more and less than 50%. The voltage conversion ratio (V2 / V1) is reduced by performing a step-down operation in which V1) is (1/2) or more and less than 1 and ON / OFF control is performed with an on-duty of 50% or more (100 × (2/3))%. A boost operation is performed so that the voltage conversion ratio (V2 / V1) is 2 or more by performing a boost operation of 1 or more and less than 2 and performing on / off control with an on-duty of (100 × (2/3)) or more. Characterized by DC / DC voltage converter according to claim 4, wherein. The said control unit sets the said switching frequency so that the alternating current component of the electric current which flows into the said inductor may become a frequency more than the upper limit of an audible frequency, DC / of any one of Claim 1 thru | or 5 characterized by the above-mentioned. DC voltage converter. The DC / DC voltage converter according to any one of claims 1 to 6, wherein the semiconductor unit is a field effect transistor. The control unit makes the switching frequency equal to or higher than the upper limit of the audible frequency,
8. The DC / DC voltage converter according to claim 7, wherein the field effect transistor is formed of a wide band gap semiconductor having a band gap larger than that of silicon. The control unit makes the switching frequency equal to or higher than the upper limit of the audible frequency,
Each of the semiconductor units is composed of a field effect transistor formed of a wide band gap semiconductor whose band gap is larger than that of silicon, and a rectifier element connected in reverse parallel to the field effect transistor. The DC / DC voltage converter according to any one of claims 1 to 6. The control unit makes the switching frequency equal to or higher than the upper limit of the audible frequency,
7. The semiconductor unit according to claim 1, wherein the semiconductor unit is composed of an IGBT and a rectifying element formed of a wide band gap semiconductor connected in anti-parallel with the IGBT and having a band gap larger than that of silicon. The DC / DC voltage converter of any one of Claims. The DC / DC voltage converter according to any one of claims 8 to 10, wherein the wide band gap semiconductor is any one of silicon carbide, gallium nitride, and diamond. The control unit adjusts the falling steepness when the gate signal to the semiconductor unit is lowered and the semiconductor unit is turned off based on an on-duty that is a ratio of an on-time of the semiconductor unit to a switching cycle. The DC / DC voltage converter according to any one of claims 1 to 11, further comprising an off signal adjusting unit. The off signal adjusting means includes a predetermined first set value regarding the falling steepness, a second set value smaller than the first set value, a predetermined first threshold value regarding the on-duty, and the first set value. Providing a second threshold greater than the threshold;
When the on-duty is less than the first threshold, the falling steepness is set as the first set value, and when the on-duty is increased to be equal to or higher than the second threshold, the falling steepness is set. Is switched to the second set value, and when the on-duty falls and becomes less than the first threshold value, the falling steepness is switched to the first set value. The DC / DC voltage converter according to claim 12. The control unit is configured to detect a temperature of the energy transfer capacitor, the inductor, and the semiconductor unit, and to set the switching frequency based on the detected temperature of the energy transfer capacitor, the inductor, and the semiconductor unit. The DC / DC voltage converter according to any one of claims 1 to 13, further comprising a switching frequency adjusting means for adjusting. The switching frequency adjusting means is configured to increase the switching frequency when the detection temperature of the energy transfer capacitor and the inductor is increased, and to decrease the switching frequency when the detection temperature of the semiconductor unit is increased. The DC / DC voltage converter according to claim 14, wherein the switching frequency is adjusted. Incorporated in a vehicle electric drive system comprising a DC power source, a rotating electrical machine serving as a driving power source for a vehicle, and an inverter connected to the rotating electrical machine and performing power conversion between a DC voltage and an AC voltage Because
16. The method according to claim 1, wherein the DC power source is inserted between the DC power source and the inverter and bi-directionally exchanges power between the DC power source and the inverter to perform step-up / step-down DC voltage conversion. The DC / DC voltage converter of any one of Claims.

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