JP2012169891A - Counter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a counter circuit that performs double precision measurement while using a smaller circuit scale and/or lower power consumption than before.SOLUTION: The counter circuit includes: a first circuit for counting pulses in synchronism with rising edges of a clock signal for a measuring period to generate a first count value; a second circuit for counting pulses in synchronism with falling edges of the clock signal for the measuring period to generate a second count value; a third circuit for holding flag information indicating an order relationship between the rising edges and the falling edges of the clock signal in the measuring period; and a fourth circuit for decoding the first count value and second count value according to the flag information to output a measured count value with double precision with respect to the frequency of the clock signal.

Description

  The present invention relates to a counter circuit used for counting the number of pulses of a clock signal in a set measurement period.

  For example, in a pressure measurement control circuit using a crystal resonator as a sensor element, after generating a divided signal by dividing a sensor pulse signal obtained by an oscillation operation using a crystal resonator by an arbitrary division ratio, In the measurement period determined by the pulse width of the divided signal, the pulse width of the divided signal is obtained by counting the number of pulses of the reference clock signal, and the measured pressure value is obtained based on the pulse width of the divided signal. ing.

  Here, in order to improve the measurement accuracy (resolution), it is conceivable to increase the frequency of the reference clock signal. For example, it is conceivable to generate a clock signal having a high frequency by multiplying a reference clock signal using a PLL (phase locked loop) circuit and to count the number of pulses.

  However, using a PLL circuit or generating a high-frequency clock signal by other methods in order to acquire highly accurate measurement values leads to complication of the configuration of the pressure measurement control circuit and the entire system. This leads directly to increased design burden, increased costs, and increased current consumption. Therefore, it is desired to improve measurement accuracy without increasing the frequency of the reference clock signal.

  As a related technique, Patent Document 1 discloses that a pulse to be measured has a half cycle accuracy of a sampling clock signal without changing the frequency of the sampling clock signal (reference clock signal), that is, twice the accuracy of the conventional circuit. A pulse width measuring counter circuit capable of measuring the pulse width of the above is disclosed.

  As shown in FIGS. 1 and 3 of Patent Document 1, this pulse width measurement counter circuit operates only during a period (pulse width PW period) in which the measured pulse 21 is at a high level or a low level. A first-stage frequency divider that outputs a signal obtained by dividing the frequency of the sampling clock signal by 1/2, and a first-stage frequency divider that is synchronized with the sampling clock signal 22 having a predetermined period sufficiently shorter than the length of the period; One or a plurality of post-stage dividers (D flip-flops 2 to 4 etc.) that output a signal obtained by dividing the frequency of the output signal by 1/2, and sequentially cascade the output signal. A counter circuit for measuring the pulse width of the pulse to be measured from the output signals (counter outputs C0 to C3, etc.) of each frequency dividing means at the end of the period, wherein the first stage frequency dividing means The first first-stage frequency dividing means (D flip-flop 11) that operates at the rising edge of the sampling clock signal and the second first-stage frequency dividing means (D flip-flop 12) that operates at the falling edge of the sampling clock signal. Divide and synthesize the output signals of these two first stage frequency dividers, output a signal synchronized with the sampling clock signal and the same frequency as the sampling clock signal, and one of the output signals of the two first stage frequency dividers exists If not, the subsequent stage frequency dividing means are connected in cascade in sequence through a signal synthesizing means for outputting a signal corresponding to the other output signal.

  Patent Document 2 discloses a counter device that can increase the counting accuracy without increasing the clock frequency and can suppress a significant increase in the current consumption of the counter unit.

  As shown in FIG. 1 and FIG. 2 of Patent Document 2, this counter device receives a signal in common, and counts a predetermined level period of this signal using a clock signal (reference clock signal). Counter means (counter units 1 and 2), clock supply means (inverter 5) for supplying clock signals shifted in timing to the counter means, and adding means (adder) for adding the count values of these counter means And 6).

Japanese Patent Laid-Open No. 10-28048 (page 3, FIG. 1, FIG. 3) JP 2001-298360 A (2nd page, FIG. 1, FIG. 2)

  According to Patent Document 1 and Patent Document 2, the pulse width of the pulse to be measured can be measured with double the accuracy of the conventional circuit without increasing the frequency of the reference clock signal. However, in Patent Document 1, three frequency dividing means (D flip-flops 11, 12, and 2 in FIG. 1) that change an output signal in synchronization with a sampling clock signal or a signal having the same frequency as the sampling clock signal are used. As a result, the power consumption increases. In Patent Document 2, since a plurality of counter means (counter units 1 and 2 in FIG. 1) having the same number of bits are used, the circuit scale and power consumption are increased.

  A counter circuit according to one aspect of the present invention is a counter circuit that counts the number of pulses of a clock signal in a set measurement period, and counts the number of pulses in synchronization with a rising edge of the clock signal in the measurement period. A first circuit for generating a first count value, and a second circuit for generating a second count value by counting the number of pulses in synchronization with the falling edge of the clock signal in the measurement period. The clock signal is obtained by decoding the first count value and the second count value according to the third circuit that holds the flag information indicating the front-rear relationship between the rising edge and the falling edge of the clock signal in the measurement period. And a fourth circuit for outputting a measurement count value of double precision with respect to the period.

  According to one aspect of the present invention, only the first circuit and the second circuit change the output signal in synchronization with the clock signal, and among the first circuit and the second circuit, Since one of them only needs to generate a 1-bit count value, it is possible to realize a counter circuit that performs double-precision measurement while reducing the circuit scale and / or power consumption compared to the conventional one. Therefore, it is advantageous in improving the ease of design, reducing power consumption, and / or reducing costs.

  Here, the first count value or the second count value is a count value of N bits (N is an integer of 2 or more), and the N-bit first count value and the least significant bit of the second count value are combined ( The fourth circuit based on the (N + 1) -bit first combined count value or the (N + 1) -bit second combined count value obtained by combining the N-bit second count value and the least significant bit of the first count value However, at least the lower 2 bits of the first combined count value or the second combined count value may be decoded. For example, when the lower 2 bits of the first combined count value are decoded, the upper (N-1) bit of the first count value is not decoded and is used as the upper (N-1) bit of the measurement count value. Can be used.

  Further, the fourth circuit sets the lower 2 bits “0, 0” of the first combined count value to “0, when the first rising edge of the clock signal in the measurement period is before the first falling edge. 0 ”, lower 2 bits“ 1, 0 ”are decoded to“ 0, 1 ”, lower 2 bits“ 1, 1 ”are decoded to“ 1, 0 ”, and lower 2 bits“ 0, 1 ” When the first rising edge of the clock signal in the measurement period is later than the first falling edge, the lower 2 bits “0, 0” of the first combined count value are decoded. Decode to “0, 0”, lower 2 bits “0, 1” to “0, 1”, lower 2 bits “1, 1” to “1, 0”, lower 2 bits “1” , 0 ”may be decoded to“ 1, 1 ”. As described above, when the content of the decoding operation is relatively simple, the lower 2 bits of the first combined count value and the flag information held in the third circuit are used for DFT (Design For Testability (testability: design for testability) can be a target of scanning, and testability at the time of shipment selection is improved.

  In the above, the first circuit includes the first flip-flop that changes the output signal in synchronization with the rising edge of the clock signal, and the second circuit outputs the output signal in synchronization with the falling edge of the clock signal. An exclusive OR circuit for calculating an exclusive OR between the output signal of the first flip-flop and the output signal of the second flip-flop, and a measurement period. And a third flip-flop for latching the output signal of the exclusive OR circuit in synchronization with the rising edge of the clock signal. In that case, the configuration of the third circuit can be made relatively simple.

The figure of the pressure measurement control circuit using the counter circuit concerning one embodiment of the present invention. The timing chart which shows the count operation | movement of the pressure measurement control circuit shown in FIG. The timing chart which shows the count operation | movement of the pressure measurement control circuit shown in FIG. The figure for demonstrating the decoding operation | movement of the decoder shown in FIG. The figure for demonstrating the decoding operation | movement of the decoder shown in FIG. The figure which shows the 2nd circuit example of the edge information holding circuit shown in FIG. The figure which shows the 3rd circuit example of the edge information holding circuit shown in FIG. The figure which shows the 4th circuit example of the edge information holding circuit shown in FIG. The figure which shows the 5th circuit example of the edge information holding circuit shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a diagram showing a partial configuration of a pressure measurement control circuit using a counter circuit according to an embodiment of the present invention. This pressure measurement control circuit uses a crystal resonator as a sensor element, inputs a sensor pulse signal (sensor clock signal) SCK obtained by an oscillation operation using the crystal resonator, and is a measurement period determined by the sensor clock signal SCK. The number of pulses of the reference clock signal RCK is counted and a pressure measurement value is obtained based on this count value.

  In FIG. 1, a gate counter 10 that counts the number of pulses of the sensor clock signal SCK, a measurement period setting circuit 20 that sets a measurement period based on a count value output from the gate counter 10, and a measurement period setting circuit 20 A measurement counter 30 that counts the number of pulses of the reference clock signal RCK in the set measurement period is shown.

  The gate counter 10 is configured as, for example, an 18-bit toggle counter (up counter in the present embodiment). While the gate counter enable signal GCE input to the set terminal SET of the gate counter 10 is inactivated to the low level, the least significant bit BIT0 to the most significant bit BIT17 of the count value of the gate counter 10 are set to the high level. Is done. When the gate counter enable signal GCE is activated to a high level, the least significant bit BIT0 to the most significant bit BIT17 of the count value of the gate counter 10 once become a low level, and the gate counter 10 pulses the sensor clock signal SCK. Start counting the number. The gate counter 10 changes the least significant bit BIT0 of the count value to the high level when counting the first pulse, and sets the most significant bit BIT17 of the count value to the high level when counting the 2 17th pulse. When the second 18th pulse is counted, the most significant bit BIT17 of the count value is changed to a low level. The least significant bit BIT0 and the most significant bit BIT17 of the count value are supplied to the measurement period setting circuit 20.

The measurement period setting circuit 20 includes two D flip-flops DF21 and DF22. The D flip-flops DF21 and DF22 reset the output signal to the low level while the gate counter enable signal GCE is inactivated to the low level. When the least significant bit BIT0 of the count value of the gate counter 10 is changed to a low level after the gate counter enable signal GCE is activated to a high level, the D flip-flop DF21 is input to the data input terminal D at a high level ( The signal of the power supply potential V _DD ) is latched, and a high level count start signal CST is output from the output terminal Q. Thereafter, when the most significant bit BIT17 of the count value of the gate counter 10 changes to a low level, the D flip-flop DF22 latches the high-level count start signal CST input to the data input terminal D, and outputs from the output terminal Q. A high level count end signal CED is output.

  Here, a period from when the count start signal CST shifts to a high level until the count end signal CED shifts to a high level is set as a measurement period. In the above description, the least significant bit BIT0 and the most significant bit BIT17 of the count value of the gate counter 10 are used to generate the count start signal CST and the count end signal CED. Other bits may be used. By doing so, it is possible to divide the sensor clock signal SCK by an arbitrary division ratio to generate a divided signal (count value), and to set the measurement period according to the pulse width of the divided signal. The count start signal CST and the count end signal CED are supplied to the measurement counter 30.

  The measurement counter 30 is a counter circuit according to an embodiment of the present invention, and includes a latch flip-flop LF31, a main counter 31, a sub-counter 32, an edge information holding circuit 33, and a decoder 34. The latch flip-flop LF31 outputs the reference clock signal RCK input to the data input terminal D as the gate clock signal GCK while the count end signal CED is inactivated to the low level, and the count end signal CED is high. When activated to the level, the reference clock signal RCK is latched, and the output signal is fixed to the high level or the low level.

  The main counter 31 includes N D flip-flops DF31 to DF33 (N is an integer of 2 or more). In each of the D flip-flops DF31 to DF33, an inverted output signal output from the inverted output terminal Q bar is supplied to the data input terminal D. Each of the D flip-flops DF31 to DF33 is reset while the count start signal CST is inactivated to the low level, and the output signal is set to the low level and the inverted output signal is set to the high level.

  When the count start signal CST is activated to a high level, the D flip-flop DF31 changes the levels of the output signal and the inverted output signal in synchronization with the rising edge of the gate clock signal GCK supplied from the latch flip-flop LF31. As a result, the gate clock signal GCK is divided by two.

  The inverted output terminal Q bar of the D flip-flop DF31 is connected to the clock signal input terminal of the next-stage D flip-flop DF32. Are connected in series. As a result, the gate clock signal GCK is sequentially divided by two.

  The latch flip-flop LF31 supplies the gate clock signal GCK to the main counter 31 while the count end signal CED is inactivated to a low level, and counts after the measurement period set by the measurement period setting circuit 20 elapses. When the end signal CED is activated to a high level, the supply of the gate clock signal GCK is stopped. Accordingly, the main counter 31 counts the number of pulses in synchronization with the rising edge of the gate clock signal GCK during the measurement period set by the measurement period setting circuit 20, thereby providing an N-bit main count value CM (the least significant bit). CM0 to most significant bit CM (N-1)) are generated.

  The sub-counter 32 includes a D flip-flop DF34. In the D flip-flop DF34, the inverted output signal output from the inverted output terminal Q bar is supplied to the data input terminal D. The D flip-flop DF34 is reset while the count start signal CST is inactivated to the low level, and sets the output signal to the low level and the inverted output signal to the high level. When the count start signal CST is activated to a high level, the D flip-flop DF31 changes the levels of the output signal and the inverted output signal in synchronization with the falling edge of the gate clock signal GCK supplied from the latch flip-flop LF31. By doing so, the gate clock signal GCK is divided by two.

  The latch flip-flop LF31 supplies the gate clock signal GCK to the sub-counter 32 while the count end signal CED is inactivated to the low level, and counts after the measurement period set by the measurement period setting circuit 20 elapses. When the end signal CED is activated to a high level, the supply of the gate clock signal GCK is stopped. Therefore, the sub-counter 32 generates a 1-bit sub-count value CS by counting the number of pulses in synchronization with the falling edge of the gate clock signal GCK in the measurement period set by the measurement period setting circuit 20. .

  The edge information holding circuit 33 includes an exclusive OR circuit (EOR circuit) EX31 and a D flip-flop DF35. The EOR circuit EX31 obtains an exclusive OR of the output signal of the D flip-flop DF31 of the main counter 31 and the output signal of the D flip-flop DF34 of the sub-counter 32.

  FIG. 1 shows a case where the EOR circuit EX31 obtains an exclusive OR of the inverted output signal of the D flip-flop DF31 and the non-inverted output signal of the D flip-flop DF34, but this circuit example and other circuits are shown. In the example, the EOR circuit EX31 may obtain an exclusive OR of the non-inverted output signal of the D flip-flop DF31 and the inverted output signal of the D flip-flop DF34, An exclusive OR of the non-inverted output signal of the flip-flop DF34 may be obtained, or an exclusive OR of the inverted output signal of the D flip-flop DF31 and the inverted output signal of the D flip-flop DF34 may be obtained. Even if the polarity of the edge information flag FLG is inverted, the decoder 34 can cope with this.

  The output signal of the EOR circuit EX31 is input to the data input terminal D of the D flip-flop DF35. The D flip-flop DF35 is reset while the count start signal CST is inactivated to the low level, and sets the output signal to the low level. When the count start signal CST is activated to the high level, the D flip-flop DF35 outputs the output signal of the EOR circuit EX31 in synchronization with the rising edge of the gate clock signal GCK in the measurement period set by the measurement period setting circuit 20. Is latched (held) to generate an edge information flag FLG.

  The edge information flag FLG is information representing the front-rear relationship between the rising edge and the falling edge of the gate clock signal GCK in the measurement period set by the measurement period setting circuit 20. According to the configuration shown in FIG. 1, when the first rising edge of the gate clock signal GCK is before the first falling edge in the measurement period, the edge information flag FLG becomes high level (“1”), and the measurement is performed. When the first rising edge of the gate clock signal GCK is after the first falling edge in the period, the edge information flag FLG becomes low level (“0”).

  The decoder 34 decodes the predetermined bit of the main count value CM generated by the main counter 31 and the subcount value CS generated by the subcounter 32 according to the value of the edge information flag FLG held in the edge information holding circuit 33. As a result, a double-precision measurement count value CT is obtained.

Hereinafter, the counting operation of the pressure measurement control circuit shown in FIG. 1 will be described in detail.
2 and 3 are timing charts showing the counting operation of the pressure measurement control circuit shown in FIG. FIG. 2 shows a counting operation when the first rising edge of the gate clock signal GCK is before the first falling edge in the measurement period, and FIG. 3 shows the gate clock signal GCK in the measurement period. The counting operation is shown when the first rising edge is after the first falling edge.

  As shown in FIGS. 2 and 3, while the gate counter enable signal GCE is inactivated to the low level, the least significant bit BIT0 and the most significant bit BIT17 of the count value of the gate counter 10 are set to the high level. The Next, when the gate counter enable signal GCE is activated to a high level, the least significant bit BIT0 and the most significant bit BIT17 of the count value of the gate counter 10 are once set to a low level, and the gate counter 10 detects the sensor clock signal SCK. Start counting the number of pulses. The gate counter 10 changes the least significant bit BIT0 of the count value to the high level when counting the first pulse, and sets the most significant bit BIT17 of the count value to the high level when counting the 2 17th pulse. When the second 18th pulse is counted, the most significant bit BIT17 of the count value is changed to a low level.

  When the least significant bit BIT0 of the count value of the gate counter 10 changes to low level, the D flip-flop DF21 of the measurement period setting circuit 20 changes the count start signal CST to high level. When the most significant bit BIT17 of the count value of the gate counter 10 changes to low level, the D flip-flop DF22 of the measurement period setting circuit 20 changes the count end signal CED to high level.

  The latch flip-flop LF31 of the measurement counter 30 outputs the gate clock signal GCK while the count end signal CED is inactivated to the low level, and when the count end signal CED is activated to the high level, the gate clock The signal GCK is fixed at a high level or a low level.

  When the count start signal CST is activated to a high level, the main counter 31 of the measurement counter 30 counts the number of pulses in synchronization with the rising edge of the gate clock signal GCK supplied from the latch flip-flop LF31. An N-bit main count value CM is generated. 2 and 3 also show changes in the least significant bit CM0 of the main count value.

  When the count start signal CST is activated to a high level, the sub-counter 32 of the measurement counter 30 counts the number of pulses in synchronization with the falling edge of the gate clock signal GCK supplied from the latch flip-flop LF31. A 1-bit subcount value CS is generated.

  The edge information holding circuit 33 obtains an exclusive OR of the inverted signal of the least significant bit CM0 of the main count value and the subcount value CS, and latches the exclusive OR in synchronization with the gate clock signal GCK. An edge information flag FLG is generated. As shown in FIG. 2, when the first rising edge of the gate clock signal GCK is before the first falling edge in the measurement period (after the count start signal CST is activated to high level), the edge The information flag FLG becomes high level. On the other hand, as shown in FIG. 3, when the first rising edge of the gate clock signal GCK is later than the first falling edge in the measurement period, the edge information flag FLG becomes low level. Although the latch operation of the D flip-flop DF35 is continued thereafter, the value of the edge information flag FLG is not changed.

  The decoder 34 combines at least one of (N + 1) -bit combined count values obtained by combining the N-bit main count value CM generated by the main counter 31 and the 1-bit sub-count value CS generated by the sub-counter 32. By decoding the lower 2 bits according to the value of the edge information flag FLG, a measurement count value CT that represents the number of pulses of the gate clock signal GCK with double precision is obtained. In FIGS. 2 and 3, the decoder 34 calculates the measurement count value CT as needed. However, the measurement count value CT may be calculated after a series of counting operations in one measurement period is completed.

  4 and 5 are diagrams for explaining the decoding operation of the decoder shown in FIG. FIG. 4 shows a decoding operation when the value of the edge information flag FLG held in the edge information holding circuit 33 is “1”, and FIG. 5 shows the decoding operation held in the edge information holding circuit 33. The decoding operation when the value of the edge information flag FLG being “0” is “0” is shown.

  By combining the N-bit main count value CM generated by the main counter 31 and the 1-bit sub-count value CS generated by the sub-counter 32, a combined count value of (N + 1) bits is obtained. 4 and 5 show the lower 3 bits CM1, CM0, CS of the combined count value and the lower 3 bits of the measurement count value CT obtained as a decoding result.

  The decoder 34 may decode the lower 2 bits of the combined count value, or may decode more bits than that, but a case where the lower 2 bits are decoded will be described below. In that case, the upper (N-1) bits of the main count value generated by the main counter 31 can be used as the upper (N-1) bits of the measurement count value without decoding.

  When the value of the edge information flag FLG held in the edge information holding circuit 33 is “1”, as shown in FIG. 4, the decoder 34 sets the lower 2 bits “0, 0” of the combined count value. Decode to “0, 0”, lower 2 bits “1, 0” of combined count value to “0, 1”, lower 2 bits “1, 1” of combined count value to “1, 0” Then, the lower 2 bits “0, 1” of the combined count value are decoded to “−1, 1”. Here, when the second lower bit CM0 of the combined count value becomes “−1”, the decoder 34 decrements the value of the third lower bit CM1 of the combined count value (marked with a asterisk in FIG. 4). This carry-down may spill over to the fourth lower-order bit of the combined count value (for example, when the decoding result is “111 (7)”).

  On the other hand, when the value of the edge information flag FLG held in the edge information holding circuit 33 is “0”, as shown in FIG. 5, the decoder 34 uses the lower two bits “0, 0” of the combined count value. ”Is decoded to“ 0, 0 ”, the lower 2 bits“ 0, 1 ”of the combined count value are decoded to“ 0, 1 ”, and the lower 2 bits“ 1, 1 ”of the combined count value are“ 1, 0 ” And the lower two bits “1, 0” of the combined count value are decoded into “1, 1”.

  In this way, when the content of the decoding operation is relatively simple, the lower 2 bits of the combined count value and the value of the edge information flag FLG held in the edge information holding circuit 33 are used in DFT in IC design. (Design For Testability) makes it possible to be a target of scanning, and the testability at the time of shipping selection is improved.

  According to this embodiment, in FIG. 1, only the D flip-flops DF31 and DF34 change the output signal in synchronization with the clock signal, and the sub-counter 32 only generates a 1-bit count value. Thus, it is possible to realize a counter circuit that performs double-precision measurement while reducing the circuit scale and / or power consumption as compared with the prior art. Therefore, it is advantageous in improving the ease of design, reducing power consumption, and / or reducing costs.

Hereinafter, another circuit example of the edge information holding circuit shown in FIG. 1 will be described.
FIG. 6 is a diagram showing a second circuit example of the edge information holding circuit shown in FIG. The edge information holding circuit 33a includes an exclusive OR circuit (EOR circuit) EX31 and D flip-flops DF36 and DF37. The EOR circuit EX31 obtains an exclusive OR of the output signal (inverted output signal) of the D flip-flop DF31 of the main counter and the output signal (non-inverted output signal) of the D flip-flop DF34 of the sub-counter.

  The D flip-flop DF36 is reset while the count start signal CST is inactivated to the low level, and sets the output signal to the low level. When the count start signal CST is activated to the high level, the D flip-flop DF36 activates the output signal to the high level by latching the high level signal in synchronization with the rising edge of the gate clock signal GCK. .

  The output signal of the EOR circuit EX31 is input to the data input terminal D of the D flip-flop DF37, and the output signal of the D flip-flop DF36 is input to the clock signal input terminal of the D flip-flop DF37. The D flip-flop DF37 is reset while the count start signal CST is inactivated to the low level, and sets the output signal to the low level. When the count start signal CST is activated to a high level, the D flip-flop DF37 latches the output signal of the EOR circuit EX31 in synchronization with the rising edge of the output signal of the D flip-flop DF36, whereby the edge information flag FLG Is generated.

  According to the second circuit example shown in FIG. 6, since the D flip-flop DF37 latches the output signal of the EOR circuit EX31 only once in one measurement period, there is a risk of malfunction due to multiple latches. Disappears.

  FIG. 7 is a diagram showing a third circuit example of the edge information holding circuit shown in FIG. The edge information holding circuit 33b includes a flip-flop DF38 that latches the gate clock signal GCK in synchronization with the rising edge of the count start signal CST. The edge information flag FLG is output from the inverting output terminal Q bar of the flip-flop DF38.

  If the first rising edge of the gate clock signal GCK is before the first falling edge in the measurement period after the count start signal CST is activated to the high level, the gate is turned on when the count start signal CST rises. Since the clock signal GCK is at a low level, the edge information flag FLG is at a high level (“1”). On the other hand, when the first rising edge of the gate clock signal GCK is later than the first falling edge in the measurement period, the gate clock signal GCK is at the high level when the count start signal CST rises. The flag FLG becomes low level (“0”).

  According to the third circuit example shown in FIG. 7, the configuration of the edge information holding circuit can be greatly simplified. Further, since the D flip-flop DF38 latches the gate clock signal GCK only once in one measurement period, there is no possibility of malfunction due to multiple latches.

  FIG. 8 is a diagram showing a fourth circuit example of the edge information holding circuit shown in FIG. The edge information holding circuit 33c includes an OR circuit (OR circuit) 35, a selector 36, and a D flip-flop DF39. The OR circuit 35 inputs the least significant bit CM0 to the most significant bit CM (N−1) of the main count value output from the main counter 31, and when all the bits are at the low level (“0”). The output signal is set to a low level, and the output signal is set to a high level when at least one bit is at a high level (“1”).

  The selector 36 selects the output signal (subcount value CS) of the D flip-flop DF34 of the subcounter 32 and the output signal of the OR circuit 35 when the output signal of the OR circuit 35 is at a low level (“0”). Is at the high level (“1”), the output signal of the D flip-flop DF39 is selected. The D flip-flop DF39 latches the output signal of the selector 36 in synchronization with the rising edge of the gate clock signal GCK when the count start signal CST is activated to a high level, and receives edge information from the inverted output terminal Q bar. The flag FLG is output.

  Since the main count value CM is “0” at the time when the gate clock signal GCK rises immediately after the count start signal CST is activated to the high level, the selector 36 selects the sub-count value CS. Therefore, when the first rising edge of the gate clock signal GCK is before the first falling edge in the measurement period, the D flip-flop DF39 latches the low-level (“0”) subcount value CS. The high level (“1”) edge information flag FLG is output. After that, when the gate clock signal GCK rises, the main count value becomes “1” or more, so the selector 36 selects the output signal of the D flip-flop DF39, and the D flip-flop DF39 latches the low-level output signal. Then, the edge information flag FLG is maintained at a high level (“1”).

  On the other hand, when the first rising edge of the gate clock signal GCK is later than the first falling edge in the measurement period, the D flip-flop DF39 latches the high-level (“1”) subcount value CS. Then, the low level (“0”) edge information flag FLG is output. After that, when the gate clock signal GCK rises, the main count value becomes “1” or more, so the selector 36 selects the output signal of the D flip-flop DF39, and the D flip-flop DF39 latches the high-level output signal. Then, the edge information flag FLG is maintained at the low level (“0”).

  According to the fourth circuit example shown in FIG. 8, when the main count value becomes “1” or more, the value of the edge information flag FLG output from the D flip-flop DF39 is maintained. There is no possibility that the value of the information flag FLG changes.

  FIG. 9 is a diagram showing a fifth circuit example of the edge information holding circuit shown in FIG. The edge information holding circuit 33d includes an inverter 37, AND circuits (AND circuits) 38 to 40, and D flip-flops DF40 and DF41. The inverter 37 inverts the gate clock signal GCK.

  The AND circuit 38 inputs the gate clock signal GCK to the input terminal and inputs the output signal of the D flip-flop DF41 to the inverting input terminal. The AND circuit 39 inputs an inverted signal of the gate clock signal GCK to an input terminal, and inputs an output signal of the D flip-flop DF40 to an inverted input terminal. Further, the AND circuit 40 inputs the output signal of the D flip-flop DF40 to the inverting input terminal, inputs the output signal of the D flip-flop DF41 to the input terminal, and outputs the edge information flag FLG from the output terminal.

  When the first rising edge of the gate clock signal GCK is before the first falling edge in the measurement period, the gate clock signal GCK becomes low level when the count start signal CST is activated to high level. Therefore, the output signal of the D flip-flop DF40 is maintained at a low level, and the output signal of the D flip-flop DF41 is activated to a high level. As a result, the edge information flag FLG becomes high level (“1”).

  On the other hand, when the first rising edge of the gate clock signal GCK is later than the first falling edge in the measurement period, the gate clock signal GCK is at the high level when the count start signal CST is activated to the high level. Therefore, the output signal of the D flip-flop DF40 is activated to a high level, and the output signal of the D flip-flop DF41 is maintained at a low level. As a result, the edge information flag FLG becomes low level (“0”).

  According to the fifth circuit example shown in FIG. 9, once the levels of the output signals of the D flip-flops DF40 and DF41 are determined after the count start signal CST is activated to a high level, there is no subsequent change. Therefore, the value of the edge information flag FLG output from the AND circuit 40 is also maintained, and there is no possibility that the value of the edge information flag FLG changes in one measurement period.

  10 gate counter, 20 measurement period setting circuit, 30 measurement counter, 31 main counter, 32 sub counter, 33, 33a-33d edge information holding circuit, 34 decoder, 35 OR circuit, 36 selector, 37 inverter, 38-40 AND circuit DF21 to DF41 D flip-flop, LF31 latch flip-flop, EX31 EOR circuit

Claims (4)

A counter circuit that counts the number of pulses of a clock signal in a set measurement period,
A first circuit that generates a first count value by counting the number of pulses in synchronization with a rising edge of the clock signal in the measurement period;
A second circuit for generating a second count value by counting the number of pulses in synchronization with a falling edge of the clock signal in the measurement period;
A third circuit that holds flag information indicating a front-rear relationship between a rising edge and a falling edge of the clock signal in the measurement period;
A fourth circuit for outputting a measurement count value of double precision with respect to a cycle of the clock signal by decoding the first count value and the second count value according to the flag information;
A counter circuit comprising: The first count value or the second count value is a count value of N bits (N is an integer of 2 or more),
(N + 1) -bit first combined count value obtained by combining the first count value of N bits and the least significant bit of the second count value, or the second count value of N bits and the first count value Based on the second combined count value of (N + 1) bits combined with the least significant bit, the fourth circuit decodes at least the lower 2 bits of the first combined count value or the second combined count value. The counter circuit according to claim 1.   When the first rising edge of the clock signal in the measurement period is before the first falling edge, the fourth circuit sets the lower 2 bits “0, 0” of the first combined count value to “ 0, 0 ”, lower 2 bits“ 1, 0 ”are decoded to“ 0, 1 ”, lower 2 bits“ 1, 1 ”are decoded to“ 1, 0 ”, and lower 2 bits“ 0, 0 ”are decoded. 1 ”is decoded into“ −1, 1 ”, and when the first rising edge of the clock signal in the measurement period is later than the first falling edge, the lower two bits“ 1 ”of the first combined count value “0, 0” is decoded to “0, 0”, the lower 2 bits “0, 1” are decoded to “0, 1”, the lower 2 bits “1, 1” are decoded to “1, 0”, Decode lower 2 bits “1, 0” to “1, 1”, Counter circuit of Motomeko 2 described. The first circuit includes a first flip-flop that changes an output signal in synchronization with a rising edge of the clock signal;
The second circuit includes a second flip-flop that changes an output signal in synchronization with a falling edge of the clock signal;
The third circuit includes an exclusive OR circuit that obtains an exclusive OR of the output signal of the first flip-flop and the output signal of the second flip-flop, and a rising edge of the clock signal in the measurement period. The counter circuit according to claim 1, further comprising a third flip-flop that latches an output signal of the exclusive OR circuit in synchronization with an edge.

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