JP2012168737A - Memory unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory unit having a security function which clears data in the memory by pseudo-volatilization when power supply breaks down in operation, and capable of executing non-volatilization processing of the data at a high speed when finishing operation.SOLUTION: A memory is constituted of a volatile memory part and a non-volatile memory part, and stores a part of a writing data unit in the non-volatile memory part and a part of the writing data unit in the volatile memory part. The data to be written in the non-volatile memory part is encrypted by using the data to be written in the volatile memory part as a key. Thereby, when the memory is removed, the whole data disappears due to extinction of the data stored in the volatile memory part. When operation is finished, the volatile data is moved to the non-volatile memory part by an inside data movement engine and the whole data can be non-volatilized. As the amount of data movement is small, high speed data movement can be executed in comparison with the case that the whole data is in the volatile memory part.

Description

  The present invention relates to a memory device, and more particularly to a memory device in which a nonvolatile memory is applied to a main memory.

  Various memory devices have been developed as means for storing information. There is a temporary storage register in the processor for processing operations, a main storage device composed of DRAM for storing information necessary for executing a series of program processing, an external storage device such as a hard disk capable of storing data, etc. . These storage media are classified into a nonvolatile memory and a volatile memory depending on whether power supply is necessary for maintaining information. Conventionally, volatile memories that require power supply have been used for temporary storage registers and main storage devices because of their high speed and small capacity. Nonvolatile memories that do not require power supply are low speed, but have a large capacity and do not require a power supply, and thus have been used for external storage devices for information storage. In recent years, a non-volatile but high-speed memory such as a flash memory has been developed, and it is becoming possible to apply a non-volatile memory to registers and main memory that require high speed.

  As a prior art, Patent Document 1 discloses an information processing apparatus using a flash memory for a main storage unit in an information processing apparatus including a central processing unit, a main storage unit, a display system, and a bus connecting them. It is disclosed.

  Patent Document 2 also discloses special hardware and processing so that the system operates normally when power is turned on again after a sudden power shutdown in an apparatus in which the main memory is composed entirely of a non-volatile memory. An apparatus with a procedure is disclosed.

  Further, in Patent Document 3, when a nonvolatile memory is used as a program memory, the program is executed after being transferred from the nonvolatile memory to the CPU main memory. However, the program execution is delayed due to the low speed of the nonvolatile memory. In order to solve this problem, a memory control system is disclosed in which a plurality of nonvolatile memories are operated in parallel and the switching is performed using busy information of individual nonvolatile memories.

  Patent Document 4 discloses a computer system that can access the same area of a nonvolatile memory as both a main storage area and a file area.

  Further, in Patent Document 5, in order to protect important data from a third party, when an operation to turn off the power is detected, data necessary for the operation and data from a working storage device that stores a program are stored. An apparatus for erasing is disclosed.

  Patent Document 6 aims to prevent access to the contents of the secondary storage device, which is a nonvolatile memory, when the information processing device or the secondary storage device is stolen. An apparatus is disclosed in which the file management area in the apparatus is saved in the SRAM and the power is actually turned off after the contents of the file management area are destroyed.

JP 5-334168 JP2010-108253 JP2004-48428 JP2004-362464 JP2004-334626 JP-A-11-212730

  By applying a nonvolatile storage medium to the volatile main memory, information can be retained even when the power is turned off. If this is used, the main memory can be used not only as a working area for program execution but also as a place for storing information. However, when this is realized, there is a possibility of causing a problem in a conventional system based on the premise that the main memory volatilizes at a high speed and the external storage device has a nonvolatile low speed. For example, the problem of information protection has been increasing in recent years, but in current computer systems, the main memory is almost volatile, so that measures are often insufficient from the viewpoint of information protection. The present invention provides a non-volatile memory that can provide a characteristic of a volatile memory by mixing a volatile memory and a non-volatile memory. The first problem to be solved by the configuration according to the present invention is to realize security by realizing pseudo volatility of data. For data in the middle of execution, if the normal procedure is not passed, the security function is realized by volatilizing the data without leaving it. The second problem is to provide a complete non-volatile memory after a normal procedure. A function of moving the volatile data portion to the nonvolatile memory at high speed as the nonvolatile processing of the volatile data is realized.

  A storage device constituting the main memory is constituted by a volatile memory and a nonvolatile memory. A part of the write data unit is stored in a nonvolatile memory and a part is stored in a volatile memory. Writing to the main memory is usually performed in units of data having a certain length, but the lower bits of the address are used for determination and stored in volatile memory or nonvolatile memory. In the storage device having this configuration, data stored in the volatile unit is lost when the storage device is suddenly removed. By encrypting the data to be written to the nonvolatile memory part using the data to be written to the volatile memory part as a key, it becomes possible to make it impossible to retrieve the entire data due to the data loss of the volatile part, realizing a pseudo volatile memory it can. After the normal operation is completed, the entire storage device can be made non-volatile by transferring the volatile data to the non-volatile memory by the internal data movement engine. Compared to the case where all the data is stored in the volatile memory, since the movement data is small, it is possible to move to the nonvolatile memory at high speed. This memory configuration is the first configuration for realizing data security.

  The first configuration solves the problem that is the subject of the present invention. However, in order to be compatible with the conventional memory configuration method in which the main memory is a volatile memory and the other extended memory is an extended memory, the volatile memory is used. It is also possible to realize a memory configuration in which main memory and nonvolatile memory are expanded. In this configuration, the lower part of the address is assigned to the volatile memory as the main memory, the upper part is assigned to the nonvolatile memory as the extended storage, and the main storage data necessary for program execution is stored in the volatile memory. Between the extended memory and the main memory, data movement is executed by a data movement engine provided in the storage device, and the storage areas can be switched. This memory configuration is a second configuration in which the main memory is a volatile memory.

  The first configuration for realizing data security and the second configuration using the main memory as a volatile memory are realized by changing the address allocation in the storage device. By holding the logic for switching the address setting of the storage device inside, the first configuration that realizes data security and the second configuration that uses the main memory as a volatile memory are realized by a single storage device. .

  According to the present invention, it is possible to realize a non-volatile memory having a security function by pseudo-volatility that does not leave complete data in the memory with respect to the memory removed without performing a regular procedure during operation. The pseudo-volatile data is made non-volatile by moving the data in the volatile memory unit to the non-volatile memory unit, but can be executed at a higher speed than when all the data is stored in the volatile memory.

It is a figure which shows the basic composition of the memory by this invention. It is a figure which shows the content of the register incorporated in the memory by this invention. It is a figure which shows the data movement process (initialization process) from a non-volatile memory to a volatile memory. It is a figure which shows the operation | movement at the time of security mode. It is a figure which shows the encryption circuit incorporated in the memory by this invention. It is a figure which shows the compound circuit built in the memory by this invention. It is a figure which shows the operation | movement at the time of main memory volatile mode. It is a figure which shows the data movement process (nonvolatization process) from a volatile memory to a non-volatile memory. It is a figure which shows the address generation method at the time of security mode and main memory volatile mode. It is a figure which shows the internal circuit of a data movement engine circuit.

  The basic configuration of a memory according to the present invention is shown in FIG. The storage unit includes a nonvolatile memory A1, a nonvolatile memory B2, a nonvolatile memory C3, a nonvolatile memory D4, and a volatile memory 5 having the same capacity and configuration. The nonvolatile memory and the volatile memory can be configured to have an arbitrary number, but in this embodiment, the configuration of four nonvolatile memories and one volatile memory is shown. The memory according to the present invention has an address generation circuit 6 for generating addresses from the input address to the internal nonvolatile memory A1, nonvolatile memory B2, nonvolatile memory C3, nonvolatile memory D4, and volatile memory 5, and the address generation circuit 6 includes: It has a mode register 9 that determines the security mode configuration or main memory volatile mode configuration by changing the allocation of each memory. A memory address is input from the outside to the address generation circuit 6 via the address pin 16, and a mode setting value is input to the mode register 9 via the mode pin 17. As shown in FIG. 2, the mode register 9 is a 1-bit setting register that defines the memory configuration. A value of 0 is a security mode configuration, and a value of 1 is a main memory volatile mode configuration.

  The memory according to the present invention has an encryption circuit 8 that converts data input via the input data pin 20 into data with security.

  The memory according to the present invention has a data movement engine circuit 7 that realizes data movement between the nonvolatile memory A1, the nonvolatile memory B2, the nonvolatile memory C3, the nonvolatile memory D4, and the volatile memory 5. In the data movement engine circuit 7, a nonvolatile memory A 1, a nonvolatile memory B 2, a nonvolatile memory C 3, a nonvolatile memory D 4 for setting whether or not the nonvolatile memory A 4 shares data with the volatile memory 5, and a nonvolatile memory A 1, a nonvolatile memory It has a memory status flag 11 indicating whether the latest data of the memory B2, the nonvolatile memory C3, or the nonvolatile memory D4 is placed in the volatile memory 5 or in the nonvolatile memory.

  As shown in FIG. 2, the memory allocation register 10 is a register of 1 bit for each nonvolatile memory, and a total of 4 bits in this embodiment. A value of 0 means that the nonvolatile memory is not sharing data with the volatile memory, and a value of 1 is that the nonvolatile memory is sharing data with the volatile memory. A set value is input to the memory allocation register 10 via the memory allocation pin 19. The memory allocation register 10 can set only one bit out of four bits to the value 1, and in this embodiment, the value “0001” is shown in a state where the nonvolatile memory D4 is designated.

  As shown in FIG. 2, the memory status flag 11 is a register of 1 bit for each nonvolatile memory, and a total of 4 bits in this embodiment. A value of 0 means that the latest data of the nonvolatile memory is on the nonvolatile memory, that is, the corresponding data is in a nonvolatile state, and a value of 1 indicates that the latest data of the nonvolatile memory is on the volatile memory, that is, the corresponding data. Is in a volatile state. The memory status flag 11 is meaningful only for the portion corresponding to the nonvolatile memory in which the memory allocation register 10 has the value 1. The memory status flag 11 is output to the outside from the memory status flag output pin 22 and can monitor whether the memory data is in a non-volatile state or a volatile state.

  The data movement engine circuit 7 is activated by a signal from the activation signal pin 18. The start signal pin 18 includes two signals, and can start an initialization process for moving data from the nonvolatile memory to the volatile memory and a nonvolatile process for moving data from the volatile memory to the nonvolatile memory.

  In addition, the memory according to the present invention has a composite circuit 12 that combines data with normal data when the data read from the memory is data with security. The composite circuit 12 outputs the memory read data via the output data pin 21.

  The memory according to the present invention has a memory address selector 13, a memory write data selector 14, and an output data selector 15 for selecting an address and data by operation. The memory address selector 13 selects the address generated by the address generation circuit 6 during normal operation and moves data between the nonvolatile memory A1, the nonvolatile memory B2, the nonvolatile memory C3, the nonvolatile memory D4, and the volatile memory 5. The address output from the data movement engine circuit 7 is selected, and the address is output to the nonvolatile memory A1, the nonvolatile memory B2, the nonvolatile memory C3, the nonvolatile memory D4, and the volatile memory 5.

  The memory write data selector 14 selects data sent from the encryption circuit 8 during normal operation, and moves data between the nonvolatile memory A1, nonvolatile memory B2, nonvolatile memory C3, nonvolatile memory D4 and volatile memory 5, Data output from the nonvolatile memory A1, nonvolatile memory B2, nonvolatile memory C3, nonvolatile memory D4, or volatile memory 5 is selected.

  The output data selector 15 selects data read from the nonvolatile memory A1, nonvolatile memory B2, nonvolatile memory C3, nonvolatile memory D4, and volatile memory 5. The first-stage selector selects the non-volatile memory A1, the non-volatile memory B2, the non-volatile memory C3, the non-volatile memory D4, and the volatile memory 5. In this embodiment, since the nonvolatile memory D4 shares data with the volatile memory 5, the nonvolatile memory A1, the nonvolatile memory B2, the nonvolatile memory C3, and the volatile memory 5 are selected during normal operation. During normal operation, the nonvolatile memory D 4 shares data with the volatile memory 5, and the latest data is in the volatile memory 5. When moving data between the non-volatile memory and volatile memory by initialization processing of the entire memory and non-volatile processing of the entire memory, when moving data from the non-volatile memory to the volatile memory, select the non-volatile memory and change from the volatile memory to the non-volatile memory. When moving data, volatile memory is selected.

  The second-stage selector selects a memory area. During normal operation, data from the memory designated by the address to the memory is selected, and the data is transferred to the composite circuit 12. At the time of data movement between the nonvolatile memory and the volatile memory by the initialization process of the entire memory and the nonvolatile process of the entire memory, the part where the volatile memory and the nonvolatile memory share data, in this embodiment, the nonvolatile memory D4 and the volatile memory Five selection data portions are selected in a fixed manner.

  Prior to using this memory, the following initialization processing is performed. First, the mode register 9 that determines the security mode configuration or the main memory volatile mode configuration is set. When the security mode is configured, the data written to the non-volatile memory will be encrypted with the data written to the volatile memory, and if the power is cut off due to unnatural work, the data in the volatile memory will disappear. Security of all data is maintained. In the case of the main memory volatile mode configuration, all data that can be directly accessed from a program or the like is stored in the volatile memory, thereby realizing a storage hierarchy according to the prior art.

  Next, a nonvolatile memory corresponding to the volatile memory is determined and set in the memory allocation register 10. In this embodiment, the memory allocation register 10 has a value “0001” for designating the nonvolatile memory D4. The non-volatile memory set here can be volatile or non-volatile by transferring data between the volatile memories.

  The setting of the mode register 9 and the setting of the memory allocation register 10 are set from the mode pin 17 and the memory allocation pin 19, but when the usage method is fixed in the device, a fixed signal must be input from the mounted board to this memory. It may be realized with. When the usage method is appropriately changed in the apparatus, it may be realized by writing a set value for each use from an external controller such as a CPU.

  Finally, the nonvolatile memory data set by the memory allocation register 10 is copied to the volatile memory. Data movement from the nonvolatile memory to the volatile memory is performed by starting the data movement engine circuit 7. The data movement engine circuit 7 has an address counter inside, reads data sequentially from the lowest address of the nonvolatile memory set by the memory allocation register 10 to the highest address, and sequentially data from the lowest address of the volatile memory to the highest address. Write. In a normal volatile memory, “0” writing is performed as initialization, but in the memory according to the present invention, the volatile memory is initialized by copying the data in the designated nonvolatile memory. When the address counter reaches the highest address and copying is completed, the data movement engine circuit 7 sets a flag indicating that the latest data is in the volatile memory in the memory status flag 11 of the corresponding nonvolatile memory.

  FIG. 3 shows the movement of data from the non-volatile memory to the volatile memory during initialization. In this embodiment, the memory allocation register 10 is “0001” and the nonvolatile memory D4 shares data 5 with the volatile memory. The memory status flag 11 before data transfer is “0000”. When the data movement engine circuit 7 starts the initialization process by a signal from the start signal pin 18, the lowest address of the nonvolatile memory D4 and the volatile memory 5 is sent to the memory address selector 13 from the internal address counter. While the data movement engine circuit 7 is activated, an address sent from the data movement engine circuit 7 is selected, and the address is sent to the nonvolatile memory D4, the volatile memory 5 and the output data selector 15. The output data selector 15 always selects the nonvolatile memory D4.

  The memory write data selector 14 always selects the data read from the internal nonvolatile memory D 4 and sends the data to the volatile memory 5. When the data read from the nonvolatile memory D4 is written to the volatile memory 5, the internal address counter of the data movement engine circuit 7 is updated to the next address, and the same movement process is executed. When the internal address counter of the data movement engine circuit 7 reaches the highest address of the nonvolatile memory D4 and the volatile memory 5, and the data movement is completed, the data movement engine circuit 7 updates the memory status flag 11 to “0001”. The process ends. The external device can recognize the completion of initialization by monitoring the state of the memory state flag 11 via the memory state flag output pin 22. For the data movement at the time of initialization, the same processing is executed regardless of the mode in both the security mode and the main memory volatile mode.

  In this embodiment, only one address counter is required in the data movement engine circuit 7, but there is a configuration in which two read address counters and two write address counters are prepared for the purpose of speeding up the processing. If the read address counter and the write address counter are separate, memory read and write can be executed in parallel, and data movement can be performed quickly.

  FIG. 4 shows a normal operation in the security mode. In this mode, the mode register is set to “0”, and the unit of each input data is written in the nonvolatile memory and the volatile memory. Here, it is assumed that the memory allocation register is “0001” and the nonvolatile memory D4 is designated as a memory sharing data with the volatile memory 5. Data a, b, c, and d are data write units, where data a is written in nonvolatile memory A1, data b is written in nonvolatile memory B2, data c is written in nonvolatile memory C3, and data d is written in volatile memory 5. Is shown. Here, the non-volatile memory D4 is not used and is allocated to the same storage area as the volatile memory portion. When the storage device is made non-volatile, the data in the volatile memory 5 is transferred to the non-volatile memory D4 to make it non-volatile. Is done. During normal operation, the latest data d exists only in the volatile memory and does not exist in the nonvolatile memory D4. For this reason, when the power supply is cut off by forcibly removing the storage device, the data d in the volatile memory portion is lost.

  The data abcd input from the data input pin 20 is sent to the encryption circuit 8 and encrypted. As shown in FIG. 5, in the encryption, the data abc of the input data abcd is cryptographically converted using the data d to be converted into data xyz. Data xyz can be converted to data abc by inverse conversion using data d as a key. The data converted into data xyzd by the encryption circuit 8 is written into the nonvolatile memory A1, the data y as the nonvolatile memory B2, the data z as the nonvolatile memory C3, and the data d as the volatile memory 5.

  If power is not supplied to the storage device due to an unnatural action during normal operation, the data d on the volatile memory disappears. Although the data xyz remains in the nonvolatile memory, the original data cannot be read because the key data d is lost. When reading data from the memory, data x is read from the nonvolatile memory A1, data y is read from the nonvolatile memory B2, data z is read from the nonvolatile memory C3, and data d is read from the volatile memory 5. The read data is sent to the composite circuit 12. The data xyz is encrypted by the data d, but as shown in FIG. 6, the data abc can be obtained from the data xyz by combining the data d with the key.

  As the read / write address, the address input from the address pin 16 is converted by the address generation circuit 6 according to the contents of the mode register 9 and the address selector 13 passes through the nonvolatile memory A1, nonvolatile memory B2, nonvolatile memory C3, and volatile memory. Sent to 5. FIG. 9 shows an address generation result in the security mode. In the security mode, data is allocated to the non-volatile memory or the volatile memory by the relatively lower bits of the address. In this embodiment, since the write data width of each memory area is 8 bytes, the lower 3 bits of the address are not used. In this example, since the nonvolatile memory D4 corresponds to the volatile memory, it is not used during normal operation. Address 000xxx is nonvolatile memory A1, address 001xxx is nonvolatile memory B2, address 010xxx is nonvolatile memory C3, address 011xxx is allocated to volatile memory 5, address 100xxx is nonvolatile memory A1, address 101xxx is nonvolatile memory B2, The address 110xxx is assigned to the non-volatile memory C3, the address 111xxx is assigned to the volatile memory 5, and the addresses are sequentially assigned in the higher address direction. The address generation circuit 6 outputs an address and a selection signal to the memory according to this assignment.

  FIG. 7 shows a configuration in which volatile memory is assigned to main memory and nonvolatile memory is assigned to extended storage. In this mode, the mode register is set to “1”, and a conventional memory hierarchical structure is realized in which all data necessary for instruction processing is placed in the volatile memory. Here, it is assumed that the memory allocation register is “0001” and the nonvolatile memory D4 is designated as a memory sharing data with the volatile memory 5. Data a, b, c, d is a unit of data writing once, and data a, data b, data c, data d are all written in the volatile memory 5. Also in this configuration, the nonvolatile memory D4 corresponds to the volatile memory 5, and performs data movement from the nonvolatile memory to the volatile memory during the initialization process and from the volatile memory to the nonvolatile memory during the nonvolatile process.

  The input data abcd is input from the data input pin 20 to the encryption circuit 8, but encryption is not performed in this main memory volatile mode. The data that has passed through the encryption circuit 8 passes through the data selector 14 and is all written into the volatile memory 5. At the time of reading data, the data is read through the output data selector 15 and the composite circuit 8. Data decryption is not performed in the main memory volatile mode.

  As the read / write address, the address input from the address pin 16 is converted by the address generation circuit 6 according to the contents of the mode register 9 and sent to the volatile memory 5 via the address selector. The address generation in the main memory volatile mode is shown in FIG. In the main memory volatile memory mode, all data corresponding to the main memory is allocated to the volatile memory, and the address is used as it is as the address of the volatile memory. When the nonvolatile memory is designated as an extended storage that cannot be directly used from a program, the upper bits of the address exceeding the main storage capacity can be used. In this example, the address 01x ... x000xxx is used as the nonvolatile memory A1, the address 10x ... x000xxx is used as the nonvolatile memory B2, and the address 11x ... x000xxx is used as the nonvolatile memory C3. In this example, since the non-volatile memory D4 corresponds to the volatile memory 5, it has the same address as the volatile memory and is not used during normal operation.

  FIG. 8 shows a process of moving data from volatile data to nonvolatile data. In this embodiment, the memory allocation register 10 is “0001” and the nonvolatile memory D 4 shares data with the volatile memory 5. The memory status flag 11 before data transfer is “0001”. When the data movement engine circuit 7 starts the nonvolatile process by a signal from the start signal pin 18, the lowest address of the nonvolatile memory D4 and the volatile memory 5 is output from the internal address counter and sent to the memory address selector 13. . While the data movement engine circuit 7 is activated, an address sent from the data movement engine circuit 7 is selected, and the address is sent to the nonvolatile memory D4, the volatile memory 5 and the output data selector 15. The output data selector 15 always selects the volatile memory 5. The memory write data selector 14 always selects the data read from the internal volatile memory 5 and sends the data to the nonvolatile memory D4. When the data read from the volatile memory 5 is written to the nonvolatile memory D4, the internal address counter of the data movement engine circuit 7 is updated, and the same movement process is executed for the next address. When the internal address counter of the data movement engine circuit 7 reaches the highest address of the non-volatile memory D4 and the volatile memory 5, the data movement engine circuit 7 updates the memory status flag 11 to “0000”, and the process ends. The external device can recognize the completion of the nonvolatile process by monitoring the state of the memory state flag 11 via the memory state flag output pin 22. The data movement at the time of non-volatility performs the same processing regardless of the mode in both the security mode and the main memory volatile mode.

  In this embodiment, only one address counter is required in the data movement engine circuit 7, but there is a configuration in which two read address counters and two write address counters are prepared for the purpose of speeding up the processing. If the read address counter and the write address counter are separate, memory read and write can be executed in parallel, and data movement can be performed quickly.

  FIG. 10 shows the detailed structure of the data movement engine circuit 7. In response to an activation signal from the activation pin 18, the data movement engine sequencer 24 is activated. While the data movement engine circuit 7 is operating, three data movement engine selector signals 26 are output from the data movement engine sequencer 24. This is a selection signal to the memory address selector 13, the memory write data selector 14, and the output data selector 15, and outputs a data selection signal corresponding to each operation as described above. The data movement engine sequencer 24 sends a reset signal to the data movement engine internal address counter 23 to set the lowest address of the memory. The data movement engine internal address counter 23 outputs the data movement memory address 25 to the internal memory via the selector 13.

  When the data movement between the memories at the corresponding address is completed, the data movement engine internal address counter 23 is incremented by 1 and the next address is output. When the address counter 23 in the data movement engine reaches the highest address of the memory, the memory status flag 11 corresponding to the bit specified in the memory allocation register 10 is set to “1” at the initialization process, and at the nonvolatile process. Set to '0', the operation of the data movement engine sequencer 24 ends.

  In the present embodiment, a configuration in which there are four nonvolatile memories and one volatile memory is shown. However, as long as the number of nonvolatile memories is greater than or equal to the volatile memories, a larger number of nonvolatile memories and volatile memories may be used. When the number of nonvolatile memories increases, the number of bits of the memory allocation register and the memory status flag increases correspondingly. When the number of volatile memories increases, the number of memory allocation registers and memory status flags increases correspondingly, and the number of volatile memories managed independently includes as many memory allocation registers and memory status flags. For this, the same processing is executed.

1 Nonvolatile memory A
2 Nonvolatile memory B
3 Nonvolatile memory C
4 Nonvolatile memory D
5 Volatile memory
6 Address generation circuit
7 Data movement engine circuit
8 Encryption circuit
9 Mode register
10 Memory allocation register
11 Memory status flag
12 Compound circuit
13 Memory address selector
14 Memory write data selector
15 Output data selector
16 Address input pin
17 Mode input pin
18 Activation pin
19 Memory allocation pin
20 Data input pin
21 Data output pin
22 Memory status flag output pin
23 Data movement engine internal address counter
24 Data movement engine sequencer
25 Data movement memory address
26 Data movement selector signal

Claims (6)

  A memory composed of a non-volatile memory part and a volatile memory part, and has a configuration in which a part of one read / write data unit is stored in a non-volatile memory part and a part is stored in a volatile memory part. Is a memory device including a circuit that encrypts and decrypts data to be written to the nonvolatile memory portion using data to be written to the volatile memory portion as a key.   2. The memory device according to claim 1, wherein when the power supply is cut off, the data in the volatile memory portion is lost, thereby preventing the data in the nonvolatile memory portion from being read out.   2. The memory device according to claim 1, wherein the entire data is lost due to data loss of the volatile memory portion by encrypting data to be written to the nonvolatile memory portion with the data to be written to the volatile memory portion as a key. apparatus.   A memory device composed of a plurality of nonvolatile memory portions and a plurality of volatile memory portions, and a function for moving data recorded in the volatile memory portion and data recorded in the nonvolatile memory portion to each other, and for each volatile memory portion If the non-volatile memory part is shared with a register that stores whether data is shared with the volatile memory part or not, the status flag that indicates whether the data is in the volatile memory part or the non-volatile memory part A memory device prepared for.   5. The memory device according to claim 4, wherein, for each volatile memory portion, when each nonvolatile memory portion shares data with the volatile memory portion prior to power-off, the data is in the volatile memory portion or the nonvolatile memory portion. The data in the volatile memory part is moved to the corresponding non-volatile memory part according to the status flag indicating whether or not, and after the transfer, the status flag is updated to move all the volatile memory part data to the non-volatile memory part. The memory device is characterized in that the entire data is held as nonvolatile data by confirming the completion of the nonvolatileization from the logical product of all the state flags and then turning off the power.   A memory device composed of a non-volatile memory portion and a volatile memory portion, and has a built-in circuit for changing the correspondence between the address and each memory portion. By setting the change circuit, the non-volatile memory portion and the volatile memory for each address in the memory device A memory device that can change the memory part.

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