JP2012166289A - Method for cutting semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for cutting a semiconductor wafer in which a burr is prevented from being generated at an edge of a cut surface.SOLUTION: When the semiconductor wafer 3 is cut by wire electric discharge machining, a discharge energy per unit area applied to the semiconductor wafer 3 from a wire 2 is gradually decreased while a discharge gap G is increased through a process of inserting the wire 2 into the semiconductor wafer 3, and discharge energy per unit area applied to the semiconductor wafer 3 from the wire 2 is gradually increased while the discharge gap G is gradually decreased through a process of removing the wire 2 from the semiconductor wafer 3. This allows an edge of a cut surface of the semiconductor wafer 3 to be shaped into a round shape.

Description

  The present invention relates to a method for cutting a semiconductor wafer using a wire electric discharge machining technique.

  As a technique for separating and cutting a semiconductor wafer on which a device is formed into device chips, wire electric discharge machining is known (for example, Patent Document 1 below). In wire electric discharge machining, the workpiece is cut by causing the wire to cross the workpiece while applying a discharge pulse to the metal wire. Since the workpiece is melted and removed by electric discharge from the wire, the wire electric discharge machining is a non-contact type machining method in which the wire does not contact the workpiece. The cutting of a wafer in Patent Document 1 is performed by applying a voltage pulse to a wire stretched perpendicular to the surface of the wafer, transporting the wafer in a lateral direction at a constant speed, and causing the wire to cross the wafer. .

  In recent years, semiconductor elements using silicon carbide (SiC) have been promising as next-generation switching elements that can achieve high withstand voltage, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. Has been. However, many problems to be solved remain in the SiC semiconductor device. For example, since SiC has a higher hardness than silicon (Si), one example is the establishment of a breakthrough technology that enables efficient chip cutting from a SiC semiconductor wafer.

JP-A-8-321209

  As described above, in Patent Document 1, the wire used for cutting the wafer is stretched perpendicular to the surface of the wafer. Further, by sending the wafer to the wire at a constant speed, the distance between the cut surface of the wafer and the wire (hereinafter referred to as “discharge gap”) at the time of cutting the wafer is always constant.

  On the other hand, sharp protrusions (so-called “burrs”) are formed on the cut surface of the chip cut from the wafer by conventional wire electric discharge machining, due to the wafer material that cannot be completely removed at the edge portion. If burrs are generated at the edge portion of the chip, the chip is easily damaged in the subsequent process and chipping is likely to occur, and the device element formed near the edge of the chip may be damaged. It can also be a factor of reducing the bending strength (bending strength) of the chip. Therefore, the burr at the chip edge portion causes a decrease in the quality and yield of the device chip.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor wafer cutting method capable of preventing the occurrence of burrs at the edge of the cut surface.

  The method of cutting a semiconductor wafer according to the present invention includes a step of stretching a wire on the first main surface side of a semiconductor wafer having first and second main surfaces, and applying the discharge pulse to the wire, And a step of cutting the semiconductor wafer by relatively moving the wire and the semiconductor wafer so that the semiconductor wafer passes from the first main surface side to the second main surface side. .

  Preferably, in the step of cutting the semiconductor wafer, in the process of inserting the wire from the first main surface into the semiconductor wafer, discharge energy per unit area given from the wire to the wafer is gradually reduced, and the wire Is discharged from the second main surface to the outside of the semiconductor wafer, the discharge energy per unit area given from the wire to the wafer is gradually increased.

  According to the present invention, since the wire is passed in the thickness direction of the semiconductor wafer to cut the semiconductor wafer, the cutting time can be shortened, and application to a highly hard semiconductor wafer such as SiC is expected. If the discharge energy per unit area given from the wire to the wafer is increased when the wire enters and exits the semiconductor wafer, the discharge gap at that time becomes particularly large. The lower edge is rounded to prevent burrs. As a result, in the device chip cut out from the semiconductor wafer, the occurrence of chipping and the decrease in the bending strength can be prevented, and the quality and yield of the device chip can be improved.

It is a perspective view which shows the structure of the wire electric discharge machining apparatus which concerns on this invention. FIG. 6 is a process diagram illustrating a process of a wire entering a semiconductor wafer in the semiconductor chip cutting method according to the first embodiment. FIG. 6 is a process diagram illustrating a process in which a wire goes out of a semiconductor wafer in the semiconductor chip cutting method according to the first embodiment. FIG. 5 is a diagram showing a method for controlling discharge energy per unit area in the semiconductor chip cutting method according to the first embodiment. It is a figure which shows the control method of the discharge energy per unit area in the cutting method of the semiconductor chip concerning Embodiment 2. FIG. It is a figure which shows the control method of the discharge energy per unit area in the cutting method of the semiconductor chip concerning Embodiment 3. FIG. It is a figure which shows the control method of the discharge energy per unit area in the cutting method of the semiconductor chip concerning Embodiment 4. FIG.

<Embodiment 1>
FIG. 1 is a perspective view showing a structure of a wire electric discharge machining apparatus according to the present invention. A semiconductor wafer 3 as a workpiece is fixed on a conductive carbon plate 41 fixed to the work stage 4 using a conductive adhesive or the like. The work stage 4 includes not only an upper and lower feed mechanism, but also a feed mechanism in the horizontal direction (X, Y direction) and the rotation direction (θ direction). The position control of the work stage 4 is performed by the stage control unit 42 setting parameters in each direction.

  The wire 2 for cutting the semiconductor wafer 3 is sent out from the feed-side reel 21, and taken up on the take-up reel 22 through the three guide rollers 1 in which the wire holding grooves 11 are formed at equal intervals. Two of the three guide rollers 1 are arranged on the same plane parallel to the upper surface of the work stage 4, and the wire 2 stretched between them is a semiconductor fixed on the upper surface of the work stage 4 and the upper surface of the work stage 4. It travels parallel to the upper surface of the wafer 3. The tension and traveling speed of the wire 2 can be adjusted by the wire reel control unit 23 controlling the feeding reel 21 and the take-up reel 22.

  The applied pulse control power supply 52 generates a discharge pulse to be applied to the wire 2, and the discharge pulse generated by the applied pulse control power supply 52 is supplied to the wire 2 through the power supply wiring 51 and the power supply 5. The The discharge energy control unit 9 controls the discharge energy (processing energy) applied from the wire 2 to the semiconductor wafer 3 by controlling the parameters of the voltage, current and frequency of the discharge pulse generated by the applied pulse control power source 52. Is.

  In the wire electric discharge machining apparatus of FIG. 1, the semiconductor wafer 3 is lifted so that the wire 2 passes through the semiconductor wafer 3 while applying a discharge pulse to the wire 2 stretched on the upper surface side of the semiconductor wafer 3. The wafer 3 is cut.

  Although FIG. 1 shows a configuration in which the semiconductor wafer 3 (work stage 4) moves up and down and the wire 2 (guide roller 1) does not move up and down, it is only necessary that the wire 2 and the semiconductor wafer 3 can move relatively. Therefore, the structure which the wire 2 moves without the semiconductor wafer 3 moving may be sufficient, and the structure which both the wire 2 and the semiconductor wafer 3 move may be sufficient.

  Here, the distance (discharge gap) between the cut surface of the semiconductor wafer 3 and the wire 2 when the semiconductor wafer 3 is cut depends on the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3. The discharge energy per unit area depends on the voltage, current, and frequency of the discharge pulse, and the time during which the discharge energy is applied, that is, the speed at which the wire 2 passes through the semiconductor wafer 3 (relative speed between the wire 2 and the semiconductor wafer 3). Also depends on. Therefore, the discharge energy (discharge gap) per unit area can be controlled not only by the discharge energy control unit 9 that can control the voltage, current, and frequency of the discharge pulse, but also by the rising speed (processing speed) of the semiconductor wafer 3. It can also be carried out with a simple stage control unit 42.

  Hereinafter, a semiconductor wafer cutting method according to the first embodiment will be described. FIG. 2 and FIG. 3 are process diagrams, showing an enlarged cross section of a portion where the semiconductor wafer 3 having the device element 6 on the upper surface is cut by the wire 2. Further, a relief groove 43 is provided at a position corresponding to the wire 2 in the carbon plate 41 to which the semiconductor wafer 3 is attached. In the present embodiment, it is assumed that the voltage value, current value, and frequency of the discharge pulse applied to the wire 2 are maintained constant.

  First, the semiconductor wafer 3 is fixed to the carbon plate 41 on the work stage 4. Since the wire 2 is stretched parallel to the upper surface of the work stage 4, if the semiconductor wafer 3 is fixed to the work stage 4, the wire 2 is stretched on the upper surface (first main surface) side of the semiconductor wafer 3. .

  Subsequently, the work stage 4 is raised while applying a discharge pulse to the wire 2, thereby bringing the workpiece 2 close to the upper surface of the semiconductor wafer 3. At this time, the wire 2 is maintained parallel to the upper surface of the semiconductor wafer 3. At this stage, the rising speed of the semiconductor wafer 3 is made extremely low, and the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is sufficiently increased. In this case, the discharge gap G increases as shown in FIG. Therefore, the surface portion of the semiconductor wafer 3 is removed in a relatively wide range.

  Then, the work stage 4 is continuously raised, and the wire 2 is penetrated into the semiconductor wafer 3 from the upper surface while being maintained parallel to the upper surface of the semiconductor wafer 3. At this stage, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is gradually reduced by gradually increasing the rising speed (processing speed) of the semiconductor wafer 3. Then, as the wire 2 enters the semiconductor wafer 3, the discharge gap G becomes smaller. Therefore, as shown in FIGS. 2B and 2C, the upper edge portion of the cut surface of the semiconductor wafer 3 is R. (Round) shape and no burr is formed.

  When the wire 2 completely enters the semiconductor wafer 3 as shown in FIG. 2C, the semiconductor wafer 3 is continuously lifted while maintaining the processing speed at a constant level. 2 main surface). When the processing speed is constant, since the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is constant, the discharge gap G is kept constant. Therefore, as shown in FIG. 3A, the width of the groove formed through the wire 2 is constant. That is, the cut surface of the semiconductor wafer 3 becomes flat.

  Thereafter, the work stage 4 is further raised, and the semiconductor wafer 3 is cut by bringing the wire 2 out of the lower surface of the semiconductor wafer 3. At this time, the wire 2 is maintained parallel to the lower surface of the semiconductor wafer 3. At this stage, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is gradually increased by gradually decreasing the rising speed (processing speed) of the semiconductor wafer 3. Then, since the discharge gap G increases as the wire 2 goes out of the semiconductor wafer 3, as shown in FIGS. 3B and 3C, the lower edge portion of the cut surface of the semiconductor wafer 3. Becomes R-shaped and no burr is formed.

  Through the above steps, the cutting of the semiconductor wafer 3 is completed. The wire 2 that has passed through the lower surface of the semiconductor wafer 3 enters the escape groove 43 of the carbon plate 41. The escape groove 43 is provided for the purpose of preventing the wire 2 from being obstructed from processing the lower edge portion of the cut surface of the semiconductor wafer 3 into an R shape.

  FIG. 4 is a diagram showing a change in discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 in the method for cutting the semiconductor wafer 3 described above. As shown in FIG. 4, during the period in which the processing position of the semiconductor wafer 3 by the wire 2 is near the upper surface of the semiconductor wafer 3, the processing speed (rising speed of the semiconductor wafer 3) is gradually increased as the processing position becomes deeper. As a result, the discharge energy per unit area gradually decreases and the discharge gap G gradually decreases.

  The period during which the processing speed is increased is at least when the lowermost part of the wire 2 and the upper surface of the semiconductor wafer 3 have the same height, and the uppermost part of the wire 2 and the upper surface of the semiconductor wafer 3 have the same height. It is preferable to include a period until the wire 3 completely enters the inside of the semiconductor wafer 3. By doing so, the upper edge part of the cross section of the semiconductor wafer 3 can be made into a smooth R shape, and the generation | occurrence | production of a burr | flash can be prevented more reliably.

  On the other hand, the period from when the processing position passes near the upper surface of the semiconductor wafer 3 until it approaches the lower surface is kept constant with the processing speed kept high. Meanwhile, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 becomes constant, and the discharge gap G is kept constant. Thereby, the width of the groove formed through the wire 2 is constant.

  Further, during the period in which the processing position is near the lower surface of the semiconductor wafer 3, the processing speed is gradually decreased as the processing position becomes deeper (as the wire 2 comes out of the semiconductor wafer 3). Thereby, the discharge energy per unit area gradually increases, and the discharge gap G gradually increases.

  The period during which the processing speed is lowered is at least when the lowermost part of the wire 2 and the lower surface of the semiconductor wafer 3 have the same height, and the uppermost part of the wire 2 and the lower surface of the semiconductor wafer 3 have the same height. It is preferable to include a period until the wire 3 completely enters the semiconductor wafer 3 from the outside. By doing so, the lower edge part of the cross section of the semiconductor wafer 3 can be made into a smooth R shape, and the generation | occurrence | production of a burr | flash can be prevented more reliably.

  In the present invention, the semiconductor wafer 3 is cut by passing the wire 2 in the thickness direction of the semiconductor wafer 3 (from the upper surface to the lower surface). Therefore, the time required for the cutting can be shortened as compared with the cutting performed by transferring the semiconductor wafer in the lateral direction as in Patent Document 1 described above. Therefore, application to a high hardness semiconductor wafer such as SiC is expected.

  In the present embodiment, the discharge gap G is particularly increased when the wire 2 enters the semiconductor wafer 3 and when the wire 2 exits the semiconductor wafer 3. As a result, the upper and lower edge portions of the cut surface of the semiconductor wafer 3 have an R shape, thereby preventing the occurrence of burrs. As a result, it is possible to prevent damage to the device element 6 and a decrease in the bending strength of the device chip due to chipping, and it is possible to improve the quality and yield of the device chip.

<Embodiment 2>
In the first embodiment, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is controlled by the processing speed of the semiconductor wafer 3 (relative speed between the wire 2 and the semiconductor wafer 3). The hit discharge energy can also be controlled by the voltage, current or frequency of the discharge pulse.

  Embodiment 2 shows an example in which the control is performed by the voltage value of the discharge pulse. FIG. 5 is a diagram for explaining a method of cutting the semiconductor wafer 3 according to the second embodiment, and shows a change in discharge energy per unit area given from the wire 2 to the semiconductor wafer 3.

  Also in each of the following embodiments, the structure of the wire electrical discharge machining apparatus used for cutting the semiconductor wafer 3 is the same as that in FIG. 1, and the semiconductor wafer 3 is cut from the upper surface side to the lower surface side of the semiconductor wafer 3. It is performed by raising the semiconductor wafer 3 so as to pass through. However, in the present embodiment, it is assumed that the processing speed of the semiconductor wafer 3 (rising speed of the semiconductor wafer 3), the current value and frequency of the discharge pulse applied to the wire 2 are maintained constant.

  As shown in FIG. 5, when the processing position of the semiconductor wafer 3 by the wire 2 is in the vicinity of the upper surface of the semiconductor wafer 3, the voltage of the discharge pulse (pulse voltage) is initially increased, and the discharge is performed as the processing position becomes deeper. Reduce the pulse voltage gradually. As a result, the discharge energy per unit area gradually decreases and the discharge gap G gradually decreases. As a result, the upper edge of the cut surface of the semiconductor wafer 3 has an R shape.

  The period during which the pulse voltage is lowered includes at least a period from when the lowermost part of the wire 2 and the upper surface of the semiconductor wafer 3 become the same height until the wire 3 completely enters the semiconductor wafer 3. Good. By doing so, the upper edge part of the cross section of the semiconductor wafer 3 can be made into a smooth R shape, and the generation | occurrence | production of a burr | flash can be prevented more reliably.

  On the other hand, the period from when the processing position passes near the upper surface of the semiconductor wafer 3 until it approaches the lower surface is kept constant with the pulse voltage kept low. In the meantime, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is constant, and the discharge gap G is kept constant. Thereby, the width of the groove formed through the wire 2 is constant.

  Further, during the period in which the processing position is near the lower surface of the semiconductor wafer 3, the pulse voltage is gradually increased as the processing position becomes deeper. Thereby, the discharge energy per unit area gradually increases, and the discharge gap G gradually increases. As a result, the lower edge of the cut surface of the semiconductor wafer 3 has an R shape.

  The period during which the pulse voltage is increased includes at least a period from when the lowermost part of the wire 2 and the lower surface of the semiconductor wafer 3 become the same height until the wire 3 completely enters the semiconductor wafer 3 from the outside. Good. By doing so, the lower edge part of the cross section of the semiconductor wafer 3 can be made into a smooth R shape, and the generation | occurrence | production of a burr | flash can be prevented more reliably.

  Thus, also in the present embodiment, as in the first embodiment, the discharge gap G when the wire 2 enters the semiconductor wafer 3 and when it exits the semiconductor wafer 3 becomes particularly large. Thereby, the upper and lower edge portions of the cut surface of the semiconductor wafer 3 are formed in an R shape, and the generation of burrs is prevented, and the same effect as in the first embodiment can be obtained.

<Embodiment 3>
The third embodiment shows an example in which the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is controlled by the current value of the discharge pulse. FIG. 6 is a diagram for explaining the control method. In the present embodiment, it is assumed that the processing speed of the semiconductor wafer 3 (rising speed of the semiconductor wafer 3) and the voltage value and frequency of the discharge pulse applied to the wire 2 are maintained constant.

  As shown in FIG. 6, during the period in which the processing position of the semiconductor wafer 3 by the wire 2 is in the vicinity of the upper surface of the semiconductor wafer 3, the discharge pulse current (pulse current) is initially increased, and gradually as the processing position becomes deeper. Make it smaller. As a result, the discharge energy per unit area gradually decreases and the discharge gap G gradually decreases. As a result, the upper edge of the cut surface of the semiconductor wafer 3 has an R shape. The period during which the pulse current is lowered includes at least a period from when the lowermost part of the wire 2 and the upper surface of the semiconductor wafer 3 become the same height until the wire 3 completely enters the semiconductor wafer 3. Good.

  On the other hand, the period from when the processing position passes near the upper surface of the semiconductor wafer 3 until it approaches the lower surface is kept constant with the pulse current kept low. In the meantime, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is constant, and the discharge gap G is kept constant. Thereby, the width of the groove formed through the wire 2 is constant.

  Further, during the period in which the processing position is near the lower surface of the semiconductor wafer 3, the pulse current is gradually increased as the processing position becomes deeper. Thereby, the discharge energy per unit area gradually increases, and the discharge gap G gradually increases. As a result, the lower edge of the cut surface of the semiconductor wafer 3 has an R shape. The period during which the pulse current is increased includes at least a period from when the lowermost part of the wire 2 and the lower surface of the semiconductor wafer 3 become the same height until the wire 3 completely enters the semiconductor wafer 3 from the outside. Good.

  In the present embodiment, the same effect as in the first embodiment can be obtained.

<Embodiment 4>
In the fourth embodiment, an example in which the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is controlled by the frequency value of the discharge pulse will be described. FIG. 7 is a diagram for explaining the control method. In the present embodiment, it is assumed that the processing speed of the semiconductor wafer 3 (rising speed of the semiconductor wafer 3) and the voltage value and current value of the discharge pulse applied to the wire 2 are kept constant.

  As shown in FIG. 7, when the processing position of the semiconductor wafer 3 by the wire 2 is in the vicinity of the upper surface of the semiconductor wafer 3, the frequency of the discharge pulse (pulse frequency) is initially increased, and the discharge is performed as the processing position becomes deeper. Gradually lower the pulse frequency (pulse frequency). As a result, the discharge energy per unit area gradually decreases and the discharge gap G gradually decreases. As a result, the upper edge of the cut surface of the semiconductor wafer 3 has an R shape. The period during which the pulse frequency is lowered includes at least a period from when the lowermost part of the wire 2 and the upper surface of the semiconductor wafer 3 become the same height until the wire 3 completely enters the semiconductor wafer 3. Good.

  On the other hand, the period from when the processing position passes near the upper surface of the semiconductor wafer 3 until it approaches the lower surface is kept constant with the pulse frequency kept low. In the meantime, the discharge energy per unit area given from the wire 2 to the semiconductor wafer 3 is constant, and the discharge gap G is kept constant. Thereby, the width of the groove formed through the wire 2 is constant.

  Further, during the period in which the processing position is near the lower surface of the semiconductor wafer 3, the pulse frequency is gradually increased as the processing position becomes deeper. Thereby, the discharge energy per unit area gradually increases, and the discharge gap G gradually increases. As a result, the lower edge of the cut surface of the semiconductor wafer 3 has an R shape. The period in which the pulse frequency is increased includes at least a period from when the lowermost part of the wire 2 and the lower surface of the semiconductor wafer 3 become the same height until the wire 3 completely enters the semiconductor wafer 3 from the outside. Good.

  In the present embodiment, the same effect as in the first embodiment can be obtained.

  DESCRIPTION OF SYMBOLS 1 Guide roller, 2 wires, 3 Semiconductor wafer, 4 Work stage, 5 Electricity supply, 6 Device element, 9 Discharge energy control unit, 11 Wire holding groove, 21 Feeding side reel, 22 Winding side reel, 23 Wire reel control Unit, 41 carbon plate, 42 stage control unit, 43 escape groove, 51 power supply wiring, 52 power supply for controlling applied pulse.

Claims (8)

Stretching a wire on the first main surface side of the semiconductor wafer having the first and second main surfaces;
While applying a discharge pulse to the wire, the wire and the semiconductor wafer are relatively moved so that the wire passes through the semiconductor wafer from the first main surface side to the second main surface side. And a step of cutting the semiconductor wafer. In the step of cutting the semiconductor wafer,
In the process of inserting the wire from the first main surface into the semiconductor wafer, the discharge energy per unit area given from the wire to the wafer is gradually reduced,
The semiconductor wafer cutting method according to claim 1, wherein in the process of taking out the wire from the second main surface to the outside of the semiconductor wafer, discharge energy per unit area given from the wire to the wafer is gradually increased. The semiconductor wafer cutting method according to claim 2, wherein discharge energy per unit area given from the wire to the wafer is controlled by a relative speed between the wire and the semiconductor wafer. The semiconductor wafer cutting method according to claim 2, wherein discharge energy per unit area given from the wire to the wafer is controlled by a voltage value of the discharge pulse. The semiconductor wafer cutting method according to claim 2, wherein discharge energy per unit area given from the wire to the wafer is controlled by a current value of the discharge pulse. The semiconductor wafer cutting method according to claim 2, wherein discharge energy per unit area given from the wire to the wafer is controlled by a frequency of the discharge pulse. The semiconductor wafer according to any one of claims 1 to 6, further comprising a step of fixing the second main surface side of the semiconductor wafer to a conductive carbon plate prior to the step of cutting the semiconductor wafer. Cutting method. The semiconductor wafer cutting method according to claim 7, wherein a groove corresponding to the position of the wire is formed on a mounting surface of the semiconductor wafer on the carbon plate.

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