JP2012164384A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device capable of reducing voltage drop and leakage current at the time of data erasing/writing.SOLUTION: A non-volatile semiconductor memory device relating to an embodiment comprises: a memory cell array having multiple memory cells that include multiple column lines extending in a column direction, multiple row lines extending in a row direction intersecting with the column direction and a variable resistive element arranged at each intersection part; and a column decoder that is arranged at least at one of a first end part and a second end part of the column lines which supply the memory cell with voltage required for state transition of the variable resistive element through the column lines. The column lines include: a first part; a second part farther from the column decoder than the first part; and a third part farther from the column decoder than the second part. A line width in the row direction in the second part is equal to or wider than that in the first part and is narrower than that in the third part.

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device.

  In recent years, resistance change type memories such as ReRAM (Resistive RAM) composed of memory cells made of variable resistance elements have been proposed. Since this resistance change type memory is easy to stack memory cells, higher integration than that of a flash memory can be achieved.

  Data erasing / writing operations for memory cells of resistance change memory can be broadly divided into unipolar operation that realizes both data erasing and data writing by applying the same polarity voltage, and data erasing and data writing by applying reverse polarity voltage. There is a bipolar operation.

  In the case of bipolar operation, a memory cell between a selected bit line and an unselected word line and a memory cell cell between an unselected bit line and a selected word line (hereinafter referred to as “half-selected cell”) are also applied to the selected cell. Half the voltage is applied. In this case, a voltage drop is caused by the current flowing in the half-selected cell, so that voltage compensation is necessary, and there is a possibility that problems such as an increase in the burden of peripheral circuit development and an increase in power consumption may occur.

JP 2009-283681 A

  The present invention provides a nonvolatile semiconductor memory device in which voltage drop and leakage current during data erasing / writing are reduced.

  The nonvolatile semiconductor memory device according to the embodiment includes a plurality of column lines extending in the column direction, a plurality of row lines extending in the row direction intersecting with the column direction, and intersections of the plurality of column lines and row lines. A memory cell array having a plurality of memory cells including the arranged variable resistance elements; and a first of the column lines for supplying a voltage necessary for state transition of the variable resistance elements to the memory cells via the column lines. A column decoder disposed at at least one of an end portion and a second end portion, wherein the column line has a first portion, a second portion farther from the column decoder than the first portion, and a second portion than the second portion. A third portion far from the column decoder, wherein the line width of the second portion in the row direction is equal to or wider than the line width of the first portion in the row direction, and the third portion Characterized by being narrower than the line width in the row direction

  A non-volatile semiconductor memory device according to another embodiment includes a plurality of column lines extending in the column direction, a plurality of row lines extending in the row direction intersecting with the column direction, and each intersection of the plurality of column lines and row lines. A memory cell array having a plurality of memory cells including variable resistance elements arranged in a section, and a column line for supplying a voltage necessary for state transition of the variable resistance elements to the memory cells via the column lines. A column decoder disposed on at least one of the first end and the second end, wherein a part of the plurality of row lines is a first row line, and the other part is a second row line, The second row line may be farther from the decoder than the first row line, and may be wider in the column direction than the first row line.

1 is a perspective view showing an overall configuration of a nonvolatile semiconductor memory device according to a first embodiment. 1 is a functional block diagram of a nonvolatile semiconductor memory device according to an embodiment. It is a figure explaining the circuit and bias state of the memory cell array of the nonvolatile semiconductor memory device according to the present embodiment. It is a characteristic view of the variable resistance element of the nonvolatile semiconductor memory device according to the present embodiment. It is a characteristic view of the selection element of the nonvolatile semiconductor memory device according to the present embodiment. It is a figure explaining the subject of the nonvolatile semiconductor memory device concerning this embodiment. It is a figure which shows a part of memory cell arrangement | sequence of the non-volatile semiconductor memory device concerning this embodiment. It is a figure which shows the model of the resistance component of the memory cell arrangement | sequence shown in FIG. It is a graph which shows the relationship between the position of the memory cell of the non-volatile semiconductor memory device which concerns on this embodiment, and the reduction rate of the voltage drop with respect to a comparative example, and a leakage current. 3 is a plan view of a memory cell array of the nonvolatile semiconductor memory device according to the embodiment. FIG. FIG. 6 is a plan view of a memory cell array of a nonvolatile semiconductor memory device according to a second embodiment. 6 is a plan view of a memory cell array of a nonvolatile semiconductor memory device according to a third embodiment. FIG. It is a top view of the memory cell arrangement | sequence of the non-volatile semiconductor memory device concerning 4th Embodiment. FIG. 10 is a plan view of a memory cell array of a nonvolatile semiconductor memory device according to a fifth embodiment. It is a top view which shows the shape of the bit line of the non-volatile semiconductor memory device concerning 6th Embodiment. It is a top view which shows the shape of the word line of the non-volatile semiconductor memory device concerning 7th Embodiment. It is a figure which shows a part of memory cell arrangement | sequence of the non-volatile semiconductor memory device which concerns on a comparative example.

  Hereinafter, a nonvolatile semiconductor memory device according to an embodiment will be described with reference to the drawings.

[First Embodiment]
First, the overall configuration of the nonvolatile semiconductor memory device according to the first embodiment will be described.

  FIG. 1 is a perspective view showing the overall configuration of the nonvolatile semiconductor memory device according to the first embodiment. A CMOS circuit 2 including a wiring layer is formed on a normal silicon (Si) substrate 1 (semiconductor substrate) by a commonly used process, and a layer 3 including a plurality of memory cell portions 4 is formed thereon. . Each memory cell portion 4 shown in FIG. 1 corresponds to a memory cell array 11 described later, and wiring is formed with a design rule of 24 nm. Further, a part called a peripheral circuit in a normal nonvolatile semiconductor memory device including the driver, decoder and upper block of FIG. 1 is included in the CMOS circuit 2.

  The CMOS circuit 2 is designed and manufactured according to a design rule of 90 nm, for example, which is looser than the wiring of the memory cell unit 4 except for the connection part with the memory cell unit 4. Around each memory cell portion 4, an electrical connection portion (not shown) to the CMOS circuit 2 is provided. Blocks having these memory cell portions 4 and peripheral electrical connection portions as a unit are arranged in a matrix. Further, a through hole (not shown) is formed in the layer 3 including the memory cell portion 4. The electrical connection portion of the memory cell portion 4 is connected to the CMOS circuit 2 through this through hole. The operation of the memory cell unit 4 is controlled by the CMOS circuit 2. The input / output unit 5 includes a terminal having electrical coupling with the input / output unit of the CMOS circuit 2. These terminals are also connected to the input / output portion of the CMOS circuit 2 through the above-described through holes. Data, commands, addresses, and the like necessary for the CMOS circuit 2 to control the operation of the memory cell unit 4 are exchanged with the outside through the input / output unit 5. The input / output unit 5 is formed at the end of the layer 3 including the memory cell unit 4.

  With the above configuration, a portion corresponding to the protective film of the CMOS circuit 2 can be shared with the insulating film formed in the memory cell portion 4. In this embodiment, since the memory cell unit 4 and the CMOS circuit 2 are coupled in the stacking direction (Z direction), the operation time can be reduced without increasing the chip area, and the number of memory cells that can be accessed simultaneously is increased. Significant increase is possible. The input / output unit 5 is bonded to the lead frame in the packaging process in the same manner as the input / output unit of a normal nonvolatile semiconductor memory device.

  Next, functional blocks of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG.

  The nonvolatile semiconductor memory device includes a memory cell array 11 having a plurality of row lines, a plurality of column lines, and a plurality of memory cells selected by these row lines and column lines. This memory cell array 11 corresponds to the memory cell section 4 shown in FIG. In the following description, the row line is referred to as a word line and the column line is referred to as a bit line, in accordance with a normal nonvolatile semiconductor memory device.

  The nonvolatile semiconductor memory device also includes a row decoder 12 that selects a word line and a column decoder 13 that selects a bit line when erasing / writing data. The column decoder 13 includes a driver that controls a data erasing / writing operation.

  Further, the nonvolatile semiconductor memory device includes an upper block 14 as a control circuit that selects a memory cell to be accessed in the memory cell array 11. The upper block 14 gives a row address and a column address to the row decoder 12 and the column decoder 13, respectively. The power supply 15 generates a predetermined voltage combination corresponding to each operation of data erasing / writing and supplies it to the row decoder 12 and the column 13.

  With the above functional block, all the memory cells connected to the same word line can be erased / written collectively. The CMOS circuit 2 shown in FIG. 1 is provided with peripheral circuits such as the row decoder 12, the column decoder 13 and the upper block 14 shown in FIG.

  Next, the memory cell array 11 of the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIG.

  The memory cell array 11 is arranged so that a plurality of word lines WL and bit lines BL intersect, and a memory cell MC having a variable resistance element VR is formed at each intersection of the word lines WL and bit lines BL. ing. A selection element S is connected in series to the variable resistance element VR of the memory cell MC, and the variable resistance element VR is supplied with a voltage from the word line WL and the bit line BL via the selection element S.

According to the structure of the memory cell array 11 as described above, the word lines WL and the bit lines BL have a simple line and space pattern, and the word lines WL and the bit lines BL intersect when the memory cell array 11 is formed. There is no need to consider misalignment because the positional relationship is acceptable. That is, since the alignment accuracy of the memory cell MC can be extremely relaxed, the nonvolatile semiconductor memory device can be easily manufactured. Further, in the case of the above structure, one memory cell MC can be formed per 4F ² region, so that high integration of the nonvolatile semiconductor memory device can be achieved.

  A row decoder 12 is connected to each word line WL of the memory cell array 11, and a column decoder 13 is connected to each bit line BL. The row decoder 12 and the column decoder 13 are supplied with a predetermined voltage corresponding to each data erasing / writing operation from the power supply 15.

Data erasing / writing to the memory cell MC is performed by first selecting the selected cell MC to be accessed in the memory cell array 11 by the row decoder 12 and the column decoder 13 based on the row address and column address output from the upper block 14. A word line WL and a bit line BL connected to _S are selected. In the case of FIG. 3, the row decoder 12 and the column decoder 13 select the word line WL0 and the bit line BL0, respectively.

  Subsequently, the row decoder 12 supplies the selected word line voltage VSW to the selected word line WL (WL0 in the case of FIG. 3), and applies the unselected word line voltage VUW to other unselected word lines WL and the like. Supply. On the other hand, the column decoder 13 supplies the selected bit line voltage VSB to the selected bit line BL (BL0 in the case of FIG. 3) and supplies the unselected bit line voltage VUB to the other unselected bit lines BL. . By setting the selected word line voltage VSW, unselected word line voltage VUW, selected bit line voltage VSB, and unselected bit line voltage VUB to appropriate voltages, access to a predetermined memory cell MC in the memory cell array 11 can be performed. it can.

  Next, characteristics of the memory cell MC will be described.

  First, the characteristics of the variable resistance element VR of the memory cell MC will be described with reference to FIG.

The variable resistance element VR is formed using, for example, a resistance change material typified by TiO ₂ . This resistance change material is a material that transitions between at least two resistance values of a low resistance state (LRS) and a high resistance state (HRS).

  When a voltage of a certain level or higher (in the case of FIG. 4, a voltage equal to or higher than the voltage Vmset in the negative direction) is applied to the resistance change material in the high resistance state, as shown by an arrow A1 in FIG. Transition. Such a transition of the variable resistance material from the low resistance state to the high resistance state is called a set operation. Data writing in the present embodiment is realized by this “set operation”. In FIG. 4, the current flowing through the resistance change material at the start of the set operation is shown as Iset.

  On the other hand, the resistance change material in the low resistance state transitions to the high resistance state as indicated by an arrow A2 in FIG. 4 when a current of a certain level or more (in the case of FIG. 4, a current equal to or greater than the current Ireset) flows. Such a transition of the variable resistance material from the low resistance state to the high resistance state is referred to as “reset operation”. Data erasure in the present embodiment is realized by this reset operation. In FIG. 4, the voltage applied to the resistance change material at the start of the reset operation is shown as Vmreset.

  In particular, as shown in FIG. 4, a variable resistance element VR in which a set operation and a reset operation are performed by applying voltages of different polarities is referred to as a “bipolar operation element”, and is combined with a selection element S described later to form a memory cell MC. Used for.

The variable resistance element VR can be formed of a thin film made of ZnMn ₂ O ₄ , HfO _x , NiO, SrZrO ₃ , Pr _0.7 Ca _0.3 MnO ₃ , carbon, or the like, in addition to TiO ₂ .

  Next, the characteristics of the selection element S of the memory cell MC will be described with reference to FIG.

  Since the variable resistance element VR is a bipolar operation element as described above, the selection element S needs to have a characteristic of flowing a predetermined current with both positive and negative polarities as shown in FIG. For this reason, a diode, a tunnel element, or the like with a large reverse leakage current is used as the selection element S.

The most important parameter as a characteristic of the selection element S is a half-selected cell current I _H. Here, the half-selected cell current I _H is the variable resistor VR set operation / reset select current necessary for operating the cell current I _S of _the voltage applied to the memory cell MC to stream the selected cell current I _S the when V _S, refers to the current flowing through the memory cell MC when a voltage is applied to V _{S /} 2 to the memory cell MC. The memory cell MC through which this half-selected cell current flows is called a “half-selected cell”.

Next, a bias state at the time of data erasing / writing of the memory cell array 11 of the nonvolatile semiconductor memory device according to the present embodiment will be described with reference to FIG. As an example, the word line WL0 is selected word line, the bit line BL0 selected bit line, shows a biased state when the memory cells connected MC _S at intersections of word lines WL0 and the bit line BL0 and the selected cell Yes.

Since the nonvolatile semiconductor memory device according to the present embodiment performs data erasing / writing by a bipolar operation, a predetermined bit line voltage VSB, a non-selected bit line VUB, a selected word line VSW, and a non-selected word line VUW are respectively predetermined. Voltages V, 0, V / 2 and V / 2. In this case, approximately the voltage V will be applied to the selected cell MC _S. That is, if the voltage V _S that indicates the voltage V in FIG. 5, it is possible to apply a voltage V _S necessary for data erase / write the variable resistance element VR. At this time, flow through the selected cell current I _S required for data erase / write through the bit line BL0 and word line WL0 to the selected cell MC _S.

However, in practice, the influence of the wiring resistance of the bit lines BL and the word line WL, and as shown in FIG. 3 dashed arrows, the leakage current flowing through the half-selected cell MC _H of (half-selected cell current I _H) It is necessary to consider the impact.

For example, as shown in the upper diagram of FIG. 6, it is assumed that the selected bit line BL0 is supplied with the voltage V _S as the selected bit line voltage VSB, and the selected word line WL0 is supplied with 0 V as the selected word line voltage VSW. In this case, the influence of the wiring resistance of the selected bit line BL0 in between the column decoder 13 and select cells MC _S, the selected bit line voltage VSB is reduced. Further, the influence of the wiring resistance of the selected word line WL0 is between the row decoder 12 and the selected cell MC _S, the selected word line voltage VSW is increased. Therefore the voltage applied to the selected cell MC _S is lower than the voltage V _S necessary for data erase / write, it can not be normal data erase / write for the selected cell MC _S. In particular, when the memory cell MC far from the row decoder 12 and the column decoder 13 is selected, the influence of the wiring resistance of the word line WL and the bit line BL becomes large.

In order to solve this problem, voltage compensation is performed on the selected bit line voltage VSB and the selected word line voltage VSW as shown in the lower diagram of FIG. That is, the selected bit line voltage VSB is a further voltage drop by voltage higher due to the wiring resistance of the selected bit line BL0 than the voltage V _S. Further, the selected word line voltage VSW is set to a voltage lower than 0V by a voltage drop due to the wiring resistance of the selected word line WL0. This makes it possible to voltage _{V S} to the selected cell MC _S.

However, connected to the selected bit line BL0, and, in the half-selected cell MC _H located between the selected cell MC _S from the column decoder 13, a high voltage of the selected bit line VSB supplied than the voltage _V S / 2 It will be. In this case, the leakage current through the half-selected cell MC _H increases. Moreover, when the half-selected cells MC _H closer to the column decoder 13, there is a possibility that the voltage higher than the voltage V _S will be applied, in this case, the disturbance is also half-selected cells MC _H resulting in the set operation / reset operation Problems arise. This is similarly caused the half-selected cells MC _H connected to the selected word line WL0.

  Therefore, in the nonvolatile semiconductor memory device according to the present embodiment, the memory cell array 11 is formed as follows in order to suppress such a voltage drop and an increase in leakage current due to the wiring resistance.

  FIG. 7 is a diagram showing the shape of the memory cell array 11 of the nonvolatile semiconductor memory device according to this embodiment. In FIG. 7, only one bit line BL is shown for n (n is an integer of 2 or more) word lines WL for easy understanding of the outline of the present embodiment. In FIG. 7, the t-th (t is an integer of 2 to n) word line from the end T1 side (first end) of the bit line BL is WLt, and the word line WLt and the bit line BL are crossed. The arranged memory cell is called MCt.

  In the nonvolatile semiconductor memory device according to this embodiment, the width of the bit line BL in the word line direction (hereinafter referred to as “bit line width”) is wide from the end T1 to the end T2 (second end). is doing. In other words, the line width of the bit line BL in the memory cell MC2 (second portion) is wider than the line width of the bit line BL in the memory cell MC1 (first portion), and the memory cell MC3 (third portion). Are formed so as to be narrower than the line width of the bit line BL.

In this embodiment, as described above, data erasing / writing is performed by a bipolar operation. For example, when the memory cell MCk arranged at the intersection of the bit line BL and the word line WLk (k is an integer of 2 or more and n or less) is the selected memory cell, the voltage V V from the end T1 side of the selected word line BL. ^* Supply. Further, 0 V is supplied from the row decoder 12 to the selected word line WLk, and V / 2 is supplied to the other non-selected word lines WL. At this time, since the bit line BL has the structure shown in FIG. 7 as described above, the resistance components of the selected cell MCk are memory cells MC1 to MCk− that are closer to the A end than the selected cell MCk. Since it always becomes larger than the resistance component of 1, the voltage drop and the leakage current are reduced.

  Here, the effect of the nonvolatile semiconductor memory device according to the present embodiment will be described in comparison with the nonvolatile semiconductor memory device according to the comparative example shown in FIG. In the case of this comparative example, the bit line BL has a constant line width.

  FIG. 8 is a diagram in which FIGS. 7 and 17 are modeled by resistance components. In FIG. 8, a resistance component RLt indicates a wiring resistance of the bit line BL between the word line WLt-1 and the word line WLt, and a resistance component RCt indicates a resistance component of the memory cell MCt.

  The width of the word line WL in the bit line direction (hereinafter referred to as “word line width”) and the line width of the bit line BL shown in FIGS. Further, the line width of the bit line BL at the center of the word line WL1 in FIG. 7 is 2/3 × F, and the line width of the bit line BL at the center of the word line WLn is 4/3 × F.

  Here, the effect of this embodiment relative to the case of the comparative example is calculated using the model shown in FIG. In this calculation, the resistance components RL and RC shown in FIG. 8 are calculated using the sheet resistance. Further, the wiring resistance of the word line WL is not considered. In this case, the voltage V / 2 is supplied to the junctions of the memory cells MC1 to MCk-1 with the word lines WL1 to WLk-1. Further, it is assumed that the voltage V is supplied to the junction between the memory cell MCk and the bit line BL, and the current is 0A.

In this case, if the voltage V ^* and the current I on the end T1 side of the bit line BL are obtained, the voltage difference ΔV = (V ^* −V) is a voltage drop, and the current I becomes the leak current Ileak.

  FIG. 9 is a graph showing the reduction rate of the voltage drop ΔV and the leakage current Ileak of this embodiment relative to the comparative example. In this graph, the horizontal axis is the number of the memory cell, that is, the position from the end T1. The number of memory cells is 1000.

  When the voltage drop of this embodiment is ΔV1, the leak current I1, the voltage drop of the comparative example is ΔV2, and the leak current is I2, the reduction rate of the voltage drop ΔV is 100 × (ΔV2−ΔV1) / ΔV2 (%), The reduction rate of the leakage current Ileak can be calculated by 100 × (I2−I1) / I2 (%).

  As can be seen from the graph shown in FIG. 9, it can be seen that both the reduction rate of the voltage drop ΔV and the reduction rate of the leakage current Ileak increase as the distance from the end T1 increases. Specifically, when the memory cell MC1000 farthest from the end T1 (closest from the end T2) is the selected cell, the reduction rate of the voltage drop ΔV is 48.3%, and the reduction rate of the leakage current Ileak is 30. It turns out that the effect of 7% is acquired.

  Next, FIG. 10 shows a plan view of the memory cell array 11 according to this embodiment in which the bit lines BL having the shape shown in FIG. 7 are arranged. Here, of the end portions of the bit line BL, the end portion on the left side of the paper surface is T1, and the end portion on the right side of the paper surface is T2.

  In the case of this memory cell array 11, the even-numbered bit lines BLe counted from the upper side of FIG. 10 are connected to the first column decoder 13a constituting the column decoder 13 disposed on the left side of FIG. The line widths of the even-numbered bit lines BLe are formed so as to increase from the end T1 to the end T2. On the other hand, the odd-numbered bit lines BLo counted from the upper side of FIG. 10 are connected to the second column decoder 13b constituting the column decoder 13 arranged on the right side of FIG. The odd-numbered bit lines BLo are formed so that the line width increases from the end T2 to the end T1.

  As described above, the bit line BLo whose line width increases from the end portion T1 to the end portion T2 and the bit line BLe which decreases from the end portion T1 to the end portion T2 are alternately arranged, thereby alternately arranging the memory cells. The effect of suppressing the voltage drop ΔV and the leakage current Ileak can be obtained without increasing the size of the array 11.

  Here, the line width of the word line WL is F, the space width of the bit line BL is F, the line width of the bit line BL in the smallest memory cell MC is s × F (where 0 <s <1), and the largest memory. When the line width of the bit line BL in the cell MC is (2-s) × F, the memory according to the comparative example in which the line width of the bit line BL is constant and the half pitch of the word line WL and the bit line BL is F The memory cell array 11 can be formed with the same size as the cell array.

  Further, when s = 2/3, the voltage drop ΔV can be reduced by 48.3% at the maximum as compared with the comparative example. Further, when s can be reduced, that is, when the difference between the size of the smallest memory cell MC and the largest memory cell MC can be increased, the voltage of the memory cell array is maintained while maintaining the same size as the comparative example. The drop ΔV can be reduced. For example, when s = 0.1, the reduction rate of the voltage drop ΔV of the present embodiment relative to the comparative example can be reduced to 93% at the maximum.

  As described above, according to the present embodiment, the voltage drop and the leakage current can be reduced as compared with the case where the line width of the bit line is made constant as in the comparative example, and therefore, the data erasure / write reliability is high. A semiconductor memory device can be provided. Furthermore, by using the memory cell array 11 shown in FIG. 10, this effect can be obtained without increasing the size of the memory cell array.

[Second Embodiment]
As in the first embodiment, the nonvolatile semiconductor memory device according to the second embodiment extends from the end T1 to the end T2 over the bit line BL and the end T1 to the end T2. In this embodiment, it is assumed that the bit lines BL whose line width is narrow cannot be alternately arranged.

  FIG. 11 is a plan view of the memory cell array 21 of the nonvolatile semiconductor memory device according to this embodiment. FIG. 11 shows a row decoder 22 corresponding to the row decoder 12 and a column decoder 23 corresponding to the column decoder 13 in addition to the memory cell array 21. Other functional blocks are the same as those in the first embodiment.

  In the case of the memory cell array 21 according to the present embodiment, all the bit lines BL are connected to the column decoder 23 disposed on the left side of FIG. 10 at the end T1. Further, the line widths of all the bit lines BL are formed so as to increase from the end T1 to the end T2.

  Even in the case where the bit lines BL cannot be arranged as in the first embodiment, according to the present embodiment, a voltage drop and a leakage current can be reduced as in the first embodiment.

[Third Embodiment]
In the first and second embodiments, it is assumed that the selected bit line voltage and the non-selected bit line voltage are supplied from one side of the bit line, but the third embodiment selects the selected bit from both sides of the bit line. In this embodiment, the line voltage and the unselected bit line voltage are supplied.

  FIG. 12 is a plan view of the memory cell array 31 of the nonvolatile semiconductor memory device according to this embodiment. In addition to the memory cell array 31, FIG. 12 shows a row decoder 32 corresponding to the row decoder 12, and a first column decoder 33a and a second column decoder 33b constituting a column decoder corresponding to the column decoder 13. . Other functional blocks are the same as those in the first embodiment.

  In the case of the memory cell array 31 according to the present embodiment, the first column decoder 33a disposed on the left side in FIG. 12 at the end portion T1 and the second row disposed on the right side in FIG. It is connected to the column decoder 33b. These bit lines BL are formed so that the line width increases from the end portion T1 and the end portion T2 to the intermediate portion between the end portions T1 and T2.

  According to the present embodiment, a voltage drop and a leakage current can be reduced as in the first embodiment.

  Furthermore, by disposing the column decoders 33a and 33b on both sides of the bit line BL, the memory cell MC farthest from both the column decoders 33a and 33b is located at the center of the bit line BL. As a result, the voltage drop can be halved compared to the comparative example shown in FIG.

  Specifically, as in the first embodiment, the narrowest line width of the bit line BL is s × F, the widest line width is (2-s) × F, and s = 2/3. About 75% can be obtained as the reduction rate of the voltage drop of the present embodiment with respect to the example.

[Fourth Embodiment]
In the first to third embodiments, the change in the line width of one bit line BL is intended to reduce the voltage and the leakage current. However, the third embodiment is different from the column decoder. In this embodiment, the line width of the word line WL is changed according to the distance.

  FIG. 13 is a plan view of the memory cell array 41 of the nonvolatile semiconductor memory device according to this embodiment. In addition to the memory cell array 41, FIG. 13 shows a row decoder 42 corresponding to the row decoder 12 and a column decoder 43 corresponding to the column decoder 13. Other functional blocks are the same as those in the first embodiment.

  In the case of the memory cell array 41 according to this embodiment, the line width and space width of all the bit lines BL are constant at F. On the other hand, for the word lines WL, each word line WL is formed with a constant line width, but the line width increases in a linear function as the distance from the column decoder 43 increases. For example, in the case of FIG. 13, the word line WL ′ (first row line) is a line compared to the word line WL ″ (second row line) that is farther from the column decoder 43 than the word line WL ′. The width is narrow. On the other hand, the space width of the word line WL is constant regardless of the distance from the column decoder 43.

  For example, the line width of the word line WL closest to the column decoder 43 is s × F (where 0 <s <1), the line width of the farthest word line WL is (2-s) × F, and the space of the word line WL When the width is F, the effect of reducing the voltage drop ΔV and the leakage current Ileak shown in the graph of FIG. 9 can be obtained.

  As described above, according to the present embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, since the line width for each bit line and the line width for each word line are constant, the wiring pattern is simpler than that of the first to third embodiments, and the processing of the memory cell array is easy.

[Fifth Embodiment]
The fifth embodiment is a combination of the second embodiment and the fourth embodiment.

  FIG. 14 is a plan view of the memory cell array 51 of the nonvolatile semiconductor memory device according to this embodiment. FIG. 14 shows a row decoder 52 corresponding to the row decoder 12 and a column decoder 53 corresponding to the column decoder 13 in addition to the memory cell array 51. Other functional blocks are the same as those in the first embodiment.

  In the case of the memory cell array 51 according to the present embodiment, as in the second embodiment, all the bit lines BL are connected to the column decoder 53 disposed on the left side in FIG. The line width increases from the end T2 to the end T2. The word lines WL are each formed with a constant line width as in the fourth embodiment, but the line width increases linearly as the distance from the column decoder 53 increases. On the other hand, the space width of the word line WL is constant regardless of the distance from the column decoder 53.

  According to the present embodiment, it is possible to further reduce the voltage drop and the leakage current as compared with the first embodiment.

  Specifically, the narrowest line width of the bit line BL is s × F (where 0 <s <1), the widest line width is (2-s) × F, and the word line WL closest to the column decoder 53 When the line width is s × F, the line width of the farthest word line WL is (2-s) × F, and s = 2/3, the reduction rate of the voltage drop of the present embodiment relative to the comparative example is about 68. 6% can be obtained.

[Sixth Embodiment]
The sixth embodiment is a modification of the first to third and fifth embodiments.

  FIG. 15 is a diagram showing the shape of the bit line of the nonvolatile semiconductor memory device according to the sixth embodiment. In FIG. 15, reference numerals are given in the same manner as FIG. 7.

  In the first to third and fifth embodiments, slope-shaped bit lines are formed in which the line width gradually increases with distance from the column decoder.

On the other hand, in the present embodiment, as shown in FIG. 15, a step-like line width gradually increases from the end T1 (column decoder) side to which the voltage V ^* is supplied to the end T2. A bit line BL is formed.

  In the case of FIG. 15, the lines at the intersections (first part, second part, third part, fourth part,...) Of the bit line BL1 with the word lines WL1, WL2, WL3, WL4,. When the widths are expressed as W1, W2, W3, W4,..., Stepwise bit lines whose line width is widened every two word lines WL so that W1≈W2 <W3≈W4 <. BL is formed.

  As described above, in the first to third and fifth embodiments, even if the stepped bit line whose line width changes stepwise is formed instead of the slope shape, the first to third and fifth embodiments are formed. The same effect as that of the fifth embodiment can be obtained.

  This embodiment can also be applied to the fifth embodiment together with the seventh embodiment described later.

[Seventh Embodiment]
The seventh embodiment is a modification of the fourth and fifth embodiments.

  FIG. 16 is a diagram showing the shape of the word line of the nonvolatile semiconductor memory device according to the seventh embodiment. In FIG. 16, reference numerals are given in the same manner as FIG. 7.

  In the fourth and fifth embodiments, the word lines are formed so that the line width increases for each line as it is far from the column decoder.

On the other hand, in this embodiment, as shown in FIG. 16, the line width is widened for each of a plurality of groups from the end T1 (column decoder) side to which the voltage V ^* is supplied to the end T2. Thus, the word line WL is formed.

  In the case of FIG. 16, the line widths of the word lines WL1 (first row line), WL2 (first row line), WL3 (second row line), WL4 (second row line),. , W3, W4,..., The width of the word line WL is increased every two groups so that W1≈W2 <W3≈W4 <.

  As described above, in the fourth and fifth embodiments, even when the line width of the word line is changed for each of a plurality of groups instead of for each one, the same as in the fourth and fifth embodiments. The effect of can be obtained.

  Note that this embodiment can also be applied to the fifth embodiment together with the sixth embodiment.

[Others]
As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, in the first to seventh embodiments, even when the word lines and row decoders as row lines are replaced with the bit lines and column decoders as column lines, the same effects as those of the embodiments can be obtained. Can do.

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... CMOS circuit, 3 ... Layer including memory cell part, 4 ... Memory cell part, 5 ... Input / output part, 11, 21, 31, 41, 51 ... Memory cell array, 12, 22, 32, 42, 52 ... Row decoder, 13, 23, 33, 43, 53 ... Column decoder, 14 ... Upper block, 15 ... Power supply.

Claims (7)

A plurality of memories including a plurality of column lines extending in the column direction, a plurality of row lines extending in the row direction intersecting with the column direction, and variable resistance elements arranged at intersections of the plurality of column lines and the row lines A memory cell array having cells;
A column decoder disposed at at least one of a first end and a second end of the column line for supplying a voltage necessary for the state transition of the variable resistance element to the memory cell via the column line; Prepared,
The column line has a first portion, a second portion farther from the column decoder than the first portion, and a third portion farther from the column decoder than the second portion, and the row direction of the second portion The non-volatile semiconductor memory device is characterized in that the line width of the first portion is equal to or wider than the line width of the first portion in the row direction and narrower than the line width of the third portion in the row direction. The column decoder comprises a first column decoder and a second column decoder,
A part of the plurality of column lines is a first column line, and another part is a second column line;
The first column decoder is disposed at the first end of the first column line;
The second column decoder is disposed at the second end of the second column line;
The first column line has a wider line width in the row direction from the first end to the second end,
The nonvolatile semiconductor memory device according to claim 1, wherein the second column line has a line width in the row direction that increases from the second end portion to the first end portion. The nonvolatile semiconductor memory device according to claim 2, wherein the first column lines and the second column lines are alternately arranged in the row direction. The column decoder is disposed at the first end of the plurality of column lines;
The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of column lines have a line width in the row direction that increases from the first end to the second end. The column decoder comprises a first column decoder and a second column decoder,
The first column decoder and the second column decoder are disposed at the first end and the second end of the column line, respectively.
2. The line width in the row direction increases from the first end portion and the second end portion to an intermediate portion between the first end portion and the second end portion. Nonvolatile semiconductor memory device. The line width in the column direction of the other row line near the column decoder is wider than the line width in the column direction of the predetermined row line far from the column decoder. 5. The nonvolatile semiconductor memory device according to 4. A plurality of memories including a plurality of column lines extending in the column direction, a plurality of row lines extending in the row direction intersecting with the column direction, and variable resistance elements arranged at intersections of the plurality of column lines and the row lines A memory cell array having cells;
A column decoder disposed at at least one of a first end and a second end of the column line for supplying a voltage necessary for the state transition of the variable resistance element to the memory cell via the column line; Prepared,
A part of the plurality of row lines is a first row line, another part is a second row line, the second row line is farther from the decoder than the first row line, and the A non-volatile semiconductor memory device, wherein a line width in the column direction is wider than one row line.

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