JP2012164209A - Cache control method, cache control device, and program for cache control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache control method capable of suppressing deterioration of processing performance even if receiving a large amount of data, when processing the received data by writing it in a cache memory.SOLUTION: Area setting means 81 sets a writing area, to which a predetermined amount of received data is writable, to a cache memory. Area deletion means 82 deletes an area to which received data of an object of processing is written, for each processing to a part or all of the received data written in the writing area. The area setting means 81 newly sets an area of an amount which corresponds to the deleted area as an area to which received data is writable in a position to which received data to be received after having received the predetermined amount of received data is written, for each processing to the received data.

Description

  The present invention relates to a cache control method, a cache control apparatus, and a cache control program for controlling a cache memory using cache injection.

  First, reception processing when receiving a packet via a communication network will be described. In general reception processing, a reception buffer / reception queue (Receive Queue, hereinafter referred to as RQ) prepared in advance by the device driver on the main memory (hereinafter referred to as memory) is used.

  FIG. 13 is an explanatory diagram illustrating a general reception process and a state of the RQ when performing the reception process. When the NIC (Network Interface Card) receives the packet (step S601 in FIG. 13A), the received data is transferred to the memory by DMA (Direct Memory Access) (step S602). In the memory, as shown in step B1 in FIG. 13B, the data transferred by the driver to the reception buffer / reception queue (RQ) prepared on the memory is written (step S603).

  Thereafter, when the NIC notifies the CPU of a hardware interrupt (hereinafter referred to as H / W interrupt) (step S604), the CPU starts processing on the received data (step S605).

  At this time, since the received data is not registered in the cache memory (hereinafter also referred to as a cache), as shown in Step B2 in FIG. S606), a cache miss occurs (step S607). As a result, data is read from the reception buffer on the memory to the cache (step S608). While the data is read from the memory, the CPU interrupts the process and waits for the data to be acquired (step S609). When the data read from the memory is registered in the cache (step S610), the CPU reads the data and resumes the process (step S611). The processes in steps S601 to S611 described above are performed, and the reception process ends (step S612).

  Next, prefetch widely used as a method for solving a delay caused by memory access will be described. Prefetch is a cache control method for solving a delay due to memory access by reading the data from the memory into the cache before referring to the data.

  Next, cache injection, which is a cache control method for solving a delay due to memory access from the viewpoint of data writing, will be described. Cache injection is a cache control method for writing data directly to the cache without writing it to the memory.

  Non-Patent Document 1 describes a cache injection mounting method. In the method described in Non-Patent Document 1, the address of data to be injected is registered in a table attached to the cache, and writing to the address is performed by snooping, and writing to the cache is performed. Non-Patent Document 1 describes a method of using an open_window instruction (opwd) as an instruction for registering a cache injection target address.

  Further, Patent Document 1 describes a method for implementing cache injection for data that has already been cached. The method described in Patent Document 1 uses a cached address area as a target for cache injection. By creating a cache, it is possible to set the target for cache injection.

  Note that Non-Patent Document 2 describes a cache creation method based on the Power architecture. In the method described in Non-Patent Document 2, a cache is created by a Data Cache Block Set to Zero (dcbz) instruction that creates a cache initialized with 0 without accessing the memory.

  Patent Document 2 describes an information processing apparatus that communicates with the outside via a network. The information processing apparatus described in Patent Document 2 uses the data stored in the cache memory, and then erases the cache line corresponding to the used data in the cache memory.

  Patent Document 3 describes a packet transfer apparatus having a buffer memory. The packet transfer apparatus described in Patent Document 3 releases the buffer area when the buffer area becomes unnecessary after the packet processing is completed, and the capacity required as the header area is larger than the capacity of one in the buffer array Allocate multiple buffers.

  Patent Document 4 describes a data transfer method between processors. In the data transfer method described in Patent Document 4, in a series of packet transfers, a reception end interrupt is applied to the CPU when the last packet data of the first packet sequence is written to the main memory. Then, according to the address range information indicating the write range of the main memory notified at the time of interruption, the range written in the main memory at this time is recognized, and the cache processing for that portion is executed.

US Pat. No. 7,836,254 JP 2008-35202 A JP 2009-88622 A JP-A-8-287031

A. Milenkovic and V. Milutinovic, "Cache injection on bus based multiprocessors", SRDS'98 Proceedings of the The 17th IEEE Symposium on Reliable Distributed Systems, p.341-346, 1998. IBM, "Power ISA Version 2.06 Revision B", p. 685, 965, July 23, 2010.

  The general reception process shown in FIG. 13A has a problem that the reception process is delayed because the process in the CPU is interrupted while the process of reading data from the memory to the cache is being performed.

  In order to perform prefetching, it is assumed that data to be read already exists in the memory. That is, after data is written to the network reception buffer on the memory and the CPU detects the writing (after the CPU detects an interrupt), the CPU can prefetch.

  Therefore, if the CPU tries to refer to the packet immediately, the prefetch is not in time and the processing of the CPU is interrupted, causing a delay. Specifically, when the CPU tries to prefetch various headers of the received packet or the beginning of the received data, the target packet is referred to immediately after the reception processing is started or at a relatively early stage. Not in time. Therefore, the processing of the CPU is interrupted, and the delay due to memory access cannot be solved. In particular, in the reception process of a packet having a small data size, the prefetch effect cannot be obtained.

  Furthermore, memory access is not reduced by the prefetch method. For example, when a multi-core processor performs a packet reception process via a communication network and a process in which another memory access occurs in parallel, if the memory access is concentrated, the memory access bandwidth is compressed. As a result, there is a problem that the processing performance does not improve (does not scale out).

  On the other hand, in cache injection, since data is directly written into the cache, the CPU only needs to read the data in the cache and does not need to read from the memory, so there is no delay due to memory access. This method is useful when data that does not exist in the memory is received from the NIC or another core in a reception process for receiving a packet via a communication network or parallel processing by a multi-core.

  Further, in the cache injection, since data is generally not written to the memory, memory access can be reduced. In addition, the use of cache injection for packet reception processing and data transfer between cores via a communication network can solve the problem that the processing performance does not improve (does not scale out) due to pressure on the memory access bandwidth. .

  However, when cache injection is simply used in packet reception processing or multi-core parallel processing, there is a problem that the effect of cache injection cannot be sufficiently obtained at high load. Specifically, in the case of a high load, it is not possible to sufficiently obtain effects such as resolution of processing delay due to memory access and resolution of processing performance limit due to memory access bandwidth limitation.

  Since the capacity of the cache is generally small, in a situation where a large amount of data is written to the cache, other data is evicted from the cache. That is, when the packet reception processing becomes heavy and a large amount of data exceeding the reception processing performance is sent to the cache by cache injection, the cache overflows and the data referenced by the CPU is transferred from the cache to the memory before processing. It will be kicked out.

  If the data before processing is evicted to the memory, a cache miss occurs when the CPU tries to refer to the evicted data. At this time, the CPU reads the target data from the memory as in the case where the cache injection is not used. Therefore, a processing delay due to memory access occurs.

  Also, even when parallel processing is performed in a multi-core sharing a cache memory, a large amount of cache is used for reception processing in one core, so that data processed in other cores is evicted from the cache to the memory. When this occurs, a delay due to memory access occurs to refer to the evicted data. This reduces the overall processing performance.

  Therefore, the present invention provides a cache control method, a cache control device, and a cache control method capable of suppressing a decrease in processing performance even when a large amount of data is received when processing is performed by writing the received data to a cache memory. An object is to provide a cache control program.

  The cache control method according to the present invention sets a write area, which is an area in which a predetermined amount of received data can be written, in the cache memory, and performs processing for some or all of the received data written in the write area. Delete the area where the received data to be processed is written, and write the received data to the position where the received data to be received is written after receiving a predetermined amount of received data for each process on the received data As a possible area, an area corresponding to the deleted area is newly set.

  The cache control device according to the present invention includes an area setting means for setting a write area, which is an area in which a predetermined amount of received data can be written, in the cache memory, and a part or all of the received data written in the write area. A deletion unit that deletes an area in which received data to be processed is written for each process, and the area setting unit receives a predetermined amount of received data for each process on the received data An area corresponding to the deleted area is newly set as an area where the received data can be written at a position where received data to be received later is written.

  The cache control program according to the present invention includes an area setting process for setting a write area, which is an area in which a predetermined amount of received data can be written, in a cache memory, and a part or For each process for all received data, a deletion process is executed to delete the area in which the received data to be processed is written. In the area setting process, a predetermined amount is set for each process for the received data. It is characterized in that an area corresponding to the deleted area is newly set as an area where the received data can be written at a position where received data to be received after receiving the received data is written.

  According to the present invention, when the received data is written in the cache memory for processing, it is possible to suppress a decrease in processing performance even when a large amount of data is received.

It is a block diagram which shows the example of the cache control apparatus in the 1st Embodiment of this invention. It is a block diagram which shows the example of CPU in 1st Embodiment. It is a flowchart which shows the operation example of the cache control apparatus in 1st Embodiment. It is a flowchart which shows the operation example of the cache control apparatus in 1st Embodiment, and the example of a state of RQ. It is a block diagram which shows the example of the cache control apparatus in the 2nd Embodiment of this invention. It is a block diagram which shows the example of CPU in 3rd Embodiment. It is explanatory drawing which shows the example of the data structure set to a reception buffer queue. It is a flowchart which shows the operation example of the cache control apparatus in 3rd Embodiment. It is explanatory drawing which shows the other example of the data structure set to a reception buffer queue. It is a block diagram which shows the example of CPU in 5th Embodiment. It is a flowchart which shows the operation example of the cache control apparatus in 5th Embodiment. It is a block diagram which shows the example of the minimum structure of the cache control apparatus by this invention. It is explanatory drawing which shows the state of RQ at the time of performing a general reception process and a reception process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1. FIG.
FIG. 1 is a block diagram showing an example of a cache control device according to the first embodiment of the present invention. The cache control device in this embodiment includes a processor 1, a NIC 2, and a memory 3.

  The processor 1 includes a CPU 11, a cache memory 12 (hereinafter referred to as a cache 12), a memory controller 13 (hereinafter referred to as an MC 13), and an I / O controller 15 (hereinafter referred to as an IOC 15). . The NIC 2 is connected to the IOC 15, and the memory 3 is connected to the MC 13.

  Inside the processor 1, the CPU 11 is connected to the cache 12, and the cache 12, MC 13, and IOC 15 are connected to each other via the internal bus 14.

  A reception buffer (not shown) is secured on the memory 3, and a part of the reception buffer is temporarily stored in the cache 12 by access or cache injection by the CPU 11.

  FIG. 2 is a block diagram illustrating an example of the CPU 11 in the present embodiment. The CPU 11 includes an area setting unit 21 and an area deleting unit 22.

  The area setting means 21 sets an area in which a predetermined amount of received data can be written (hereinafter referred to as a write area) in the cache 12 as a target for cache injection. Specifically, at the time of initialization, the area setting unit 21 sets an area in which an integer number (n) of packets from the head of the reception queue (RQ) are written in the cache 12 as a target for cache injection. For example, as described in Patent Document 1 and Non-Patent Document 2, the area setting unit 21 may create a cache initialized with 0 to set the cache area as a target of cache injection. However, the method for setting an area to be cache-injected on the cache 12 is not limited to the above method.

  The area setting means 21 newly sets an area corresponding to the deleted area in the cache 12 as a target for cache injection after the area deleting means 22 described later deletes a part or all of the write area. . At this time, the area setting unit 21 sets a new writing area at a position to write the received data received after receiving a predetermined amount of received data.

  The area deleting unit 22 deletes an area in which received data that is a target of a predetermined process is written out of the received data written in the writing area of the cache 12. Examples of the predetermined process include a process of analyzing a header of a received packet, a process of discarding a packet, and a process of starting a higher layer handler. However, the processing to be performed is not limited to the above processing. In the following description, deleting an area in which data is written in the cache 12 may be described as deleting the cache.

  The IOC 15 selects either the memory 3 or the cache 12 and writes the received data. Specifically, the IOC 15 writes the received data in the write area of the cache 12. On the other hand, if the received data cannot be written to the cache 12, the IOC 15 writes the received data that could not be written to the memory 3.

  The CPU 11 may read a program (a cache control program) stored in a storage unit (not shown) of the cache control device and operate as the area setting unit 21 and the area deletion unit 22 according to the program.

  Next, the operation in the processor 1 will be described. FIG. 3 is a flowchart illustrating an operation example of the cache control device according to the present embodiment. First, at the time of initialization, the area setting unit 21 sets an area in which an integer number (n) of packets are written from the head of the reception queue (RQ) as a target for cache injection. Thereafter, each time a packet is received, the processing of steps S301 to S303 illustrated in FIG. 3 is performed.

  When the cache control device receives the packet, general packet processing is performed (step S301). For example, the CPU 11 may discard the packet when the destination MAC address of the Ether header is different from its own. Further, the CPU 11 may perform a process of starting a higher layer handler according to the protocol information of the Ether header. However, the packet processing performed here is not limited to the above content, and other processing may be performed.

  After completion of the packet processing, the area deleting unit 22 deletes the cache of the target data that has been processed (step S302). Thereafter, the area setting unit 21 sets an area of the cache 12 in which a packet received after n packets to be processed (that is, n-th packet) is written as a target for cache injection (step S303).

  Next, the operation of the entire cache control device will be described. FIG. 4 is a flowchart showing an example of the operation of the cache control device and an example of the RQ state in the present embodiment. In the example of the RQ state illustrated in FIG. 4B, the case where n = 3 is illustrated.

  When the NIC 2 receives the packet (step S701 in FIG. 4A), the IOC 15 transfers the received data to the cache 12 by cache injection (step S702). As a result, as illustrated in step B3 in FIG. 4B, the received data is written in the cache 12 as a cache of the reception buffer / reception queue (RQ) on the memory 3 (step S703).

  Thereafter, when the NIC 2 notifies the CPU 11 of an H / W interrupt (step S704), the CPU 11 starts reception processing (step S705). At this time, since the target data is written into the cache 12 by the cache injection, when the CPU 11 refers to the received data in the reception process (step S706), as illustrated in step B4 in FIG. Data can be referred to immediately without causing a mistake (step S707).

  Thereafter, as illustrated in step B5 in FIG. 4B, the region deletion unit 22 operates the cache 12 at the end of the reception process to delete the cache of the processing target data (step S711). Then, the area setting unit 21 newly sets an area of the cache 12 where the n-th packet is written as a target for cache injection. As a result, the contents of the cache 12 are updated (step S710). The processes in steps S701 to S711 described above are performed, and the reception process ends (step S712).

  As described above, according to the present embodiment, the area setting unit 21 sets a writable area in the cache 12, and the deletion unit 22 performs processing for each part or all of the received data written in the cache 12. Delete the area where the received data that is the target of is written. Then, for each process on the received data, the area setting unit 21 newly adds an area corresponding to the deleted area to the position where the received data received after receiving the predetermined amount of received data is written. Set.

  With such a configuration, when the received data is written in the cache memory for processing, it is possible to suppress a decrease in processing performance even in a situation where a large amount of data is received. That is, it is possible to maximize the effects of cache injection by reducing memory access and suppressing cache usage.

  For example, when compared with the general reception process shown in FIG. 13A, the write process from the NIC 2 to the memory 3 shown in step S603, the read process from the CPU 11 to the memory 3 shown in step S608, and these processes. Accordingly, when the data stored in the cache 12 is evicted, memory access associated with the process of writing the data to the memory 3 is reduced. By reducing these memory accesses, the processing delay associated with the memory access is eliminated, so that the processing performance can be improved.

  Further, according to the present embodiment, the cache 12 to be used is limited to n packets. Therefore, the cache usage can be controlled by setting n to an appropriate value. Furthermore, it is possible to avoid a large amount of use of the cache, and it is possible to avoid that received data to be processed next is evicted from the cache to the memory. In other words, it is possible to suppress a decrease in processing performance due to reading the evicted data from the memory again.

Embodiment 2. FIG.
Next, a second embodiment will be described. FIG. 5 is a block diagram illustrating an example of the cache control device according to the second embodiment of the present invention. In addition, about the structure similar to 1st Embodiment, the code | symbol same as FIG. 1 is attached | subjected and description is abbreviate | omitted. The cache control apparatus according to the present embodiment also includes a processor 1, a NIC 2, and a memory 3. The NIC 2 and the memory 3 are the same as those in the first embodiment.

  The processor 1 includes two CPUs 11, a cache 12, an MC 13, and an IOC 15. The two CPUs 11 are each connected to the cache 12. That is, the cache control device according to the present embodiment is a multi-core processor configured such that a plurality of CPUs 11 share a cache 12 as illustrated in FIG. The contents of the CPU 11, the cache 12, the MC 13, and the IOC 15 are the same as those in the first embodiment.

  As described above, even when the cache control apparatus has the configuration illustrated in FIG. 5, the processing performance can be improved by reducing the memory access and suppressing the cache usage, as in the first embodiment. .

  Furthermore, according to the present embodiment, it is possible to suppress the use of a large amount of shared cache. Therefore, since data handled by processing by other cores is less expelled from the cache to the memory, it is possible to suppress degradation in performance of other processing. That is, according to this embodiment, scale-out by parallel processing becomes possible.

Embodiment 3. FIG.
Next, a third embodiment will be described. The configuration of the cache control device in this embodiment is the same as that in the first embodiment. That is, the cache control device according to the present embodiment also includes the processor 1, the NIC 2, and the memory 3. The processor 1 includes a CPU 11, a cache 12, an MC 13, and an IOC 15. However, as illustrated in FIG. 5, the cache control device may include a plurality of CPUs 11.

  In the third embodiment, a process when the cache control apparatus newly receives n or more packets while the CPU 11 is processing a received packet will be described.

  FIG. 6 is a block diagram illustrating an example of the CPU 11 in the present embodiment. The CPU 11 in this embodiment includes an area setting unit 21, an area deletion unit 22, a received data determination unit 23, and a data reading unit 24. The area setting unit 21 and the area deleting unit 22 are the same as those in the first embodiment. Further, the CPU 11 reads a program (cache control program) stored in a storage unit (not shown) of the cache control device, and according to the program, an area setting means 21, an area deletion means 22, a received data determination means 23, and The data reading unit 24 may be operated.

  The reception data determination unit 23 determines whether or not data exceeding an amount that can be written in a predetermined area (that is, a write area) in which a predetermined amount of reception data can be written is received. Specifically, the reception data determination means 23 confirms whether or not n-th reception data has been received. For example, the reception data determination unit 23 receives data that exceeds the amount that can be set in the write area by determining whether or not the target of cache injection set in the cache 12 is a predetermined amount. It may be determined whether or not. When data exceeding the settable amount is received, the received data determination unit 23 instructs the IOC 15 to write data exceeding the settable amount to the memory 3.

  FIG. 7 is an explanatory diagram showing an example of a data structure set in the reception buffer queue (RQ). In the example illustrated in FIG. 7, the reception buffer queue includes a reception data area that is an area for storing received data and a management data area that is an area for managing the received data. In this way, a management data area and a reception data area are secured for each packet in the reception buffer queue. FIG. 7 illustrates the case where the reception buffer queue is secured as a continuous area, but the data structure when the reception buffer queue is managed in a list structure is the same. Further, only the reception data area may be the target of cache injection, and both the reception data area and the management data area may be the target of cache injection.

  The received data is written in the reception data area from the beginning of the area. In addition, the management data area includes a time stamp at the time of reception, a reception data size, a reception completion flag indicating that reception has been completed, and the like. The reception data determination unit 23 instructs to write information to be set in the management data area together with the received data when giving an instruction to write data to the memory 3.

  The data reading unit 24 selects either the memory 3 or the cache 12 and reads the written data. For example, when the memory 3 has the data structure illustrated in FIG. 7, if the reception data flag indicates reception completion for the received data, this means that the reception data is written in the memory. . In this case, the data reading unit 24 performs prefetching. On the other hand, when the received data is not stored in the memory 3, the area setting unit 21 newly sets an area for storing the received data in the cache 12 as a target of cache injection.

  As described above, when the received data determination unit 23 determines that data exceeding the amount that can be set in the writing area is received (that is, when it is determined that n-th data is received), the data reading unit 24 Received data is prefetched from the memory 3.

  Next, the operation in the processor 1 will be described. FIG. 8 is a flowchart illustrating an operation example of the cache control device according to the present embodiment. Note that the process of setting a write area as a target for cache injection at the time of initialization is the same as in the first embodiment. Thereafter, every time a packet is received, the processing of step S401 to step S405 illustrated in FIG. 8 is performed.

  When the cache control device receives the packet, packet processing is performed on the received packet (step S401). Note that the processing in step S401 is the same as the processing in step S301 in the first embodiment. After completing the packet processing, the area deleting unit 22 deletes the cache of the target data that has been processed (step S402).

  After deleting the cache, the reception data determination unit 23 checks whether or not the n-th packet has already been received (step S403). For example, the reception data determination unit 23 checks whether or not the n-th packet has already been received based on the reception completion flag included in the management data area illustrated in FIG.

  If the n-th packet has already been received (YES in step S403), since the n-th packet data has been written in the memory, the data reading unit 24 performs prefetching (step S404). On the other hand, when the n-th packet has not been received yet (NO in step S403), the area setting unit 21 sets an area in which the packet data is written as a cache injection target (step S405). In this case, the data reading unit 24 reads the target data from the cache 12.

  As described above, according to the present embodiment, the reception data determination unit 23 determines whether or not data exceeding the amount that can be written to the write area has been received. When data exceeding the amount that can be written to the write area is received, the IOC 15 writes the received data in the memory 3. Then, the data reading unit 24 prefetches the received data from the memory 3. Therefore, in addition to the effects of the first embodiment, even when the cache control device receives a packet that temporarily exceeds the reception processing performance, the packet is not lost and the delay due to memory access is suppressed. Can process the received data.

  For example, when setting a cache initialized to 0 by the dcbz instruction, the data in the memory is not referred to. Therefore, in the method of creating a cache by the dcbz instruction after the nth and subsequent packet data are written to the memory by DMA, the CPU reads the data on the cache initialized with 0. That is, data different from the data received by the CPU is referred to.

  However, in the present embodiment, the cache 12 is controlled based on the processing illustrated in FIG. 8 and packet data written on the memory 3 is also processed. Can be avoided.

Embodiment 4 FIG.
Next, a fourth embodiment will be described. The configuration of the cache control device in this embodiment is the same as that in the first embodiment. However, as illustrated in FIG. 5, the cache control device may include a plurality of CPUs 11.

  In the first to third embodiments, the case has been described in which the entirety of each reception data area is the target of cache injection. This embodiment is different from the first to third embodiments in that only the top portion of the received data in the received data is subjected to cache injection in order to further suppress the cache usage. About other than that, it is the same as that of 1st Embodiment-3rd Embodiment.

  FIG. 9 is an explanatory diagram showing another example of the data structure set in the reception buffer queue (RQ). The RQ illustrated in FIG. 9 includes a reception data area and a management data area, similarly to the RQ illustrated in FIG. Further, the shaded portion of the RQ illustrated in FIG. 9 corresponds to a region targeted for cache injection in the present embodiment.

  The area setting unit 21 sets at least a part of each received data in the cache 12 as a target of cache injection. Hereinafter, an area corresponding to this part is referred to as a reduced area.

  Specifically, the area setting means 21 sets the area of the first k cache line among the received data areas as a target for cache injection. Here, k is a predetermined integer value. By doing so, it is possible to reduce the amount of use of the cache area in the received data area where the received data is not written.

  For example, when the received data is less than or equal to the size of k cache lines, the cache usage is reduced by (received data area size)-(k cache line size) for each packet as compared to writing all the received data. it can. If the received data is larger than the size of k cache lines, the CPU 11 may refer to the memory 3 and refer to the remaining portion of the received data.

  Although FIG. 9 illustrates the case where the information in the received data area is the target of cache injection, the information in the management data area may be included in the target of cache injection.

  As described above, according to the present embodiment, the area setting unit 21 sets at least a part of the received data in the cache 12 as a cache injection target area. Therefore, in addition to the effects in the first to third embodiments, the cache usage can be reduced.

  That is, for example, when the process of receiving a packet is performed using the reception buffer queue illustrated in FIG. 9, when all the reception data areas are set as cache injection targets in the cache 12, the reception data is included in the reception data areas. The cache of the area that is not written is wasted. However, in this embodiment, since the area portion where received data is not written is reduced, the cache usage can be further suppressed.

Embodiment 5. FIG.
Next, a fifth embodiment will be described. In the fourth embodiment, a case has been described in which a part of the received data area is set in the cache 12 as a target for cache injection. In addition to the processing in the fourth embodiment, the cache control device in the present embodiment performs processing for prefetching the remaining portion of the received data that has not been cache-injected according to the size of the received data.

  The configuration of the cache control device in this embodiment is the same as that in the first embodiment. That is, the cache control device according to the present embodiment also includes the processor 1, the NIC 2, and the memory 3. The processor 1 includes a CPU 11, a cache 12, an MC 13, and an IOC 15. However, as illustrated in FIG. 5, the cache control device may include a plurality of CPUs 11.

  FIG. 10 is a block diagram illustrating an example of the CPU 11 in the present embodiment. The CPU 11 in this embodiment includes an area setting unit 21, an area deletion unit 22, a received data determination unit 23, a data reading unit 24, and a size comparison unit 25. The region setting unit 21, the region deletion unit 22, and the reception data determination unit 23 are the same as those in the fourth embodiment. In addition, the CPU 11 reads a program (cache control program) stored in a storage unit (not shown) of the cache control device, and in accordance with the program, an area setting unit 21, an area deletion unit 22, a received data determination unit 23, The data reading unit 24 and the size comparison unit 25 may operate.

  The size comparison means 25 compares the size of the area corresponding to a part from the head of each received data (that is, the reduced area) and the size of the received data. The size comparison unit 25 may determine the size of the received data based on, for example, the received data size included in the management data area illustrated in FIG.

  If the size of the received data is less than or equal to the size of the reduced area, the received data is cache injected. On the other hand, when the received data size is larger than the size of the reduced area, there is an area that has not been cache-injected. In this case, the data reading unit 24 prefetches the data in that area from the memory 3. By doing so, it is possible to reduce the usage amount of the cache and reduce the delay due to memory access.

  Next, the operation will be described. FIG. 11 is a flowchart illustrating an operation example of the cache control device according to the present embodiment. When the cache control device receives the packet, the size comparison unit 25 compares the size of the received data with the size of the k cache line registered in the cache injection target (step S501). The size comparison unit 25 may determine the size of the received data with reference to the management data area in the reception buffer queue, for example.

  If the received data size is equal to or smaller than the size of the reduced area (NO in step S501), the received data is cache injected. On the other hand, if the received data size is larger than the size of the reduced area (YES in step S501), the data reading unit 24 prefetches the data in that area from the memory 3 (step S502).

  Thereafter, packet processing of the received packet is performed (step S503). Note that the processing in step S501 is the same as the processing in step S301 in the first embodiment. After the packet processing is completed, the area deleting unit 22 deletes the cache of the target data that has been processed (step S504). Then, the area setting unit 21 sets an area in which n-th packet is written as a target for cache injection (step S405).

  As described above, according to the present embodiment, the size comparison unit 25 compares the size of the reduced area with the size of the received data. If the size of the received data is equal to or smaller than the size of the reduced area, the IOC 15 writes the portion of the received data that exceeds the size of the reduced area to the memory 3, and the data reading means 24 is a portion that exceeds the size of the reduced area. Is prefetched from the memory 3. Therefore, in addition to the effects of the fourth embodiment, the delay due to memory access can be further reduced.

  Hereinafter, the present invention will be described with reference to specific examples, but the scope of the present invention is not limited to the contents described below. In the present embodiment, it is assumed that cache injection is realized using the mounting method described in Patent Document 1. That is, as described in Patent Document 1, the processor according to the present embodiment assumes cached data as a target for cache injection.

  In addition, the processor in this embodiment can operate the cache by the dcbz instruction and the Data Cache Block Invalidate (dcbi) instruction described in Non-Patent Document 2. Note that the dcbi instruction described in Non-Patent Document 2 is an instruction for deleting a cache without writing it to a memory.

  Next, the data configuration of the reception buffer used in this embodiment will be described. As shown in FIG. 9, the reception buffer used in the present embodiment assumes a queue in which data is sequentially stored in a continuous area at equal intervals. The reception buffer has a management data area and a reception data area for each packet. Further, the management data area includes a reception time stamp, a reception data size, a reception completion flag, and the like. The sizes of the management data area and the reception data area are each an integral multiple of the cache line size.

  In addition, the area setting unit 21 sets an area in which n packets from the head of the queue are written to the cache 12 as a target of cache injection at the time of initialization. Here, an optimal value is set in advance for n from the cache size and the performance of the reception process. For example, as shown in the second embodiment, when two CPUs perform packet processing in parallel, by selecting n such that “cache size / 2> size of received data area × n”, the received data It is possible to prevent the cache from being evicted into the memory. Further, as shown in the third embodiment, by selecting n that satisfies “the time required for completing prefetch <the processing time for n packets”, it is possible to eliminate the delay due to memory access. Note that the value of the integer n is not changed during program execution.

  Next, the operation of the cache control apparatus according to this embodiment will be described. First, the entire received data area is set as a DMA target. Thereafter, in order to set the received data area for the n packets received first as the target of cache injection, the processor (for example, the area setting unit 21) creates a cache by the dcbz instruction.

  Thereafter, after a general reception process performed for each packet, the processor (for example, the area deletion unit 22 and the area setting unit 21) operates the cache as illustrated in step S711. Specifically, the processor (for example, the region deletion unit 22) deletes the cache of the reception data region corresponding to the packet that was the processing target with the dcbi instruction. Then, the processor (for example, the area setting unit 21) creates a cache by the dcbz instruction in order to set the received data area in which the n-th packet is written to be the target of cache injection. As a result, the contents of the cache 12 are updated as exemplified in step S710.

  In the area where n-th received data (packet) is written, (management data area size + received data area size) × n is added to the address indicating the received data area of the packet to be processed. It can be calculated by The processor (for example, the area deleting unit 22 and the area setting unit 21) performs each cache operation on all the cache lines in the received data area.

  By performing such processing, for example, only n packet data are always cached as in the reception buffer illustrated in FIG.

  Next, the minimum configuration of the present invention will be described. FIG. 12 is a block diagram showing an example of the minimum configuration of the cache control device according to the present invention. A cache control device according to the present invention uses a write area (for example, a cache injection target area), which is an area into which a predetermined amount of received data (for example, n packets) can be written, as a cache memory (for example, a cache memory). 12) and for each process (for example, packet processing) for part or all of the received data written in the write area, the area in which the received data to be processed is written An area deleting unit 82 (for example, area deleting unit 22) for deleting (for example, deleting a cache) is provided.

  The area setting unit 81 writes the received data (for example, n ahead packets) received after receiving a predetermined amount of received data (for example, n packets) for each process on the received data. In addition, an area corresponding to the deleted area is newly set as an area in which received data can be written.

  With the configuration as described above, when the received data is written in the cache memory for processing, it is possible to suppress a decrease in processing performance even when a large amount of data is received.

  In addition, the cache control device selects any one of received data writing means (for example, IOC15), main memory (for example, memory 3), and cache memory for writing received data to the write area, and writes the received data to be written. Data reading means for reading (for example, data reading means 24) and reception data determining means (for example, receiving data determining means 23) for determining whether or not data exceeding the amount that can be written to the writing area has been received. It may be.

  Then, the reception data writing means may write the reception data exceeding the amount that can be written to the writing area into the main memory, and the data reading means may prefetch the reception data from the main memory.

  The area setting unit 81 may set a reduced area, which is at least a part of the received data (for example, the area of the first k cache line), in the cache memory as a writable area.

  In addition, the cache control apparatus may include size comparison means (for example, size comparison means 25) that compares the size of the reduced area with the size of the received data. When the received data size is equal to or smaller than the size of the reduced area, the received data writing means writes the portion of the received data that exceeds the size of the reduced area to the main memory, and the data reading means has a size of the received data. If the size is equal to or smaller than the size of the reduced area, a portion of received data that exceeds the size of the reduced area may be prefetched from the main memory.

  Although the present invention has been described with reference to the embodiments and examples, the present invention is not limited to the above embodiments and examples. Various changes and adjustments are possible within the scope of the embodiments and examples of the present invention.

  The present invention is preferably applied to a cache control device that controls cache memory using cache injection. Further, the present invention can be applied to other apparatuses that perform processing using a buffer queue. For example, the present invention can be applied to processing using an accelerator in an architecture that supports memory writing and cache injection from the accelerator.

  Specifically, when a plurality of jobs are input to the accelerator and processing is performed while sequentially receiving the results, output data for each job is generated. At this time, the use of the cache can be controlled to a certain amount by applying the method according to the present invention to control the area where the output data is written, so that the effect of cache injection such as memory access reduction can be maximized.

1 processor 2 NIC
3 Memory 11 CPU
12 cache memory 13 memory controller 14 internal bus 15 I / O controller 21 area setting means 22 area deleting means 23 received data determining means 24 data reading means 25 size comparing means

Claims (10)

Set a write area, which is an area in which a predetermined amount of received data can be written, in the cache memory,
For each process on part or all of the received data written in the write area, delete the area where the received data that is the target of the process is written,
For each process on the received data, an area corresponding to the deleted area is set as an area where the received data can be written at a position where the received data received after receiving the predetermined amount of received data is written. A cache control method characterized by newly setting. Write the received data to the writing area,
Select either main memory or cache memory, read the received data written,
Determine if you have received more data than can be written to the write area,
When writing received data to the write area, write the received data exceeding the amount that can be written to the write area to the main memory,
The cache control method according to claim 1, wherein the received data is prefetched from a main memory. The cache control method according to claim 1 or 2, wherein when the write area is set, a reduced area that is at least a part of each received data is set as a writable area in the cache memory. Compare the size of the reduced area with the size of the received data,
If the size of the received data is equal to or smaller than the size of the reduced area, the portion of the received data that exceeds the size of the reduced area is written to the main memory, and the portion of the received data that exceeds the size of the reduced area is prefetched from the main memory. 3. The cache control method according to 3. The cache control method according to any one of claims 1 to 4, wherein a write area is set in a cache memory as a target for cache injection. An area setting means for setting a write area, which is an area in which a predetermined amount of received data can be written, in the cache memory;
An area deletion unit that deletes an area in which received data that is a target of the process is written for each process on a part or all of the received data written in the writing area;
In each of the processes for the received data, the area setting unit sets the received data as a writable area at a position where the received data received after receiving the predetermined amount of received data is written. A cache control apparatus characterized by newly setting a corresponding amount of area. Received data writing means for writing received data to a writing area;
A data reading unit that selects either the main memory or the cache memory and reads the written received data;
Receiving data determination means for determining whether or not data exceeding the amount that can be written to the write area has been received,
The received data writing means writes received data exceeding the amount that can be written to the writing area to the main memory,
The cache control device according to claim 6, wherein the data reading unit prefetches the received data from a main memory. The cache control device according to claim 6 or 7, wherein the area setting means sets a reduced area, which is at least a part of each received data, as a writable area in the cache memory. Received data writing means for writing received data to a writing area;
A data reading unit that selects either the main memory or the cache memory and reads the written received data;
Size comparison means for comparing the size of the reduced area and the size of the received data,
When the size of the received data is equal to or smaller than the size of the reduced area, the received data writing means writes the portion of the received data that exceeds the size of the reduced area to the main memory,
The cache control device according to claim 8, wherein the data reading means prefetches the received data in a portion exceeding the size of the reduced area from the main memory when the size of the received data is equal to or smaller than the size of the reduced area. On the computer,
An area setting process for setting a write area, which is an area in which a predetermined amount of received data can be written, in the cache memory; and
For each process on part or all of the received data written in the writing area, execute a deletion process to delete the area in which the received data to be processed is written,
In the area setting process, each time the received data is processed, the received data received after receiving the predetermined amount of received data is written into the area where the received data is written, and the deleted data is written into the deleted area. A cache control program to set a new equivalent area.

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