JP2012164194A - Storage control device and cache data saving method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power required for saving cache data into a nonvolatile memory.SOLUTION: Based on a saving instruction of cache data, a CPU11 reads out cache data stored in a cache memory 13 to compress it and creates the compressed cache data. Also, a nonvolatile memory controller 14 writes the compressed cache data created by the CPU11 into a nonvolatile memory 15.

Description

  The present invention relates to a storage control device and a cache data saving method for the storage control device.

  A storage control device, for example, a controller in a disk array device, needs to save cache data in order to hold cache data when power supply is interrupted. As a method for saving cache data, a method for saving cache data in a nonvolatile memory is known.

  There is also known a disk array device that saves data stored in a cache memory and a shared memory, for example, dirty data not reflected in a storage device, to a nonvolatile memory (see, for example, Patent Document 1).

JP 2008-192028 A

  When data is saved from the cache memory when the power supply is cut off, it is necessary to write to all the data non-volatile memories stored in the cache memory. In order to write data to the non-volatile memory, power is supplied from the secondary battery in the storage control device to each processing unit such as a cache memory. Therefore, until all the data has been written, It is necessary for the secondary battery to be able to maintain power supply to each processing unit described above.

  In recent years, since the capacity of the cache memory has increased, the amount of data stored in the cache memory has also increased. Therefore, the amount of cache data saved in the non-volatile memory is also increasing, and the amount of power required to operate each processing unit in the storage control device is also increasing.

  Further, for example, when saving cache data from the cache memory to the nonvolatile memory, first, the first cache data is read from the cache memory and written to the nonvolatile memory. In addition, after the first cache data is read out to the nonvolatile memory, the next cache data is immediately read out from the cache memory. Generally, the speed at which data is written into the nonvolatile memory is read from the cache memory. Since it is sufficiently slower than the speed, the cache data read out next time is not transferred until the writing of the first cache data is completed, resulting in a transfer waiting time.

  Since the cache data transfer waiting time occurs in this way, the save time for saving the cache data to the nonvolatile memory is further increased, and the power required for operating each processing unit in the storage control device. The amount is even larger.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a storage control device capable of reducing power required for saving cache data in a nonvolatile memory, and cache data saving of the storage control device. It is to provide a method.

  The present invention provides a storage control device that saves cache data to be saved in a cache memory to a nonvolatile memory when power supply is interrupted, and stores cache data to be saved in the cache memory based on a cache data save instruction. A first control unit that reads and compresses and generates the compressed cache data; and a second control unit that writes the compressed cache data generated by the first control unit into a nonvolatile memory. .

  Another aspect of the present invention is a cache data saving method of a storage control device for saving cache data to be saved in a cache memory to a nonvolatile memory when power supply is interrupted. The method includes a step of reading cache data stored in a memory, a step of compressing the read cache data, generating compressed cache data, and a step of writing the generated compressed cache data to a nonvolatile memory.

  According to the present invention, it is possible to provide a storage control device and a cache data saving method for the storage control device that can reduce the power required to save the cache data in the nonvolatile memory.

It is a figure which shows the structure of the storage control apparatus which concerns on embodiment of this invention. It is a flowchart which shows the cache data saving process which concerns on the embodiment. It is a figure for demonstrating the operation | movement and time of the saving process which concern on the embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration of a disk array controller 1 to which a storage control device of the present invention is applied. The disk array controller 1 is provided in, for example, a disk array device (not shown), and controls data writing to the disk array device or a disk array based on a command from a host device (not shown). Data read control from the device is performed.

  As shown in FIG. 1, the disk array controller 1 includes a CPU (Central Processing Unit) 11 that is a first control unit, a cache memory 13, a nonvolatile memory controller 14 that is a second control unit, a nonvolatile memory 15, and a program. A storage memory 16, a secondary battery 17, and various communication units 20 are included.

  The CPU 11 is communicably connected to the cache memory 13, the nonvolatile memory controller 14, the nonvolatile memory 15, the program storage memory 16, and the secondary battery 17. The CPU 11 has a high-speed interface, and communicates with the disk array device and the host device using various control communication units 20.

  Further, the CPU 11 has a cache data compression unit 12, and the CPU 11 reads the cache data to be stored in the cache memory 13 and compresses the cache data by the cache data compression unit 12 based on the cache data save instruction. Generate data.

  The cache memory 13 is a volatile memory, and is composed of, for example, a high-speed SDRAM (synchronous DRAM). The cache memory 13 stores, for example, cache data related to processing to the disk array device.

  The nonvolatile memory controller 14 writes the compressed cache data transferred from the CPU 11 to the nonvolatile memory 15.

  The nonvolatile memory 15 holds the compressed cache data written from the nonvolatile memory controller 14.

  The program storage memory 16 is, for example, a ROM, and stores a cache data save control program for saving cache data stored in the cache memory 13. Details of the processing realized by executing the cache data saving control program will be described later with reference to FIG.

  The secondary battery 17 is a chargeable / dischargeable battery. The secondary battery 17 includes the CPU 11, the cache memory 13, and the nonvolatile memory until the cache data cached in the cache memory 13 is saved to the nonvolatile memory 15 when power supply to the disk array controller 1 is interrupted. Power for operating the controller 14, the nonvolatile memory 15 and the program storage memory 16 is supplied. An alternate long and short dash line 10 in FIG. 1 indicates a power supply area of the secondary battery 17.

  Next, processing realized by the CPU 11 executing the above-described cache data saving control program when the power supply to the disk array controller 1 is interrupted will be described with reference to FIG.

  When the CPU 11 receives the cache data save instruction (S101), the CPU starts discharging the secondary battery 17 (S102). Thereby, even if the power supply to the disk array controller 1 is cut off, the CPU 11, the cache memory 13, the nonvolatile memory controller 14, the nonvolatile memory 15 and the program storage memory 16 operate.

  The CPU 11 reads the cache data save control program from the program storage memory 16 (S103), and executes the cache data save control program (S104).

  Next, the CPU 11 determines whether all the compressed cache data has been written in the nonvolatile memory 15 (S105).

  When determining that all the compressed cache data has not been written in the nonvolatile memory (S105: NO), the CPU 11 reads one cache data cached in the cache memory 13 (S106).

  Next, the CPU 11 compresses the cache data read from the cache memory 13 by the cache data compression unit 12 (S107), and transfers the compressed compressed cache data to the nonvolatile memory controller 14 (S108).

  The nonvolatile memory controller 14 writes the compressed cache data transferred from the CPU 11 to the nonvolatile memory 15 (S109). Next, the CPU 11 returns to the process of step S105 described above, and determines whether or not all the compressed cache data has been written in the nonvolatile memory 15.

  When it is determined that all the compressed cache data has not been written (S105: NO), the processes of steps S106 to S109 described above are repeated. Therefore, the processing of steps S106 to S109 is performed on all cache data cached in the cache memory 13.

  On the other hand, if it is determined that all the compressed cache data has been written in the nonvolatile memory 15 (S105: YES), the CPU 11 ends the execution of the cache data saving control program (S110) and ends the discharge of the secondary battery 17 (S111).

  Next, taking as an example a case where the cache data A to C is saved from the cache memory 13 to the nonvolatile memory 15, the operation and time for the disk array controller 1 to save the cache data will be described with reference to FIG.

  The CPU 11 reads the cache data A from the cache memory 13, compresses the cache data A by the cache data compression unit 12, and transfers the compressed compressed cache data A to the nonvolatile memory controller 14.

  When the compressed cache data A is transferred from the CPU 11, the nonvolatile memory controller 14 writes the compressed cache data A into the nonvolatile memory 15.

  After the transfer of the compressed cache data A to the nonvolatile memory controller 14 is completed, the CPU 11 immediately reads the cache data B from the cache memory 13 and performs a process of compressing the cache data B by the cache data compression unit 12.

  Here, since the speed at which data is written to the nonvolatile memory 15 is sufficiently slower than the speed at which the cache data is read from the cache memory 13, the compression of the cache data B is completed before the writing of the compressed cache data A to the nonvolatile memory 15 is completed. Is completed.

  The CPU 11 then transfers the compressed cache data B to the nonvolatile memory controller 14 immediately after the compressed cache data A is written to the nonvolatile memory 15.

  When the compressed cache data B is transferred from the CPU 11, the nonvolatile memory controller 14 writes the compressed cache data B into the nonvolatile memory 15.

  After the transfer of the compressed cache data B to the nonvolatile memory controller 14 is completed, the CPU 11 immediately reads the cache data C from the cache memory 13 and performs a process of compressing the cache data C by the cache data compression unit 12.

  As described above, the cache data A to C is read from the cache memory 13 and the compressed cache data A to C is written to the nonvolatile memory 15.

  According to the disk array controller 1 of this embodiment, the cache data read out from the cache memory 13 by the cache data compression unit 12 in the CPU 11 is compressed, and the compressed cache data is written into the nonvolatile memory 15. It is possible to shorten the time for writing the cache data.

  Therefore, the power required to operate the disk array controller 1 in order to save the cache data from the cache memory 13 to the nonvolatile memory 15 can be reduced. Therefore, the storage capacity of the secondary battery 17 can be reduced, and the size of the secondary battery 17 can be reduced.

  In addition, since the speed at which data is written into the nonvolatile memory 15 is sufficiently slower than the speed at which the cache data is read from the cache memory 13, a transfer waiting time for compressed cache data occurs as shown in FIG. Since the cache data compression unit 12 compresses the cache data using this transfer waiting time, the write time to the non-volatile memory 15 is reduced without being affected by the time for compressing the cache data. It can be shortened.

  Further, in the above-described embodiment, the nonvolatile memory controller 14 is described as a configuration different from the CPU 11, but the present invention is not limited to this. For example, the nonvolatile memory controller 14 described above is provided in the CPU 11. You may do it.

  More specifically, for example, when control such as reading of cache data from the cache memory 13 is handled by an I / O block (for example, DMA) in the CPU 11, the cache data is transferred to the I / O block. And the CPU 11 enters a transfer waiting state. The CPU 11 is configured to compress the cache data during this transfer waiting state.

  With this configuration, it is possible to omit the power for operating the nonvolatile memory controller 14 and to further reduce the power consumption of the secondary battery 17.

  In addition, this invention is not limited to the above-mentioned embodiment, A various deformation | transformation is possible in the case of the implementation.

  A part or all of the above embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A storage control device for saving cache data to be saved in a cache memory to a nonvolatile memory when power supply is cut off,
A first control unit that reads and compresses cache data to be stored in the cache memory based on a cache data save instruction, and generates the compressed cache data;
A second control unit for writing the compressed cache data generated by the first control unit into a nonvolatile memory;
A storage control apparatus comprising:

(Appendix 2)
The storage control apparatus according to appendix 1, wherein the first control unit compresses the cache data before the second control unit writes the compressed cache data.

(Appendix 3)
The storage control apparatus according to appendix 1 or 2, wherein the first control unit is configured to include the second control unit.

(Appendix 4)
When the power supply is cut off, the cache data saving method of the storage control device for saving the cache data to be saved in the cache memory to the nonvolatile memory,
Reading cache data to be stored in the cache memory based on a cache data save instruction;
Compressing the read cache data to generate compressed cache data; and
Writing the generated compressed cache data into a non-volatile memory;
A cache data evacuation method for a storage control device, comprising:

  The present invention can be widely applied to storage devices and the like that save cache data stored in a cache memory when power supply is interrupted.

DESCRIPTION OF SYMBOLS 1 ... Disk array controller 10 ... Secondary battery power supply range 11 ... CPU
12 ... Cache data compression unit 13 ... Cache 14 ... Non-volatile memory controller 15 ... Non-volatile memory 16 ... Program storage memory 17 ... Secondary battery

Claims (4)

A storage control device for saving cache data to be saved in a cache memory to a nonvolatile memory when power supply is cut off,
A first control unit that reads and compresses cache data to be stored in the cache memory based on a cache data save instruction, and generates the compressed cache data;
A second control unit for writing the compressed cache data generated by the first control unit into a nonvolatile memory;
A storage control apparatus comprising:   The storage control device according to claim 1, wherein the first control unit compresses the cache data before the second control unit writes the compressed cache data.   The storage control apparatus according to claim 1, wherein the first control unit is configured to include the second control unit. When the power supply is cut off, the cache data saving method of the storage control device for saving the cache data to be saved in the cache memory to the nonvolatile memory,
Reading cache data to be stored in the cache memory based on a cache data save instruction;
Compressing the read cache data to generate compressed cache data; and
Writing the generated compressed cache data into a non-volatile memory;
A cache data evacuation method for a storage control device, comprising:

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