JP2012164072A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve shortening of error correction processing time, reduction of power consumption and reduction of data for error correction.SOLUTION: A memory controller comprises: a memory interface; and a control part for controlling the memory interface in accordance with a command from a host. The memory interface comprises: an error correction bit number setting part 161 for setting a first error correction bit number with i-bit to data in the case of binary writing into a memory, and for setting a second error correction bit number with j-bit (i<j) to the data in the case of multi-value writing; and an error correction code generation and addition part 162 for generating and adding a first error correction code with k-byte to the data when the first error correction bit number is set by the error correction bit number setting part, and for generating and adding a second error correction code with l-byte (k<l) to the data when the second error correction bit number is set.

Description

  Embodiments described herein relate generally to a memory controller.

  In recent years, NAND flash memories have increased storage capacity by applying multilevel technology to memory cells. In order to improve the reliability of such a NAND flash memory, error checking and correction (ECC) is performed in a memory controller that can be connected to a host and the NAND flash memory and manages the NAND flash memory. ECC circuit technology to perform has been proposed.

  Usually, a memory controller that performs ECC fixes the number of error correction bits. For this reason, the number of error correction bits becomes excessive depending on the reliability of the flash memory. As a result, the error correction processing time and power consumption are more than necessary. Also, extra data for error correction is required.

JP 2009-259113 A

  A memory controller that shortens error correction processing time, reduces power consumption, and reduces error correction data is provided.

  The memory controller according to the present embodiment is a memory controller that controls a memory having a plurality of memory cells that can be written, read, and erased in binary or multi-value according to a command from the host. A host interface for accessing commands and data; a memory interface for accessing commands and data to and from the memory; and a control unit for controlling the memory interface according to commands from the host via the host interface. When the memory interface writes the data from the host into the memory, if the write to the memory is binary writing, the memory interface sets the first error correction bit number of i bits to the data from the host. Set When the multi-level write is performed, the error correction bit number setting unit for setting the second error correction bit number of j bits (i <j) for the data from the host, and the error correction bit number setting When the first error correction bit number is set by the unit, a first error correction code of k bytes is generated and added to the data from the host, and when the second error correction bit number is set, an error correction code generation / addition unit that generates a second error correction code of l (k <l) bytes and adds the second error correction code to data from the host.

FIG. 3 is a block diagram showing a configuration example of a memory controller in the present embodiment. 1 is a block diagram showing a configuration example of a flash memory in the present embodiment. The figure for demonstrating the binary mode and multi-value mode of the flash memory in this embodiment. The block diagram which shows the structural example of the ECC circuit in this embodiment. FIG. 5A is a block diagram showing a comparative example of the data configuration written in the flash memory in the present embodiment, and FIG. 5B is a block diagram showing the data configuration written in the flash memory 300 in the present embodiment. Figure. The flowchart of the write-in operation | movement in this embodiment. 6 is a flowchart of an error correction bit number setting operation in the present embodiment.

  The present embodiment will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals.

<Configuration example>
Hereinafter, the configuration of the memory controller 100 according to this embodiment will be described with reference to FIGS. 1 to 5. FIG. 1 is a block diagram illustrating a configuration example of the memory controller 100 according to the present embodiment.

  As shown in FIG. 1, the memory controller 100 can be connected to a host 200 and a NAND flash memory (hereinafter simply referred to as a flash memory) 300. When the memory controller 100 is connected to the host 200, the memory controller 100 operates by being supplied with power, and performs processing according to access from the host 200. For example, the memory controller 100 manages and controls the flash memory 300 in access such as data writing, data reading, and data erasing to the flash memory 300.

  The host 200 includes hardware and software (system) for accessing the connected flash memory 300. The host 200 accesses the flash memory 300 via the memory controller 100 such as data writing, data reading, and data erasing.

  The memory controller 100 includes a host interface 110, an MPU (Micro Processing Unit) 120, a data buffer 130, and a flash memory interface 140.

  The host interface 110 is provided for accessing commands, data, and the like between the memory controller 100 and the host 200, and performs interface processing between them.

  The data buffer 130 temporarily stores a certain amount (for example, one page) of data according to a command from the MPU when writing data sent from the host 200 to the flash memory 300. The data buffer 130 temporarily stores a certain amount of data in accordance with a command from the MPU when sending data read from the flash memory 300 to the host 200.

  The MPU 120 controls the overall operation of the memory controller 100. For example, when power is supplied to the memory controller 100, the MPU 120 starts processing according to firmware (control program) stored in the MPU 120. That is, the MPU 120 creates various tables (management data) necessary for processing, or receives a write command, a read command, an erase command, etc. from the host 200 and accesses the corresponding area on the flash memory 300. . Further, the MPU 120 converts a logical address and a physical address from the host 200 when accessing the flash memory 300, and controls data transfer processing via the data buffer 130. In the following, the address of the memory controller 100 given from the host 200 is referred to as a logical address, and the actual address in the flash memory 300 is referred to as a physical address.

  The flash memory interface 140 is provided to transmit and receive commands and data between the memory controller 100 and the flash memory 300, and performs interface processing between them. Further, the flash memory interface 140 has an ECC circuit 150 that performs ECC. Details of the ECC circuit 150 will be described later.

  FIG. 2 is a block diagram showing a configuration example of the flash memory 300 in FIG.

  As shown in FIG. 2, the flash memory 300 includes a memory cell array 310 and a page buffer 320.

  The memory cell array 310 includes a plurality of memory blocks BLK0 to BLKn (n is a natural number). Each memory block BLK includes a plurality of memory cell transistors. The case where the memory cell array 310 of this example is a multi-level NAND flash memory capable of recording multi-bit data in one memory cell transistor will be described as an example. In the following description, the memory blocks BLK0 to BLKn may be simply referred to as a memory block BLK.

  Here, a mode in which multi-bit data is written into the memory cell transistor is referred to as a multi-value mode, and a mode in which 1-bit data is written into the memory cell transistor is referred to as a binary mode. At this time, the memory cell transistor in which data is written in the binary mode can be written again in the multi-value mode.

  Data is erased in units of memory blocks BLK. That is, the data in the same memory block BLK is erased collectively. Each memory block BLK includes a plurality of memory cell transistors. In the memory block BLK, a plurality of word lines WL0, WL1,... (Hereinafter referred to as word lines WL) and bit lines BL0, BL1,... (Hereinafter referred to as bit lines BL) orthogonal to the word lines WL. ) And are provided. The memory cell transistors in the same row are commonly connected to the same word line. The memory cell transistors in the same column are commonly connected to the bit line BL in units of a plurality of memory cell transistors.

  Data writing and reading are performed for each set of a plurality of memory cell transistors, and this set of memory cell transistors is called one page. At the time of reading and writing, one of the word lines WL is selected by the row address, and one of the bit lines BL is selected by the column address.

  The page buffer 320 inputs / outputs data to / from the memory cell array 310 and temporarily holds data. The data size that can be held by the page buffer 320 is the same as the page size of each memory block BLK. When writing data, the page buffer 320 executes data input / output processing for the memory cell array 310 in units of one page corresponding to its own storage capacity.

  Here, in writing data to the flash memory 300 in the present embodiment, when writing data in units of blocks, an empty block BLK is secured and writing is performed from the leading page of the block BLK. On the other hand, when writing data in units of pages, a block BLK that is all free is secured and writing is performed from the leading page of the block BLK, or a block BLK that is partially free is secured and the block BLK is written. Writing is performed from the leading page of the vacant area of the block BLK.

  In addition, the memory controller 100 stores and manages the number of erases of each block BLK of the flash memory 300, and when the data from the host 200 is written to the block BLK, the erase number data of the write block BLK is stored in the flash memory 300. Remember. Further, the memory controller 100 stores and manages the number of readings of each block BLK in which a part of the area is vacant, and when the data is written from the host 200, the number of readings of the writing block BLK is stored in the flash memory 300. To remember. At this time, the flash memory 300 also stores address information of the leading page of the vacant area of the block BLK.

  FIG. 3 is a diagram for explaining a binary (SLC: Single Level Cell) mode and a multi-level (MLC: Multi Level Cell) mode of the flash memory 300. In this example, the four-value mode will be described as an example of the multi-value mode. In FIG. 3, the horizontal axis indicates the threshold voltage Vth, and the vertical axis indicates the existence probability of the memory cell.

  First, the quaternary mode will be described. As shown in FIG. 3, the memory cell transistor can hold four data of “11”, “01”, “10”, and “00” in ascending order of the threshold voltage Vth. The threshold voltage Vth of the memory cell transistor holding “11” data is Vth <0V. The threshold voltage Vth of the memory cell transistor holding “01” data is 0V <Vth <Vth1. The threshold voltage Vth of the memory cell transistor holding “10” data is Vth1 <Vth <Vth2. The threshold voltage Vth of the memory cell transistor holding “00” data is Vth2 <Vth <Vth3.

  Next, the binary mode will be described. As shown in the figure, the memory cell transistor can hold two data of “1” and “0” in ascending order of the threshold voltage Vth. The threshold voltage Vth of the memory cell transistor holding “1” data is Vth <0V. The threshold voltage Vth of the memory cell transistor holding “0” data is Vth1 <Vth <Vth2. That is, “1” data has a threshold voltage equal to “11” data in the 4-level mode, and “0” data has a threshold voltage equal to “10” data in the 4-level mode.

  In other words, the binary mode can be said to be an operation mode using only the lower page of the 2-bit data in the quaternary mode. More specifically, a lower page address is assigned to lower bits of 2-bit data, and an upper page address is assigned to upper bits. When writing data to the memory cell transistor in the binary mode, the memory controller 100 writes data to the flash memory 300 using only the lower page address among these page addresses. When writing data to the memory cell transistor in the multi-value mode, the memory controller 100 writes data to the flash memory 300 using both the upper page address and the lower page address.

  Data is written first from the lower page. If the erase state is “11” (“−−”, − means indefinite), first, the lower page is written, so that the memory cell transistor becomes “11” (“−1”) or “10” (“ −0 ″). In the binary mode, the writing is completed. When writing in the 4-value mode, the upper page is written next. As a result, the memory cell transistor holding “11” (“−1”) holds “11” or “01”, and the memory cell transistor holding “10” (“−0”) is “10”. Or, “00” is held. The same applies to the other 8-value mode and 16-value mode. Hereinafter, of the memory area of the flash memory 300, an area in which the memory controller 100 writes data in the binary mode is referred to as an SLC area, and an area in which the memory controller 100 writes data in the multi-value mode is referred to as an MLC area.

  The memory controller 100 controls whether data is written to the memory cell transistor in the binary mode or in the quaternary mode. For example, according to the logical address of the memory controller 100 given from the host 200, the memory controller 100 determines whether to write to the physical address of the flash memory 300 corresponding to the logical address in the binary mode or the quaternary mode.

  FIG. 4 is a block diagram showing a configuration example of the ECC circuit 150 in FIG.

  As shown in FIG. 4, the ECC circuit 150 includes a write circuit 160 and a read circuit 170. The write circuit 160 operates when data is written from the host 200 to the flash memory 300 and includes an error correction bit number setting unit 161 and an error correction code generation / addition unit 162. The read circuit 170 operates when data is read from the flash memory 300 to the host 200, and includes an error correction unit 171.

  When writing data from the host 200 to the flash memory 300, the error correction bit number setting unit 161 changes and sets the error correction bit number for the data as necessary. More specifically, the error correction bit number setting unit 161 sets the error correction bit number according to the reliability of the flash memory 300 to be written and the importance of the data to be written in accordance with a command from the MPU 120. Here, the number of error correction bits is the number of error bits in data that can be corrected using an error correction code added to the data. That is, in the present embodiment, the number of error correction bits is variable and is set according to various conditions. For example, the number of error correction bits indicates whether the area of the flash memory 300 to be written is an SLC area or an MLC area, whether the number of erases of the block BLK of the flash memory 300 to be written is greater than or equal to a threshold, or the data to be written is important data It is set depending on whether or not there is.

  When writing data from the host 200 to the flash memory 300, the error correction code generation / addition unit 162 has an error correction code (error correction data) corresponding to the error correction bit number set by the error correction bit number setting unit 161. Is added to the data written to the flash memory 300. The data amount of the error correction code is changed according to the number of error correction bits. More specifically, the data amount of the error correction code decreases as the number of error correction bits decreases, and increases as the number of error correction bits increases.

  When the error correction unit 171 reads data from the flash memory 300 to the host 200, the error correction unit 171 performs data error correction based on the error correction code generated and added by the error correction code generation and addition unit 162.

  FIG. 5A is a block diagram showing a comparative example of the data configuration written in the flash memory 300 in the present embodiment, and FIG. 5B shows the data configuration written in the flash memory 300 in the present embodiment. It is a block diagram.

  As shown in FIGS. 5A and 5B, data written to the flash memory 300 includes data 400 and 500, necessary information (for example, management data) 410 and 510 other than data, and error correction data 420. , 520.

  In the comparative example, the data 400 is x bytes (for example, 512 bytes), the necessary information 410 other than data is y bytes (for example, 8 bytes), and the error correction data 420 is z bytes (for example, 22 bytes). In contrast, in the present embodiment, the data 500 is x bytes, the necessary information 510 other than the data is y + n bytes, and the error correction data 520 is z−n bytes. That is, the error correction data 520 can be reduced by n bytes, and the necessary information 510 other than the data can be increased by n bytes compared to the comparative example. This is because the error correction data 520 is reduced by reducing the number of error correction bits as described above.

<Write operation>
The write operation in this embodiment will be described below with reference to FIGS. FIG. 6 is a flowchart of the write operation in this embodiment.

  As shown in FIG. 6, first, in step S <b> 11, the memory controller 100 receives data input from the host 200 via the host interface 110 and stores it in the data buffer 130.

  Next, in step S <b> 12, the memory controller 100 receives the parameter setting command input from the host 200 via the host interface 110 and stores it in the MPU 120. This parameter setting command notifies whether or not the data stored in the data buffer 130 is important. The parameter setting command is a command in which parameters such as the number of valid bits of data input from the host 200, the number of data, and the data compression method are set, for example. The MPU 120 receives the parameter setting command and determines whether or not the data is important.

  Next, in step S <b> 13, the memory controller 100 receives the write logical address of the memory controller 100 input from the host 200 via the host interface 110 and stores it in the MPU 120. Based on this logical address, the MPU 120 determines whether to write the data stored in the data buffer 130 as SLC or MLC. Thereafter, the MPU 120 converts the logical address into a physical address of the flash memory 300 to be written.

  Next, in step S <b> 14, the memory controller 100 receives a write command input from the host 200 via the host interface 110. Thereafter, the MPU 120 transfers the data stored in the data buffer 130 to the flash memory interface 140.

  Next, in step S15, the error correction bit number setting unit 161 sets the error correction bit number of the data transferred from the data buffer 130. Details of step S15 will be described later with reference to FIG.

  Next, in step S <b> 16, the error correction code generation / addition unit 162 generates an error correction code based on the error correction bit number set by the error correction bit number setting unit 161. The data amount of this error correction code increases as the number of error correction bits increases, and decreases as the number of error correction bits decreases. Thereafter, the error correction code generation / addition unit 162 adds the error correction code to the data transferred from the data buffer 130.

  Next, in step S17, the data with the error correction code added is written to the designated physical address of the flash memory 300. In this way, the write operation from the host 200 to the flash memory 300 is performed.

  FIG. 7 is a flowchart showing details of the operation in step S15 in FIG.

  As shown in FIG. 7, when setting the number of error correction bits, first, in step S21, the maximum number of error correction bits is set. The maximum number of error correction bits is the maximum number of bits that can be error-corrected with respect to data to be written. Here, as an example, the maximum number of error correction bits is 16 bits.

  Next, in step S22, it is determined whether the memory area to be accessed is an MLC area or an SLC area. The determination as to whether it is the MLC area or the SLC area is made based on the logical address received in step S13 in FIG.

  If it is determined in step S22 that the memory area to be accessed is the SLC area (No in step S22), then the number of error correction bits set in step S23 is decreased. This is because the SLC region in the flash memory 300 is a region with higher reliability than the MLC region, and the number of error bits can be reduced.

  As described with reference to FIGS. 2 and 3, in the flash memory 300, the SLC region and the MLC region are not separated in the memory cell array 310, and each memory cell can function as an SLC or an MLC.

  Next, in step S24, it is determined whether the data to be written is important data. The determination as to whether the data is important is made based on the parameter setting command received in step S12 in FIG. The important data is not limited to data that the memory controller 100 is notified of as important by the parameter setting command from the host 200, but also includes data that the memory controller 100 manages internally.

  If it is determined in step S24 that the data to be written is not important data (No in step S24), then the number of error correction bits set in step S25 is decreased.

  Next, in step S26, it is determined whether or not the erase count of the flash memory 300 to be written exceeds a threshold value. Since the erase operation is performed for each block BLK in the flash memory 300, the number of times of erasure differs for each block BLK. The erase count for each block BLK is stored in the flash memory 300. That is, whether or not the erase count of the flash memory 300 exceeds the threshold value is determined by the memory controller 100 converting the logical address received from the host 200 into a physical address, and the erase count data of the block BLK at the physical address. Is received from the flash memory 300 and compared with a threshold value. An appropriate value is stored in advance in the MPU 120 as the threshold value for the number of times of erasure.

  If it is determined in step S27 that the number of erasures does not exceed the threshold (No in step S26), then the number of error correction bits set in step S27 is decreased. This is because the block BLK with a smaller number of erases has higher reliability. In other words, as the number of erases increases in the flash memory 300, the reliability decreases and the number of error bits increases. That is, the number of error correction bits is made variable for each block BLK according to the number of erasures.

  Through the above steps, the number of error correction bits written to the flash memory 300 is set. For example, when any one of step S23, step S25, and step S27 is performed, the number of error correction bits is reduced from 16 bits set in step S21 to 12 bits. For example, when any two steps are performed, the number of error correction bits is reduced from 16 bits to 8 bits. Further, for example, when all the steps are performed, the number of error correction bits is reduced from 16 bits to 4 bits. As described above, the error correction bit number setting unit 161 can change the error correction bit number according to various conditions. The number of error correction bits is an example, and various values can be set according to the standard of the flash memory 300 or the like. In addition, the order of steps S22, S24, and S26 can be changed.

  Further, the condition for making the number of error correction bits variable is not limited to the determination in the steps S22, S24, and S26.

  For example, the number of error correction bits may be made variable depending on whether or not the read count of the flash memory 300 to be written exceeds a threshold value. When page unit data is written to the flash memory 300, page unit data is written to a block BLK in which a part of the area is vacant. The reliability of a block BLK in which a part of the area is vacant is changed according to the number of times of reading data stored in the block BLK. The read count of this block BLK is stored in the flash memory 300. That is, the determination as to whether or not the read count of the flash memory 300 exceeds the threshold value is made by converting the logical address received by the memory controller 100 from the host 200 into a physical address and reading the read count data of the block BLK at the physical address. It is performed by receiving from the flash memory 300 and comparing with the threshold value.

  After that, when it is determined that the number of readings exceeds the threshold, the error correction code having a larger number of error correction bits than the error correction bit number of the error correction code added to the data already written in the block BLK Is written in an empty area of the block BLK. This is because when the number of readings in the flash memory 300 increases, the reliability decreases and the number of error bits increases. That is, the number of error correction bits is made variable for each block BLK.

  Note that when writing data in units of pages, the number of error correction bits for each page in the block BLK is stored in the flash memory 300, so that the number of error correction bits can be changed for each page in the block BLK, not for each block BLK. It is also possible to make it.

<Read operation>
Hereinafter, the read operation in the present embodiment will be described.

  In the read operation, first, the memory controller 100 receives the read logical address of the memory controller 100 input from the host 200 via the host interface 110 and stores it in the MPU 120. Thereafter, the MPU 120 converts the logical address into a physical address of the flash memory 300 to be read.

  Next, the memory controller 100 receives a read command input from the host 200 via the host interface 110. Thereafter, the MPU 120 reads the data stored at the specified physical address of the flash memory 300 to the flash memory interface 140.

  Next, the error correction unit 171 performs error correction on the data read from the data buffer 130. This error correction is performed based on the error correction code added to the data read from the data buffer 130, and is performed for the number of bits set by the error correction bit number setting unit 161. That is, in this error correction, the smaller the number of error correction bits and the data amount of the error correction code, the shorter the error correction processing time and the power consumption. Note that details of error correction of data are well known and will be omitted. When the error correction is completed, the error correction code is removed from the data.

  Thereafter, the error-corrected data is temporarily stored in the data buffer 130 and read out to the host 200 via the host interface 110.

<Effect>
According to the embodiment, the memory controller 100 that can be connected to the host 200 and the flash memory 300 changes the number of error correction bits according to various conditions when writing data from the host 200 to the flash memory 300. Then, an error correction code is created based on the set error correction bit number, added to the data, and written to the flash memory 300. That is, the number of error correction bits can be reduced when writing in a highly reliable area or when the importance of data is low. As a result, the amount of extra error correction code data can be reduced, and the amount of management data can be increased accordingly. In addition, when data is read from the flash memory 300 to the host 200, the error correction processing time can be shortened, and power consumption can be reduced accordingly.

  In addition, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  DESCRIPTION OF SYMBOLS 100 ... Memory controller, 110 ... Host interface, 120 ... MPU (control part), 161 ... Error correction bit number setting part, 162 ... Error correction code production | generation addition part, 200 ... Host, 300 ... Flash memory (memory).

Claims (5)

A memory controller for controlling a memory having a plurality of memory cells capable of writing, reading and erasing in binary or multi-value according to a command from a host,
A host interface for accessing commands and data with the host;
A memory interface for accessing commands and data to and from the memory;
A control unit for controlling the memory interface according to a command from the host via the host interface;
Comprising
The memory interface is
When writing data from the host to the memory, if writing to the memory is binary writing, a first error correction bit number of i bits is set for the data from the host, and If the write is a multi-value write, an error correction bit number setting unit << 161 >> for setting a second error correction bit number of j bits (i <j) for the data from the host;
When the first error correction bit number is set by the error correction bit number setting unit, a first error correction code of k bytes is generated and added to the data from the host, and the second error correction bit number Is set, an error correction code generation / addition unit that generates a second error correction code of l (k <l) bytes and adds it to the data from the host;
A memory controller comprising:   2. The memory controller according to claim 1, wherein the determination as to whether the data from the host is written in binary or multi-value in the memory is made in accordance with a logical address input from the host. A memory controller for controlling a memory having a plurality of memory cells that can be written, read and erased according to a command from a host,
A host interface to access commands and data to and from the host;
A memory interface for accessing commands and data to and from the memory;
A control unit for controlling the memory interface according to a command from the host via the host interface;
Comprising
The memory interface is
When writing data from the host to the memory, if the data from the host is data notified by a command from the host, the first error correction bit number of m bits with respect to the data from the host And the second error correction bit number of n bits (m <n) is set for the data from the host when the data from the host is not notified by the command from the host. An error correction bit number setting section;
When the first error correction bit number is set by the error correction bit number setting unit, a first error correction code of k bytes is generated and added to the data from the host, and the second error correction bit number Is set, an error correction code generation / addition unit that generates a second error correction code of l (k <l) bytes and adds it to the data from the host;
A memory controller comprising: A memory controller for controlling a memory having a plurality of memory cells that can be written, read and erased according to a command from a host,
A host interface to access commands and data to and from the host;
A memory interface for accessing commands and data to and from the memory;
A control unit for controlling the memory interface according to a command from the host via the host interface;
Comprising
The memory interface is
When writing data from the host to the memory, if the number of erases of the memory is less than a threshold, a first error correction bit number of m bits is set for the data from the host, and the number of erases of the memory Is equal to or greater than a threshold value, an error correction bit number setting unit that sets a second error correction bit number of n bits (m <n) for data from the host;
When the first error correction bit number is set by the error correction bit number setting unit, a first error correction code of k bytes is generated and added to the data from the host, and the second error correction bit number Is set, an error correction code generation / addition unit that generates a second error correction code of l (k <l) bytes and adds it to the data from the host;
A memory controller comprising:   5. The memory includes a plurality of blocks each including a predetermined number of memory cells among the plurality of memory cells, and the number of times of erasure of the memory is different for each block in the memory. Memory controller as described in.

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